Quartus II Settings File Reference Manual - Altera
Quartus II Settings File Reference Manual - Altera
Quartus II Settings File Reference Manual - Altera
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<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong><br />
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© 2012 <strong>Altera</strong> Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos<br />
are trademarks of <strong>Altera</strong> Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as<br />
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. <strong>Altera</strong> warrants performance of its<br />
semiconductor products to current specifications in accordance with <strong>Altera</strong>'s standard warranty, but reserves the right to make changes to any products and<br />
services at any time without notice. <strong>Altera</strong> assumes no responsibility or liability arising out of the application or use of any information, product, or service<br />
described herein except as expressly agreed to in writing by <strong>Altera</strong>. <strong>Altera</strong> customers are advised to obtain the latest version of device specifications before relying<br />
on any published information and before placing orders for products or services.<br />
ISO<br />
9001:2008<br />
Registered<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
Contents<br />
Chapter 1. Project-Wide Assignments<br />
AGGREGATE_REVISION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1<br />
AHDL_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2<br />
AHDL_TEXT_DESIGN_OUTPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3<br />
ASM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4<br />
AUTO_EXPORT_VER_COMPATIBLE_DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5<br />
BASE_REVISION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6<br />
BASE_REVISION_PROJECT_OUTPUT_DIRECTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7<br />
BDF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8<br />
BINARY_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9<br />
BSF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10<br />
CDF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11<br />
COMMAND_MACRO_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12<br />
CPP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–13<br />
CPP_INCLUDE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–14<br />
CUSP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–15<br />
CVP_REVISION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–16<br />
C_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17<br />
DEPENDENCY_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18<br />
DSPBUILDER_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–19<br />
EDIF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–20<br />
ELF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–21<br />
ENABLE_COMPACT_REPORT_TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–22<br />
ENABLE_REDUCED_MEMORY_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–23<br />
EQUATION_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–24<br />
FLOW_DISABLE_ASSEMBLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–25<br />
FLOW_ENABLE_HC_COMPARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–26<br />
FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–27<br />
FLOW_ENABLE_PARALLEL_MODULES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–28<br />
FLOW_ENABLE_POWER_ANALYZER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–29<br />
FLOW_ENABLE_RTL_VIEWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–30<br />
FLOW_HARDCOPY_DESIGN_READINESS_CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–31<br />
GDF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–32<br />
HC_OUTPUT_DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–33<br />
HEX_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–34<br />
HEX_OUTPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–35<br />
HTML_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–36<br />
HTML_REPORT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–37<br />
INCLUDE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–38<br />
IPA_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–39<br />
IP_TOOL_ENV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–40<br />
IP_TOOL_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–41<br />
IP_TOOL_VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–42<br />
ISC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–43<br />
JAM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–44<br />
JBC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–45<br />
LICENSE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–46<br />
LMF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–47<br />
LOGIC_ANALYZER_INTERFACE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–48<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
ii Contents<br />
MAP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–49<br />
MASK_REVISION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–50<br />
MESSAGE_DISABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–51<br />
MESSAGE_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–52<br />
MESSAGE_SUPPRESSION_RULE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–53<br />
MIF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–54<br />
MIGRATION_DIFFERENT_SOURCE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–55<br />
MISC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–56<br />
NUM_PARALLEL_PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–57<br />
OBJECT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–59<br />
OCP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–60<br />
PARTIAL_SRAM_OBJECT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–61<br />
PERSONA_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–62<br />
PIN_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–63<br />
POWER_INPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–64<br />
PPF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–65<br />
PROGRAMMER_OBJECT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–66<br />
PROJECT_OUTPUT_DIRECTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–67<br />
PROJECT_SHOW_ENTITY_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–68<br />
PROJECT_USE_SIMPLIFIED_NAMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–69<br />
QARLOG_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–70<br />
QAR_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–71<br />
QIP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–72<br />
QSYS_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–73<br />
QUARTUS_PTF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–74<br />
QUARTUS_SBD_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–75<br />
QUARTUS_STANDARD_DELAY_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–76<br />
QVAR_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–77<br />
QXP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–78<br />
RAW_BINARY_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–79<br />
READ_OR_WRITE_IN_BYTE_ADDRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–80<br />
RECONFIGURABLE_REVISION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–81<br />
REVISION_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–82<br />
RUN_FULL_COMPILE_ON_DEVICE_CHANGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–83<br />
SAVE_MIGRATION_INFO_DURING_COMPILATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–84<br />
SBI_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–85<br />
SDC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–86<br />
SDF_OUTPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–87<br />
SERIAL_BITSTREAM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–88<br />
SIGNALTAP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–89<br />
SIP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–90<br />
SMART_RECOMPILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–91<br />
SMF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–92<br />
SOFTWARE_LIBRARY_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–93<br />
SOPC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–94<br />
SOURCE_TCL_SCRIPT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–95<br />
SPD_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–96<br />
SRAM_OBJECT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–97<br />
SRECORDS_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–98<br />
SVF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–99<br />
SYM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–100<br />
SYNTHESIS_ONLY_QIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–101<br />
SYSTEMVERILOG_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–102<br />
TCL_SCRIPT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–103<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Contents iii<br />
TEMPLATE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–104<br />
TEXT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–105<br />
TEXT_FORMAT_REPORT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–106<br />
TIMING_ANALYSIS_OUTPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–107<br />
VCD_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–108<br />
VECTOR_TABLE_OUTPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–109<br />
VECTOR_TEXT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–110<br />
VECTOR_WAVEFORM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–111<br />
VERILOG_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–112<br />
VERILOG_INCLUDE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–113<br />
VERILOG_OUTPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–114<br />
VERILOG_TEST_BENCH_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–115<br />
VER_COMPATIBLE_DB_DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–116<br />
VHDL_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–117<br />
VHDL_OUTPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–118<br />
VHDL_TEST_BENCH_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–119<br />
VQM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–120<br />
ZIP_VECTOR_WAVEFORM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–121<br />
Chapter 2. Pin & Locations Assignments<br />
FAST_INPUT_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1<br />
FAST_OCT_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3<br />
FAST_OUTPUT_ENABLE_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4<br />
FAST_OUTPUT_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6<br />
IP_DEBUG_VISIBLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8<br />
LL_IGNORE_IO_PIN_SECURITY_CONSTRAINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9<br />
LOCATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10<br />
MAX7K_CLIQUE_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11<br />
MEMBER_OF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12<br />
PIN_CONNECT_FROM_NODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13<br />
RESERVE_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14<br />
SUBCLIQUE_OF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15<br />
VIRTUAL_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16<br />
Chapter 3. Assignment Group Assignments<br />
ASSIGNMENT_GROUP_EXCEPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1<br />
ASSIGNMENT_GROUP_MEMBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2<br />
Chapter 4. Analysis & Synthesis Assignments<br />
ADV_NETLIST_OPT_ALLOWED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1<br />
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3<br />
ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5<br />
ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7<br />
ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9<br />
ALLOW_CHILD_PARTITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11<br />
ALLOW_POWER_UP_DONT_CARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12<br />
ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13<br />
ALLOW_SYNCH_CTRL_USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15<br />
ALLOW_XOR_GATE_USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17<br />
AUTO_CARRY_CHAINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18<br />
AUTO_CLOCK_ENABLE_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20<br />
AUTO_DSP_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22<br />
AUTO_ENABLE_SMART_COMPILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
iv Contents<br />
AUTO_GLOBAL_CLOCK_MAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25<br />
AUTO_GLOBAL_OE_MAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26<br />
AUTO_LCELL_INSERTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–27<br />
AUTO_OPEN_DRAIN_PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28<br />
AUTO_PARALLEL_EXPANDERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–30<br />
AUTO_RAM_BLOCK_BALANCING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–31<br />
AUTO_RAM_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–33<br />
AUTO_RAM_TO_LCELL_CONVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–35<br />
AUTO_RESOURCE_SHARING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–37<br />
AUTO_ROM_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–38<br />
AUTO_SHIFT_REGISTER_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–40<br />
BLOCK_DESIGN_NAMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–42<br />
CLKLOCKX1_INPUT_FREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–44<br />
CYCLONE<strong>II</strong>_OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–45<br />
CYCLONE_OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–47<br />
DEVICE_FILTER_PACKAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–49<br />
DEVICE_FILTER_PIN_COUNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–50<br />
DEVICE_FILTER_SPEED_GRADE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–51<br />
DEVICE_FILTER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–52<br />
DISABLE_OCP_HW_EVAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–53<br />
DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–54<br />
DONT_MERGE_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–55<br />
DQS_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–56<br />
DQS_FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–57<br />
DQS_SHIFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–58<br />
DQS_SYSTEM_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–59<br />
DSE_SYNTH_EXTRA_EFFORT_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–60<br />
DSP_BLOCK_BALANCING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–61<br />
EDA_DESIGN_ENTRY_SYNTHESIS_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–63<br />
EDA_INPUT_DATA_FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–64<br />
EDA_INPUT_GND_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–65<br />
EDA_INPUT_VCC_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–66<br />
EDA_LMF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–67<br />
EDA_RUN_TOOL_AUTOMATICALLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–68<br />
EDA_SHOW_LMF_MAPPING_MESSAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–69<br />
EDA_VHDL_LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–70<br />
ENABLE_IP_DEBUG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–71<br />
ENABLE_M512 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–72<br />
EXTRACT_VERILOG_STATE_MACHINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–73<br />
EXTRACT_VHDL_STATE_MACHINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–74<br />
FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–75<br />
FORCE_SYNCH_CLEAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–76<br />
HDL_INITIAL_FANOUT_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–78<br />
HDL_MESSAGE_LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–79<br />
HDL_MESSAGE_OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–80<br />
HDL_MESSAGE_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–81<br />
HPS_PARTITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–82<br />
IGNORE_CARRY_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–83<br />
IGNORE_CASCADE_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–84<br />
IGNORE_GLOBAL_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–85<br />
IGNORE_LCELL_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–86<br />
IGNORE_MAX_FANOUT_ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–88<br />
IGNORE_ROW_GLOBAL_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–90<br />
IGNORE_SOFT_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–91<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Contents v<br />
IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–93<br />
IGNORE_VERILOG_INITIAL_CONSTRUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–94<br />
IMPLEMENT_AS_CLOCK_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–95<br />
IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–97<br />
INFER_RAMS_FROM_RAW_LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–98<br />
LCELL_INSERTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–99<br />
LIMIT_AHDL_INTEGERS_TO_32_BITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–100<br />
MAX7000_FANIN_PER_CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–101<br />
MAX7000_IGNORE_LCELL_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–103<br />
MAX7000_IGNORE_SOFT_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–105<br />
MAX7000_OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–106<br />
MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–108<br />
MAX<strong>II</strong>_OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–109<br />
MAX_AUTO_GLOBAL_REGISTER_CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–111<br />
MAX_BALANCING_DSP_BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–113<br />
MAX_FANOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–115<br />
MAX_LABS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–117<br />
MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–118<br />
MAX_RAM_BLOCKS_M4K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–119<br />
MAX_RAM_BLOCKS_M512 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–121<br />
MAX_RAM_BLOCKS_MRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–123<br />
MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED<br />
_THROUGH_MODE_SETTING_DONT_CARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–125<br />
MUX_RESTRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–127<br />
NOT_GATE_PUSH_BACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–129<br />
NUMBER_OF_INVERTED_REGISTERS_REPORTED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–130<br />
NUMBER_OF_REMOVED_REGISTERS_REPORTED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–131<br />
NUMBER_OF_SWEPT_NODES_REPORTED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–132<br />
OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–133<br />
OPTIMIZE_POWER_DURING_SYNTHESIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–135<br />
PARALLEL_SYNTHESIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–137<br />
PARAMETER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–138<br />
POWER_UP_LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–139<br />
PRESERVE_FANOUT_FREE_NODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–141<br />
PRESERVE_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–142<br />
PRE_MAPPING_RESYNTHESIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–143<br />
RBCGEN_CRITICAL_WARNING_TO_ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–144<br />
REMOVE_DUPLICATE_REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–145<br />
REMOVE_REDUNDANT_LOGIC_CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–146<br />
REPORT_CONNECTIVITY_CHECKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–148<br />
REPORT_PARAMETER_SETTINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–149<br />
REPORT_SOURCE_ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–150<br />
RESYNTHESIS_PHYSICAL_SYNTHESIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–151<br />
RESYNTHESIS_RETIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–152<br />
SAFE_STATE_MACHINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–153<br />
SAVE_DISK_SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–154<br />
SEARCH_PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–155<br />
SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–156<br />
SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES . . . . . . . . . . . . . . . . . . . . . . . 4–157<br />
STATE_MACHINE_PROCESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–158<br />
STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_<br />
DETECT_SIGNAL_THRESHOLD_SELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–160<br />
STRATIX<strong>II</strong>_CARRY_CHAIN_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–161<br />
STRATIX<strong>II</strong>_OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–163<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
vi Contents<br />
STRATIX_CARRY_CHAIN_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–165<br />
STRATIX_OPTIMIZATION_TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–166<br />
STRICT_RAM_RECOGNITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–168<br />
SYNCHRONIZATION_REGISTER_CHAIN_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–170<br />
SYNTHESIS_EFFORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–172<br />
SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER . . . . . . . . . . . . . . . . 4–173<br />
SYNTHESIS_SEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–174<br />
SYNTH_CLOCK_MUX_PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–175<br />
SYNTH_CRITICAL_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–177<br />
SYNTH_GATED_CLOCK_CONVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–179<br />
SYNTH_MESSAGE_LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–181<br />
SYNTH_PROTECT_SDC_CONSTRAINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–182<br />
SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–184<br />
SYNTH_TIMING_DRIVEN_SYNTHESIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–186<br />
TOP_LEVEL_ENTITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–188<br />
TRUE_WYSIWYG_FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–189<br />
USER_LIBRARIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–190<br />
USE_HIGH_SPEED_ADDER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–191<br />
USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–192<br />
VERILOG_CONSTANT_LOOP_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–193<br />
VERILOG_INPUT_VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–194<br />
VERILOG_LMF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–195<br />
VERILOG_MACRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–196<br />
VERILOG_NON_CONSTANT_LOOP_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–197<br />
VERILOG_SHOW_LMF_MAPPING_MESSAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–198<br />
VHDL_INPUT_LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–199<br />
VHDL_INPUT_VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–200<br />
VHDL_LMF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–201<br />
VHDL_SHOW_LMF_MAPPING_MESSAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–202<br />
Chapter 5. Incremental Compilation Assignments<br />
ALLOW_MULTIPLE_PERSONAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1<br />
AUTO_EXPORT_INCREMENTAL_COMPILATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2<br />
IGNORE_PARTITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3<br />
INCREMENTAL_COMPILATION_EXPORT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4<br />
INCREMENTAL_COMPILATION_EXPORT_PARTITION_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5<br />
INCREMENTAL_COMPILATION_EXPORT_POST_FIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6<br />
INCREMENTAL_COMPILATION_EXPORT_POST_SYNTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7<br />
INCREMENTAL_COMPILATION_EXPORT_ROUTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8<br />
INPUT_PERSONA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9<br />
PARTITION_ALWAYS_USE_QXP_NETLIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10<br />
PARTITION_FITTER_PRESERVATION_LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11<br />
PARTITION_HIERARCHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12<br />
PARTITION_IGNORE_SOURCE_FILE_CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13<br />
PARTITION_IMPORT_ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–14<br />
PARTITION_IMPORT_EXISTING_ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15<br />
PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16<br />
PARTITION_IMPORT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17<br />
PARTITION_IMPORT_PROMOTE_ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18<br />
PARTITION_LAST_IMPORTED_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–19<br />
PARTITION_NETLIST_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–20<br />
PARTITION_PRESERVE_HIGH_SPEED_TILES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–21<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Contents vii<br />
Chapter 6. Fitter Assignments<br />
ACTIVE_SERIAL_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1<br />
ADCE_ENABLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3<br />
ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER . . . . . . . . . . . . . . 6–4<br />
ALWAYS_ENABLE_INPUT_BUFFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5<br />
ASYNC_PIPELINE_DISABLE_DESTINATION_CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6<br />
ASYNC_PIPELINE_REG_REACH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7<br />
AUTO_C3_M9K_BIT_SKIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8<br />
AUTO_DELAY_CHAINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9<br />
AUTO_GLOBAL_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11<br />
AUTO_GLOBAL_MEMORY_CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13<br />
AUTO_GLOBAL_REGISTER_CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14<br />
AUTO_MERGE_PLLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16<br />
AUTO_PACKED_REGISTERS_CYCLONE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18<br />
AUTO_PACKED_REGISTERS_MAX<strong>II</strong> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20<br />
AUTO_PACKED_REGISTERS_STRATIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–22<br />
AUTO_PACKED_REGISTERS_STRATIX<strong>II</strong> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–24<br />
AUTO_TURBO_BIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–26<br />
BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–27<br />
BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES . . . . . . . . . . . . . . . . 6–28<br />
BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS . . . . . . . . . . . . . . . . . . . . 6–30<br />
BLOCK_RAM_TO_MLAB_CELL_CONVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–32<br />
C3_M9K_BIT_SKIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–33<br />
CDR_BANDWIDTH_PRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–34<br />
CKN_CK_PAIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–35<br />
CLAMPING_DIODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–36<br />
CLOCK_TO_OUTPUT_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–37<br />
CONFIGURATION_VCCIO_LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–38<br />
CRC_ERROR_CHECKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–40<br />
CRC_ERROR_OPEN_DRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–42<br />
CURRENT_STRENGTH_NEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–43<br />
CVP_CONFDONE_OPEN_DRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–45<br />
CVP_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–46<br />
CYCLONE<strong>II</strong>I_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–47<br />
CYCLONE<strong>II</strong>_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–48<br />
CYCLONE<strong>II</strong>_RESERVE_NCEO_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–49<br />
CYCLONE<strong>II</strong>_TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–50<br />
CYCLONE_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–51<br />
D1_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–52<br />
D1_FINE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–53<br />
D2_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–54<br />
D3_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–55<br />
D4_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–56<br />
D4_FINE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–57<br />
D5_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–58<br />
D5_FINE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–59<br />
D5_OCT_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–60<br />
D5_OE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–61<br />
D6_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–62<br />
D6_FINE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–63<br />
D6_OCT_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–64<br />
D6_OE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–65<br />
D6_OE_FINE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–66<br />
DATA0_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–67<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
viii Contents<br />
DCLK_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–68<br />
DC_CURRENT_FOR_ELECTROMIGRATION_CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–69<br />
DDIO_INPUT_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–70<br />
DDIO_OUTPUT_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–71<br />
DDIO_OUTPUT_REGISTER_DISTANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–72<br />
DECREASE_INPUT_DELAY_TO_INPUT_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–73<br />
DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–74<br />
DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–75<br />
DEVICE_MIGRATION_LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–76<br />
DEVICE_TECHNOLOGY_MIGRATION_LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–77<br />
DPRIO_CHANNEL_NUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–78<br />
DPRIO_CRUCLK_NUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–79<br />
DPRIO_INTERFACE_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–80<br />
DPRIO_QUAD_NUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–81<br />
DPRIO_QUAD_PLL_NUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–82<br />
DPRIO_TX_PLL0_REFCLK_NUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–83<br />
DPRIO_TX_PLL1_REFCLK_NUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–84<br />
DPRIO_TX_PLL_NUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–85<br />
DQSB_DQS_PAIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–86<br />
DQSOUT_DELAY_CHAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–87<br />
DQS_ENABLE_DELAY_CHAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–88<br />
DQS_LOCAL_CLOCK_DELAY_CHAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–89<br />
DQ_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–90<br />
DQ_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–91<br />
DUAL_PURPOSE_CLOCK_PIN_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–92<br />
DUPLICATE_ATOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–93<br />
DYNAMIC_OCT_CONTROL_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–95<br />
ECO_ALLOW_ROUTING_CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–96<br />
ECO_OPTIMIZE_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–97<br />
ECO_REGENERATE_REPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–98<br />
ENABLE_ASMI_FOR_FLASH_LOADER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–99<br />
ENABLE_BENEFICIAL_SKEW_OPTIMIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–100<br />
ENABLE_BUS_HOLD_CIRCUITRY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–101<br />
ENABLE_CRC_ERROR_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–103<br />
ENABLE_CVP_CONFDONE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–104<br />
ENABLE_DEVICE_WIDE_OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–105<br />
ENABLE_DEVICE_WIDE_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–107<br />
ENABLE_HOLD_BACK_OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–109<br />
ENABLE_INIT_DONE_OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–110<br />
ENABLE_NCEO_OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–112<br />
ENABLE_PR_PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–113<br />
ENABLE_VREFA_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–114<br />
ENABLE_VREFB_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–115<br />
ERROR_CHECK_FREQUENCY_DIVISOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–116<br />
EXCLUSIVE_IO_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–118<br />
EXTERNAL_LVDS_RX_USES_DPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–119<br />
FINAL_PLACEMENT_OPTIMIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–120<br />
FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–122<br />
FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–123<br />
FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–125<br />
FITTER_EARLY_TIMING_ESTIMATE_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–127<br />
FITTER_EFFORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–129<br />
FIT_ATTEMPTS_TO_SKIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–130<br />
FIT_ONLY_ONE_ATTEMPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–132<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Contents ix<br />
FLEX10K_MAX_PERIPHERAL_OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–133<br />
FORCE_CONFIGURATION_VCCIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–134<br />
FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS . . . . . . . . . . . . . . . . . . . . . 6–136<br />
FORCE_FRACTURED_MODE_ALM_IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–137<br />
FORCE_MERGE_PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–138<br />
FORCE_MERGE_PLL_FANOUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–139<br />
FORCE_NON_FRACTURED_MODE_ALM_IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–140<br />
GENERATE_GXB_RECONFIG_MIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–141<br />
GENERATE_GXB_RECONFIG_MIF_WITH_PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–142<br />
GLOBAL_SIGNAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–143<br />
GLOBAL_SIGNAL_CLKCTRL_LOCATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–145<br />
GNDIO_CURRENT_1PT8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–146<br />
GNDIO_CURRENT_2PT5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–147<br />
GNDIO_CURRENT_GTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–148<br />
GNDIO_CURRENT_GTL_PLUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–149<br />
GNDIO_CURRENT_LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–150<br />
GNDIO_CURRENT_LVTTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–151<br />
GNDIO_CURRENT_PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–152<br />
GNDIO_CURRENT_SSTL2_CLASS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–153<br />
GNDIO_CURRENT_SSTL2_CLASS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–154<br />
GNDIO_CURRENT_SSTL3_CLASS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–155<br />
GNDIO_CURRENT_SSTL3_CLASS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–156<br />
GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–157<br />
GXB_0PPM_CLOCK_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–158<br />
GXB_0PPM_CLOCK_GROUP_DRIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–159<br />
GXB_0PPM_CORECLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–160<br />
GXB_0PPM_CORE_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–161<br />
GXB_CLOCK_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–162<br />
GXB_CLOCK_GROUP_DRIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–163<br />
GXB_RECONFIG_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–164<br />
GXB_RECONFIG_MIF_PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–165<br />
GXB_REFCLK_COUPLING_TERMINATION_SETTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–166<br />
HPS_IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–167<br />
IGNORE_MODE_FOR_MERGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–168<br />
IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–169<br />
INCREASE_DELAY_TO_OUTPUT_ENABLE_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–170<br />
INCREASE_DELAY_TO_OUTPUT_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–171<br />
INCREASE_INPUT_CLOCK_ENABLE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–172<br />
INCREASE_OUTPUT_CLOCK_ENABLE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–173<br />
INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–174<br />
INCREASE_TZX_DELAY_TO_OUTPUT_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–175<br />
INC_PLC_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–176<br />
INIT_DONE_OPEN_DRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–177<br />
INPUT_REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–178<br />
INPUT_TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–179<br />
INSERT_ADDITIONAL_LOGIC_CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–180<br />
INTERNAL_SCRUBBING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–181<br />
IO_MAXIMUM_TOGGLE_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–182<br />
IO_PLACEMENT_OPTIMIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–184<br />
IO_STANDARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–186<br />
LVDS_DIRECT_LOOPBACK_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–188<br />
LVDS_RX_REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–189<br />
M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–190<br />
MATCH_PLL_COMPENSATION_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–191<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
x Contents<br />
MAX7000B_VCCIO_IOBANK1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–192<br />
MAX7000B_VCCIO_IOBANK2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–193<br />
MAX7000_DEVICE_IO_STANDARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–194<br />
MAX7000_ENABLE_JTAG_BST_SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–195<br />
MAX7000_INDIVIDUAL_TURBO_BIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–196<br />
MAX_CLOCKS_ALLOWED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–197<br />
MAX_CONSECUTIVE_OUTPUTS_FOR_ELECTROMIGRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–198<br />
MAX_CONSECUTIVE_VIO_OUTPUTS_FOR_ELECTROMIGRATION . . . . . . . . . . . . . . . . . . . . . . . 6–199<br />
MAX_CURRENT_FOR_ELECTROMIGRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–200<br />
MAX_CURRENT_FOR_VIO_ELECTROMIGRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–201<br />
MAX_GLOBAL_CLOCKS_ALLOWED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–202<br />
MAX_PERIPHERY_CLOCKS_ALLOWED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–203<br />
MAX_REGIONAL_CLOCKS_ALLOWED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–204<br />
MEMORY_INTERFACE_DATA_PIN_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–205<br />
MEM_INTERFACE_DELAY_CHAIN_CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–206<br />
MERGE_TX_PLL_DRIVEN_BY_REGISTERS_WITH_SAME_CLEAR . . . . . . . . . . . . . . . . . . . . . . . . . 6–207<br />
MIGRATION_CONSTRAIN_CORE_RESOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–208<br />
MIGRATION_DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–209<br />
NCEO_OPEN_DRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–210<br />
NDQS_LOCAL_CLOCK_DELAY_CHAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–211<br />
OPTIMIZE_FOR_METASTABILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–212<br />
OPTIMIZE_HOLD_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–213<br />
OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–215<br />
OPTIMIZE_MULTI_CORNER_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–216<br />
OPTIMIZE_POWER_DURING_FITTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–218<br />
OPTIMIZE_SSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–220<br />
OPTIMIZE_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–222<br />
OUTPUT_BUFFER_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–224<br />
OUTPUT_BUFFER_DELAY_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–225<br />
OUTPUT_ENABLE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–227<br />
OUTPUT_ENABLE_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–228<br />
OUTPUT_PIN_LOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–230<br />
OUTPUT_TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–231<br />
OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–232<br />
PAD_TO_CORE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–233<br />
PAD_TO_DDIO_REGISTER_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–234<br />
PAD_TO_INPUT_REGISTER_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–235<br />
PCI_IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–236<br />
PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING . . . . . . . . . . . . . . . . . . . . . . . 6–238<br />
PHYSICAL_SYNTHESIS_COMBO_LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–240<br />
PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–242<br />
PHYSICAL_SYNTHESIS_EFFORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–244<br />
PHYSICAL_SYNTHESIS_LOG_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–246<br />
PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA . . . . . . . . . . . . . . . . . . . . . . . . 6–247<br />
PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–248<br />
PHYSICAL_SYNTHESIS_REGISTER_RETIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–250<br />
PLACEMENT_EFFORT_MULTIPLIER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–252<br />
PLL_AUTO_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–254<br />
PLL_BANDWIDTH_PRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–255<br />
PLL_CHANNEL_SPACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–256<br />
PLL_COMPENSATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–257<br />
PLL_COMPENSATION_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–259<br />
PLL_ENFORCE_USER_PHASE_SHIFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–261<br />
PLL_FEEDBACK_CLOCK_SIGNAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–262<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Contents xi<br />
PLL_FORCE_OUTPUT_COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–263<br />
PLL_FORCE_OUTPUT_COUNTER_HARDCOPY_REPLAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–265<br />
PLL_IGNORE_MIGRATION_DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–266<br />
PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–267<br />
PLL_OUTPUT_CLOCK_FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–268<br />
PLL_PFD_CLOCK_FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–269<br />
PLL_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–270<br />
PLL_VCO_CLOCK_FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–271<br />
PRESERVE_PLL_COUNTER_ORDER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–272<br />
PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_<br />
FRACTION_OF_USED_LAB_TILES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–273<br />
PROGRAMMABLE_POWER_TECHNOLOGY_SETTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–274<br />
PROGRAMMABLE_PREEMPHASIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–275<br />
PROGRAMMABLE_VOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–277<br />
PR_DONE_OPEN_DRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–279<br />
PR_ERROR_OPEN_DRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–280<br />
PR_READY_OPEN_DRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–281<br />
QDR_D_PIN_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–282<br />
RESERVE_ALL_UNUSED_PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–283<br />
RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–284<br />
RESERVE_ASDO_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–285<br />
RESERVE_DATA0_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–286<br />
RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . 6–288<br />
RESERVE_DATA1_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–289<br />
RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . 6–290<br />
RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . 6–291<br />
RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . 6–293<br />
RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . 6–294<br />
RESERVE_DCLK_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–295<br />
RESERVE_FLASH_NCE_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–296<br />
RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–297<br />
RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–298<br />
RESERVE_RDYNBUSY_AFTER_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–299<br />
ROUTER_CLOCKING_TOPOLOGY_ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–300<br />
ROUTER_EFFORT_MULTIPLIER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–301<br />
ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–303<br />
ROUTER_REGISTER_DUPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–305<br />
ROUTER_TIMING_OPTIMIZATION_LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–307<br />
ROUTING_BACK_ANNOTATION_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–309<br />
SCE_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–310<br />
SDO_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–311<br />
SEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–312<br />
SLEW_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–313<br />
SLOW_SLEW_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–315<br />
STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET . . . . . . . . . . . . . . . . . . . . . . . . 6–317<br />
STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE . . . . . . . . . . . . . . . . . . . . . . . . 6–318<br />
STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE . . . . . . . . . . . . . . . . . . . . . . . . 6–319<br />
STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–320<br />
STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER . . . . . . . . . . 6–321<br />
STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE . . . . . . . . . 6–322<br />
STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE . . . . . . . 6–323<br />
STRATIXGX_ALLOW_POST8B10B_LOOPBACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–324<br />
STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–325<br />
STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
xii Contents<br />
SOURCE_IN_DOUBLE_DATA_WIDTH_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–326<br />
STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–327<br />
STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE . . . . . . . . . . . . . . . . . . . . . . . . . 6–328<br />
STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER . . . . . . . . . 6–329<br />
STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE . . . . . . . . . 6–330<br />
STRATIXGX_TERMINATION_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–331<br />
STRATIX<strong>II</strong>GX_TERMINATION_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–332<br />
STRATIX<strong>II</strong>I_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–333<br />
STRATIX<strong>II</strong>I_MRAM_COMPATIBILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–334<br />
STRATIX<strong>II</strong>I_UPDATE_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–335<br />
STRATIX<strong>II</strong>_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–336<br />
STRATIX<strong>II</strong>_TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–337<br />
STRATIXV_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–338<br />
STRATIX_CONFIGURATION_SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–339<br />
STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–340<br />
STRATIX_DEVICE_IO_STANDARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–341<br />
STRATIX_UPDATE_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–343<br />
SYNCHRONIZER_IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–344<br />
SYNCHRONIZER_TOGGLE_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–346<br />
T11_0_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–347<br />
T11_1_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–348<br />
T11_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–349<br />
T11_FINE_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–350<br />
T4_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–351<br />
T8_DELAY0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–352<br />
T8_DELAY1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–353<br />
TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–354<br />
TERMINATION_CONTROL_BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–355<br />
TREAT_BIDIR_AS_OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–356<br />
TRI_STATE_SPI_PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–358<br />
TXPMA_SLEW_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–359<br />
UNUSED_TSD_PINS_GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–360<br />
USER_START_UP_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–361<br />
VCCIO_CURRENT_1PT8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–363<br />
VCCIO_CURRENT_2PT5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–364<br />
VCCIO_CURRENT_GTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–365<br />
VCCIO_CURRENT_GTL_PLUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–366<br />
VCCIO_CURRENT_LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–367<br />
VCCIO_CURRENT_LVTTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–368<br />
VCCIO_CURRENT_PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–369<br />
VCCIO_CURRENT_SSTL2_CLASS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–370<br />
VCCIO_CURRENT_SSTL2_CLASS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–371<br />
VCCIO_CURRENT_SSTL3_CLASS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–372<br />
VCCIO_CURRENT_SSTL3_CLASS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–373<br />
VCCPD_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–374<br />
WEAK_PULL_UP_RESISTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–375<br />
XCVR_ANALOG_SETTINGS_PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–377<br />
XCVR_GT_IO_PIN_TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–379<br />
XCVR_GT_RX_COMMON_MODE_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–380<br />
XCVR_GT_RX_CTLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–381<br />
XCVR_GT_RX_DC_GAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–382<br />
XCVR_GT_TX_COMMON_MODE_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–383<br />
XCVR_GT_TX_PRE_EMP_1ST_POST_TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–384<br />
XCVR_GT_TX_PRE_EMP_INV_PRE_TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–385<br />
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<strong>Reference</strong> <strong>Manual</strong>
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XCVR_GT_TX_PRE_EMP_PRE_TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–386<br />
XCVR_GT_TX_VOD_MAIN_TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–387<br />
XCVR_IO_PIN_TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–388<br />
XCVR_REFCLK_PIN_TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–389<br />
XCVR_RX_ACGAIN_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–390<br />
XCVR_RX_ACGAIN_V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–391<br />
XCVR_RX_BYPASS_EQ_STAGES_234 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–392<br />
XCVR_RX_COMMON_MODE_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–393<br />
XCVR_RX_DC_GAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–394<br />
XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–395<br />
XCVR_RX_EQ_BW_SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–396<br />
XCVR_RX_INPUT_VCM_SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–397<br />
XCVR_RX_LINEAR_EQUALIZER_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–398<br />
XCVR_RX_SD_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–399<br />
XCVR_RX_SD_OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–400<br />
XCVR_RX_SD_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–401<br />
XCVR_RX_SD_THRESHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–402<br />
XCVR_RX_SEL_HALF_BW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–403<br />
XCVR_TX_COMMON_MODE_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–404<br />
XCVR_TX_PLL_RECONFIG_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–405<br />
XCVR_TX_PRE_EMP_1ST_POST_TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–406<br />
XCVR_TX_PRE_EMP_2ND_POST_TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–407<br />
XCVR_TX_PRE_EMP_2ND_POST_TAP_USER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–408<br />
XCVR_TX_PRE_EMP_INV_2ND_TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–409<br />
XCVR_TX_PRE_EMP_INV_PRE_TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–410<br />
XCVR_TX_PRE_EMP_PRE_TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–411<br />
XCVR_TX_PRE_EMP_PRE_TAP_USER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–412<br />
XCVR_TX_RX_DET_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–413<br />
XCVR_TX_RX_DET_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–414<br />
XCVR_TX_RX_DET_OUTPUT_SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–415<br />
XCVR_TX_SLEW_RATE_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–416<br />
XCVR_TX_VCM_CTRL_SRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–417<br />
XCVR_TX_VOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–418<br />
XCVR_TX_VOD_PRE_EMP_CTRL_SRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–419<br />
XCVR_VCCA_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–420<br />
XCVR_VCCR_VCCT_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–421<br />
XSTL_INPUT_ALLOW_SE_BUFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–422<br />
Chapter 7. Power Estimation Assignments<br />
POWER_AUTO_COMPUTE_TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1<br />
POWER_BOARD_TEMPERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3<br />
POWER_BOARD_THERMAL_MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4<br />
POWER_DEFAULT_INPUT_IO_TOGGLE_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5<br />
POWER_DEFAULT_TOGGLE_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7<br />
POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9<br />
POWER_HPS_ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10<br />
POWER_HPS_DYNAMIC_POWER_DUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12<br />
POWER_HPS_DYNAMIC_POWER_SINGLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14<br />
POWER_HPS_JUNCTION_TEMPERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–16<br />
POWER_HPS_PROC_FREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–18<br />
POWER_HPS_STATIC_POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–20<br />
POWER_HPS_TOTAL_POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–22<br />
POWER_HSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–24<br />
POWER_HSSI_LEFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–25<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
xiv Contents<br />
POWER_HSSI_RIGHT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–26<br />
POWER_HSSI_VCCHIP_LEFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–27<br />
POWER_HSSI_VCCHIP_RIGHT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–28<br />
POWER_INPUT_FILE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–29<br />
POWER_INPUT_FILE_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–31<br />
POWER_INPUT_SAF_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–33<br />
POWER_INPUT_VCD_FILE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–34<br />
POWER_OCS_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–35<br />
POWER_OJB_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–36<br />
POWER_OJC_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–37<br />
POWER_OSA_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–38<br />
POWER_OUTPUT_SAF_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–39<br />
POWER_PRESET_COOLING_SOLUTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–41<br />
POWER_READ_INPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–42<br />
POWER_REPORT_POWER_DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–44<br />
POWER_REPORT_SIGNAL_ACTIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–46<br />
POWER_SIGNAL_ACTIVITY_END_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–48<br />
POWER_SIGNAL_ACTIVITY_START_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–49<br />
POWER_STATIC_PROBABILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–50<br />
POWER_TJ_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–52<br />
POWER_TOGGLE_RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–54<br />
POWER_TOGGLE_RATE_PERCENTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–56<br />
POWER_USE_CUSTOM_COOLING_SOLUTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–58<br />
POWER_USE_DEVICE_CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–60<br />
POWER_USE_INPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–62<br />
POWER_USE_INPUT_FILES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–63<br />
POWER_USE_PVA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–65<br />
POWER_USE_TA_VALUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–67<br />
POWER_VCCAUX_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–69<br />
POWER_VCCA_GXB_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–70<br />
POWER_VCCA_L_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–71<br />
POWER_VCCA_R_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–72<br />
POWER_VCCCB_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–73<br />
POWER_VCCH_GXBL_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–74<br />
POWER_VCCH_GXBR_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–75<br />
POWER_VCCH_GXB_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–76<br />
POWER_VCCIO_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–77<br />
POWER_VCCL_GXB_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–78<br />
POWER_VCCPD_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–79<br />
POWER_VCCR_GXBL_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–80<br />
POWER_VCCR_GXBR_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–81<br />
POWER_VCCR_GXB_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–82<br />
POWER_VCCT_GXBL_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–83<br />
POWER_VCCT_GXBR_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–84<br />
POWER_VCCT_GXB_USER_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–85<br />
POWER_VCD_FILE_END_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–86<br />
POWER_VCD_FILE_START_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–88<br />
POWER_VCD_FILTER_GLITCHES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–90<br />
VCCAUX_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–92<br />
VCCA_GXBL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–93<br />
VCCA_GXBR_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–94<br />
VCCA_GXB_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–95<br />
VCCA_L_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–96<br />
VCCA_PLL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–97<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Contents xv<br />
VCCA_R_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–98<br />
VCCA_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–99<br />
VCCCB_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–100<br />
VCCD_PLL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–101<br />
VCCD_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–102<br />
VCCE_GXBL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–103<br />
VCCE_GXBR_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–104<br />
VCCE_GXB_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–105<br />
VCCE_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–106<br />
VCCEH_GXBL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–107<br />
VCCEH_GXBR_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–108<br />
VCCEH_GXB_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–109<br />
VCCHIP_L_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–110<br />
VCCHIP_R_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–111<br />
VCCHIP_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–112<br />
VCCHSSI_L_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–113<br />
VCCHSSI_R_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–114<br />
VCCH_GXBL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–115<br />
VCCH_GXBR_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–116<br />
VCCH_GXB_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–117<br />
VCCH_L_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–118<br />
VCCH_R_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–119<br />
VCCINT_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–120<br />
VCCIO_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–121<br />
VCCL_GXBL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–122<br />
VCCL_GXBR_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–123<br />
VCCL_GXB_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–124<br />
VCCL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–125<br />
VCCPD_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–126<br />
VCCPT_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–127<br />
VCCP_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–128<br />
VCCR_GXBL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–129<br />
VCCR_GXBR_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–130<br />
VCCR_GXB_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–131<br />
VCCR_L_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–132<br />
VCCR_R_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–133<br />
VCCR_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–134<br />
VCCT_GXBL_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–135<br />
VCCT_GXBR_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–136<br />
VCCT_GXB_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–137<br />
VCCT_L_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–138<br />
VCCT_R_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–139<br />
VCCT_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–140<br />
VCC_USER_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–141<br />
Chapter 8. EDA Netlist Writer Assignments<br />
EDA_BOARD_BOUNDARY_SCAN_OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1<br />
EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2<br />
EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3<br />
EDA_BOARD_DESIGN_SYMBOL_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–4<br />
EDA_BOARD_DESIGN_TIMING_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–5<br />
EDA_BOARD_DESIGN_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6<br />
EDA_DESIGN_EXTRA_ALTERA_SIM_LIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–7<br />
EDA_DESIGN_INSTANCE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–8<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
xvi Contents<br />
EDA_ENABLE_GLITCH_FILTERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–9<br />
EDA_ENABLE_IPUTF_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–10<br />
EDA_EXTRA_ELAB_OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–11<br />
EDA_FLATTEN_BUSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–12<br />
EDA_FORMAL_VERIFICATION_ALLOW_RETIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–13<br />
EDA_FORMAL_VERIFICATION_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–14<br />
EDA_FV_HIERARCHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–15<br />
EDA_GENERATE_FUNCTIONAL_NETLIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–16<br />
EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT . . . . . . . . . . . . . . . . . . . . . 8–17<br />
EDA_GENERATE_POWER_INPUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–18<br />
EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–19<br />
EDA_GENERATE_TIMING_CLOSURE_DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–20<br />
EDA_IBIS_MODEL_SELECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–21<br />
EDA_IBIS_MUTUAL_COUPLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–22<br />
EDA_IBIS_SPECIFICATION_VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–23<br />
EDA_IPFS_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–24<br />
EDA_LAUNCH_CMD_LINE_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–25<br />
EDA_MAINTAIN_DESIGN_HIERARCHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–26<br />
EDA_MAP_ILLEGAL_CHARACTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–27<br />
EDA_NATIVELINK_GENERATE_SCRIPT_ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–28<br />
EDA_NATIVELINK_PORTABLE_FILE_PATHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–29<br />
EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–30<br />
EDA_NATIVELINK_SIMULATION_TEST_BENCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–31<br />
EDA_NETLIST_WRITER_OUTPUT_DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–32<br />
EDA_RESYNTHESIS_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–33<br />
EDA_RTL_SIMULATION_RUN_SCRIPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–34<br />
EDA_RTL_SIM_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–35<br />
EDA_RTL_TEST_BENCH_FILE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–36<br />
EDA_RTL_TEST_BENCH_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–37<br />
EDA_RTL_TEST_BENCH_RUN_FOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–38<br />
EDA_SDC_FILE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–39<br />
EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED . . . . . . . . . . . . . 8–40<br />
EDA_SIMULATION_RUN_SCRIPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–41<br />
EDA_SIMULATION_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–42<br />
EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–43<br />
EDA_SIMULATION_VCD_OUTPUT_TCL_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–44<br />
EDA_SIMULATION_VCD_OUTPUT_TCL_FILE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–45<br />
EDA_TEST_BENCH_DESIGN_INSTANCE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–46<br />
EDA_TEST_BENCH_ENABLE_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–47<br />
EDA_TEST_BENCH_ENTITY_MODULE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–48<br />
EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–49<br />
EDA_TEST_BENCH_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–50<br />
EDA_TEST_BENCH_FILE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–51<br />
EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–52<br />
EDA_TEST_BENCH_MODULE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–53<br />
EDA_TEST_BENCH_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–54<br />
EDA_TEST_BENCH_RUN_FOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–55<br />
EDA_TEST_BENCH_RUN_SIM_FOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–56<br />
EDA_TIME_SCALE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–57<br />
EDA_TIMING_ANALYSIS_TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–58<br />
EDA_TRUNCATE_LONG_HIERARCHY_PATHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–59<br />
EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–60<br />
EDA_VHDL_ARCH_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–61<br />
EDA_WAIT_FOR_GUI_TOOL_COMPLETION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–62<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Contents xvii<br />
EDA_WRITER_DONT_WRITE_TOP_ENTITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–63<br />
EDA_WRITE_DEVICE_CONTROL_PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–64<br />
EDA_WRITE_NODES_FOR_POWER_ESTIMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–65<br />
Chapter 9. Assembler Assignments<br />
ARRIA<strong>II</strong>GX_RX_CDR_LOCKUP_FIX_OVERRIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1<br />
AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2<br />
AUTO_RESTART_CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–3<br />
CLOCK_SOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–5<br />
COMPRESSION_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–6<br />
CONFIGURATION_CLOCK_DIVISOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–7<br />
CONFIGURATION_CLOCK_FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8<br />
CYCLONE<strong>II</strong>I_CONFIGURATION_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–9<br />
CYCLONE<strong>II</strong>_M4K_COMPATIBILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10<br />
CYCLONE_CONFIGURATION_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–11<br />
DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–12<br />
ENABLE_AUTONOMOUS_PCIE_HIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–13<br />
ENABLE_OCT_DONE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–14<br />
EPROM_USE_CHECKSUM_AS_USERCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–15<br />
GENERATE_HEX_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–16<br />
GENERATE_RBF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–17<br />
GENERATE_TTF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–18<br />
HARDCOPY<strong>II</strong>_POWER_ON_EXTRA_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–19<br />
HEXOUT_FILE_COUNT_DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–20<br />
HEXOUT_FILE_START_ADDRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–21<br />
MAX7000S_JTAG_USER_CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–22<br />
MAX7000_JTAG_USER_CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–23<br />
MAX7000_USE_CHECKSUM_AS_USERCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–24<br />
ON_CHIP_BITSTREAM_DECOMPRESSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–25<br />
RELEASE_CLEARS_BEFORE_TRI_STATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–26<br />
RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–28<br />
SECURITY_BIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–29<br />
STRATIX<strong>II</strong>_CONFIGURATION_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–30<br />
STRATIX<strong>II</strong>_MRAM_COMPATIBILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–31<br />
STRATIX_CONFIGURATION_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–32<br />
STRATIX_CONFIG_DEVICE_JTAG_USER_CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–33<br />
STRATIX_JTAG_USER_CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–34<br />
USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT . . . . . . . . . . . . . . . . . . . . . 9–36<br />
USE_CHECKSUM_AS_USERCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–37<br />
USE_CONFIGURATION_DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–39<br />
Chapter 10. Design Assistant Assignments<br />
ACLK_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1<br />
ACLK_RULE_IMSZER_ADOMAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2<br />
ACLK_RULE_NO_SZER_ACLK_DOMAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–3<br />
ACLK_RULE_SZER_BTW_ACLK_DOMAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–4<br />
CLK_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–5<br />
CLK_RULE_CLKNET_CLKSPINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–6<br />
CLK_RULE_CLKNET_CLKSPINES_THRESHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–7<br />
CLK_RULE_COMB_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–8<br />
CLK_RULE_GATED_CLK_FANOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–9<br />
CLK_RULE_INPINS_CLKNET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–10<br />
CLK_RULE_INV_CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–11<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
xviii Contents<br />
CLK_RULE_MIX_EDGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–12<br />
DA_CUSTOM_RULE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–13<br />
DISABLE_DA_GX_RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–14<br />
DISABLE_DA_RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–15<br />
DRC_DEADLOCK_STATE_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–16<br />
DRC_DETAIL_MESSAGE_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–17<br />
DRC_FANOUT_EXCEEDING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–18<br />
DRC_GATED_CLOCK_FEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–19<br />
DRC_REPORT_FANOUT_EXCEEDING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–20<br />
DRC_REPORT_TOP_FANOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–21<br />
DRC_TOP_FANOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–22<br />
DRC_VIOLATION_MESSAGE_LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–23<br />
ENABLE_DA_RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–24<br />
ENABLE_DRC_SETTINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–25<br />
FSM_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–26<br />
FSM_RULE_DEADLOCK_STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–27<br />
FSM_RULE_NO_RESET_STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–28<br />
FSM_RULE_NO_SZER_ACLK_DOMAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–29<br />
FSM_RULE_UNREACHABLE_STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–30<br />
FSM_RULE_UNUSED_TRANSITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–31<br />
HARDCOPY_FLOW_AUTOMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–32<br />
HARDCOPY_NEW_PROJECT_PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–33<br />
HCPY_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–34<br />
NONSYNCHSTRUCT_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–35<br />
NONSYNCHSTRUCT_RULE_COMBLOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–36<br />
NONSYNCHSTRUCT_RULE_DELAY_CHAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–37<br />
NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–38<br />
NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–39<br />
NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–40<br />
NONSYNCHSTRUCT_RULE_REG_LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–41<br />
NONSYNCHSTRUCT_RULE_RIPPLE_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–42<br />
NONSYNCHSTRUCT_RULE_SRLATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–43<br />
RESET_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–44<br />
RESET_RULE_COMB_ASYNCH_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–45<br />
RESET_RULE_IMSYNCH_ASYNCH_DOMAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–46<br />
RESET_RULE_IMSYNCH_EXRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–47<br />
RESET_RULE_UNSYNCH_ASYNCH_DOMAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–48<br />
RESET_RULE_UNSYNCH_EXRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–49<br />
SIGNALRACE_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–50<br />
SIGNALRACE_RULE_CLK_PORT_RACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–51<br />
SIGNALRACE_RULE_RESET_RACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–52<br />
SIGNALRACE_RULE_SECOND_SIGNAL_RACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–53<br />
SIGNALRACE_RULE_TRISTATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–54<br />
TIMING_CAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–55<br />
Chapter 11. Programmer Assignments<br />
EXCALIBUR_HEX_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1<br />
GENERATE_CONFIG_HEXOUT_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2<br />
GENERATE_CONFIG_ISC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–3<br />
GENERATE_CONFIG_JAM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–4<br />
GENERATE_CONFIG_JBC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–5<br />
GENERATE_CONFIG_JBC_FILE_COMPRESSED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–6<br />
GENERATE_CONFIG_SVF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–7<br />
GENERATE_ISC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–8<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Contents xix<br />
GENERATE_JAM_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–9<br />
GENERATE_JBC_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–11<br />
GENERATE_JBC_FILE_COMPRESSED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–13<br />
GENERATE_SVF_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–15<br />
ISP_CLAMP_STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–17<br />
ISP_CLAMP_STATE_DEFAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–18<br />
MERGE_HEX_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–19<br />
Chapter 12. SignalTap <strong>II</strong> Assignments<br />
ENABLE_LOGIC_ANALYZER_INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–1<br />
ENABLE_SIGNALTAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–2<br />
STP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–3<br />
USE_LOGIC_ANALYZER_INTERFACE_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–4<br />
USE_SIGNALTAP_FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–5<br />
Chapter 13. LogicLock Region Assignments<br />
LL_AUTO_SIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–1<br />
LL_ENABLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–2<br />
LL_HEIGHT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–3<br />
LL_MEMBER_EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–4<br />
LL_MEMBER_OF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–5<br />
LL_MEMBER_OF_SECURITY_ROUTING_INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–6<br />
LL_ORIGIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–7<br />
LL_PARENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–8<br />
LL_PRIORITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–9<br />
LL_RESERVED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–10<br />
LL_ROOT_REGION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–11<br />
LL_STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–12<br />
LL_WIDTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–13<br />
Chapter 14. Migration Assignments<br />
MIGRATION_AUTO_PACKED_REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–1<br />
MIGRATION_AUTO_PORT_SWAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–2<br />
MIGRATION_RAM_INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–3<br />
Chapter 15. Netlist Viewer Assignments<br />
RTLV_GROUP_COMB_LOGIC_IN_CLOUD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–1<br />
RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–2<br />
RTLV_GROUP_RELATED_NODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–3<br />
RTLV_GROUP_RELATED_NODES_TMV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–4<br />
RTLV_REMOVE_FANOUT_FREE_REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–5<br />
RTLV_SIMPLIFIED_LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–6<br />
Chapter 16. Advanced I/O Timing Assignments<br />
BOARD_MODEL_EBD_FAR_END . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–1<br />
BOARD_MODEL_EBD_FILE_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–2<br />
BOARD_MODEL_EBD_SIGNAL_NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–3<br />
BOARD_MODEL_FAR_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–4<br />
BOARD_MODEL_FAR_DIFFERENTIAL_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–5<br />
BOARD_MODEL_FAR_PULLDOWN_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–6<br />
BOARD_MODEL_FAR_PULLUP_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–7<br />
BOARD_MODEL_FAR_SERIES_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–8<br />
BOARD_MODEL_NEAR_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–9<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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xx Contents<br />
BOARD_MODEL_NEAR_DIFFERENTIAL_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–10<br />
BOARD_MODEL_NEAR_PULLDOWN_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–11<br />
BOARD_MODEL_NEAR_PULLUP_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–12<br />
BOARD_MODEL_NEAR_SERIES_R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–13<br />
BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–14<br />
BOARD_MODEL_NEAR_TLINE_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–15<br />
BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–16<br />
BOARD_MODEL_TERMINATION_V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–17<br />
BOARD_MODEL_TLINE_C_PER_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–18<br />
BOARD_MODEL_TLINE_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–19<br />
BOARD_MODEL_TLINE_L_PER_LENGTH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–20<br />
ENABLE_ADVANCED_IO_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–21<br />
OUTPUT_IO_TIMING_ENDPOINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–22<br />
OUTPUT_IO_TIMING_FAR_END_VMEAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–23<br />
OUTPUT_IO_TIMING_NEAR_END_VMEAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–24<br />
PCB_LAYER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–25<br />
PCB_LAYERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–26<br />
PCB_LAYER_THICKNESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–27<br />
SYNCHRONOUS_GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–28<br />
Chapter 17. TimeQuest Timing Assignments<br />
ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–1<br />
DO_COMBINED_ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–2<br />
INPUT_TRANSITION_TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–4<br />
MAX_CORE_JUNCTION_TEMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–5<br />
MIN_CORE_JUNCTION_TEMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–6<br />
NOMINAL_CORE_SUPPLY_VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–7<br />
PACKAGE_SKEW_COMPENSATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–8<br />
PLL_EXTERNAL_FEEDBACK_BOARD_DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–9<br />
TIMEQUEST_DO_CCPP_REMOVAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–10<br />
TIMEQUEST_DO_REPORT_TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–12<br />
TIMEQUEST_MULTICORNER_ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–13<br />
TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–15<br />
TIMEQUEST_REPORT_SCRIPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–16<br />
TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . 17–17<br />
TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–18<br />
Additional Information<br />
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About–1<br />
How to Contact <strong>Altera</strong> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About–2<br />
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About–2<br />
Assignment Value Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About–3<br />
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About–5<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
AGGREGATE_REVISION<br />
Type<br />
© 2012 <strong>Altera</strong> Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos<br />
are trademarks of <strong>Altera</strong> Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as<br />
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. <strong>Altera</strong> warrants performance of its<br />
semiconductor products to current specifications in accordance with <strong>Altera</strong>'s standard warranty, but reserves the right to make changes to any products and<br />
services at any time without notice. <strong>Altera</strong> assumes no responsibility or liability arising out of the application or use of any information, product, or service<br />
described herein except as expressly agreed to in writing by <strong>Altera</strong>. <strong>Altera</strong> customers are advised to obtain the latest version of device specifications before relying<br />
on any published information and before placing orders for products or services.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong><br />
June 2012<br />
Specifies an AGGREGATE revision type.<br />
String<br />
Device Support<br />
1. Project-Wide Assignments<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name AGGREGATE_REVISION <br />
ISO<br />
9001:2008<br />
Registered<br />
Subscribe
1–2 Chapter 1: Project-Wide Assignments<br />
AHDL_FILE<br />
AHDL_FILE<br />
Type<br />
Associates an AHDL source file with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive..<br />
Syntax<br />
set_global_assignment -name AHDL_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–3<br />
AHDL_TEXT_DESIGN_OUTPUT_FILE<br />
AHDL_TEXT_DESIGN_OUTPUT_FILE<br />
Type<br />
Associates an AHDL Text Design Output <strong>File</strong> (.tdo) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name AHDL_TEXT_DESIGN_OUTPUT_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–4 Chapter 1: Project-Wide Assignments<br />
ASM_FILE<br />
ASM_FILE<br />
Type<br />
Associates an Assembly source file with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name ASM_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–5<br />
AUTO_EXPORT_VER_COMPATIBLE_DB<br />
AUTO_EXPORT_VER_COMPATIBLE_DB<br />
Type<br />
Automatically exports version-compatible database files when compilation<br />
completes.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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1–6 Chapter 1: Project-Wide Assignments<br />
BASE_REVISION<br />
BASE_REVISION<br />
Type<br />
Specifies a BASE revision type.<br />
String<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name BASE_REVISION <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–7<br />
BASE_REVISION_PROJECT_OUTPUT_DIRECTORY<br />
BASE_REVISION_PROJECT_OUTPUT_DIRECTORY<br />
Type<br />
Specifies the directory where project output files such as the Text-Format Report <strong>File</strong>s<br />
(.rpt) and Equation <strong>File</strong>s (.eqn) were saved for the base revision. By default, all project<br />
output files are saved in the project directory.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name BASE_REVISION_PROJECT_OUTPUT_DIRECTORY <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–8 Chapter 1: Project-Wide Assignments<br />
BDF_FILE<br />
BDF_FILE<br />
Type<br />
Associates a Block Design <strong>File</strong> (.bdf) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name BDF_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–9<br />
BINARY_FILE<br />
BINARY_FILE<br />
Type<br />
Associates a Binary <strong>File</strong> (.bin) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name BINARY_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–10 Chapter 1: Project-Wide Assignments<br />
BSF_FILE<br />
BSF_FILE<br />
Type<br />
Associates a Block Symbol <strong>File</strong> (.bsf) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name BSF_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–11<br />
CDF_FILE<br />
CDF_FILE<br />
Type<br />
Associates a Chain Description <strong>File</strong> (.cdf) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name CDF_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–12 Chapter 1: Project-Wide Assignments<br />
COMMAND_MACRO_FILE<br />
COMMAND_MACRO_FILE<br />
Type<br />
Associates a script file or ModelSim Macro <strong>File</strong> with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name COMMAND_MACRO_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–13<br />
CPP_FILE<br />
CPP_FILE<br />
Type<br />
Associates a C++ source file with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name CPP_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–14 Chapter 1: Project-Wide Assignments<br />
CPP_INCLUDE_FILE<br />
CPP_INCLUDE_FILE<br />
Type<br />
Associates a C++ include file with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name CPP_INCLUDE_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–15<br />
CUSP_FILE<br />
CUSP_FILE<br />
Type<br />
Associates a C++ source file with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name CUSP_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–16 Chapter 1: Project-Wide Assignments<br />
CVP_REVISION<br />
CVP_REVISION<br />
Type<br />
Specifies a CVP revision type.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix V<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name CVP_REVISION <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–17<br />
C_FILE<br />
C_FILE<br />
Type<br />
Associates a C source file with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name C_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–18 Chapter 1: Project-Wide Assignments<br />
DEPENDENCY_FILE<br />
DEPENDENCY_FILE<br />
Type<br />
Associates a Dependency file with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name DEPENDENCY_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–19<br />
DSPBUILDER_FILE<br />
DSPBUILDER_FILE<br />
Type<br />
Associates a DSPBuilder source file with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name DSPBUILDER_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–20 Chapter 1: Project-Wide Assignments<br />
EDIF_FILE<br />
EDIF_FILE<br />
Type<br />
Associates an EDIF source file with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDIF_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–21<br />
ELF_FILE<br />
ELF_FILE<br />
Type<br />
Associates an ELF file with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name ELF_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–22 Chapter 1: Project-Wide Assignments<br />
ENABLE_COMPACT_REPORT_TABLE<br />
ENABLE_COMPACT_REPORT_TABLE<br />
Type<br />
Allows you to view the report table in compact format.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–23<br />
ENABLE_REDUCED_MEMORY_MODE<br />
ENABLE_REDUCED_MEMORY_MODE<br />
Type<br />
Determines whether to enable the Compiler to run in reduced memory mode. This<br />
assignment controls a small number of memory-intensive fitter optimizations.<br />
Therefore, enabling the reduced memory mode may slightly impact the performance<br />
of your design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–24 Chapter 1: Project-Wide Assignments<br />
EQUATION_FILE<br />
EQUATION_FILE<br />
Type<br />
Associates an Equation <strong>File</strong> with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EQUATION_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–25<br />
FLOW_DISABLE_ASSEMBLER<br />
FLOW_DISABLE_ASSEMBLER<br />
Type<br />
Allows you to turn on or turn off the Assembler during compilation.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name FLOW_DISABLE_ASSEMBLER <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–26 Chapter 1: Project-Wide Assignments<br />
FLOW_ENABLE_HC_COMPARE<br />
FLOW_ENABLE_HC_COMPARE<br />
Type<br />
Enables HardCopy Compare during compilation.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
Syntax<br />
set_global_assignment -name FLOW_ENABLE_HC_COMPARE <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–27<br />
FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS<br />
FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS<br />
Type<br />
Allows you to run I/O assignment analysis before compilation.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–28 Chapter 1: Project-Wide Assignments<br />
FLOW_ENABLE_PARALLEL_MODULES<br />
FLOW_ENABLE_PARALLEL_MODULES<br />
Type<br />
Allows you to run Assembler and TimeQuest Timing Analyzer in parallel during<br />
compilation.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES <br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–29<br />
FLOW_ENABLE_POWER_ANALYZER<br />
FLOW_ENABLE_POWER_ANALYZER<br />
Type<br />
Allows you to turn on or turn off the Power Analyzer during compilation.<br />
Boolean<br />
Device Support<br />
You can use this setting in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–30 Chapter 1: Project-Wide Assignments<br />
FLOW_ENABLE_RTL_VIEWER<br />
FLOW_ENABLE_RTL_VIEWER<br />
Type<br />
Allows the RTL Viewer to process the schematic during design compilation. Turning<br />
on this option also allows you to open the RTL Viewer after the Analysis & Synthesis<br />
portion of design compilation completes, rather than waiting for the full compilation<br />
to complete.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–31<br />
FLOW_HARDCOPY_DESIGN_READINESS_CHECK<br />
FLOW_HARDCOPY_DESIGN_READINESS_CHECK<br />
Type<br />
Allows you to turn on or turn off the HardCopy Design Readiness Check during<br />
compilation.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GZ<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK <br />
Default Value<br />
On<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–32 Chapter 1: Project-Wide Assignments<br />
GDF_FILE<br />
GDF_FILE<br />
Type<br />
Associates a GDF source file with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name GDF_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–33<br />
HC_OUTPUT_DIR<br />
HC_OUTPUT_DIR<br />
Type<br />
Specifies the directory to which HardCopy handoff files should be generated.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name HC_OUTPUT_DIR <br />
Default Value<br />
hc_output<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–34 Chapter 1: Project-Wide Assignments<br />
HEX_FILE<br />
HEX_FILE<br />
Type<br />
Associates a Hexadecimal (Intel-Format) <strong>File</strong> (.hex) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name HEX_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–35<br />
HEX_OUTPUT_FILE<br />
HEX_OUTPUT_FILE<br />
Type<br />
Associates a Hexadecimal (Intel-Format) Output <strong>File</strong> (.hexout) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name HEX_OUTPUT_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–36 Chapter 1: Project-Wide Assignments<br />
HTML_FILE<br />
HTML_FILE<br />
Type<br />
Associates an HTML <strong>File</strong> (.html) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name HTML_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–37<br />
HTML_REPORT_FILE<br />
HTML_REPORT_FILE<br />
Type<br />
Associates an HTML-Format Report <strong>File</strong> (.htm) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name HTML_REPORT_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–38 Chapter 1: Project-Wide Assignments<br />
INCLUDE_FILE<br />
INCLUDE_FILE<br />
Type<br />
Associates an Include <strong>File</strong> (.inc) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name INCLUDE_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–39<br />
IPA_FILE<br />
IPA_FILE<br />
Type<br />
Associates an IP Advisor file with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name IPA_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–40 Chapter 1: Project-Wide Assignments<br />
IP_TOOL_ENV<br />
IP_TOOL_ENV<br />
Type<br />
Specifies the tool which generated the IP core.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name IP_TOOL_ENV <br />
set_global_assignment -name IP_TOOL_ENV -entity <br />
set_instance_assignment -name IP_TOOL_ENV -to -entity <br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–41<br />
IP_TOOL_NAME<br />
IP_TOOL_NAME<br />
Type<br />
Specifies the IP core name.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name IP_TOOL_NAME <br />
set_global_assignment -name IP_TOOL_NAME -entity <br />
set_instance_assignment -name IP_TOOL_NAME -to -entity <br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–42 Chapter 1: Project-Wide Assignments<br />
IP_TOOL_VERSION<br />
IP_TOOL_VERSION<br />
Type<br />
Specifies the IP core version.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name IP_TOOL_VERSION <br />
set_global_assignment -name IP_TOOL_VERSION -entity <br />
set_instance_assignment -name IP_TOOL_VERSION -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–43<br />
ISC_FILE<br />
ISC_FILE<br />
Type<br />
IEEE 1532 file.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name ISC_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–44 Chapter 1: Project-Wide Assignments<br />
JAM_FILE<br />
JAM_FILE<br />
Type<br />
Associates a Jam Standard Test and Programming Language (STAPL) Format <strong>File</strong><br />
(.jam) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name JAM_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–45<br />
JBC_FILE<br />
JBC_FILE<br />
Type<br />
Associates a JAM Byte Code <strong>File</strong> (.jbc) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name JBC_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–46 Chapter 1: Project-Wide Assignments<br />
LICENSE_FILE<br />
LICENSE_FILE<br />
Type<br />
Associates a License <strong>File</strong> with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name LICENSE_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–47<br />
LMF_FILE<br />
LMF_FILE<br />
Type<br />
Associates a Library Mapping <strong>File</strong> (.lmf) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name LMF_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–48 Chapter 1: Project-Wide Assignments<br />
LOGIC_ANALYZER_INTERFACE_FILE<br />
LOGIC_ANALYZER_INTERFACE_FILE<br />
Type<br />
Associates a Logic Analyzer Interface <strong>File</strong> (.lai) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name LOGIC_ANALYZER_INTERFACE_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–49<br />
MAP_FILE<br />
MAP_FILE<br />
Type<br />
Contains the byte addresses of pages and HEX data stored in the memory of an EPC4,<br />
EPC8, or EPC16 configuration device.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name MAP_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–50 Chapter 1: Project-Wide Assignments<br />
MASK_REVISION<br />
MASK_REVISION<br />
Type<br />
Specifies a MASK revision type.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix V<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name MASK_REVISION <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–51<br />
MESSAGE_DISABLE<br />
MESSAGE_DISABLE<br />
Type<br />
Tells the Compiler to suppress the specified user message(s).<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_global_assignment -name MESSAGE_DISABLE <br />
set_global_assignment -name MESSAGE_DISABLE -entity <br />
set_instance_assignment -name MESSAGE_DISABLE -to -entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–52 Chapter 1: Project-Wide Assignments<br />
MESSAGE_ENABLE<br />
MESSAGE_ENABLE<br />
Type<br />
Tells the Compiler to enable the specified user message(s).<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_global_assignment -name MESSAGE_ENABLE <br />
set_global_assignment -name MESSAGE_ENABLE -entity <br />
set_instance_assignment -name MESSAGE_ENABLE -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–53<br />
MESSAGE_SUPPRESSION_RULE_FILE<br />
MESSAGE_SUPPRESSION_RULE_FILE<br />
Type<br />
Associates a message suppression rule file with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
The name of this file is based on the project revision name.<br />
Syntax<br />
set_global_assignment -name MESSAGE_SUPPRESSION_RULE_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–54 Chapter 1: Project-Wide Assignments<br />
MIF_FILE<br />
MIF_FILE<br />
Type<br />
Associates a Memory Initialization <strong>File</strong> (.mif) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name MIF_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–55<br />
MIGRATION_DIFFERENT_SOURCE_FILE<br />
MIGRATION_DIFFERENT_SOURCE_FILE<br />
Type<br />
Specifies a HDL source file that is different in the companion revision. This is used to<br />
allow setting differences between the current and companion revision. The<br />
companion revision has a different source file than the one specified here.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name MIGRATION_DIFFERENT_SOURCE_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–56 Chapter 1: Project-Wide Assignments<br />
MISC_FILE<br />
MISC_FILE<br />
Type<br />
Associates a file with this project. <strong>File</strong>s assigned to this assignment is archived by the<br />
Project Archive command if the ‘Project source and settings files’ file subset is<br />
selected.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name MISC_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–57<br />
NUM_PARALLEL_PROCESSORS<br />
NUM_PARALLEL_PROCESSORS<br />
Type<br />
Specifies the maximum number of processors allocated for parallel compilation on a<br />
single machine. For parallel compilation, you can use all available processors on your<br />
machine, or specify the number of processors you want to use. For example, if you<br />
have a quad-core processor machine and want to leave one processor free for other<br />
tasks, specify 3 as the setting of this option. A setting of 1 disables parallel<br />
compilation.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–58 Chapter 1: Project-Wide Assignments<br />
NUM_PARALLEL_PROCESSORS<br />
Syntax<br />
set_global_assignment -name NUM_PARALLEL_PROCESSORS <br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
MAX_PROCESSORS_USED_FOR_MULTITHREADING<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–59<br />
OBJECT_FILE<br />
OBJECT_FILE<br />
Type<br />
Associates an Object <strong>File</strong> with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name OBJECT_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–60 Chapter 1: Project-Wide Assignments<br />
OCP_FILE<br />
OCP_FILE<br />
Type<br />
Specifies the OpenCore Plus <strong>File</strong> (.ocp) generated by the MegaWizard Plug-In<br />
Manager. The <strong>Quartus</strong> <strong>II</strong> software uses this file to compile and generate an SRAM<br />
Object <strong>File</strong> (.sof) of the core without a license.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name OCP_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–61<br />
PARTIAL_SRAM_OBJECT_FILE<br />
PARTIAL_SRAM_OBJECT_FILE<br />
Type<br />
Associates a Partial SRAM Object <strong>File</strong> with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name PARTIAL_SRAM_OBJECT_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–62 Chapter 1: Project-Wide Assignments<br />
PERSONA_FILE<br />
PERSONA_FILE<br />
Type<br />
Associates a <strong>Quartus</strong> <strong>II</strong> Persona with this project as a source file.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name PERSONA_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–63<br />
PIN_FILE<br />
PIN_FILE<br />
Type<br />
Associates a Pin-Out <strong>File</strong> (.pin) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name PIN_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–64 Chapter 1: Project-Wide Assignments<br />
POWER_INPUT_FILE<br />
POWER_INPUT_FILE<br />
Type<br />
Associates a Power Input <strong>File</strong> (.pwf) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name POWER_INPUT_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–65<br />
PPF_FILE<br />
PPF_FILE<br />
Type<br />
Specifies the name of the MegaWizard-generated Pin Planner <strong>File</strong> (.ppf) containing<br />
core-specific pin assignments. This file is loaded by the Pin Planner.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name PPF_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–66 Chapter 1: Project-Wide Assignments<br />
PROGRAMMER_OBJECT_FILE<br />
PROGRAMMER_OBJECT_FILE<br />
Type<br />
Associates a Programmer Object <strong>File</strong> (.pof) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name PROGRAMMER_OBJECT_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–67<br />
PROJECT_OUTPUT_DIRECTORY<br />
PROJECT_OUTPUT_DIRECTORY<br />
Type<br />
Specifies the directory in which to save all project output files such as the Text-Format<br />
Report <strong>File</strong>s (.rpt) and Equation <strong>File</strong>s (.eqn). By default, all project output files are<br />
saved in the project directory.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–68 Chapter 1: Project-Wide Assignments<br />
PROJECT_SHOW_ENTITY_NAME<br />
PROJECT_SHOW_ENTITY_NAME<br />
Type<br />
Determines whether to display the entity name for node names.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME <br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–69<br />
PROJECT_USE_SIMPLIFIED_NAMES<br />
PROJECT_USE_SIMPLIFIED_NAMES<br />
Type<br />
Determines whether to use the simplified naming scheme.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–70 Chapter 1: Project-Wide Assignments<br />
QARLOG_FILE<br />
QARLOG_FILE<br />
Type<br />
Associates a <strong>Quartus</strong> <strong>II</strong> Archive Log <strong>File</strong> (.qarlog) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name QARLOG_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–71<br />
QAR_FILE<br />
QAR_FILE<br />
Type<br />
Associates a <strong>Quartus</strong> <strong>II</strong> Archive <strong>File</strong> (.qar) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name QAR_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–72 Chapter 1: Project-Wide Assignments<br />
QIP_FILE<br />
QIP_FILE<br />
Type<br />
Associates a <strong>Quartus</strong> <strong>II</strong> IP <strong>File</strong> (.qip) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name QIP_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–73<br />
QSYS_FILE<br />
QSYS_FILE<br />
Type<br />
Associates a Qsys System <strong>File</strong> (.qsys) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name QSYS_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–74 Chapter 1: Project-Wide Assignments<br />
QUARTUS_PTF_FILE<br />
QUARTUS_PTF_FILE<br />
Type<br />
Associates a <strong>Quartus</strong> <strong>II</strong> Peripheral Template <strong>File</strong> (.ptf) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name QUARTUS_PTF_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–75<br />
QUARTUS_SBD_FILE<br />
QUARTUS_SBD_FILE<br />
Type<br />
Associates a <strong>Quartus</strong> <strong>II</strong> System Build Descriptor <strong>File</strong> (.sbd) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name QUARTUS_SBD_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–76 Chapter 1: Project-Wide Assignments<br />
QUARTUS_STANDARD_DELAY_FILE<br />
QUARTUS_STANDARD_DELAY_FILE<br />
Type<br />
Associates a <strong>Quartus</strong> <strong>II</strong> Standard Delay <strong>File</strong> (.sdf) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name QUARTUS_STANDARD_DELAY_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–77<br />
QVAR_FILE<br />
QVAR_FILE<br />
Type<br />
Associates a <strong>Quartus</strong> <strong>II</strong> IP Variation <strong>File</strong> (.qvar) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
Syntax<br />
You can use this setting in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
set_global_assignment -name QVAR_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–78 Chapter 1: Project-Wide Assignments<br />
QXP_FILE<br />
QXP_FILE<br />
Type<br />
Associates a <strong>Quartus</strong> <strong>II</strong> Exported Partition <strong>File</strong> (.qxp) source file with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name QXP_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–79<br />
RAW_BINARY_FILE<br />
RAW_BINARY_FILE<br />
Type<br />
Associates a Raw Binary <strong>File</strong> (.rbf) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name RAW_BINARY_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–80 Chapter 1: Project-Wide Assignments<br />
READ_OR_WRITE_IN_BYTE_ADDRESS<br />
READ_OR_WRITE_IN_BYTE_ADDRESS<br />
Type<br />
Determines whether to read or write Hexadecimal <strong>File</strong>s (.hex) in byte addressable<br />
mode for this project.<br />
Enumeration<br />
■ Off<br />
■ On<br />
Device Support<br />
■ Use global settings<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS <br />
Default Value<br />
Use global settings<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–81<br />
RECONFIGURABLE_REVISION<br />
RECONFIGURABLE_REVISION<br />
Type<br />
Specifies a RECONFIGURABLE revision type.<br />
String<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name RECONFIGURABLE_REVISION <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–82 Chapter 1: Project-Wide Assignments<br />
REVISION_TYPE<br />
REVISION_TYPE<br />
Type<br />
Describes the type of revision. The possible revision types are BASE,<br />
RECONFIGURABLE, AGGREGATE, CVP, and MASK.<br />
The default revision type is BASE.<br />
Enumeration<br />
■ Aggregate<br />
■ Base<br />
■ CVP<br />
■ Mask<br />
Device Support<br />
■ Reconfigurable<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name REVISION_TYPE <br />
Default Value<br />
Base<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–83<br />
RUN_FULL_COMPILE_ON_DEVICE_CHANGE<br />
RUN_FULL_COMPILE_ON_DEVICE_CHANGE<br />
Type<br />
Runs Full Compilation when the device changes.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE <br />
Default Value<br />
On<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–84 Chapter 1: Project-Wide Assignments<br />
SAVE_MIGRATION_INFO_DURING_COMPILATION<br />
SAVE_MIGRATION_INFO_DURING_COMPILATION<br />
Type<br />
Saves the migration information during compilation.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
Syntax<br />
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION <br />
Default Value<br />
Off<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
HARDCOPY<strong>II</strong>_SAVE_MIGRATION_INFO_DURING_COMPILATION<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–85<br />
SBI_FILE<br />
SBI_FILE<br />
Type<br />
Associates a Slave Binary Interface <strong>File</strong> (.sbi) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name SBI_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–86 Chapter 1: Project-Wide Assignments<br />
SDC_FILE<br />
SDC_FILE<br />
Type<br />
Associates a Synopsys Design Constraints <strong>File</strong> (.sdc) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name SDC_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–87<br />
SDF_OUTPUT_FILE<br />
SDF_OUTPUT_FILE<br />
Type<br />
Associates a Standard Delay Format Output <strong>File</strong> (.sdo) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name SDF_OUTPUT_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–88 Chapter 1: Project-Wide Assignments<br />
SERIAL_BITSTREAM_FILE<br />
SERIAL_BITSTREAM_FILE<br />
Type<br />
Associates a Serial Bitstream <strong>File</strong> (.sbf) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name SERIAL_BITSTREAM_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–89<br />
SIGNALTAP_FILE<br />
SIGNALTAP_FILE<br />
Type<br />
Associates a SignalTap <strong>II</strong> <strong>File</strong> (.stp) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name SIGNALTAP_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–90 Chapter 1: Project-Wide Assignments<br />
SIP_FILE<br />
SIP_FILE<br />
Type<br />
Associates a simulation IP with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name SIP_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–91<br />
SMART_RECOMPILE<br />
SMART_RECOMPILE<br />
Type<br />
Specifies whether to use the Smart Compilation option. Turning this option on helps<br />
future compilations run faster.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name SMART_RECOMPILE <br />
Default Value<br />
Off<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
SPEED_DISK_USAGE_TRADEOFF<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–92 Chapter 1: Project-Wide Assignments<br />
SMF_FILE<br />
SMF_FILE<br />
Type<br />
Associates a State Machine <strong>File</strong> (.smf) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name SMF_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–93<br />
SOFTWARE_LIBRARY_FILE<br />
SOFTWARE_LIBRARY_FILE<br />
Type<br />
Associates a software library file with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name SOFTWARE_LIBRARY_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–94 Chapter 1: Project-Wide Assignments<br />
SOPC_FILE<br />
SOPC_FILE<br />
Type<br />
Associates a SOPC Builder Design <strong>File</strong> (.sopc) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name SOPC_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–95<br />
SOURCE_TCL_SCRIPT_FILE<br />
SOURCE_TCL_SCRIPT_FILE<br />
Type<br />
Runs Tcl Script <strong>File</strong> (.tcl). This assignment has the same effect as ‘source ’.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name SOURCE_TCL_SCRIPT_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–96 Chapter 1: Project-Wide Assignments<br />
SPD_FILE<br />
SPD_FILE<br />
Type<br />
Associates a Simulation Package Descriptor <strong>File</strong> (.spd) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name SPD_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–97<br />
SRAM_OBJECT_FILE<br />
SRAM_OBJECT_FILE<br />
Type<br />
Associates an SRAM Object <strong>File</strong> (.sof) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name SRAM_OBJECT_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–98 Chapter 1: Project-Wide Assignments<br />
SRECORDS_FILE<br />
SRECORDS_FILE<br />
Type<br />
Associates a Motorola S-Record <strong>File</strong> (.srec) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name SRECORDS_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–99<br />
SVF_FILE<br />
SVF_FILE<br />
Type<br />
Associates a Serial Vector Format <strong>File</strong> (.svf) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name SVF_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–100 Chapter 1: Project-Wide Assignments<br />
SYM_FILE<br />
SYM_FILE<br />
Type<br />
Associates a Symbol <strong>File</strong> (.sym) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name SYM_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–101<br />
SYNTHESIS_ONLY_QIP<br />
SYNTHESIS_ONLY_QIP<br />
Type<br />
Determines whether a <strong>Quartus</strong> <strong>II</strong> IP <strong>File</strong> (.qip) is not for simulation.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name SYNTHESIS_ONLY_QIP <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–102 Chapter 1: Project-Wide Assignments<br />
SYSTEMVERILOG_FILE<br />
SYSTEMVERILOG_FILE<br />
Type<br />
Associates a System Verilog Design <strong>File</strong> (.sv) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name SYSTEMVERILOG_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–103<br />
TCL_SCRIPT_FILE<br />
TCL_SCRIPT_FILE<br />
Type<br />
Associates a Tcl Script <strong>File</strong> (.tcl) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name TCL_SCRIPT_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–104 Chapter 1: Project-Wide Assignments<br />
TEMPLATE_FILE<br />
TEMPLATE_FILE<br />
Type<br />
Associates a Template <strong>File</strong> with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name TEMPLATE_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–105<br />
TEXT_FILE<br />
TEXT_FILE<br />
Type<br />
Associates a Text <strong>File</strong> (.txt) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name TEXT_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–106 Chapter 1: Project-Wide Assignments<br />
TEXT_FORMAT_REPORT_FILE<br />
TEXT_FORMAT_REPORT_FILE<br />
Type<br />
Associates a Text-Format Report <strong>File</strong> (.rpt) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name TEXT_FORMAT_REPORT_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–107<br />
TIMING_ANALYSIS_OUTPUT_FILE<br />
TIMING_ANALYSIS_OUTPUT_FILE<br />
Type<br />
Associates a Timing Analysis Output <strong>File</strong> (.tao) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name TIMING_ANALYSIS_OUTPUT_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–108 Chapter 1: Project-Wide Assignments<br />
VCD_FILE<br />
VCD_FILE<br />
Type<br />
Associates a Verilog Value Change Dump <strong>File</strong> (.vcd) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name VCD_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–109<br />
VECTOR_TABLE_OUTPUT_FILE<br />
VECTOR_TABLE_OUTPUT_FILE<br />
Type<br />
Associates a Vector Table Output <strong>File</strong> (.tbl) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name VECTOR_TABLE_OUTPUT_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–110 Chapter 1: Project-Wide Assignments<br />
VECTOR_TEXT_FILE<br />
VECTOR_TEXT_FILE<br />
Type<br />
Associates a Vector Text <strong>File</strong> (.vec) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name VECTOR_TEXT_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–111<br />
VECTOR_WAVEFORM_FILE<br />
VECTOR_WAVEFORM_FILE<br />
Type<br />
Associates a Vector Waveform <strong>File</strong> (.vwf) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name VECTOR_WAVEFORM_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–112 Chapter 1: Project-Wide Assignments<br />
VERILOG_FILE<br />
VERILOG_FILE<br />
Type<br />
Associates a Verilog HDL source file (.v) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name VERILOG_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–113<br />
VERILOG_INCLUDE_FILE<br />
VERILOG_INCLUDE_FILE<br />
Type<br />
Associates a Verilog Include <strong>File</strong> (.v) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name VERILOG_INCLUDE_FILE <br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
VERILOG_VH_FILE<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–114 Chapter 1: Project-Wide Assignments<br />
VERILOG_OUTPUT_FILE<br />
VERILOG_OUTPUT_FILE<br />
Type<br />
Associates a Verilog Output <strong>File</strong> (.vo) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name VERILOG_OUTPUT_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–115<br />
VERILOG_TEST_BENCH_FILE<br />
VERILOG_TEST_BENCH_FILE<br />
Type<br />
Associates a Verilog HDL Test Bench <strong>File</strong> (.vt) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name VERILOG_TEST_BENCH_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–116 Chapter 1: Project-Wide Assignments<br />
VER_COMPATIBLE_DB_DIR<br />
VER_COMPATIBLE_DB_DIR<br />
Type<br />
Specifies the directory to which version-compatible database files should be saved.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name VER_COMPATIBLE_DB_DIR <br />
Default Value<br />
export_db<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–117<br />
VHDL_FILE<br />
VHDL_FILE<br />
Type<br />
Associates a VHDL Source <strong>File</strong> (.vhd) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name VHDL_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–118 Chapter 1: Project-Wide Assignments<br />
VHDL_OUTPUT_FILE<br />
VHDL_OUTPUT_FILE<br />
Type<br />
Associates a VHDL Output <strong>File</strong> (.vho) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name VHDL_OUTPUT_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–119<br />
VHDL_TEST_BENCH_FILE<br />
VHDL_TEST_BENCH_FILE<br />
Type<br />
Associates a VHDL Test Bench <strong>File</strong> (.vht) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name VHDL_TEST_BENCH_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–120 Chapter 1: Project-Wide Assignments<br />
VQM_FILE<br />
VQM_FILE<br />
Type<br />
Associates a structural Verilog HDL source file (.v) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name VQM_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 1: Project-Wide Assignments 1–121<br />
ZIP_VECTOR_WAVEFORM_FILE<br />
ZIP_VECTOR_WAVEFORM_FILE<br />
Type<br />
Associates a Compressed Vector Waveform <strong>File</strong> (.cvwf) with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name ZIP_VECTOR_WAVEFORM_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
1–122 Chapter 1: Project-Wide Assignments<br />
ZIP_VECTOR_WAVEFORM_FILE<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
FAST_INPUT_REGISTER<br />
Type<br />
© 2012 <strong>Altera</strong> Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos<br />
are trademarks of <strong>Altera</strong> Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as<br />
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. <strong>Altera</strong> warrants performance of its<br />
semiconductor products to current specifications in accordance with <strong>Altera</strong>'s standard warranty, but reserves the right to make changes to any products and<br />
services at any time without notice. <strong>Altera</strong> assumes no responsibility or liability arising out of the application or use of any information, product, or service<br />
described herein except as expressly agreed to in writing by <strong>Altera</strong>. <strong>Altera</strong> customers are advised to obtain the latest version of device specifications before relying<br />
on any published information and before placing orders for products or services.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong><br />
June 2012<br />
2. Pin & Locations Assignments<br />
Implements an input register in a cell that has a fast, direct connection from an I/O<br />
pin. If such a fast, direct connection from the I/O pin is not available on the I/O cell<br />
hardware, this option instructs the Fitter to lock the input register in the logic array<br />
black (LAB) adjacent to the I/O cell feeding it. Turning on the Fast Input Register<br />
option can help maximize I/O timing performance, for example, by permitting fast<br />
setup times. Turning this option off for a particular signal prevents the Fitter from<br />
implementing the signal automatically in an I/O cell or locking down the input<br />
register in the LAB adjacent to the I/O cell. This option is ignored if it is applied to<br />
anything other than a register or an input or bidirectional pin that feeds a register.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
ISO<br />
9001:2008<br />
Registered<br />
Subscribe
2–2 Chapter 2: Pin & Locations Assignments<br />
FAST_INPUT_REGISTER<br />
■ MAX V<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name FAST_INPUT_REGISTER -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 2: Pin & Locations Assignments 2–3<br />
FAST_OCT_REGISTER<br />
FAST_OCT_REGISTER<br />
Type<br />
Implements an on-chip termination (OCT) register in a cell that has a fast, direct<br />
connection to an I/O pin. Turning on the Fast OCT Register option can help<br />
maximize I/O timing performance, for example, by permitting fast clock-to-output<br />
times. Turning this option off for a particular signal prevents the Fitter from<br />
implementing the signal automatically in an I/O cell. This option is ignored if it is<br />
applied to anything other than a register or an output or bidirectional pin fed by a<br />
register.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name FAST_OCT_REGISTER -to -entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
2–4 Chapter 2: Pin & Locations Assignments<br />
FAST_OUTPUT_ENABLE_REGISTER<br />
FAST_OUTPUT_ENABLE_REGISTER<br />
Type<br />
Implements an output enable register in a cell that has a fast, direct connection to an<br />
I/O pin. If such a fast, direct connection to the I/O pin is not available in the I/O cell<br />
hardware, this option instructs the Fitter to lock the output enable register in the LAB<br />
adjacent to the I/O cell it is feeding.Turning on the Fast Output Enable Register<br />
option can help maximize I/O timing performance, for example, by permitting fast<br />
clock-to-output times. Turning this option off for a particular signal prevents the Fitter<br />
from implementing the signal automatically in an I/O cell or locking down the output<br />
enable register in the LAB adjacent to the I/O cell. This option is ignored if it is<br />
applied to anything other than a register or an output or bidirectional pin fed by a<br />
register.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 2: Pin & Locations Assignments 2–5<br />
FAST_OUTPUT_ENABLE_REGISTER<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
2–6 Chapter 2: Pin & Locations Assignments<br />
FAST_OUTPUT_REGISTER<br />
FAST_OUTPUT_REGISTER<br />
Type<br />
Implements an output register in a cell that has a fast, direct connection to an I/O pin.<br />
If such a fast, direct connection to the I/O pin is not available in the I/O cell<br />
hardware, this option instructs the Fitter to lock the output register in the LAB<br />
adjacent to the I/O cell it is feeding.Turning on the Fast Output Register option can<br />
help maximize I/O timing performance, for example, by permitting fast clock-tooutput<br />
times. Turning this option off for a particular signal prevents the Fitter from<br />
implementing the signal automatically in an I/O cell or locking down the output<br />
register in the LAB adjacent to the I/O cell. This option is ignored if it is applied to<br />
anything other than a register or an output or bidirectional pin fed by a register.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 2: Pin & Locations Assignments 2–7<br />
FAST_OUTPUT_REGISTER<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name FAST_OUTPUT_REGISTER -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
2–8 Chapter 2: Pin & Locations Assignments<br />
IP_DEBUG_VISIBLE<br />
IP_DEBUG_VISIBLE<br />
Type<br />
When assigned to an Encrypted IP node, this option directs the <strong>Quartus</strong> <strong>II</strong> software to<br />
display the node in the Node Finder.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_instance_assignment -name IP_DEBUG_VISIBLE -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 2: Pin & Locations Assignments 2–9<br />
LL_IGNORE_IO_PIN_SECURITY_CONSTRAINT<br />
LL_IGNORE_IO_PIN_SECURITY_CONSTRAINT<br />
Type<br />
Allows the specified I/O pin to ignore security constraints.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
The value of this assignment must be a node name.<br />
Syntax<br />
set_instance_assignment -name LL_IGNORE_IO_PIN_SECURITY_CONSTRAINT -to<br />
-entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
2–10 Chapter 2: Pin & Locations Assignments<br />
LOCATION<br />
LOCATION<br />
Type<br />
Assigns a location on the device for the current node(s) and/or pin(s).<br />
Location<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_location_assignment -to <br />
Example<br />
set_location_assignment -to dst LOC<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 2: Pin & Locations Assignments 2–11<br />
MAX7K_CLIQUE_TYPE<br />
MAX7K_CLIQUE_TYPE<br />
Type<br />
Specifies the type of a clique.<br />
Enumeration<br />
■ LAB<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
Syntax<br />
set_global_assignment -name MAX7K_CLIQUE_TYPE -entity -<br />
section_id <br />
Default Value<br />
LAB, requires section identifier and entity name<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
2–12 Chapter 2: Pin & Locations Assignments<br />
MEMBER_OF<br />
MEMBER_OF<br />
Type<br />
Assigns one or more currently selected nodes and/or entities to a clique, which is a<br />
group of functions that the Compiler attempts to place together in the same area. You<br />
must also assign a name to the clique. A clique assignment allows you to group all<br />
logic on a speed-critical path to help achieve optimum performance.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_instance_assignment -name MEMBER_OF -to -entity -<br />
section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 2: Pin & Locations Assignments 2–13<br />
PIN_CONNECT_FROM_NODE<br />
PIN_CONNECT_FROM_NODE<br />
Type<br />
Directs the Compiler to generate a device pin with the specified name and connect the<br />
device pin to an internal signal.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_instance_assignment -name PIN_CONNECT_FROM_NODE -to <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
2–14 Chapter 2: Pin & Locations Assignments<br />
RESERVE_PIN<br />
RESERVE_PIN<br />
Type<br />
Reserves the pin in one of the following seven states:<br />
■ As an input that is tri-stated<br />
■ As an output that drives ground<br />
■ As an output that drives VCC<br />
■ As an output that drives an unspecified signal<br />
■ As SignalProbe output<br />
■ As a voltage reference (VREF)<br />
■ As bidirectional<br />
The As VREF setting is not appropriate for all device families. For more information<br />
about V REF support, refer to the device data sheet.<br />
Enumeration<br />
■ As SignalProbe output<br />
■ As VREF<br />
Device Support<br />
■ As bidirectional<br />
■ As input tri-stated<br />
■ As output driving VCC<br />
■ As output driving an unspecified signal<br />
■ As output driving ground<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_instance_assignment -name RESERVE_PIN -to <br />
set_global_assignment -name RESERVE_PIN <br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
RESERVED_PIN<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 2: Pin & Locations Assignments 2–15<br />
SUBCLIQUE_OF<br />
SUBCLIQUE_OF<br />
Type<br />
Specifies that the current clique is a member of another clique.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_instance_assignment -name SUBCLIQUE_OF -to -entity -<br />
section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
2–16 Chapter 2: Pin & Locations Assignments<br />
VIRTUAL_PIN<br />
VIRTUAL_PIN<br />
Type<br />
Specifies whether an I/O element in a lower-level design entity can be temporarily<br />
mapped to a logic element and not to a pin during compilation. The virtual pin is then<br />
implemented as a LUT. This option should be specified only for I/O elements that<br />
become nodes when imported to the top-level design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 2: Pin & Locations Assignments 2–17<br />
VIRTUAL_PIN<br />
Syntax<br />
set_instance_assignment -name VIRTUAL_PIN -to -entity <br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
2–18 Chapter 2: Pin & Locations Assignments<br />
VIRTUAL_PIN<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
ASSIGNMENT_GROUP_EXCEPTION<br />
Type<br />
© 2012 <strong>Altera</strong> Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos<br />
are trademarks of <strong>Altera</strong> Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as<br />
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. <strong>Altera</strong> warrants performance of its<br />
semiconductor products to current specifications in accordance with <strong>Altera</strong>'s standard warranty, but reserves the right to make changes to any products and<br />
services at any time without notice. <strong>Altera</strong> assumes no responsibility or liability arising out of the application or use of any information, product, or service<br />
described herein except as expressly agreed to in writing by <strong>Altera</strong>. <strong>Altera</strong> customers are advised to obtain the latest version of device specifications before relying<br />
on any published information and before placing orders for products or services.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong><br />
June 2012<br />
3. Assignment Group Assignments<br />
Defines a node or nodes to be excluded as an exception to a previously added<br />
member. The node can be an instance name or a wildcard representing multiple<br />
instance names.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name ASSIGNMENT_GROUP_EXCEPTION -section_id<br />
<br />
ISO<br />
9001:2008<br />
Registered<br />
Subscribe
3–2 Chapter 3: Assignment Group Assignments<br />
ASSIGNMENT_GROUP_MEMBER<br />
ASSIGNMENT_GROUP_MEMBER<br />
Type<br />
Defines an element of a group. The element can be an instance name or a wildcard<br />
representing multiple instance names<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER -section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
ADV_NETLIST_OPT_ALLOWED<br />
Type<br />
© 2012 <strong>Altera</strong> Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos<br />
are trademarks of <strong>Altera</strong> Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as<br />
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. <strong>Altera</strong> warrants performance of its<br />
semiconductor products to current specifications in accordance with <strong>Altera</strong>'s standard warranty, but reserves the right to make changes to any products and<br />
services at any time without notice. <strong>Altera</strong> assumes no responsibility or liability arising out of the application or use of any information, product, or service<br />
described herein except as expressly agreed to in writing by <strong>Altera</strong>. <strong>Altera</strong> customers are advised to obtain the latest version of device specifications before relying<br />
on any published information and before placing orders for products or services.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong><br />
June 2012<br />
4. Analysis & Synthesis Assignments<br />
Specifies whether the Compiler should perform advanced netlist optimizations, such<br />
as gate-level retiming or physical synthesis, on the specified node or entity.<br />
You can choose one of the following settings:<br />
■ Always Allow—Allows the Compiler to alter the node or entity, even if doing so<br />
affects the timing or performance of the design. <strong>Altera</strong> does not recommend using<br />
this setting.<br />
■ Never Allow—Prevents the Compiler from altering the node or entity.<br />
■ Default—Allows the Compiler to duplicate, move, or change the synthesis of the<br />
node or entity, or allows register retiming during netlist optimization, only if<br />
doing so does not negatively affect the timing or performance of the design.<br />
You can use this option to preserve I/O timing on specific pins and registers in a<br />
design in which you want to perform netlist optimization. This option is also useful<br />
for preserving the synthesis of a specific node or entity, for example, preserving the<br />
name of a register.<br />
This option can be assigned to individual nodes or design entities only.<br />
Enumeration<br />
■ Always Allow<br />
■ Default<br />
Device Support<br />
■ Never Allow<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
ISO<br />
9001:2008<br />
Registered<br />
Subscribe
4–2 Chapter 4: Analysis & Synthesis Assignments<br />
ADV_NETLIST_OPT_ALLOWED<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name ADV_NETLIST_OPT_ALLOWED -entity <br />
<br />
set_instance_assignment -name ADV_NETLIST_OPT_ALLOWED -to -entity<br />
<br />
Example<br />
set_instance_assignment -name adv_netlist_opt_allowed "always allow" -to<br />
reg<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–3<br />
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP<br />
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP<br />
Type<br />
Specifies whether to perform WYSIWYG primitive resynthesis during synthesis. This<br />
option uses the setting specified in the Optimization Technique logic option.<br />
This option is useful for resynthesizing some or all of the WYSIWYG primitives in the<br />
design for better area or performance.<br />
This option defaults to Off.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–4 Chapter 4: Analysis & Synthesis Assignments<br />
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP <br />
set_instance_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP -to <br />
-entity <br />
Example<br />
set_global_assignment -name adv_netlist_opt_synth_wysiwyg_remap on<br />
set_instance_assignment -name adv_netlist_opt_synth_wysiwyg_remap on -to<br />
foo<br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–5<br />
ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION<br />
ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION<br />
Type<br />
Allows the Compiler to infer RAMs of any size, even if they do not meet the current<br />
minimum requirements.<br />
This option is useful for minimizing the area of a design that is close to the device<br />
limit.<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option defaults to Off.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–6 Chapter 4: Analysis & Synthesis Assignments<br />
ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION<br />
Syntax<br />
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION <br />
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION -entity<br />
<br />
set_instance_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION -to <br />
-entity <br />
Example<br />
set_global_assignment -name allow_any_ram_size_for_recognition off<br />
set_instance_assignment -name allow_any_ram_size_for_recognition off -to<br />
foo<br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–7<br />
ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION<br />
ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION<br />
Type<br />
Allows the Compiler to infer ROMs of any size even if the ROMs do not meet the<br />
design’s current minimum size requirements.<br />
This option is useful for minimizing the area of a design that is close to the device<br />
limit.<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option defaults to Off.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–8 Chapter 4: Analysis & Synthesis Assignments<br />
ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION<br />
Syntax<br />
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION <br />
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION -entity<br />
<br />
set_instance_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION -to <br />
-entity <br />
Example<br />
set_global_assignment -name allow_any_rom_size_for_recognition off<br />
set_instance_assignment -name allow_any_rom_size_for_recognition off -to<br />
foo<br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–9<br />
ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION<br />
ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION<br />
Type<br />
Allows the Compiler to infer shift registers of any size even if they do not meet the<br />
design's current minimum size requirements.<br />
This option is useful for minimizing the area of a design that is close to the device<br />
limit.<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option defaults to Off.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–10 Chapter 4: Analysis & Synthesis Assignments<br />
ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION<br />
Syntax<br />
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION<br />
<br />
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION<br />
-entity <br />
set_instance_assignment -name<br />
ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION -to -entity <br />
Example<br />
set_global_assignment -name allow_any_shift_register_size_for_recognition<br />
off<br />
set_instance_assignment -name<br />
allow_any_shift_register_size_for_recognition off -to foo<br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–11<br />
ALLOW_CHILD_PARTITIONS<br />
ALLOW_CHILD_PARTITIONS<br />
Type<br />
Specifies whether or not an instance or a section of design hierarchy can contain user<br />
partitions.<br />
A logic option that allows you to control whether or not an instance or entity can have<br />
child partitions.<br />
This option is useful to prevent a hierarchy from being partitioned. If applied globally,<br />
this option can also be used to prevent any user partitions from being created.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name ALLOW_CHILD_PARTITIONS -entity <br />
<br />
set_instance_assignment -name ALLOW_CHILD_PARTITIONS -to -entity<br />
<br />
Example<br />
set_global_assignment -name allow_child_partitions off<br />
set_instance_assignment -name allow_child_partitions off -to "sub:inst"<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–12 Chapter 4: Analysis & Synthesis Assignments<br />
ALLOW_POWER_UP_DONT_CARE<br />
ALLOW_POWER_UP_DONT_CARE<br />
Type<br />
Causes registers that do not have a Power-Up Level logic option setting to power up<br />
with a don't care logic level (X). A Power-Up Don't Care setting allows the Compiler<br />
to change the power-up level of a register to minimize the area of the design.<br />
This option is useful for allowing the Compiler to change the power-up level of a<br />
register to minimize the area of the design.<br />
This option can be used as a project-wide option only.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE <br />
Example<br />
set_global_assignment -name allow_power_up_dont_care off<br />
Default Value<br />
On<br />
See Also<br />
■ “POWER_UP_LEVEL” on page 4–139<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–13<br />
ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES<br />
ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES<br />
Type<br />
Allows the Compiler to take shift registers from different hierarchies of your design<br />
and place the shift registers in the same RAM.<br />
Merging shift registers across hierarchies is good for logic utilization, as it allows<br />
more shift registers to be put in RAM, and it allows the different shift registers to<br />
share the same external counter logic. However, merging shift registers across<br />
hierarchies can be bad for timing as it pulls together registers from different unrelated<br />
hierarchies.<br />
When this option is set to Auto, the Compiler decides whether it wants to merge shift<br />
registers across hierarchies based on resource availability, timing and the<br />
Optimization Technique setting. When the option is set to On, shift registers are<br />
merged across hierarchies as much as possible. When the option is set to Off, shift<br />
registers are not be merged across hierarchies at all. This option is ignored when the<br />
Auto Shift Register Replacement setting is set to Off.<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option is turned on by default.<br />
Enumeration<br />
■ Always<br />
■ Auto<br />
■ Off<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–14 Chapter 4: Analysis & Synthesis Assignments<br />
ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
This assignment supports wildcards.<br />
Syntax<br />
set_global_assignment -name<br />
ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES <br />
set_global_assignment -name<br />
ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES -entity <br />
<br />
set_instance_assignment -name<br />
ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES -to -entity <br />
Example<br />
set_global_assignment -name<br />
allow_shift_register_merging_across_hierarchies off<br />
set_instance_assignment -name<br />
allow_shift_register_merging_across_hierarchies off -to foo<br />
Default Value<br />
Auto<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–15<br />
ALLOW_SYNCH_CTRL_USAGE<br />
ALLOW_SYNCH_CTRL_USAGE<br />
Type<br />
Allows the Compiler to utilize synchronous clear and/or synchronous load signals in<br />
normal mode logic cells. Turning on this option helps to reduce the total number of<br />
logic cells used in the design, but might negatively impact the fitting since<br />
synchronous control signals are shared by all the logic cells in a LAB.<br />
This option is useful for finding areas of the design that can be implemented more<br />
efficiently with synchronous clear and/or synchronous load signals in normal mode<br />
logic cells, and as a result, minimize the number of logic cells used in the design.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–16 Chapter 4: Analysis & Synthesis Assignments<br />
ALLOW_SYNCH_CTRL_USAGE<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE <br />
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE -entity <br />
<br />
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE -to -entity<br />
<br />
Example<br />
set_global_assignment -name allow_synch_ctrl_usage off<br />
set_instance_assignment -name allow_synch_ctrl_usage off -to foo<br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–17<br />
ALLOW_XOR_GATE_USAGE<br />
ALLOW_XOR_GATE_USAGE<br />
Type<br />
Allows the Compiler to use the XOR gate that exists in a macrocell (that is, in an<br />
embedded cell within an Embedded System Block [ESB] that is set to use Product<br />
Term mode). This option is ignored if you select LUT or ROM as the setting for the<br />
Technology Mapper option.<br />
This option is ignored if it is assigned to anything other than a design entity. The<br />
Allow XOR Gate Usage option is also ignored if you select LUT or ROM as the setting<br />
for the Technology Mapper option. This option can be set in the Assignment Editor<br />
in the Assignments menu, the Analysis & Synthesis <strong>Settings</strong> page, or the Fitter<br />
<strong>Settings</strong> page of the <strong>Settings</strong> dialog box in the Assignments menu. This option is<br />
available for APEX 20K, APEX 20KC, APEX 20KE, APEX <strong>II</strong>, Excalibur, MAX 3000,<br />
MAX 7000A, MAX 7000AE, MAX 7000B, and MAX 7000S devices.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name ALLOW_XOR_GATE_USAGE <br />
set_global_assignment -name ALLOW_XOR_GATE_USAGE -entity <br />
<br />
set_instance_assignment -name ALLOW_XOR_GATE_USAGE -to -entity<br />
<br />
Example<br />
set_instance_assignment -name allow_xor_gate_usage off -to clock<br />
Default Value<br />
On<br />
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<strong>Reference</strong> <strong>Manual</strong>
4–18 Chapter 4: Analysis & Synthesis Assignments<br />
AUTO_CARRY_CHAINS<br />
AUTO_CARRY_CHAINS<br />
Type<br />
Allows the Compiler to create carry chains automatically by inserting CARRY_SUM<br />
buffers into the design. This option is also required to recognize carry chains in any<br />
design containing MAX+PLUS <strong>II</strong>-style CARRY buffers. The length of the chains is<br />
controlled with the Carry Chain Length option. If this option is turned off, CARRY<br />
buffers are ignored, but CARRY_SUM buffers are unaffected. The Auto Carry Chains<br />
option is ignored if you select Product Term or ROM as the setting for the Technology<br />
Mapper option.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–19<br />
AUTO_CARRY_CHAINS<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name AUTO_CARRY_CHAINS <br />
set_global_assignment -name AUTO_CARRY_CHAINS -entity <br />
<br />
set_instance_assignment -name AUTO_CARRY_CHAINS -to -entity <br />
Default Value<br />
On<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–20 Chapter 4: Analysis & Synthesis Assignments<br />
AUTO_CLOCK_ENABLE_RECOGNITION<br />
AUTO_CLOCK_ENABLE_RECOGNITION<br />
Type<br />
Allows the Compiler to find logic that feeds a register and move the logic to the<br />
register’s clock enable input port.<br />
This option can bet set to Off on individual registers or design entities to solve fitting<br />
and performance issues with designs that have many clock enables generated by<br />
Analysis & Synthesis.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–21<br />
AUTO_CLOCK_ENABLE_RECOGNITION<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
This assignment supports wildcards.<br />
Syntax<br />
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION <br />
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION -entity <br />
set_instance_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION -to -<br />
entity <br />
Example<br />
set_global_assignment -name auto_clock_enable_replacement off<br />
set_instance_assignment -name auto_clock_enable_replacement off -to reg<br />
Default Value<br />
On<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–22 Chapter 4: Analysis & Synthesis Assignments<br />
AUTO_DSP_RECOGNITION<br />
AUTO_DSP_RECOGNITION<br />
Type<br />
Allows the Compiler to find a multiply-accumulate function or a multiply-add<br />
function that can be replaced with the altmult_accum or the altmult_add<br />
megafunction.<br />
This option is useful for finding areas of the design that can be implemented more<br />
efficiently, and as a result, minimizing the area and maximizing the speed of the<br />
design.<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–23<br />
AUTO_DSP_RECOGNITION<br />
This assignment supports wildcards.<br />
Syntax<br />
set_global_assignment -name AUTO_DSP_RECOGNITION <br />
set_global_assignment -name AUTO_DSP_RECOGNITION -entity <br />
<br />
set_instance_assignment -name AUTO_DSP_RECOGNITION -to -entity<br />
<br />
Example<br />
set_global_assignment -name auto_dsp_recognition off<br />
set_instance_assignment -name auto_dsp_recognition off -to foo<br />
Default Value<br />
On<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–24 Chapter 4: Analysis & Synthesis Assignments<br />
AUTO_ENABLE_SMART_COMPILE<br />
AUTO_ENABLE_SMART_COMPILE<br />
Type<br />
Specifies whether the SignalTap <strong>II</strong> Logic Analyzer should perform a smart<br />
compilation if conditions exist in which you use incremental routing with the<br />
SignalTap <strong>II</strong> Logic Analyzer.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name AUTO_ENABLE_SMART_COMPILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–25<br />
AUTO_GLOBAL_CLOCK_MAX<br />
AUTO_GLOBAL_CLOCK_MAX<br />
Type<br />
Allows the Compiler to choose the signal that feeds the most clock inputs to flipflops<br />
as a global clock signal that is made available throughout the device on the global<br />
routing paths. If you want to prevent the Compiler from automatically selecting a<br />
particular signal as global clock, set the Global Signal option to Off on that signal.<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
Syntax<br />
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX <br />
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX -entity <br />
<br />
set_instance_assignment -name AUTO_GLOBAL_CLOCK_MAX -to -entity<br />
<br />
Example<br />
set_global_assignment -name auto_global_clock_max off<br />
set_instance_assignment -name auto_global_clock_max off -to foo<br />
Default Value<br />
On<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
Auto Global Clock -- MAX 7000B/7000AE/3000A/7000S/7000A<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–26 Chapter 4: Analysis & Synthesis Assignments<br />
AUTO_GLOBAL_OE_MAX<br />
AUTO_GLOBAL_OE_MAX<br />
Type<br />
Allows the Compiler to choose the signal that feeds the most TRI buffers as a global<br />
output enable signal that is made available throughout the device on the global<br />
routing paths. If you want to prevent the Compiler from automatically selecting a<br />
particular signal as global output enable, set the Global Signal option to Off on that<br />
signal.<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
Syntax<br />
set_global_assignment -name AUTO_GLOBAL_OE_MAX <br />
set_global_assignment -name AUTO_GLOBAL_OE_MAX -entity <br />
<br />
set_instance_assignment -name AUTO_GLOBAL_OE_MAX -to -entity <br />
Example<br />
set_global_assignment -name auto_global_oe_max off<br />
set_instance_assignment -name auto_global_oe_max off -to foo<br />
Default Value<br />
On<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
Auto Global Output Enable -- MAX 7000B/7000AE/3000A/7000S/7000A<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–27<br />
AUTO_LCELL_INSERTION<br />
AUTO_LCELL_INSERTION<br />
Type<br />
Allows the Compiler to insert macrocells into the design. This option is ignored if it is<br />
assigned to anything other than a design entity. If you want to prevent the Compiler<br />
from automatically inserting macrocells into the design, set the Auto Logic Cell<br />
Insertion option to Off on that signal.<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name AUTO_LCELL_INSERTION <br />
set_global_assignment -name AUTO_LCELL_INSERTION -entity <br />
<br />
set_instance_assignment -name AUTO_LCELL_INSERTION -to -entity<br />
<br />
Example<br />
set_global_assignment -name auto_lcell_insertion off<br />
set_instance_assignment -name auto_lcell_insertion off -to foo<br />
Default Value<br />
On<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–28 Chapter 4: Analysis & Synthesis Assignments<br />
AUTO_OPEN_DRAIN_PINS<br />
AUTO_OPEN_DRAIN_PINS<br />
Type<br />
Allows the Compiler to automatically convert a tri-state buffer with a strong low data<br />
input into the equivalent open-drain buffer.<br />
This option cannot be used with a netlists that are synthesized with third-party<br />
synthesis tools. To use this option, you must turn on the Perform WYSIWYG<br />
Primitive Resynthesis logic option.<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
■ Stratix<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–29<br />
AUTO_OPEN_DRAIN_PINS<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name AUTO_OPEN_DRAIN_PINS <br />
set_global_assignment -name AUTO_OPEN_DRAIN_PINS -entity <br />
<br />
set_instance_assignment -name AUTO_OPEN_DRAIN_PINS -to -entity<br />
<br />
Example<br />
set_global_assignment -name auto_open_drain_pins off<br />
set_instance_assignment -name auto_open_drain_pins off -to foo<br />
Default Value<br />
On<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–30 Chapter 4: Analysis & Synthesis Assignments<br />
AUTO_PARALLEL_EXPANDERS<br />
AUTO_PARALLEL_EXPANDERS<br />
Type<br />
Allows the Compiler to automatically create chains of parallel expander product<br />
terms. Parallel expanders are available in macrocells, that is, embedded cells within<br />
an Embedded System Block [ESB] that is set to use Product Term mode. The length of<br />
the chains is controlled with the Parallel Expander Chain Length option. The Auto<br />
Parallel Expanders option is ignored if you select LUT or ROM as the setting for the<br />
Technology Mapper option.<br />
This option can be set in the Assignment Editor in the Assignments menu, the<br />
Analysis & Synthesis <strong>Settings</strong> page, or the Fitter <strong>Settings</strong> page of the <strong>Settings</strong> dialog<br />
box in the Assignments menu. This option is available for APEX 20K, APEX 20KC,<br />
APEX 20KE, APEX <strong>II</strong>, Excalibur, MAX 3000, MAX 7000AE, MAX 7000B, and MAX<br />
7000S devices.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name AUTO_PARALLEL_EXPANDERS <br />
set_global_assignment -name AUTO_PARALLEL_EXPANDERS -entity <br />
<br />
set_instance_assignment -name AUTO_PARALLEL_EXPANDERS -to -entity<br />
<br />
Example<br />
set_instance_assignment -name auto_parallel_expanders on -to clock<br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–31<br />
AUTO_RAM_BLOCK_BALANCING<br />
AUTO_RAM_BLOCK_BALANCING<br />
Type<br />
Enables the Compiler to automatically use different memory types when using auto<br />
RAM blocks and allows the Compiler to use different RAM partitions with the same<br />
memory types.<br />
This option is useful for finding areas of the design that can be implemented more<br />
efficiently, and as a result, minimizing the area and maximizing the speed of the<br />
design. During design fitting, a megafunction may use a RAM partition that cannot fit<br />
in the design due to unbalanced use of RAM resources. The logic option allows the<br />
Compiler to dynamically change RAM partitions and balance resource usage when<br />
using different RAM block types.<br />
This option can be used as a project-wide option only.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–32 Chapter 4: Analysis & Synthesis Assignments<br />
AUTO_RAM_BLOCK_BALANCING<br />
Syntax<br />
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING <br />
Example<br />
set_global_assignment -name auto_ram_block_balancing off<br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–33<br />
AUTO_RAM_RECOGNITION<br />
AUTO_RAM_RECOGNITION<br />
Type<br />
Allows the Compiler to find a set of registers and logic that can be replaced with the<br />
altsyncram or the lpm_ram_dp megafunction. Turning on this option may change the<br />
functionality of the design.<br />
This option is useful for finding areas of the design that can be implemented more<br />
efficiently, and as a result, minimizing the area and maximizing the speed of the<br />
design.<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–34 Chapter 4: Analysis & Synthesis Assignments<br />
AUTO_RAM_RECOGNITION<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
This assignment supports wildcards.<br />
Syntax<br />
set_global_assignment -name AUTO_RAM_RECOGNITION <br />
set_global_assignment -name AUTO_RAM_RECOGNITION -entity <br />
<br />
set_instance_assignment -name AUTO_RAM_RECOGNITION -to -entity<br />
<br />
Example<br />
set_global_assignment -name auto_ram_recognition off<br />
set_instance_assignment -name auto_ram_recognition off -to foo<br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–35<br />
AUTO_RAM_TO_LCELL_CONVERSION<br />
AUTO_RAM_TO_LCELL_CONVERSION<br />
Type<br />
Allows the Compiler to convert small RAM blocks into logic cells.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION <br />
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION -entity <br />
set_instance_assignment -name AUTO_RAM_TO_LCELL_CONVERSION -to -<br />
entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–36 Chapter 4: Analysis & Synthesis Assignments<br />
AUTO_RAM_TO_LCELL_CONVERSION<br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–37<br />
AUTO_RESOURCE_SHARING<br />
AUTO_RESOURCE_SHARING<br />
Type<br />
Allows the Compiler to share hardware resources among many similar, but mutually<br />
exclusive, operations in your HDL source code. If you enable this option, the<br />
Compiler will merge compatible addition, subtraction, and multiplication operations.<br />
By merging operations, this may reduce the area required by your design. Because<br />
resource sharing introduces extra muxing and control logic on each shared resource, it<br />
may negatively impact the final f max of your design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name AUTO_RESOURCE_SHARING <br />
set_global_assignment -name AUTO_RESOURCE_SHARING -entity <br />
<br />
set_instance_assignment -name AUTO_RESOURCE_SHARING -to -entity<br />
<br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–38 Chapter 4: Analysis & Synthesis Assignments<br />
AUTO_ROM_RECOGNITION<br />
AUTO_ROM_RECOGNITION<br />
Type<br />
Allows the Compiler to find logic that can be replaced with the altsyncram or the<br />
lpm_rom megafunction. Turning on this option may change the power-up state of the<br />
design.<br />
This option is useful for finding areas of the design that can be implemented more<br />
efficiently, and as a result, minimizing the area and maximizing the speed of the<br />
design.<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–39<br />
AUTO_ROM_RECOGNITION<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
This assignment supports wildcards.<br />
Syntax<br />
set_global_assignment -name AUTO_ROM_RECOGNITION <br />
set_global_assignment -name AUTO_ROM_RECOGNITION -entity <br />
<br />
set_instance_assignment -name AUTO_ROM_RECOGNITION -to -entity<br />
<br />
Example<br />
set_global_assignment -name auto_rom_recognition off<br />
set_instance_assignment -name auto_rom_recognition off -to foo<br />
Default Value<br />
On<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–40 Chapter 4: Analysis & Synthesis Assignments<br />
AUTO_SHIFT_REGISTER_RECOGNITION<br />
AUTO_SHIFT_REGISTER_RECOGNITION<br />
Type<br />
Allows the Compiler to find a group of shift registers of the same length that can be<br />
replaced with the altshift_taps megafunction. The shift registers must all use the same<br />
clock and clock enable signals, must not have any other secondary signals, and must<br />
have equally spaced taps that are at least three registers apart.<br />
This option is useful for finding areas of the design that can be implemented more<br />
efficiently, and as a result, minimizing the area and maximizing the speed of the<br />
design.<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option is turned on by default.<br />
Enumeration<br />
■ Always<br />
■ Auto<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–41<br />
AUTO_SHIFT_REGISTER_RECOGNITION<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
This assignment supports wildcards.<br />
Syntax<br />
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION <br />
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION -entity<br />
<br />
set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION -to -<br />
entity <br />
Example<br />
set_global_assignment -name auto_shift_register_recognition off<br />
set_instance_assignment -name auto_shift_register_recognition off -to foo<br />
Default Value<br />
Auto<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–42 Chapter 4: Analysis & Synthesis Assignments<br />
BLOCK_DESIGN_NAMING<br />
BLOCK_DESIGN_NAMING<br />
Type<br />
Specifies the naming scheme used for the block design. This option is ignored if it is<br />
assigned to anything other than a design entity.<br />
The following three settings are available:<br />
■ MAX+PLUS <strong>II</strong>—This option specifies the naming scheme used in previous<br />
versions of the <strong>Quartus</strong> <strong>II</strong> software.<br />
■ <strong>Quartus</strong> <strong>II</strong>—This option specifies the new naming scheme on block designs. When<br />
a bus is split, the resulted pins are named with a base name followed by square<br />
brackets, with indicies between the bracket pair.<br />
■ Auto—This option informs the <strong>Quartus</strong> <strong>II</strong> software to use the naming scheme that<br />
is specified by the source file.<br />
This option is useful if your design contains design files that are generated by the<br />
<strong>Quartus</strong> <strong>II</strong> software versions 7.2 and earlier. You can use this option to specify which<br />
naming scheme you want the <strong>Quartus</strong> <strong>II</strong> software to use on the specified design entity.<br />
This option can be used as a project-wide option, or assigned to a block design entity.<br />
This option defaults to Auto.<br />
Enumeration<br />
■ Auto<br />
■ MaxPlus<strong>II</strong><br />
■ <strong>Quartus</strong><strong>II</strong><br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name BLOCK_DESIGN_NAMING -entity <br />
<br />
set_instance_assignment -name BLOCK_DESIGN_NAMING -to -entity <br />
set_global_assignment -name BLOCK_DESIGN_NAMING <br />
Example<br />
set_global_assignment -name block_design_naming MaxPlus<strong>II</strong><br />
set_instance_assignment -name block_design_naming MaxPlus<strong>II</strong> -to top<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–43<br />
BLOCK_DESIGN_NAMING<br />
Default Value<br />
Auto<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–44 Chapter 4: Analysis & Synthesis Assignments<br />
CLKLOCKX1_INPUT_FREQ<br />
CLKLOCKX1_INPUT_FREQ<br />
Type<br />
Creates an internal ClockLock phase-locked loop (PLL) and specifies its frequency.<br />
Turning this option on is equivalent to instantiating an altclklock megafunction with<br />
either of its ClockBoost parameters set to a value of 1. The CLKLOCKx1 Input<br />
Frequency option is provided primarily for backward compatibility with MAX+PLUS<br />
<strong>II</strong> designs. <strong>Altera</strong> recommends using the MegaWizard Plug-In Manager to instantiate<br />
PLLs in new designs. This option is ignored if it is assigned to anything other than an<br />
input pin or to a device that does not have the PLL feature.<br />
Frequency<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Syntax<br />
set_instance_assignment -name CLKLOCKX1_INPUT_FREQ -to -entity <br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–45<br />
CYCLONE<strong>II</strong>_OPTIMIZATION_TECHNIQUE<br />
CYCLONE<strong>II</strong>_OPTIMIZATION_TECHNIQUE<br />
Type<br />
Specifies the overall optimization goal for Analysis & Synthesis, that is, whether to<br />
attempt to maximize performance, minimize logic usage, or balance high<br />
performance with minimal logic usage during compilation.<br />
You can select one of the following settings:<br />
■ Area—The Compiler makes the design as small as possible in order to minimize<br />
resource usage<br />
■ Speed—The Compiler chooses a design implementation that has the fastest f max<br />
■ Balanced—The Compiler chooses a design implementation that balances high<br />
performance with minimal logic usage<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option defaults to Balanced.<br />
Enumeration<br />
■ Area<br />
■ Balanced<br />
■ Speed<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name CYCLONE<strong>II</strong>_OPTIMIZATION_TECHNIQUE <br />
set_global_assignment -name CYCLONE<strong>II</strong>_OPTIMIZATION_TECHNIQUE -entity<br />
<br />
set_instance_assignment -name CYCLONE<strong>II</strong>_OPTIMIZATION_TECHNIQUE -to -<br />
entity <br />
Example<br />
set_global_assignment -name cycloneii_optimization_technique speed<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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4–46 Chapter 4: Analysis & Synthesis Assignments<br />
CYCLONE<strong>II</strong>_OPTIMIZATION_TECHNIQUE<br />
Default Value<br />
Balanced<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
Optimization Technique -- Cyclone <strong>II</strong>/Cyclone <strong>II</strong>I<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–47<br />
CYCLONE_OPTIMIZATION_TECHNIQUE<br />
CYCLONE_OPTIMIZATION_TECHNIQUE<br />
Type<br />
Specifies the overall optimization goal for Analysis & Synthesis, that is, whether to<br />
attempt to maximize performance, minimize logic usage, or balance high<br />
performance with minimal logic usage during compilation.<br />
You can select one of the following settings:<br />
■ Area—The Compiler makes the design as small as possible in order to minimize<br />
resource usage<br />
■ Speed—The Compiler chooses a design implementation that has the fastest f max<br />
■ Balanced—The Compiler chooses a design implementation that balances high<br />
performance with minimal logic usage<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option defaults to Balanced.<br />
Enumeration<br />
■ Area<br />
■ Balanced<br />
■ Speed<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE <br />
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE -entity <br />
set_instance_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE -to -<br />
entity <br />
Example<br />
set_global_assignment -name cyclone_optimization_technique speed<br />
Default Value<br />
Balanced<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–48 Chapter 4: Analysis & Synthesis Assignments<br />
CYCLONE_OPTIMIZATION_TECHNIQUE<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
Optimization Technique -- Cyclone<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–49<br />
DEVICE_FILTER_PACKAGE<br />
DEVICE_FILTER_PACKAGE<br />
Type<br />
Package filter for available devices.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name DEVICE_FILTER_PACKAGE <br />
Default Value<br />
Any<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–50 Chapter 4: Analysis & Synthesis Assignments<br />
DEVICE_FILTER_PIN_COUNT<br />
DEVICE_FILTER_PIN_COUNT<br />
Type<br />
Pin count filter for available devices.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name DEVICE_FILTER_PIN_COUNT <br />
Default Value<br />
Any<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–51<br />
DEVICE_FILTER_SPEED_GRADE<br />
DEVICE_FILTER_SPEED_GRADE<br />
Type<br />
Speed grade filter for available devices.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE <br />
Default Value<br />
Any<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–52 Chapter 4: Analysis & Synthesis Assignments<br />
DEVICE_FILTER_VOLTAGE<br />
DEVICE_FILTER_VOLTAGE<br />
Type<br />
Voltage filter for available devices.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name DEVICE_FILTER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–53<br />
DISABLE_OCP_HW_EVAL<br />
DISABLE_OCP_HW_EVAL<br />
Type<br />
Turns off OpenCore Plus hardware evaluation feature.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name DISABLE_OCP_HW_EVAL <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–54 Chapter 4: Analysis & Synthesis Assignments<br />
DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES<br />
DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES<br />
Type<br />
Specifies whether registers that are in different hierarchies are allowed to be merged if<br />
their inputs are the same.<br />
Enumeration<br />
■ Auto<br />
■ Off<br />
■ On<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES<br />
<br />
Default Value<br />
Auto<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–55<br />
DONT_MERGE_REGISTER<br />
DONT_MERGE_REGISTER<br />
Type<br />
When set to On, this option prevents the specified register from merging with other<br />
registers, and prevents other registers from merging with the specified register.<br />
You can use this option to instruct the Compiler to use the user-specified timing<br />
constraints on the register during synthesis. For example, if the register has a<br />
multicycle constraint, this option prevents the Compiler from merging other registers<br />
into the specified register, avoiding unintended timing and functional effects.<br />
This option is different from Preserve Register logic option because it does not<br />
prevent a register with constant drivers or a redundant register from being removed.<br />
In addition, this option prevents other registers from merging with the specified<br />
register.<br />
This option is ignored if the register does not drive anything or if it has constant<br />
drivers, in which case the register is removed during synthesis.<br />
This option is ignored if it is applied to anything other than a register or a design<br />
entity containing registers.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_global_assignment -name DONT_MERGE_REGISTER -entity <br />
<br />
set_instance_assignment -name DONT_MERGE_REGISTER -to -entity <br />
Example<br />
set_instance_assignment -name dont_merge_register on -to foo<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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4–56 Chapter 4: Analysis & Synthesis Assignments<br />
DQS_DELAY<br />
DQS_DELAY<br />
Type<br />
Increases the propagation delay from a DQS I/O pin to the interior of the device. This<br />
option is used to center-align the DQS signal to the DQ data signals and should be<br />
selected to ensure the desired setup and hold margins across process, voltage, and<br />
temperature ranges.<br />
Time<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
Syntax<br />
set_instance_assignment -name DQS_DELAY -to -entity <br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–57<br />
DQS_FREQUENCY<br />
DQS_FREQUENCY<br />
Type<br />
Specifies the DQS system clock frequency by which data is transferred between a<br />
device and an external RAM that uses double data rate (DDR). You can specify the<br />
desired frequency setting.<br />
Frequency<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_instance_assignment -name DQS_FREQUENCY -to -entity <br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–58 Chapter 4: Analysis & Synthesis Assignments<br />
DQS_SHIFT<br />
DQS_SHIFT<br />
Type<br />
Specifies the interval of arrival between the DQ data signals and DQS signal during<br />
data transfer between a device and an external RAM that uses DDR. This option is<br />
ignored if it is applied to anything other than pins intended for use with the dedicated<br />
DDR SDRAM interface.<br />
Enumeration<br />
Device Support<br />
■ Phase of 0 degrees<br />
■ Phase of 72 degrees<br />
■ Phase of 90 degrees<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_instance_assignment -name DQS_SHIFT -to -entity <br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–59<br />
DQS_SYSTEM_CLOCK<br />
DQS_SYSTEM_CLOCK<br />
Type<br />
Specifies the clock input used as a frequency reference for a DQS I/O pin. The clock is<br />
the pin that drives the DDIO circuitry for the dedicated DDR SDRAM interface.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix<br />
■ Stratix GX<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_instance_assignment -name DQS_SYSTEM_CLOCK -to -entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–60 Chapter 4: Analysis & Synthesis Assignments<br />
DSE_SYNTH_EXTRA_EFFORT_MODE<br />
DSE_SYNTH_EXTRA_EFFORT_MODE<br />
Type<br />
Specifies the Design Space Explorer synthesis extra effort mode.<br />
Enumeration<br />
■ MODE_1<br />
■ MODE_2<br />
■ MODE_3<br />
■ MODE_4<br />
■ MODE_5<br />
Device Support<br />
■ MODE_DEFAULT<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name DSE_SYNTH_EXTRA_EFFORT_MODE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–61<br />
DSP_BLOCK_BALANCING<br />
DSP_BLOCK_BALANCING<br />
Type<br />
Allows you to control the conversion of certain DSP block slices during DSP block<br />
balancing.<br />
This option is useful for controlling the DSP block balancer when it produces results<br />
that conflict with your design, such as converting DSP block slices that you do not<br />
want to be converted.<br />
You can select one of the following settings:<br />
■ Auto<br />
■ Off<br />
■ DSP blocks<br />
■ Logic Elements<br />
■ Simple Multipliers<br />
■ Width 18-bit Multipliers<br />
■ Simple 18-bit Multipliers<br />
This option defaults to Auto.<br />
Enumeration<br />
■ Auto<br />
■ DSP blocks<br />
■ Logic Elements<br />
■ Off<br />
Device Support<br />
■ Simple 18-bit Multipliers<br />
■ Simple Multipliers<br />
■ Width 18-bit Multipliers<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–62 Chapter 4: Analysis & Synthesis Assignments<br />
DSP_BLOCK_BALANCING<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name DSP_BLOCK_BALANCING -entity <br />
<br />
set_instance_assignment -name DSP_BLOCK_BALANCING -to -entity <br />
set_global_assignment -name DSP_BLOCK_BALANCING <br />
Example<br />
set_global_assignment -name dsp_block_balancing "dsp blocks"<br />
set_instance_assignment -name dsp_block_balancing "logic elements" -to<br />
mult0<br />
Default Value<br />
Auto<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–63<br />
EDA_DESIGN_ENTRY_SYNTHESIS_TOOL<br />
EDA_DESIGN_ENTRY_SYNTHESIS_TOOL<br />
Type<br />
Specifies the third-party EDA tool used for design entry/synthesis<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL <br />
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL -entity<br />
<br />
Default Value<br />
None<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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4–64 Chapter 4: Analysis & Synthesis Assignments<br />
EDA_INPUT_DATA_FORMAT<br />
EDA_INPUT_DATA_FORMAT<br />
Type<br />
Specifies the format of the input data read from other EDA design entry/synthesis<br />
tools.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name EDA_INPUT_DATA_FORMAT -section_id <br />
set_global_assignment -name EDA_INPUT_DATA_FORMAT -entity -<br />
section_id <br />
Default Value<br />
None, requires section identifier<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–65<br />
EDA_INPUT_GND_NAME<br />
EDA_INPUT_GND_NAME<br />
Type<br />
Specifies the global high signal used in the files generated by the EDA synthesis tool,<br />
which is GND.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name EDA_INPUT_GND_NAME -section_id <br />
set_global_assignment -name EDA_INPUT_GND_NAME -entity -<br />
section_id <br />
Default Value<br />
GND, requires section identifier<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–66 Chapter 4: Analysis & Synthesis Assignments<br />
EDA_INPUT_VCC_NAME<br />
EDA_INPUT_VCC_NAME<br />
Type<br />
Specifies the global power-down signal.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name EDA_INPUT_VCC_NAME -section_id <br />
set_global_assignment -name EDA_INPUT_VCC_NAME -entity -<br />
section_id <br />
Default Value<br />
VCC, requires section identifier<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–67<br />
EDA_LMF_FILE<br />
EDA_LMF_FILE<br />
Type<br />
Specifies the default Library Mapping <strong>File</strong> (.lmf) for the current compilation.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDA_LMF_FILE -section_id <br />
<br />
set_global_assignment -name EDA_LMF_FILE -entity -section_id<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–68 Chapter 4: Analysis & Synthesis Assignments<br />
EDA_RUN_TOOL_AUTOMATICALLY<br />
EDA_RUN_TOOL_AUTOMATICALLY<br />
Type<br />
Runs the third-party EDA tool automatically from <strong>Quartus</strong> <strong>II</strong> when a design is<br />
compiled.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY -section_id<br />
<br />
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY -entity -section_id <br />
Default Value<br />
Off, requires section identifier<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–69<br />
EDA_SHOW_LMF_MAPPING_MESSAGES<br />
EDA_SHOW_LMF_MAPPING_MESSAGES<br />
Type<br />
Determines whether to display messages describing the mappings used in the Library<br />
Mapping <strong>File</strong> (.lmf).<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES -section_id<br />
<br />
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES -entity -section_id <br />
Default Value<br />
Off, requires section identifier<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–70 Chapter 4: Analysis & Synthesis Assignments<br />
EDA_VHDL_LIBRARY<br />
EDA_VHDL_LIBRARY<br />
Type<br />
Specifies the logical name of a user-defined VHDL design library, which is a physical<br />
name.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_instance_assignment -name EDA_VHDL_LIBRARY -to -section_id<br />
<br />
set_instance_assignment -name EDA_VHDL_LIBRARY -to -entity -section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–71<br />
ENABLE_IP_DEBUG<br />
ENABLE_IP_DEBUG<br />
Type<br />
Make certain nodes (for example, important registers, pins, and state machines)<br />
visible for all the MegaCore functions in a design. You can use a MegaCore function’s<br />
nodes to effectively debug the megafunction, particularly when using the<br />
megafunction with the SignalTap <strong>II</strong> Logic Analyzer. The Node Finder, using SignalTap<br />
<strong>II</strong> Logic Analyzer filters, displays all the nodes that Analysis & Synthesis makes<br />
visible. When making the debugging nodes visible, Analysis & Synthesis can change<br />
the f max and number of logic cells in MegaCore functions.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name ENABLE_IP_DEBUG <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–72 Chapter 4: Analysis & Synthesis Assignments<br />
ENABLE_M512<br />
ENABLE_M512<br />
Type<br />
Enables the Compiler to use M512 memory blocks in a design. Because HardCopy <strong>II</strong><br />
designs do not support M512 memory blocks, this option is useful when you migrate<br />
a compiled Stratix <strong>II</strong> design to a HardCopy <strong>II</strong> design.<br />
This option can be used as a project-wide option only.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name ENABLE_M512 <br />
Example<br />
set_global_assignment -name enable_m512 off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–73<br />
EXTRACT_VERILOG_STATE_MACHINES<br />
EXTRACT_VERILOG_STATE_MACHINES<br />
Type<br />
Allows the Compiler to extract state machines from Verilog Design <strong>File</strong>s (.v). The<br />
Compiler optimizes state machines using special techniques to reduce area and/or<br />
improve performance. If set to Off, the Compiler extracts and optimizes state<br />
machines in Verilog Design <strong>File</strong>s (.v) as regular logic.<br />
This option is useful for preventing automatic state machine optimizations to<br />
manually optimized logic.<br />
This option can be used as a project-wide option only.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES <br />
Example<br />
set_global_assignment -name extract_verilog_state_machines off<br />
Default Value<br />
On<br />
See Also<br />
■ “STATE_MACHINE_PROCESSING” on page 4–158<br />
■ “EXTRACT_VHDL_STATE_MACHINES” on page 4–74<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–74 Chapter 4: Analysis & Synthesis Assignments<br />
EXTRACT_VHDL_STATE_MACHINES<br />
EXTRACT_VHDL_STATE_MACHINES<br />
Type<br />
Allows the Compiler to extract state machines from VHDL Design <strong>File</strong>s (.vhd). The<br />
Compiler optimizes state machines using special techniques to reduce area and/or<br />
improve performance. If set to Off, the Compiler extracts and optimizes state<br />
machines in VHDL Design <strong>File</strong>s (.vhd) as regular logic.<br />
This option is useful for preventing automatic state machine optimizations to<br />
manually optimized logic.<br />
This option can be used as a project-wide option only.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES <br />
Example<br />
set_global_assignment -name extract_vhdl_state_machines off<br />
Default Value<br />
On<br />
See Also<br />
■ “STATE_MACHINE_PROCESSING” on page 4–158<br />
■ “EXTRACT_VERILOG_STATE_MACHINES” on page 4–73<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–75<br />
FAMILY<br />
FAMILY<br />
Type<br />
Specifies the device family to use for compilation.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
C<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name FAMILY <br />
Default Value<br />
Cyclone IV GX<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–76 Chapter 4: Analysis & Synthesis Assignments<br />
FORCE_SYNCH_CLEAR<br />
FORCE_SYNCH_CLEAR<br />
Type<br />
Forces the Compiler to use synchronous clear signals in normal mode logic cells.<br />
Turning on this option helps to reduce the total number of logic cells used in the<br />
design, but might negatively impact the fitting since synchronous control signals are<br />
shared by all the logic cells in a LAB.<br />
This option defaults to Off.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–77<br />
FORCE_SYNCH_CLEAR<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name FORCE_SYNCH_CLEAR <br />
set_global_assignment -name FORCE_SYNCH_CLEAR -entity <br />
<br />
set_instance_assignment -name FORCE_SYNCH_CLEAR -to -entity <br />
Example<br />
set_global_assignment -name force_synch_clear on<br />
set_instance_assignment -name force_synch_clear on -to foo<br />
Default Value<br />
Off<br />
See Also<br />
■ “ALLOW_SYNCH_CTRL_USAGE” on page 4–15<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–78 Chapter 4: Analysis & Synthesis Assignments<br />
HDL_INITIAL_FANOUT_LIMIT<br />
HDL_INITIAL_FANOUT_LIMIT<br />
Type<br />
Directs the <strong>Quartus</strong> <strong>II</strong> Integrated Synthesis to check the initial fan-out of each net in<br />
the netlist immediately after elaboration but prior to any netlist optimizations. If the<br />
fan-out for a net in the post-elaboration netlist exceeds the specified limit, the <strong>Quartus</strong><br />
<strong>II</strong> Integrated Synthesis issues a warning. The post-elaboration netlist is the initial<br />
netlist created by elaborating a single entity in your HDL source. Later synthesis and<br />
fitter optimizations may reduce or increase the fan-out of the nets in the netlist.<br />
This option is useful for identifying high-fanout signals early in the design process.<br />
This option is ignored if applied to anything other than an entity or an instance of an<br />
entity.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name HDL_INITIAL_FANOUT_LIMIT -entity <br />
<br />
set_instance_assignment -name HDL_INITIAL_FANOUT_LIMIT -to -entity<br />
<br />
Example<br />
set_instance_assignment -name hdl_initial_fanout_limit 100 -to foo<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–79<br />
HDL_MESSAGE_LEVEL<br />
HDL_MESSAGE_LEVEL<br />
Type<br />
Specifies the type of HDL messages you want to view, including messages that<br />
display processing errors in the HDL source code.<br />
■ Level1—Allows you to view only the most important HDL messages.<br />
■ Level2—Allows you to view most HDL messages, including warning and<br />
information based messages.<br />
■ Level3—Allows you to view all HDL messages, including warning and<br />
information based messages and alerts about potential design problems or lint<br />
errors.<br />
Enumeration<br />
■ Level1<br />
■ Level2<br />
■ Level3<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name HDL_MESSAGE_LEVEL <br />
Default Value<br />
Level2<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–80 Chapter 4: Analysis & Synthesis Assignments<br />
HDL_MESSAGE_OFF<br />
HDL_MESSAGE_OFF<br />
Type<br />
Specifies the list of HDL message IDs you want to turn off for this project.<br />
Integer<br />
Device Support<br />
The value must be from 10000 to 11000<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name HDL_MESSAGE_OFF <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–81<br />
HDL_MESSAGE_ON<br />
HDL_MESSAGE_ON<br />
Type<br />
Specifies the list of HDL message IDs you want to turn on for this project.<br />
Integer<br />
Device Support<br />
The value must be from 10000 to 11000<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name HDL_MESSAGE_ON <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–82 Chapter 4: Analysis & Synthesis Assignments<br />
HPS_PARTITION<br />
HPS_PARTITION<br />
Type<br />
Specifies whether an entity or instance is a special-purpose partition that models the<br />
internals of the Hard Processor System (HPS).<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name HPS_PARTITION -entity <br />
set_instance_assignment -name HPS_PARTITION -to -entity <br />
<br />
Example<br />
set_instance_assignment -name hps_partition on -entity hps<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–83<br />
IGNORE_CARRY_BUFFERS<br />
IGNORE_CARRY_BUFFERS<br />
Type<br />
Ignores CARRY_SUM buffers that are instantiated in the design. The Ignore CARRY<br />
Buffers option is ignored if it is applied to anything other than an individual<br />
CARRY_SUM buffer or to a design entity containing CARRY_SUM buffers. This<br />
option also applies to MAX+PLUS <strong>II</strong>-style CARRY buffers.<br />
This option defaults to Off.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name IGNORE_CARRY_BUFFERS <br />
set_global_assignment -name IGNORE_CARRY_BUFFERS -entity <br />
<br />
set_instance_assignment -name IGNORE_CARRY_BUFFERS -to -entity<br />
<br />
Example<br />
set_global_assignment -name ignore_carry_buffers on<br />
set_instance_assignment -name ignore_carry_buffers on -to foo<br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–84 Chapter 4: Analysis & Synthesis Assignments<br />
IGNORE_CASCADE_BUFFERS<br />
IGNORE_CASCADE_BUFFERS<br />
Type<br />
Ignores CASCADE buffers that are instantiated in the design. This option is ignored if<br />
it is applied to anything other than an individual CASCADE buffer or a design entity<br />
containing CASCADE buffers.<br />
This option defaults to Off.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name IGNORE_CASCADE_BUFFERS <br />
set_global_assignment -name IGNORE_CASCADE_BUFFERS -entity <br />
<br />
set_instance_assignment -name IGNORE_CASCADE_BUFFERS -to -entity<br />
<br />
Example<br />
set_global_assignment -name ignore_cascade_buffers on<br />
set_instance_assignment -name ignore_cascade_buffers on -to foo<br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–85<br />
IGNORE_GLOBAL_BUFFERS<br />
IGNORE_GLOBAL_BUFFERS<br />
Type<br />
Ignores GLOBAL buffers that are instantiated in the design. This option is ignored if it<br />
is applied to anything other than an individual GLOBAL buffer or a design entity<br />
containing GLOBAL buffers.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name IGNORE_GLOBAL_BUFFERS <br />
set_global_assignment -name IGNORE_GLOBAL_BUFFERS -entity <br />
<br />
set_instance_assignment -name IGNORE_GLOBAL_BUFFERS -to -entity<br />
<br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–86 Chapter 4: Analysis & Synthesis Assignments<br />
IGNORE_LCELL_BUFFERS<br />
IGNORE_LCELL_BUFFERS<br />
Type<br />
Ignores LCELL buffers that are instantiated in the design. This option is ignored if it is<br />
applied to anything other than an individual LCELL buffer or a design entity<br />
containing LCELL buffers.<br />
This option defaults to Off.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–87<br />
IGNORE_LCELL_BUFFERS<br />
Syntax<br />
set_global_assignment -name IGNORE_LCELL_BUFFERS <br />
set_global_assignment -name IGNORE_LCELL_BUFFERS -entity <br />
<br />
set_instance_assignment -name IGNORE_LCELL_BUFFERS -to -entity<br />
<br />
Example<br />
set_global_assignment -name ignore_lcell_buffers on<br />
set_instance_assignment -name ignore_lcell_buffers on -to foo<br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–88 Chapter 4: Analysis & Synthesis Assignments<br />
IGNORE_MAX_FANOUT_ASSIGNMENTS<br />
IGNORE_MAX_FANOUT_ASSIGNMENTS<br />
Type<br />
Directs the Compiler to ignore the Maximum Fan-Out assignments on a node, an<br />
entity, or the whole design. For HC<strong>II</strong> migration, the Maximum Fan-Out assignments<br />
can cause mismatches in Revision Compare. One can remove the Maximum Fan-Out<br />
assignments from the project but it is inconvenient/impossible as some assignments<br />
are embedded in the HDL sources. One should turn on this assignment to direct<br />
<strong>Quartus</strong> <strong>II</strong> to ignore the Maximum Fan-Out assignments.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–89<br />
IGNORE_MAX_FANOUT_ASSIGNMENTS<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS <br />
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS -entity <br />
set_instance_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS -to -<br />
entity <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–90 Chapter 4: Analysis & Synthesis Assignments<br />
IGNORE_ROW_GLOBAL_BUFFERS<br />
IGNORE_ROW_GLOBAL_BUFFERS<br />
Type<br />
Ignores ROW GLOBAL buffers that are instantiated in the design. This option is<br />
ignored if it is applied to anything other than an individual GLOBAL buffer or a<br />
design entity containing GLOBAL buffers.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS <br />
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS -entity <br />
set_instance_assignment -name IGNORE_ROW_GLOBAL_BUFFERS -to -entity<br />
<br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–91<br />
IGNORE_SOFT_BUFFERS<br />
IGNORE_SOFT_BUFFERS<br />
Type<br />
Ignores SOFT buffers that are instantiated in the design. This option is ignored if it is<br />
applied to anything other than an individual SOFT buffer or a design entity<br />
containing SOFT buffers.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–92 Chapter 4: Analysis & Synthesis Assignments<br />
IGNORE_SOFT_BUFFERS<br />
Syntax<br />
set_global_assignment -name IGNORE_SOFT_BUFFERS <br />
set_global_assignment -name IGNORE_SOFT_BUFFERS -entity <br />
<br />
set_instance_assignment -name IGNORE_SOFT_BUFFERS -to -entity <br />
Example<br />
set_global_assignment -name ignore_soft_buffers off<br />
set_instance_assignment -name ignore_soft_buffers off -to foo<br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–93<br />
IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF<br />
IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF<br />
Type<br />
Instructs Analysis & Synthesis to ignore all translate_off or synthesis_off<br />
synthesis directives in your Verilog and VHDL design files. You can use this option to<br />
disable these synthesis directives and include previously ignored code during<br />
elaboration.<br />
You can use this option to compile code that was previously ignored by third-party<br />
synthesis tools, for example, megafunction declarations that were treated as blackboxes<br />
in other tools but that may be compiled in the <strong>Quartus</strong> <strong>II</strong> software.<br />
This option defaults to Off.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF <br />
Example<br />
set_global_assignment -name ignore_translate_off_and_synthesis_off on<br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–94 Chapter 4: Analysis & Synthesis Assignments<br />
IGNORE_VERILOG_INITIAL_CONSTRUCTS<br />
IGNORE_VERILOG_INITIAL_CONSTRUCTS<br />
Type<br />
Instructs Analysis & Synthesis to ignore initial constructs and variable declaration<br />
assignments in your Verilog HDL design files. By default, Analysis & Synthesis<br />
derives power-up conditions for your design by elaborating these constructs. This<br />
option is provided for backwards compatibility with previous versions of the <strong>Quartus</strong><br />
<strong>II</strong> software that ignored these constructs by default. You can use this option to restore<br />
the previous behavior of your design in the current version of the software.<br />
This option defaults to Off.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS <br />
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS -entity<br />
<br />
set_instance_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS -to -<br />
entity <br />
Example<br />
set_global_assignment -name ignore_verilog_initial_constructs off<br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–95<br />
IMPLEMENT_AS_CLOCK_ENABLE<br />
IMPLEMENT_AS_CLOCK_ENABLE<br />
Type<br />
Specifies that this node should function as a clock enable signal for one or more<br />
registers.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–96 Chapter 4: Analysis & Synthesis Assignments<br />
IMPLEMENT_AS_CLOCK_ENABLE<br />
Syntax<br />
set_instance_assignment -name IMPLEMENT_AS_CLOCK_ENABLE -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–97<br />
IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL<br />
IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL<br />
Type<br />
Implements the output of a primitive in a logic cell. You can apply this option to a<br />
logic function that would not ordinarily be implemented in a logic cell, typically a<br />
combinatorial function such as an AND2 gate. Implementing the output of a primitive<br />
a logic cell makes it possible to observe its output in simulation and timing analysis.<br />
However, because an additional logic cell is used, overall device utilization will<br />
increase. This option does not insert an additional logic cell on a function that is<br />
already implemented in a logic cell, such as a flipflop. This option is ignored if it is<br />
applied to anything other than a primitive.<br />
This option can be assigned to an individual node only.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL -to -<br />
entity <br />
Example<br />
set_instance_assignment -name implement_as_output_of_logic_cell on -to foo<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–98 Chapter 4: Analysis & Synthesis Assignments<br />
INFER_RAMS_FROM_RAW_LOGIC<br />
INFER_RAMS_FROM_RAW_LOGIC<br />
Type<br />
Instructs the Compiler to infer RAM from registers and multiplexers. Some HDL<br />
patterns that differ from <strong>Altera</strong> RAM templates are initially converted into logic.<br />
However, these structures function as RAM and, because of that, the Compiler may<br />
create an altsyncram megafunction instance for them at a later stage when this<br />
assignment is on. With this assignment on, the Compiler may use more device RAM<br />
resources and less LABs.<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC <br />
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC -entity <br />
set_instance_assignment -name INFER_RAMS_FROM_RAW_LOGIC -to -entity<br />
<br />
Example<br />
set_global_assignment -name infer_rams_from_raw_logic off<br />
set_instance_assignment -name infer_rams_from_raw_logic off -to foo<br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–99<br />
LCELL_INSERTION<br />
LCELL_INSERTION<br />
Type<br />
Allows you to insert one or more logic cells between two nodes without changing the<br />
design files. The value you assign this option is the number of logic cells you want to<br />
insert. The inserted logic cell(s) act as a simple buffer and do not alter the functionality<br />
of the design. For more detailed information, go to <strong>Quartus</strong> <strong>II</strong> online help.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_instance_assignment -name LCELL_INSERTION -to -entity <br />
set_instance_assignment -name LCELL_INSERTION -from -to -<br />
entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–100 Chapter 4: Analysis & Synthesis Assignments<br />
LIMIT_AHDL_INTEGERS_TO_32_BITS<br />
LIMIT_AHDL_INTEGERS_TO_32_BITS<br />
Type<br />
Specifies whether an AHDL-based design should have a limit on integer size of 32<br />
bits. This option is provided for backward compatibility with pre-2000.09 releases of<br />
the <strong>Quartus</strong> software, which do not support integers larger than 32 bits in AHDL.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–101<br />
MAX7000_FANIN_PER_CELL<br />
MAX7000_FANIN_PER_CELL<br />
Type<br />
Specifies the maximum fan-in per macrocell. Legal integer values, in percentage<br />
terms, range from 20 through 100.<br />
You can use this option to improve the fitting of a design. The Maximum Fan-in Per<br />
Macrocell option allows you to spread routing resources and reduce congestion in a<br />
design.<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option defaults to 100.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name MAX7000_FANIN_PER_CELL <br />
set_global_assignment -name MAX7000_FANIN_PER_CELL -entity <br />
<br />
set_instance_assignment -name MAX7000_FANIN_PER_CELL -to -entity<br />
<br />
Example<br />
set_global_assignment -name max7000_fanin_per_cell 20<br />
set_instance_assignment -name max7000_fanin_per_cell 20 -to foo<br />
Default Value<br />
100<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–102 Chapter 4: Analysis & Synthesis Assignments<br />
MAX7000_FANIN_PER_CELL<br />
Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–103<br />
MAX7000_IGNORE_LCELL_BUFFERS<br />
MAX7000_IGNORE_LCELL_BUFFERS<br />
Type<br />
Ignores LCELL buffers that are instantiated in the design. This option is ignored if it is<br />
applied to anything other than an individual LCELL buffer or a design entity<br />
containing LCELL buffers.<br />
This option defaults to Auto.<br />
Enumeration<br />
■ Auto<br />
■ Off<br />
■ On<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS <br />
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS -entity <br />
set_instance_assignment -name MAX7000_IGNORE_LCELL_BUFFERS -to -<br />
entity <br />
Example<br />
set_global_assignment -name max7000_ignore_lcell_buffers on<br />
set_instance_assignment -name max7000_ignore_lcell_buffers on -to foo<br />
Default Value<br />
AUTO<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–104 Chapter 4: Analysis & Synthesis Assignments<br />
MAX7000_IGNORE_LCELL_BUFFERS<br />
Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–105<br />
MAX7000_IGNORE_SOFT_BUFFERS<br />
MAX7000_IGNORE_SOFT_BUFFERS<br />
Type<br />
Ignores SOFT buffers that are instantiated in the design. This option is ignored if it is<br />
applied to anything other than an individual SOFT buffer or a design entity<br />
containing SOFT buffers.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS <br />
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS -entity <br />
set_instance_assignment -name MAX7000_IGNORE_SOFT_BUFFERS -to -entity<br />
<br />
Example<br />
set_global_assignment -name max7000_ignore_soft_buffers on<br />
set_instance_assignment -name max7000_ignore_soft_buffers on -to foo<br />
Default Value<br />
Off<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–106 Chapter 4: Analysis & Synthesis Assignments<br />
MAX7000_OPTIMIZATION_TECHNIQUE<br />
MAX7000_OPTIMIZATION_TECHNIQUE<br />
Type<br />
Specifies the overall optimization goal for Analysis & Synthesis, which is to maximize<br />
performance, minimize logic usage, or balance high performance with minimal logic<br />
usage during compilation.You can select one of the following settings:<br />
You can select one of the following settings:<br />
■ Area—The Compiler makes the design as small as possible in order to minimize<br />
resource usage.<br />
■ Speed—The Compiler chooses a design implementation that has the fastest f max.<br />
■ Balanced—The Compiler chooses a design implementation that balances high<br />
performance with minimal logic usage.<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option defaults to Speed.<br />
Enumeration<br />
■ Area<br />
■ Balanced<br />
■ Speed<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE <br />
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE -entity <br />
set_instance_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE -to -<br />
entity <br />
Example<br />
set_global_assignment -name max7000_optimization_technique balanced<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–107<br />
MAX7000_OPTIMIZATION_TECHNIQUE<br />
Default Value<br />
Speed<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–108 Chapter 4: Analysis & Synthesis Assignments<br />
MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH<br />
MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH<br />
Type<br />
Specifies the maximum allowable length of a chain of Compiler-synthesized parallel<br />
expander product terms.<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option defaults to 4.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH <br />
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH -entity<br />
<br />
set_instance_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH -to<br />
-entity <br />
Example<br />
set_global_assignment -name max7000_parallel_expander_chain_length 3<br />
Default Value<br />
4<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–109<br />
MAX<strong>II</strong>_OPTIMIZATION_TECHNIQUE<br />
MAX<strong>II</strong>_OPTIMIZATION_TECHNIQUE<br />
Type<br />
Specifies the overall optimization goal for Analysis & Synthesis, which is to maximize<br />
performance, minimize logic usage, or balance high performance with minimal logic<br />
usage during compilation.You can select one of the following settings:<br />
■ Area—The Compiler makes the design as small as possible in order to minimize<br />
resource usage.<br />
■ Speed—The Compiler chooses a design implementation that has the fastest f max.<br />
■ Balanced—The Compiler chooses a design implementation that balances high<br />
performance with minimal logic usage.<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option defaults to Balanced.<br />
Enumeration<br />
■ Area<br />
■ Balanced<br />
■ Speed<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name MAX<strong>II</strong>_OPTIMIZATION_TECHNIQUE <br />
set_global_assignment -name MAX<strong>II</strong>_OPTIMIZATION_TECHNIQUE -entity <br />
set_instance_assignment -name MAX<strong>II</strong>_OPTIMIZATION_TECHNIQUE -to -<br />
entity <br />
Example<br />
set_global_assignment -name maxii_optimization_technique speed<br />
Default Value<br />
Balanced<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–110 Chapter 4: Analysis & Synthesis Assignments<br />
MAX<strong>II</strong>_OPTIMIZATION_TECHNIQUE<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
Optimization Technique -- MAX <strong>II</strong><br />
TSUNAMI_OPTIMIZATION_TECHNIQUE<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–111<br />
MAX_AUTO_GLOBAL_REGISTER_CONTROLS<br />
MAX_AUTO_GLOBAL_REGISTER_CONTROLS<br />
Type<br />
Allows the Compiler to choose the signals that feed the most control signal inputs to<br />
flipflops (excluding clock signals) as global signals that are made available<br />
throughout the device on the global routing paths. Depending on the target device<br />
family, these control signals can include asynchronous clear and load, synchronous<br />
clear and load, clock enable, and preset signals. This option is ignored if it is assigned<br />
to anything other than a design entity. If you want to prevent the Compiler from<br />
automatically selecting a particular signal as global register control signal, set the<br />
Global Signal option to Off on that signal.<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
Syntax<br />
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS <br />
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS -entity<br />
<br />
set_instance_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS -to -<br />
entity <br />
Example<br />
set_global_assignment -name max_auto_global_register_controls off<br />
set_instance_assignment -name max_auto_global_register_controls off -to<br />
foo<br />
Default Value<br />
On<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–112 Chapter 4: Analysis & Synthesis Assignments<br />
MAX_AUTO_GLOBAL_REGISTER_CONTROLS<br />
Auto Global Register Control Signals -- MAX 7000B/7000AE/3000A/7000S/7000A<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–113<br />
MAX_BALANCING_DSP_BLOCKS<br />
MAX_BALANCING_DSP_BLOCKS<br />
Type<br />
Allows you to specify the maximum number of DSP blocks that the DSP block<br />
balancer will assume exist in the current device for each partition. This option<br />
overrides the usual method of using the maximum number of DSP blocks the current<br />
device supports. For HardCopy <strong>II</strong> devices, the number of DSP blocks represents the<br />
number of DSP blocks used in the equivalent Stratix <strong>II</strong> device. This option is useful for<br />
HardCopy <strong>II</strong> device migration, where the number of DSP blocks that can be<br />
implemented in a HardCopy <strong>II</strong> device is more than the number of DSP blocks that can<br />
be implemented in its equivalent Stratix <strong>II</strong> device. This option is also useful in<br />
incremental compilation to set different DSP block usage limits for different<br />
partitions.<br />
You can use this option as a project-wide option or on a specific partition by setting<br />
the assignment on the instance name of the partition root. The assignment on a<br />
partition overrides the global assignment, if any, for that particular partition.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–114 Chapter 4: Analysis & Synthesis Assignments<br />
MAX_BALANCING_DSP_BLOCKS<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS <br />
set_instance_assignment -name MAX_BALANCING_DSP_BLOCKS -to -entity<br />
<br />
Example<br />
set_global_assignment -name max_balancing_dsp_blocks 4<br />
set_instance_assignment -name max_balancing_dsp -to<br />
"my_partition_root_entity:my_partition_root_entity_inst"<br />
Default Value<br />
-1 (Unlimited)<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–115<br />
MAX_FANOUT<br />
MAX_FANOUT<br />
Type<br />
Directs the Compiler to control the number of destinations the specified node feeds so<br />
the fan-out count does not exceed the value specified as the maximum number of fanout<br />
allowed from the node.<br />
You can use this option to reduce the load of critical signals, which improves<br />
performance.<br />
This option is ignored if it is applied to anything other than a register or a logic cell<br />
buffer, or a design entity that contains registers or logic cell buffers.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–116 Chapter 4: Analysis & Synthesis Assignments<br />
MAX_FANOUT<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_global_assignment -name MAX_FANOUT -entity <br />
set_instance_assignment -name MAX_FANOUT -to -entity <br />
<br />
Example<br />
set_instance_assignment -name max_fanout 10 -to foo<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–117<br />
MAX_LABS<br />
MAX_LABS<br />
Type<br />
Allows you to specify the maximum number of LABs that Analysis & Synthesis may<br />
use for a device. This option overrides the usual method of using the maximum<br />
number of LABs the current device supports, when the value is non-negative and is<br />
less than the maximum number of LABs available on the current device.<br />
This option is ignored when the value is greater than the maximum number of LABs<br />
available on the current device.<br />
You can use this option in incremental compilation to set different lab usage limits for<br />
different partitions.<br />
You can use this option as a project-wide option or on a specific partition by setting<br />
the assignment on the instance name of the partition root. The assignment on a<br />
partition overrides the global assignment, if any, for that particular partition.<br />
You can use this option for device migration.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name MAX_LABS <br />
set_instance_assignment -name MAX_LABS -to -entity <br />
<br />
Example<br />
set_global_assignment -name max_labs 100<br />
Default Value<br />
-1 (Unlimited)<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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4–118 Chapter 4: Analysis & Synthesis Assignments<br />
MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS<br />
MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS<br />
Type<br />
Allows you to specify the maximum number of registers that Analysis & Synthesis<br />
can use for conversion of uninferred RAMs. You can use this option as a project-wide<br />
option or on a specific partition by setting the assignment on the instance name of the<br />
partition root.<br />
The assignment on a partition overrides the global assignment (if any) for that<br />
particular partition.<br />
This option prevents synthesis from causing long compilations and running out of<br />
memory when many registers are used for uninferred RAMs. Instead of continuing<br />
the compilation, the <strong>Quartus</strong> <strong>II</strong> software issues an error and exits.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS<br />
<br />
set_instance_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS<br />
-to -entity <br />
Example<br />
set_global_assignment -name max_number_of_registers_from_uninferred_rams<br />
2048<br />
Default Value<br />
-1 (Unlimited)<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–119<br />
MAX_RAM_BLOCKS_M4K<br />
MAX_RAM_BLOCKS_M4K<br />
Type<br />
Allows you to specify the maximum number of M4K, M9K, M20K, or M10K memory<br />
blocks that the Compiler may use for a device. This option overrides the usual<br />
method of using the maximum number of M4K, M9K, M20K, or M10K memory<br />
blocks the current device supports, when the value is non-negative and is less than<br />
the maximum number of M4K, M9K, M20K, or M10K memory blocks available on the<br />
current device.<br />
This option is also useful in incremental compilation to set different M4K, M9K,<br />
M20K, or M10K memory block usage limits for different partitions.<br />
This option can be used as a project-wide option or on a specific partition by setting<br />
the assignment on the instance name of the partition root. The assignment on a<br />
partition overrides the global assignment (if any) for that particular partition.<br />
This option is useful for device migration.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–120 Chapter 4: Analysis & Synthesis Assignments<br />
MAX_RAM_BLOCKS_M4K<br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name MAX_RAM_BLOCKS_M4K <br />
set_instance_assignment -name MAX_RAM_BLOCKS_M4K -to -entity <br />
Example<br />
set_global_assignment -name max_ram_blocks_m4k 4<br />
Default Value<br />
-1 (Unlimited)<br />
See Also<br />
■ “MAX_RAM_BLOCKS_M512” on page 4–121<br />
■ “MAX_RAM_BLOCKS_MRAM” on page 4–123<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–121<br />
MAX_RAM_BLOCKS_M512<br />
MAX_RAM_BLOCKS_M512<br />
Type<br />
Allows you to specify the maximum number of M512 memory blocks that the<br />
Compiler may use for a device. This option overrides the usual method of using the<br />
maximum number of M512 memory blocks the current device supports, when the<br />
value is non-negative and is less than the maximum number of M512 memory blocks<br />
available on the current device.<br />
This option is also useful in incremental compilation to set different M512 memory<br />
block usage limits for different partitions.<br />
This option can be used as a project-wide option or on a specific partition by setting<br />
the assignment on the instance name of the partition root. The assignment on a<br />
partition overrides the global assignment, if any, for that particular partition.<br />
This option is useful for device migration.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name MAX_RAM_BLOCKS_M512 <br />
set_instance_assignment -name MAX_RAM_BLOCKS_M512 -to -entity <br />
Example<br />
set_global_assignment -name max_ram_blocks_m512 4<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–122 Chapter 4: Analysis & Synthesis Assignments<br />
MAX_RAM_BLOCKS_M512<br />
Default Value<br />
-1 (Unlimited)<br />
See Also<br />
■ “MAX_RAM_BLOCKS_M4K” on page 4–119<br />
■ “MAX_RAM_BLOCKS_MRAM” on page 4–123<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–123<br />
MAX_RAM_BLOCKS_MRAM<br />
MAX_RAM_BLOCKS_MRAM<br />
Type<br />
Allows you to specify the maximum number of M-RAM or M144K memory blocks<br />
that the Compiler may use for a device. This option overrides the usual method of<br />
using the maximum number of M-RAM or M144K memory blocks the selected device<br />
supports, when the value is non-negative and is less than the maximum number of M-<br />
RAM or M144K memory blocks available on the current device.<br />
This option is also useful in incremental compilation to set different M-RAM or<br />
M144K memory block usage limits for different partitions.<br />
This option can be used as a project-wide option or on a specific partition by setting<br />
the assignment on the instance name of the partition root. The assignment on a<br />
partition overrides the global assignment (if any) for that particular partition.<br />
This option is useful for device migration.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name MAX_RAM_BLOCKS_MRAM <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–124 Chapter 4: Analysis & Synthesis Assignments<br />
MAX_RAM_BLOCKS_MRAM<br />
set_instance_assignment -name MAX_RAM_BLOCKS_MRAM -to -entity <br />
Example<br />
set_global_assignment -name max_ram_blocks_mram 4<br />
Default Value<br />
-1 (Unlimited)<br />
See Also<br />
■ “MAX_RAM_BLOCKS_M512” on page 4–121<br />
■ “MAX_RAM_BLOCKS_M4K” on page 4–119<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–125<br />
MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED _THROUGH_MODE_SETTING_DONT_CARE<br />
MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED<br />
_THROUGH_MODE_SETTING_DONT_CARE<br />
Type<br />
Allows you to specify whether you want the TimeQuest Timing Analyzer to evaluate<br />
timing constraints between the write and the read operation of the MLAB memory<br />
block. Performing a write and read operation simultaneously at the same address<br />
might result in metastability because no timing constraints between those operations<br />
exist by default. Turning on this option introduces timing constraints between the<br />
write and read operation on the MLAB memory block and thereby avoids<br />
metastability issues; however, turning on this option degrades the performance of the<br />
MLAB memory blocks. If your design does not perform write and read operations<br />
simultaneously at the same address you do not need to set this option.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name<br />
MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_<br />
CARE -entity <br />
set_instance_assignment -name<br />
MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_<br />
CARE -to -entity <br />
set_global_assignment -name<br />
MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_<br />
CARE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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4–126 Chapter 4: Analysis & Synthesis Assignments<br />
MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED _THROUGH_MODE_SETTING_DONT_CARE<br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–127<br />
MUX_RESTRUCTURE<br />
MUX_RESTRUCTURE<br />
Type<br />
Allows the Compiler to reduce the number of logic elements required to implement<br />
multiplexers in a design. You can use this option if your design contains buses of<br />
fragmented multiplexers. This option restructures multiplexers more efficiently for<br />
area, allowing the design to implement multiplexers with a reduced number of logic<br />
elements.<br />
The following three settings are available:<br />
■ On—Allows the Compiler to minimize your design area. This setting decreases<br />
logic element usage but may negatively affect design clock speed (f MAX).<br />
■ Off—Multiplexer restructuring is disabled in the design. This setting does not<br />
decrease logic element usage and does not affect design clock speed (f MAX).<br />
■ Auto—Allows the <strong>Quartus</strong> <strong>II</strong> software to determine whether multiplexer<br />
restructuring should be enabled. The <strong>Quartus</strong> <strong>II</strong> software uses other synthesis<br />
settings, for example, the Optimization Technique option, to determine if<br />
multiplexer restructuring should be applied to the design. This setting decreases<br />
logic element usage but may negatively affect design clock speed ( fMAX).<br />
The Restructure Multiplexers option works on entire trees of multiplexers.<br />
Multiplexers may arise in different parts of the design through VHDL or Verilog<br />
constructs such as “if”, “case”, or “?:”. When multiplexers from one part of the design<br />
feed multiplexers in another part of the design, trees of multiplexers are formed. The<br />
Restructure Multiplexers option identifies buses of multiplexer trees that have a<br />
similar structure. Multiplexer buses occur most often as a result of multiplexing<br />
together vectors in Verilog, or array types such as STD_LOGIC_VECTOR in VHDL.<br />
When turned on, the Restructure Multiplexers option optimizes the structure of each<br />
multiplexer bus for the target device to reduce the overall number of logic elements<br />
used in the design.<br />
You can use this option as a project-wide option, or assigned to a design entity.<br />
This option defaults to Auto.<br />
Enumeration<br />
■ Auto<br />
■ Off<br />
■ On<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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4–128 Chapter 4: Analysis & Synthesis Assignments<br />
MUX_RESTRUCTURE<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name MUX_RESTRUCTURE <br />
set_global_assignment -name MUX_RESTRUCTURE -entity <br />
set_instance_assignment -name MUX_RESTRUCTURE -to -entity <br />
Example<br />
set_global_assignment -name mux_restructure off<br />
set_instance_assignment -name mux_restructure on -to accel<br />
Default Value<br />
Auto<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–129<br />
NOT_GATE_PUSH_BACK<br />
NOT_GATE_PUSH_BACK<br />
Type<br />
Allows the Compiler to push an inversion (that is, a NOT gate) back through a<br />
register and implement it on that register's data input if it is necessary to implement<br />
the design. If this option is turned on, a register may power up to an active-high state,<br />
so it may need to be explicitly cleared during initial operation of the device. This<br />
option is ignored if it is applied to anything other than an individual register or a<br />
design entity containing registers. If it is applied to an output pin that is directly fed<br />
by a register, it is automatically transferred to that register.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name NOT_GATE_PUSH_BACK -entity <br />
<br />
set_instance_assignment -name NOT_GATE_PUSH_BACK -to -entity <br />
set_global_assignment -name NOT_GATE_PUSH_BACK <br />
Example<br />
set_global_assignment -name not_gate_push_back off<br />
set_instance_assignment -name not_gate_push_back off -to reg<br />
Default Value<br />
On<br />
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NUMBER_OF_INVERTED_REGISTERS_REPORTED<br />
NUMBER_OF_INVERTED_REGISTERS_REPORTED<br />
Type<br />
Allows you to specify the maximum number of inverted registers that the Synthesis<br />
Report should display.<br />
Legal values are integers starting from 0. The value of 0 means that there is no report<br />
panel about inverted registers in the Synthesis report.<br />
The default value is 100.<br />
This option can be used as a project-wide option only.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED <br />
Example<br />
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 200<br />
Default Value<br />
100<br />
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NUMBER_OF_REMOVED_REGISTERS_REPORTED<br />
NUMBER_OF_REMOVED_REGISTERS_REPORTED<br />
Type<br />
Allows you to specify the maximum number of removed registers that the Synthesis<br />
Report should display.<br />
Legal values are integers starting from 0. The value of 0 means that there will be no<br />
report panel about removed registers in the Synthesis report.<br />
The default value is 5000.<br />
This option can be used as a project-wide option only.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED <br />
Example<br />
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 200<br />
Default Value<br />
5000<br />
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NUMBER_OF_SWEPT_NODES_REPORTED<br />
NUMBER_OF_SWEPT_NODES_REPORTED<br />
Type<br />
Allows you to specify the maximum number of swept nodes that the Synthesis Report<br />
displays. A swept node is any node which was eliminated from your design because<br />
the <strong>Quartus</strong> <strong>II</strong> software found the node to be unnecessary.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED <br />
Example<br />
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 200<br />
Default Value<br />
5000<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–133<br />
OPTIMIZATION_TECHNIQUE<br />
OPTIMIZATION_TECHNIQUE<br />
Type<br />
Specifies the overall optimization goal for Analysis & Synthesis, which is to maximize<br />
performance, minimize logic usage, or balance high performance with minimal logic<br />
usage during compilation.<br />
You can select one of the following settings:<br />
■ Area—The Compiler makes the design as small as possible in order to minimize<br />
resource usage.<br />
■ Speed—The Compiler chooses a design implementation that has the fastest f MAX.<br />
■ Balanced—The Compiler chooses a design implementation that balances high<br />
performance with minimal logic usage.<br />
You can use this option as a project-wide option, or assigned to a design entity.<br />
This option defaults to Balanced.<br />
This option is applicable to Stratix IV and Stratix V.<br />
Enumeration<br />
■ Area<br />
■ Balanced<br />
■ Speed<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone V<br />
■ HardCopy IV<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name OPTIMIZATION_TECHNIQUE <br />
set_global_assignment -name OPTIMIZATION_TECHNIQUE -entity <br />
<br />
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OPTIMIZATION_TECHNIQUE<br />
set_instance_assignment -name OPTIMIZATION_TECHNIQUE -to -entity<br />
<br />
Example<br />
set_global_assignment -name optimization_technique speed<br />
Default Value<br />
Balanced<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
Optimization Technique -- Stratix IV<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–135<br />
OPTIMIZE_POWER_DURING_SYNTHESIS<br />
OPTIMIZE_POWER_DURING_SYNTHESIS<br />
Type<br />
Controls the power-driven compilation setting of Analysis & Synthesis. This option<br />
determines how aggressively Analysis & Synthesis optimizes the design for power. If<br />
this option is set to Off, Analysis & Synthesis does not perform any power<br />
optimizations. If this option is set to Normal compilation, Analysis & Synthesis<br />
performs power optimizations as long as they are not expected to reduce design<br />
performance. When this option is set to Extra effort, Analysis & Synthesis performs<br />
additional power optimizations which may reduce design performance.<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option defaults to Normal compilation.<br />
Enumeration<br />
■ Extra effort<br />
■ Normal compilation<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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4–136 Chapter 4: Analysis & Synthesis Assignments<br />
OPTIMIZE_POWER_DURING_SYNTHESIS<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS <br />
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS -entity<br />
<br />
set_instance_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS -to -<br />
entity <br />
Example<br />
set_global_assignment -name optimize_power_during_synthesis off<br />
Default Value<br />
Normal compilation<br />
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Chapter 4: Analysis & Synthesis Assignments 4–137<br />
PARALLEL_SYNTHESIS<br />
PARALLEL_SYNTHESIS<br />
Type<br />
Enables or disables parallel synthesis.<br />
This option is used as a project-wide option.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name PARALLEL_SYNTHESIS <br />
Example<br />
set_global_assignment -name parallel_synthesis on<br />
Default Value<br />
On<br />
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PARAMETER<br />
PARAMETER<br />
Type<br />
Assigns an attribute that determines the logic created or used to implement the<br />
function, for example, the width of a bus. Parameters are characteristics that<br />
determine the size, behavior, or silicon implementation of a function. Parameter<br />
values are inherited from project defaults or higher hierarchical levels unless you<br />
make explicit assignments to individual nodes. Parameters are also overridden by<br />
explicit logic synthesis and fitting options.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_parameter <br />
set_parameter -entity <br />
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POWER_UP_LEVEL<br />
POWER_UP_LEVEL<br />
Type<br />
Causes a register to power up with the specified logic level, either High (1) or Low (0).<br />
If this option is specified for an input pin, it is automatically transferred to the register<br />
that is driven by the pin if the following conditions are present:<br />
■ There is no intervening logic, other than inversion, between the pin and the<br />
register<br />
■ The input pin drives the data input of the register<br />
■ The input pin does not fan-out to any other logic<br />
If this option is specified for an output or bidirectional pin, it is automatically<br />
transferred to the register that feeds the pin if the following conditions are present:<br />
■ There is no intervening logic, other than inversion, between the register and the<br />
pin<br />
■ The register does not fan-out to any other logic<br />
You can assign this option to any register, or to a pin with any logic configuration<br />
other than those previously described. You can also assign this option to a design<br />
entity containing registers if you want to set the power level for all registers in the<br />
design entity. In order for the register to power up with the specified logic level, the<br />
Compiler may perform NOT Gate Push-Back on the register.<br />
You can assign this option to any register, registered logic cell WYSIWYG primitive, or<br />
to a pin with any logic configuration other than those described above. If this option is<br />
assigned to a registered logic cell WYSIWYG primitive, you must turn on the Perform<br />
WYSIWYG Primitive Resynthesis logic option for it to take effect. You can also<br />
assign this option to a design entity containing registers if you want to set the power<br />
level for all registers in the design entity. In order for the register to power up with the<br />
specified logic level, the Compiler may perform NOT Gate Push-Back on the register.<br />
Enumeration<br />
■ High<br />
■ Low<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_global_assignment -name POWER_UP_LEVEL -entity <br />
set_instance_assignment -name POWER_UP_LEVEL -to -entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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4–140 Chapter 4: Analysis & Synthesis Assignments<br />
POWER_UP_LEVEL<br />
Example<br />
set_instance_assignment -name power_up_level low -to foo<br />
See Also<br />
■ “ALLOW_POWER_UP_DONT_CARE” on page 4–12<br />
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Chapter 4: Analysis & Synthesis Assignments 4–141<br />
PRESERVE_FANOUT_FREE_NODE<br />
PRESERVE_FANOUT_FREE_NODE<br />
Type<br />
Prevents a register that has no fan-out from being removed during synthesis.<br />
A logic option that specifies that the register should be preserved in the design even<br />
when it becomes fan-out free.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Syntax<br />
set_instance_assignment -name PRESERVE_FANOUT_FREE_NODE -to -entity <br />
<br />
Example<br />
set_instance_assignment -name preserve_fanout_free_node on -to reg<br />
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PRESERVE_REGISTER<br />
PRESERVE_REGISTER<br />
Type<br />
Prevents a register from minimizing away during synthesis and prevents sequential<br />
netlist optimizations. Sequential netlist optimizations can eliminate redundant<br />
registers and registers with constant drivers.<br />
This option is useful for preserving a register so you can observe it during Simulation.<br />
It is also useful for creating a preliminary version of the design in which secondary<br />
signals are not specified. This option is ignored if the register does not drive anything,<br />
in which case, the register will be removed by the netlist optimization.<br />
This option is ignored if it is applied to anything other than a register or a design<br />
entity that contains registers.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_global_assignment -name PRESERVE_REGISTER -entity <br />
<br />
set_instance_assignment -name PRESERVE_REGISTER -to -entity <br />
Example<br />
set_instance_assignment -name preserve_register on -to foo<br />
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Chapter 4: Analysis & Synthesis Assignments 4–143<br />
PRE_MAPPING_RESYNTHESIS<br />
PRE_MAPPING_RESYNTHESIS<br />
Type<br />
Specifies that the <strong>Quartus</strong> <strong>II</strong> software should perform a resynthesis optimization step<br />
immediately before technology mapping. The On setting increases design<br />
performance, which increases design clock speed (f MAX) but may also slightly increase<br />
logic element usage and compilation time. The Off selection disables this<br />
optimization.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name PRE_MAPPING_RESYNTHESIS <br />
Default Value<br />
Off<br />
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RBCGEN_CRITICAL_WARNING_TO_ERROR<br />
RBCGEN_CRITICAL_WARNING_TO_ERROR<br />
Type<br />
Converts the critical warning of the <strong>Quartus</strong> <strong>II</strong> software to error.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR <br />
Default Value<br />
On<br />
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Chapter 4: Analysis & Synthesis Assignments 4–145<br />
REMOVE_DUPLICATE_REGISTERS<br />
REMOVE_DUPLICATE_REGISTERS<br />
Type<br />
Removes a register if it is identical to another register. If two registers generate the<br />
same logic, the second register is deleted and the first register fans out to the<br />
destination of the second register. Also, if the deleted register has different logic<br />
option assignments, they are ignored. You can use this option to prevent the Compiler<br />
from removing duplicate registers that you have used deliberately. Perform this by<br />
setting the option to Off. This option is ignored if it is applied to anything other than<br />
an individual register or a design entity containing registers.<br />
This option is ignored if it is assigned to anything other than an individual register or<br />
a design entity containing registers.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
This assignment supports wildcards.<br />
Syntax<br />
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS <br />
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS -entity <br />
set_instance_assignment -name REMOVE_DUPLICATE_REGISTERS -to -entity<br />
<br />
Example<br />
set_global_assignment -name remove_duplicate_registers off<br />
set_instance_assignment -name remove_duplicate_registers off -to foo<br />
Default Value<br />
On<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
DUPLICATE_REGISTER_EXTRACTION<br />
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REMOVE_REDUNDANT_LOGIC_CELLS<br />
REMOVE_REDUNDANT_LOGIC_CELLS<br />
Type<br />
Removes redundant LCELL primitives or WYSIWYG primitives. Turning this option<br />
on optimizes a circuit for area and speed. This option is ignored if it is applied to<br />
anything other than a design entity.<br />
This option defaults to Off.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–147<br />
REMOVE_REDUNDANT_LOGIC_CELLS<br />
Syntax<br />
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS -entity <br />
set_instance_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS -to -<br />
entity <br />
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS <br />
Example<br />
set_global_assignment -name remove_redundant_logic_cells on<br />
set_instance_assignment -name remove_redundant_logic_cells on -to node<br />
Default Value<br />
Off<br />
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REPORT_CONNECTIVITY_CHECKS<br />
REPORT_CONNECTIVITY_CHECKS<br />
Type<br />
Specifies whether the synthesis report should include the panels in the Connectivity<br />
Checks folder<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS <br />
Default Value<br />
On<br />
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Chapter 4: Analysis & Synthesis Assignments 4–149<br />
REPORT_PARAMETER_SETTINGS<br />
REPORT_PARAMETER_SETTINGS<br />
Type<br />
Specifies whether the synthesis report should include the panels in the Parameter<br />
<strong>Settings</strong> by Entity Instance folder<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name REPORT_PARAMETER_SETTINGS <br />
Default Value<br />
On<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT<br />
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REPORT_SOURCE_ASSIGNMENTS<br />
REPORT_SOURCE_ASSIGNMENTS<br />
Type<br />
Specifies whether the synthesis report should include the panels in the Source<br />
Assignments folder<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS <br />
Default Value<br />
On<br />
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Chapter 4: Analysis & Synthesis Assignments 4–151<br />
RESYNTHESIS_PHYSICAL_SYNTHESIS<br />
RESYNTHESIS_PHYSICAL_SYNTHESIS<br />
Type<br />
Specifies the physical synthesis level for resynthesis.<br />
Enumeration<br />
■ Advanced<br />
■ Normal<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS -section_id<br />
<br />
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS -entity -section_id <br />
Default Value<br />
Normal, requires section identifier<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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4–152 Chapter 4: Analysis & Synthesis Assignments<br />
RESYNTHESIS_RETIMING<br />
RESYNTHESIS_RETIMING<br />
Type<br />
Specifies the paths on which retiming is performed, which are all paths, register-toregister<br />
paths only, or none.<br />
Enumeration<br />
■ Core<br />
■ Full<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name RESYNTHESIS_RETIMING -section_id <br />
set_global_assignment -name RESYNTHESIS_RETIMING -entity -<br />
section_id <br />
Default Value<br />
Full, requires section identifier<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–153<br />
SAFE_STATE_MACHINE<br />
SAFE_STATE_MACHINE<br />
Type<br />
Directs the Compiler to implement state machines that can recover gracefully from an<br />
illegal state.<br />
This option can be applied globally or to a specific entity or node.<br />
Implementation of such safe state machines can result in some area increase.<br />
This option defaults to Off.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name SAFE_STATE_MACHINE -entity <br />
<br />
set_instance_assignment -name SAFE_STATE_MACHINE -to -entity <br />
set_global_assignment -name SAFE_STATE_MACHINE <br />
Example<br />
set_global_assignment -name safe_state_machine on<br />
set_instance_assignment -name safe_state_machine on -to foo<br />
Default Value<br />
Off<br />
See Also<br />
■ “STATE_MACHINE_PROCESSING” on page 4–158<br />
■ “EXTRACT_VERILOG_STATE_MACHINES” on page 4–73<br />
■ “EXTRACT_VHDL_STATE_MACHINES” on page 4–74<br />
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SAVE_DISK_SPACE<br />
SAVE_DISK_SPACE<br />
Type<br />
Saves disk space by reducing the number of node names available for entering<br />
assignments, simulation, timing analysis, reporting, and others.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name SAVE_DISK_SPACE <br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
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Chapter 4: Analysis & Synthesis Assignments 4–155<br />
SEARCH_PATH<br />
SEARCH_PATH<br />
Type<br />
Specifies the path name of a user-defined library.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name SEARCH_PATH <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL<br />
SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL<br />
Type<br />
Allows the Compiler to find a group of shift registers of the same length that can be<br />
replaced with the altshift_taps megafunction. The shift registers must all use the same<br />
aclr signals, must not have any other secondary signals, and must have equally<br />
spaced taps that are at least three registers apart. To use this option, you must turn on<br />
the Auto Shift Register Replacement logic option.<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL <br />
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL -entity<br />
<br />
set_instance_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL -to<br />
-entity <br />
Example<br />
set_global_assignment -name shift_register_recognition_aclr_signal off<br />
set_instance_assignment -name shift_register_recognition_aclr_signal off -<br />
to foo<br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–157<br />
SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES<br />
SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES<br />
Type<br />
Allows the Compiler to skip the fitting stage during smart recompilation when design<br />
changes may affect timing requirements. This option is available only for changes to<br />
Cyclone, Stratix, and Stratix GX PLL parameters, and Stratix GX gigabit transceiver<br />
block parameters.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name<br />
SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES <br />
Default Value<br />
Off<br />
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STATE_MACHINE_PROCESSING<br />
STATE_MACHINE_PROCESSING<br />
Type<br />
Specifies the processing style used to compile a state machine. You can use your own<br />
‘User-Encoded’ style, or select ‘One-Hot’, ‘Minimal Bits’, ‘Gray’, ‘Johnson’,<br />
‘Sequential’ or ‘Auto’ (Compiler-selected) encoding.<br />
The following settings are available:<br />
■ Auto—Allows the Compiler to choose the best encoding for the state machine<br />
■ Minimal Bits—Uses the minimal number of bits to encode the state machine<br />
■ One-Hot—Encodes the state machine in the one-hot style<br />
■ User-Encoded—Encodes the state machine in the manner that you specified<br />
■ Gray—Encodes the state machine in the Gray style<br />
■ Johnson—Encodes the state machine in the Johnson style<br />
■ Sequential—Encode the state machine in the sequential binary style.<br />
This option defaults to Auto.<br />
Enumeration<br />
■ Auto<br />
■ Gray<br />
■ Johnson<br />
■ Minimal Bits<br />
■ One-Hot<br />
■ Sequential<br />
Device Support<br />
■ User-Encoded<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name STATE_MACHINE_PROCESSING -entity <br />
<br />
set_instance_assignment -name STATE_MACHINE_PROCESSING -to -entity<br />
<br />
set_global_assignment -name STATE_MACHINE_PROCESSING <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–159<br />
STATE_MACHINE_PROCESSING<br />
Example<br />
set_global_assignment -name state_machine_processing "one-hot"<br />
set_instance_assignment -name state_machine_processing "one-hot" -to foo<br />
Default Value<br />
Auto<br />
See Also<br />
■ “EXTRACT_VERILOG_STATE_MACHINES” on page 4–73<br />
■ “EXTRACT_VHDL_STATE_MACHINES” on page 4–74<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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4–160 Chapter 4: Analysis & Synthesis Assignments<br />
STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_ DETECT_SIGNAL_THRESHOLD_SELECT<br />
STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_<br />
DETECT_SIGNAL_THRESHOLD_SELECT<br />
Type<br />
Directs the Compiler to not modify the Force Signal Detect and Signal Threshold<br />
Select parameters on gigabit transceiver block receiver channels.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_global_assignment -name<br />
STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT<br />
<br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–161<br />
STRATIX<strong>II</strong>_CARRY_CHAIN_LENGTH<br />
STRATIX<strong>II</strong>_CARRY_CHAIN_LENGTH<br />
Type<br />
Specifies the maximum allowable length of a chain of both user-entered and<br />
Compiler-synthesized CARRY_SUM buffers. Carry chains that exceed this length are<br />
broken into separate chains. This option also applies to MAX+PLUS <strong>II</strong>-style CARRY<br />
buffers.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name STRATIX<strong>II</strong>_CARRY_CHAIN_LENGTH <br />
set_global_assignment -name STRATIX<strong>II</strong>_CARRY_CHAIN_LENGTH -entity <br />
set_instance_assignment -name STRATIX<strong>II</strong>_CARRY_CHAIN_LENGTH -to -<br />
entity <br />
Default Value<br />
70<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–162 Chapter 4: Analysis & Synthesis Assignments<br />
STRATIX<strong>II</strong>_CARRY_CHAIN_LENGTH<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
ARMSTRONG_CARRY_CHAIN_LENGTH<br />
Carry Chain Length -- Stratix <strong>II</strong>/Stratix <strong>II</strong>I<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–163<br />
STRATIX<strong>II</strong>_OPTIMIZATION_TECHNIQUE<br />
STRATIX<strong>II</strong>_OPTIMIZATION_TECHNIQUE<br />
Type<br />
Specifies the overall optimization goal for Analysis & Synthesis, which is to maximize<br />
performance, minimize logic usage, or balance high performance with minimal logic<br />
usage during compilation.<br />
You can select one of the following settings:<br />
■ Area—The Compiler makes the design as small as possible in order to minimize<br />
resource usage<br />
■ Speed—The Compiler chooses a design implementation that has the fastest f MAX<br />
■ Balanced—The Compiler chooses a design implementation that balances high<br />
performance with minimal logic usage<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option defaults to Balanced.<br />
This option is applicable to Arria GX, HardCopy <strong>II</strong>, Stratix <strong>II</strong>, Stratix <strong>II</strong> GX, and Stratix<br />
<strong>II</strong>I devices.<br />
Enumeration<br />
■ Area<br />
■ Balanced<br />
■ Speed<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name STRATIX<strong>II</strong>_OPTIMIZATION_TECHNIQUE <br />
set_global_assignment -name STRATIX<strong>II</strong>_OPTIMIZATION_TECHNIQUE -entity<br />
<br />
set_instance_assignment -name STRATIX<strong>II</strong>_OPTIMIZATION_TECHNIQUE -to -<br />
entity <br />
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4–164 Chapter 4: Analysis & Synthesis Assignments<br />
STRATIX<strong>II</strong>_OPTIMIZATION_TECHNIQUE<br />
Example<br />
set_global_assignment -name stratixii_optimization_technique speed<br />
Default Value<br />
Balanced<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
ARMSTRONG_OPTIMIZATION_TECHNIQUE<br />
Optimization Technique -- Stratix <strong>II</strong>/<strong>II</strong>I/HardCopy <strong>II</strong>/Stratix <strong>II</strong> GX/Arria GX<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–165<br />
STRATIX_CARRY_CHAIN_LENGTH<br />
STRATIX_CARRY_CHAIN_LENGTH<br />
Type<br />
Specifies the maximum allowable length of a chain of both user-entered and<br />
Compiler-synthesized CARRY_SUM buffers. Carry chains that exceed this length are<br />
broken into separate chains. This option also applies to MAX+PLUS <strong>II</strong>-style CARRY<br />
buffers.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH <br />
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH -entity <br />
set_instance_assignment -name STRATIX_CARRY_CHAIN_LENGTH -to -entity<br />
<br />
Default Value<br />
70<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX <strong>II</strong>/Cyclone <strong>II</strong>/Cyclone <strong>II</strong>I<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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4–166 Chapter 4: Analysis & Synthesis Assignments<br />
STRATIX_OPTIMIZATION_TECHNIQUE<br />
STRATIX_OPTIMIZATION_TECHNIQUE<br />
Type<br />
Specifies the overall optimization goal for Analysis & Synthesis, which is to maximize<br />
performance, minimize logic usage, or balance high performance with minimal logic<br />
usage during compilation.<br />
You can select one of the following settings:<br />
■ Area—The Compiler makes the design as small as possible in order to minimize<br />
resource usage<br />
■ Speed—The Compiler chooses a design implementation that has the fastest f MAX<br />
■ Balanced—The Compiler chooses a design implementation that balances high<br />
performance with minimal logic usage<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option defaults to Balanced.<br />
This option is applicable to Stratix and Stratix GX devices.<br />
Enumeration<br />
■ Area<br />
■ Balanced<br />
■ Speed<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix<br />
■ Stratix GX<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE <br />
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE -entity <br />
set_instance_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE -to -<br />
entity <br />
Example<br />
set_global_assignment -name stratix_optimization_technique speed<br />
Default Value<br />
Balanced<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–167<br />
STRATIX_OPTIMIZATION_TECHNIQUE<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
Optimization Technique -- Stratix/Stratix GX<br />
YEAGER_OPTIMIZATION_TECHNIQUE<br />
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4–168 Chapter 4: Analysis & Synthesis Assignments<br />
STRICT_RAM_RECOGNITION<br />
STRICT_RAM_RECOGNITION<br />
Type<br />
When you set this option to On, the Compiler is only allowed to replace RAM if the<br />
hardware matches the design exactly.<br />
This option defaults to Off.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name STRICT_RAM_RECOGNITION <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–169<br />
STRICT_RAM_RECOGNITION<br />
set_global_assignment -name STRICT_RAM_RECOGNITION -entity <br />
<br />
set_instance_assignment -name STRICT_RAM_RECOGNITION -to -entity<br />
<br />
Example<br />
set_global_assignment -name strict_ram_recognition on<br />
set_global_assignment -name strict_ram_recognition on -to foo<br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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4–170 Chapter 4: Analysis & Synthesis Assignments<br />
SYNCHRONIZATION_REGISTER_CHAIN_LENGTH<br />
SYNCHRONIZATION_REGISTER_CHAIN_LENGTH<br />
Type<br />
This setting specifies the maximum number of registers in a row to be considered as a<br />
synchronization chain. Synchronization chains are sequences of registers with the<br />
same clock, no fanout in between, such that the first register is fed by a pin, or by logic<br />
in another clock domain. These registers are considered for metastability analysis<br />
(available for some families), and are also protected from optimizations such as<br />
retiming. When gate-level retiming is turned on, these registers are not moved. The<br />
default length is set to two.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–171<br />
SYNCHRONIZATION_REGISTER_CHAIN_LENGTH<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
This assignment supports wildcards.<br />
Syntax<br />
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH <br />
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH -entity<br />
<br />
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH -to<br />
-entity <br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
ADV_NETLIST_OPT_METASTABLE_REGS<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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4–172 Chapter 4: Analysis & Synthesis Assignments<br />
SYNTHESIS_EFFORT<br />
SYNTHESIS_EFFORT<br />
Type<br />
Controls the synthesis trade-off between compilation speed and performance and<br />
area. The default is Auto, which means synthesis goes through all its steps. You can<br />
select Fast, which means synthesis skips a number of steps which makes it<br />
approximately 30% faster, but at the cost of performance and area. <strong>Altera</strong><br />
recommends that you only use Fast when the Fitter early timing estimate flow is used.<br />
This is because the Fast synthesis results produces a netlist that is slightly harder for<br />
the Fitter to route, thus making the Fitter slower, which cancels out the speed-up of<br />
synthesis. The Fitter early timing estimate runtime is not affected by the synthesis<br />
effort level.<br />
Enumeration<br />
■ Auto<br />
■ Fast<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name SYNTHESIS_EFFORT <br />
Example<br />
set_global_assignment -name synthesis_effort fast<br />
Default Value<br />
Auto<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–173<br />
SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER<br />
SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER<br />
Type<br />
When this option is set to On, synthesis keeps the synchronous clear or preset<br />
behavior when remapping the I/O WYSIWYG primitives (from other device families)<br />
using the DDIO INPUT feature to the targeted device family.<br />
For example, the DDIO INPUT of the Stratix <strong>II</strong>I device family behaves differently<br />
from Stratix <strong>II</strong> when you use synchronous clear or preset behavior. For the Stratix <strong>II</strong>I<br />
device family, the synchronous clear or preset behavior affects all three registers,<br />
while it only affects the two capture registers in Stratix <strong>II</strong>.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name<br />
SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER -entity <br />
set_instance_assignment -name<br />
SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER -to -entity<br />
<br />
set_global_assignment -name<br />
SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER <br />
Example<br />
set_global_assignment -name<br />
synthesis_keep_synch_clear_preset_behavior_in_unmapper on<br />
set_instance_assignment -name<br />
synthesis_keep_synch_clear_preset_behavior_in_unmapper on -to foo<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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4–174 Chapter 4: Analysis & Synthesis Assignments<br />
SYNTHESIS_SEED<br />
SYNTHESIS_SEED<br />
Type<br />
Specifies the seed that Synthesis uses to randomly do synthesis in a slightly different<br />
way. This seed can be used when a design is close to meeting requirements, in order to<br />
get a slightly different result. The value can be any non-negative integer value.<br />
Changing the starting value may or may not produce better results.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name SYNTHESIS_SEED <br />
Default Value<br />
1<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–175<br />
SYNTH_CLOCK_MUX_PROTECTION<br />
SYNTH_CLOCK_MUX_PROTECTION<br />
Type<br />
Causes the multiplexers in the clock network to be decomposed to 2 to 1 multiplexer<br />
trees, and protected from being merged with, or transferred to, other logic. This<br />
option helps the TimeQuest timing analyzer to understand clock behavior.<br />
A clock multiplexer can cause glitches. <strong>Altera</strong> recommends that you use a clock<br />
control block instead.<br />
This option can be used as a project-wide option only.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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4–176 Chapter 4: Analysis & Synthesis Assignments<br />
SYNTH_CLOCK_MUX_PROTECTION<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION <br />
Example<br />
set_global_assignment -name synth_clock_mux_protection off<br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–177<br />
SYNTH_CRITICAL_CLOCK<br />
SYNTH_CRITICAL_CLOCK<br />
Type<br />
Specifies that all combinational logic in the given clock domain, or between the given<br />
clock domains, should be mapped with optimization technique speed.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–178 Chapter 4: Analysis & Synthesis Assignments<br />
SYNTH_CRITICAL_CLOCK<br />
Syntax<br />
set_instance_assignment -name SYNTH_CRITICAL_CLOCK -to -entity<br />
<br />
set_instance_assignment -name SYNTH_CRITICAL_CLOCK -from -to -<br />
entity <br />
Example<br />
set_instance_assignment -name synth_critical_clock on -to clock<br />
set_instance_assignment -name synth_critical_clock on -from clk1 -to clk2<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–179<br />
SYNTH_GATED_CLOCK_CONVERSION<br />
SYNTH_GATED_CLOCK_CONVERSION<br />
Type<br />
Automatically converts gated clocks in the design to use clock enable pins if clock<br />
enable pins are not used in the original design. Clock gating logic can contain AND,<br />
OR, MUX, and NOT gates. Turning on this option may increase memory use and<br />
overall run time. You must use the TimeQuest Timing Analyzer for timing analysis,<br />
and you must define all base clocks in Synopsys Design Constraints <strong>File</strong> (.sdc) format.<br />
You can use this option for ASIC prototyping flow on FPGA, and only works with the<br />
TimeQuest timing analyzer. For more information, refer to <strong>Quartus</strong> <strong>II</strong> Development<br />
Software Handbook on the <strong>Altera</strong> website.<br />
This option may cause memory usage and run time increase.<br />
You can use this option as a project-wide option, or assigned to a design entity.<br />
This option defaults to Off.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–180 Chapter 4: Analysis & Synthesis Assignments<br />
SYNTH_GATED_CLOCK_CONVERSION<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION -entity <br />
set_instance_assignment -name SYNTH_GATED_CLOCK_CONVERSION -to -<br />
entity <br />
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION <br />
Example<br />
set_global_assignment -name synth_gated_clock_conversion on<br />
set_instance_assignment -name synth_gated_clock_conversion on -to foo<br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–181<br />
SYNTH_MESSAGE_LEVEL<br />
SYNTH_MESSAGE_LEVEL<br />
Type<br />
Specifies the type of Analysis & Synthesis messages you want to view. Setting this<br />
option to Low allows you to view only the most important Analysis & Synthesis<br />
messages. Setting this option to Medium allows you to view most Analysis &<br />
Synthesis messages, but hides the detailed messages in Analysis & Synthesis report.<br />
Setting this option to High allows you to view all Analysis & Synthesis messages.<br />
Enumeration<br />
■ High<br />
■ Low<br />
■ Medium<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name SYNTH_MESSAGE_LEVEL <br />
Default Value<br />
Medium<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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4–182 Chapter 4: Analysis & Synthesis Assignments<br />
SYNTH_PROTECT_SDC_CONSTRAINT<br />
SYNTH_PROTECT_SDC_CONSTRAINT<br />
Type<br />
Causes SDC constraint checking in register merging. It helps to maintain the validity<br />
of SDC constraints through compilation.<br />
This option is useful for maintaining the validity of SDC constraints through<br />
compilation.<br />
This option may cause memory usage and run time increase.<br />
This option can be used as a project-wide option only.<br />
This option defaults to Off.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–183<br />
SYNTH_PROTECT_SDC_CONSTRAINT<br />
Syntax<br />
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT <br />
Example<br />
set_global_assignment -name synth_protect_sdc_constraint on<br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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4–184 Chapter 4: Analysis & Synthesis Assignments<br />
SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM<br />
SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM<br />
Type<br />
Specifies whether Analysis & Synthesis is allowed to use information about the device<br />
and design resources to decide which logical RAMs, ROMs, and shift-registers to infer<br />
from your HDL.<br />
You can use this option when regular synthesis infers more RAMs, ROMs, and shiftregisters<br />
to be implemented in block RAM than the device can fit. Resource-aware<br />
inference tries to estimate the required number of RAM blocks and registers for your<br />
design, and makes inference decisions based on the available device resources.<br />
This option can only be used for Cyclone, Cyclone <strong>II</strong>, Cyclone <strong>II</strong>I, Cyclone <strong>II</strong>I LS,<br />
Cyclone IV, Arria <strong>II</strong> GX, Stratix <strong>II</strong>I, HardCopy <strong>II</strong>I, Stratix IV and HardCopy IV<br />
families. It is ignored for other families.<br />
When you set this option to on, <strong>Altera</strong> recommends that you specify a device for the<br />
design. If no device is specified, then the RAM, ROM, and shift-register inference is<br />
not resource-aware.<br />
This option can be used as a project-wide option only.<br />
This option is turned on by default.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong>I<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–185<br />
SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM<br />
<br />
Example<br />
set_global_assignment -name synth_resource_aware_inference_for_block_ram<br />
on<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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4–186 Chapter 4: Analysis & Synthesis Assignments<br />
SYNTH_TIMING_DRIVEN_SYNTHESIS<br />
SYNTH_TIMING_DRIVEN_SYNTHESIS<br />
Type<br />
Allows the <strong>Quartus</strong> <strong>II</strong> Synthesis to use timing information during synthesis to<br />
optimize the design.<br />
When you turn this option on, the <strong>Quartus</strong> <strong>II</strong> Synthesis runs timing analysis to obtain<br />
timing information about the netlist, and optimizes the netlist accordingly. It also<br />
automatically applies the SDC Constraint Protection logic option.<br />
You can use this option when regular synthesis does not optimize the circuit well for<br />
the given timing constraints. When you set the Timing-Driven Synthesis option to<br />
on, you can expect Synthesis to perform better at the cost of some ALUTs and/or<br />
registers. Runtime and peak memory slightly increases as well.<br />
This option can only be used for Cyclone <strong>II</strong>, Cyclone <strong>II</strong>I, Cyclone <strong>II</strong>I LS, Cyclone IV,<br />
Arria <strong>II</strong> GX, Stratix <strong>II</strong>, HardCopy <strong>II</strong>, Stratix <strong>II</strong>I, HardCopy <strong>II</strong>I, Stratix IV and HardCopy<br />
IV families. It is ignored for other families. It is also ignored when the Synthesis Effort<br />
is set to Fast. Appropriate warnings are given when the option is ignored.<br />
When you set this option to on, <strong>Altera</strong> recommends that you specify a device for the<br />
design. If no device is specified, timing-driven synthesis automatically uses the<br />
smallest device in the family that satisfies design constraints like speed grade and<br />
package. It gives an error when no valid device can be found.<br />
This option can be used as a project-wide option only.<br />
This option defaults to Off.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–187<br />
SYNTH_TIMING_DRIVEN_SYNTHESIS<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS <br />
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -entity <br />
set_instance_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -to -<br />
entity <br />
Example<br />
set_global_assignment -name synth_timing_driven_synthesis on<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–188 Chapter 4: Analysis & Synthesis Assignments<br />
TOP_LEVEL_ENTITY<br />
TOP_LEVEL_ENTITY<br />
Type<br />
Specifies the full hierarchichal path of the entity that is the focus of the current<br />
compilation or simulation.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name TOP_LEVEL_ENTITY <br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
FOCUS_ENTITY_NAME<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–189<br />
TRUE_WYSIWYG_FLOW<br />
TRUE_WYSIWYG_FLOW<br />
Type<br />
Specifies that the <strong>Quartus</strong> <strong>II</strong> software should not try to optimize this WYSIWYG<br />
design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name TRUE_WYSIWYG_FLOW <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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4–190 Chapter 4: Analysis & Synthesis Assignments<br />
USER_LIBRARIES<br />
USER_LIBRARIES<br />
Type<br />
Specifies the pathnames of user-defined libraries.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name USER_LIBRARIES <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–191<br />
USE_HIGH_SPEED_ADDER<br />
USE_HIGH_SPEED_ADDER<br />
Type<br />
Directs the Compiler whether to use high speed adder circuitry to implement<br />
arithmetic functions or not. This option is useful for improving the performance of<br />
the design when set to On and minimizing the total number of HCells used in the<br />
design when set to Off.<br />
This option applies to HardCopy series devices only.<br />
This option defaults to Auto, which has the same behavior as On when the<br />
Optimization Technique is set to Speed or Balanced, and as Off when the<br />
Optimization Technique is set to Area.<br />
Enumeration<br />
■ Auto<br />
■ Off<br />
■ On<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name USE_HIGH_SPEED_ADDER <br />
set_global_assignment -name USE_HIGH_SPEED_ADDER -entity <br />
<br />
set_instance_assignment -name USE_HIGH_SPEED_ADDER -to -entity<br />
<br />
Example<br />
set_global_assignment -name use_high_speed_adder off<br />
Default Value<br />
Auto<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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4–192 Chapter 4: Analysis & Synthesis Assignments<br />
USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING<br />
USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING<br />
Type<br />
Directs the Compiler to use LogicLock constraints during DSP and RAM balancing,<br />
thus helping the balancer to make better balancing decisions.<br />
This option defaults to Off.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING <br />
Example<br />
set_global_assignment -name use_logiclock_constraints_in_balancing on<br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–193<br />
VERILOG_CONSTANT_LOOP_LIMIT<br />
VERILOG_CONSTANT_LOOP_LIMIT<br />
Type<br />
Defines the iteration limit for Verilog loops with loop conditions that evaluate to<br />
compile-time constants on each loop iteration. For example, such loops would have<br />
loop conditions that depend only on loop variables and constant expressions. If a loop<br />
condition refers to an input to the current module or to another variable other than a<br />
loop-variable, then the loop condition is most likely a non-constant loop condition,<br />
which has a separate limit in the <strong>Quartus</strong> <strong>II</strong> software. This logic option exists<br />
primarily to catch potential infinite loops before they exhaust memory or trap the<br />
software in an actual infinite loop. In general, you should only increase the value of<br />
this option, unless you are trying to identify a loop that requires excessive amounts of<br />
logic and therefore exhausts the memory available to the <strong>Quartus</strong> <strong>II</strong> software. If you<br />
decrease the value of this logic option, you may receive errors for loops that<br />
previously passed synthesis.<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option defaults to 5000.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT <br />
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT -entity <br />
set_instance_assignment -name VERILOG_CONSTANT_LOOP_LIMIT -to -entity<br />
<br />
Example<br />
set_global_assignment -name verilog_constant_loop_limit 3000<br />
Default Value<br />
5000<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–194 Chapter 4: Analysis & Synthesis Assignments<br />
VERILOG_INPUT_VERSION<br />
VERILOG_INPUT_VERSION<br />
Type<br />
Specifies the language dialect to use when processing Verilog Design <strong>File</strong>s, which are<br />
Verilog-1995 (IEEE Std. 1364-1995), Verilog-2001 (IEEE Std. 1364-2001), or<br />
SystemVerilog-2005 (IEEE Std. 1800-2005). Verilog 2001 is the default dialect.<br />
Enumeration<br />
Device Support<br />
■ SystemVerilog_2005<br />
■ Verilog_1995<br />
■ Verilog_2001<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name VERILOG_INPUT_VERSION <br />
Default Value<br />
Verilog_2001<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–195<br />
VERILOG_LMF_FILE<br />
VERILOG_LMF_FILE<br />
Type<br />
Specifies the default Library Mapping <strong>File</strong> (.lmf) for the current compilation.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name VERILOG_LMF_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–196 Chapter 4: Analysis & Synthesis Assignments<br />
VERILOG_MACRO<br />
VERILOG_MACRO<br />
Type<br />
Defines Verilog HDL macro - same as `define directive.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name VERILOG_MACRO <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–197<br />
VERILOG_NON_CONSTANT_LOOP_LIMIT<br />
VERILOG_NON_CONSTANT_LOOP_LIMIT<br />
Type<br />
Defines the iteration limit for Verilog loops with loop conditions that depend on<br />
inputs to the current module or on non-loop variables. When the loop condition does<br />
not evaluate to a constant true or false, the <strong>Quartus</strong> <strong>II</strong> software must create extra logic<br />
to account for the potential exit from the loop. This logic may accumulate over a<br />
number of iterations and exhaust the available memory. Eventually, the loop<br />
condition must evaluate to a constant false to terminate the loop. Otherwise, the<br />
<strong>Quartus</strong> <strong>II</strong> software exhausts the available memory or generate an error. This logic<br />
option exists primarily to catch potential infinite loops before they exhaust memory or<br />
trap the software in an actual infinite loop. In general, you should only increase the<br />
value of this option, unless you are trying to identify a loop that requires excessive<br />
amounts of logic and therefore exhausts the memory available to the <strong>Quartus</strong> <strong>II</strong><br />
software. If you decrease the value of this logic option, you may receive errors for<br />
loops that previously passed synthesis.<br />
This option can be used as a project-wide option, or assigned to a design entity.<br />
This option defaults to 250.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT <br />
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT -entity<br />
<br />
set_instance_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT -to -<br />
entity <br />
Example<br />
set_global_assignment -name verilog_non_constant_loop_limit 3000<br />
Default Value<br />
250<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–198 Chapter 4: Analysis & Synthesis Assignments<br />
VERILOG_SHOW_LMF_MAPPING_MESSAGES<br />
VERILOG_SHOW_LMF_MAPPING_MESSAGES<br />
Type<br />
Determines whether to display messages describing the mappings used in the Library<br />
Mapping <strong>File</strong> (.lmf).<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–199<br />
VHDL_INPUT_LIBRARY<br />
VHDL_INPUT_LIBRARY<br />
Type<br />
Specifies the logical name of a user-defined VHDL design library, which is a physical<br />
name.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_instance_assignment -name VHDL_INPUT_LIBRARY -to <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–200 Chapter 4: Analysis & Synthesis Assignments<br />
VHDL_INPUT_VERSION<br />
VHDL_INPUT_VERSION<br />
Type<br />
Specifies the language dialect to use when processing VHDL Design <strong>File</strong>s, which are<br />
VHDL-1987 (IEEE Std 1076-1987), VHDL-1993 (IEEE Std 1076-1993) or VHDL-2008<br />
(IEEE Std 1076-2008). VHDL-1993 is the default dialect.<br />
Enumeration<br />
■ VHDL_1987<br />
■ VHDL_1993<br />
■ VHDL_2008<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name VHDL_INPUT_VERSION <br />
Default Value<br />
VHDL_1993<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 4: Analysis & Synthesis Assignments 4–201<br />
VHDL_LMF_FILE<br />
VHDL_LMF_FILE<br />
Type<br />
Specifies the default Library Mapping <strong>File</strong> (.lmf) for the current compilation.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name VHDL_LMF_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
4–202 Chapter 4: Analysis & Synthesis Assignments<br />
VHDL_SHOW_LMF_MAPPING_MESSAGES<br />
VHDL_SHOW_LMF_MAPPING_MESSAGES<br />
Type<br />
Determines whether to display messages describing the mappings used in the Library<br />
Mapping <strong>File</strong> (.lmf).<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
ALLOW_MULTIPLE_PERSONAS<br />
Type<br />
© 2012 <strong>Altera</strong> Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos<br />
are trademarks of <strong>Altera</strong> Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as<br />
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. <strong>Altera</strong> warrants performance of its<br />
semiconductor products to current specifications in accordance with <strong>Altera</strong>'s standard warranty, but reserves the right to make changes to any products and<br />
services at any time without notice. <strong>Altera</strong> assumes no responsibility or liability arising out of the application or use of any information, product, or service<br />
described herein except as expressly agreed to in writing by <strong>Altera</strong>. <strong>Altera</strong> customers are advised to obtain the latest version of device specifications before relying<br />
on any published information and before placing orders for products or services.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong><br />
June 2012<br />
5. Incremental Compilation Assignments<br />
Specifies if this partition represents a reconfigurable part of the design that can have<br />
mulitple personas (implementations).<br />
Boolean<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name ALLOW_MULTIPLE_PERSONAS -entity <br />
-section_id <br />
set_instance_assignment -name ALLOW_MULTIPLE_PERSONAS -to -entity<br />
-section_id <br />
Default Value<br />
Off, requires section identifier and entity name<br />
ISO<br />
9001:2008<br />
Registered<br />
Subscribe
5–2 Chapter 5: Incremental Compilation Assignments<br />
AUTO_EXPORT_INCREMENTAL_COMPILATION<br />
AUTO_EXPORT_INCREMENTAL_COMPILATION<br />
Type<br />
Automatically exports the project as a design partition.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 5: Incremental Compilation Assignments 5–3<br />
IGNORE_PARTITIONS<br />
IGNORE_PARTITIONS<br />
Type<br />
Specifies whether the Compiler should ignore partition assignments in the project.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name IGNORE_PARTITIONS <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
5–4 Chapter 5: Incremental Compilation Assignments<br />
INCREMENTAL_COMPILATION_EXPORT_FILE<br />
INCREMENTAL_COMPILATION_EXPORT_FILE<br />
Type<br />
Specifies the path to the exported file. The file must have a <strong>Quartus</strong> <strong>II</strong> Exported<br />
Partition <strong>File</strong> (.qxp) extension.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 5: Incremental Compilation Assignments 5–5<br />
INCREMENTAL_COMPILATION_EXPORT_PARTITION_NAME<br />
INCREMENTAL_COMPILATION_EXPORT_PARTITION_NAME<br />
Type<br />
Specifies the name of the partition that contains the design hierarchy to be exported.<br />
The root partition is exported if this assignment is not specified.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_PARTITION_NAME <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
5–6 Chapter 5: Incremental Compilation Assignments<br />
INCREMENTAL_COMPILATION_EXPORT_POST_FIT<br />
INCREMENTAL_COMPILATION_EXPORT_POST_FIT<br />
Type<br />
Specifies whether the exported <strong>Quartus</strong> <strong>II</strong> Exported Partition <strong>File</strong> (.qxp) contains the<br />
post-fit netlist<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_POST_FIT<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 5: Incremental Compilation Assignments 5–7<br />
INCREMENTAL_COMPILATION_EXPORT_POST_SYNTH<br />
INCREMENTAL_COMPILATION_EXPORT_POST_SYNTH<br />
Type<br />
Specifies whether the exported <strong>Quartus</strong> <strong>II</strong> Exported Partition <strong>File</strong> (.qxp) contains the<br />
post-synthesis netlist.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_POST_SYNTH<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
5–8 Chapter 5: Incremental Compilation Assignments<br />
INCREMENTAL_COMPILATION_EXPORT_ROUTING<br />
INCREMENTAL_COMPILATION_EXPORT_ROUTING<br />
Type<br />
Specifies whether the post-fit netlist exported to the <strong>Quartus</strong> <strong>II</strong> Exported Partition <strong>File</strong><br />
(.qxp) contains routing information.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_ROUTING <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 5: Incremental Compilation Assignments 5–9<br />
INPUT_PERSONA<br />
INPUT_PERSONA<br />
Type<br />
Specifies the input persona file to use for this partition.<br />
<strong>File</strong> name<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name INPUT_PERSONA -entity -<br />
section_id <br />
set_instance_assignment -name INPUT_PERSONA -to -entity <br />
-section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
5–10 Chapter 5: Incremental Compilation Assignments<br />
PARTITION_ALWAYS_USE_QXP_NETLIST<br />
PARTITION_ALWAYS_USE_QXP_NETLIST<br />
Type<br />
Specifies whether to always use the netlist in the <strong>Quartus</strong> <strong>II</strong> Exported Partition <strong>File</strong><br />
(.qxp) associated with the partition, either because the <strong>Quartus</strong> <strong>II</strong> Exported Partition<br />
<strong>File</strong> (.qxp) is imported into the partition, or is specified as a source file for the<br />
partition. Setting defaults to Off.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST -entity<br />
-section_id <br />
set_instance_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST -to -<br />
entity -section_id <br />
Default Value<br />
Off, requires section identifier and entity name<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 5: Incremental Compilation Assignments 5–11<br />
PARTITION_FITTER_PRESERVATION_LEVEL<br />
PARTITION_FITTER_PRESERVATION_LEVEL<br />
Type<br />
Specifies the amount of data to reuse when you specify to reuse the post-fit netlist of<br />
this partition.<br />
Enumeration<br />
Device Support<br />
■ COMPATIBLE_PLACEMENT<br />
■ COMPATIBLE_PLACEMENT_AND_ROUTING<br />
■ NETLIST_ONLY<br />
■ PLACEMENT<br />
■ PLACEMENT_AND_ROUTING<br />
■ PLACEMENT_AND_ROUTING_AND_HIGH_SPEED_TILES<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL -entity<br />
-section_id <br />
set_instance_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL -to <br />
-entity -section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
5–12 Chapter 5: Incremental Compilation Assignments<br />
PARTITION_HIERARCHY<br />
PARTITION_HIERARCHY<br />
Type<br />
The target of the assignment specifies the hierarchy path of the entity instance for the<br />
partition. The value of the assignment specifies the base output filename for writing<br />
intermediary atom netlists. <strong>Altera</strong> recommends that you rely on the default output<br />
filenames generated by the <strong>Quartus</strong> <strong>II</strong> software. If you decide to provide your own<br />
filenames, you must ensure their uniqueness among partitions.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name PARTITION_HIERARCHY -entity -<br />
section_id <br />
set_instance_assignment -name PARTITION_HIERARCHY -to -entity -section_id <br />
set_global_assignment -name PARTITION_HIERARCHY -entity <br />
<br />
set_instance_assignment -name PARTITION_HIERARCHY -to -entity <br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
INCREMENTAL_DESIGN_PARTITION<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 5: Incremental Compilation Assignments 5–13<br />
PARTITION_IGNORE_SOURCE_FILE_CHANGES<br />
PARTITION_IGNORE_SOURCE_FILE_CHANGES<br />
Type<br />
Specifies whether to use the requested post-synthesis or post-fit netlist when it is<br />
available, even when source file changes are present. Setting defaults to Off.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES -entity<br />
-section_id <br />
set_instance_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES -to<br />
-entity -section_id <br />
Default Value<br />
Off, requires section identifier and entity name<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
5–14 Chapter 5: Incremental Compilation Assignments<br />
PARTITION_IMPORT_ASSIGNMENTS<br />
PARTITION_IMPORT_ASSIGNMENTS<br />
Type<br />
Specifies whether LogicLock or non-LogicLock assignments should be imported. If<br />
set to FALSE, only the netlist will be imported.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS -entity -section_id <br />
set_instance_assignment -name PARTITION_IMPORT_ASSIGNMENTS -to -<br />
entity -section_id <br />
Default Value<br />
On, requires section identifier and entity name<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 5: Incremental Compilation Assignments 5–15<br />
PARTITION_IMPORT_EXISTING_ASSIGNMENTS<br />
PARTITION_IMPORT_EXISTING_ASSIGNMENTS<br />
Type<br />
Specifies the way existing and conflicting non-LogicLock region assignments should<br />
be handled during import.<br />
Enumeration<br />
Device Support<br />
■ REPLACE_CONFLICTING<br />
■ SKIP_CONFLICTING<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS -entity<br />
-section_id <br />
set_instance_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS -to<br />
-entity -section_id <br />
Default Value<br />
REPLACE_CONFLICTING, requires section identifier and entity name<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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5–16 Chapter 5: Incremental Compilation Assignments<br />
PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS<br />
PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS<br />
Type<br />
Specifies the way existing and conflicting LogicLock region assignments should be<br />
handled during import.<br />
Enumeration<br />
Device Support<br />
■ REPLACE_CONFLICTING<br />
■ SKIP_CONFLICTING<br />
■ UPDATE_CONFLICTING<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS -<br />
entity -section_id <br />
set_instance_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS<br />
-to -entity -section_id <br />
Default Value<br />
REPLACE_CONFLICTING, requires section identifier and entity name<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 5: Incremental Compilation Assignments 5–17<br />
PARTITION_IMPORT_FILE<br />
PARTITION_IMPORT_FILE<br />
Type<br />
Specifies the name of the file from which to import the contents for the partition. This<br />
setting is only used during importation.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name PARTITION_IMPORT_FILE -entity -<br />
section_id <br />
set_instance_assignment -name PARTITION_IMPORT_FILE -to -entity<br />
-section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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5–18 Chapter 5: Incremental Compilation Assignments<br />
PARTITION_IMPORT_PROMOTE_ASSIGNMENTS<br />
PARTITION_IMPORT_PROMOTE_ASSIGNMENTS<br />
Type<br />
Specifies whether assignments should be promoted to all instances of the imported<br />
entity.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS -entity<br />
-section_id <br />
set_instance_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS -to<br />
-entity -section_id <br />
Default Value<br />
On, requires section identifier and entity name<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 5: Incremental Compilation Assignments 5–19<br />
PARTITION_LAST_IMPORTED_FILE<br />
PARTITION_LAST_IMPORTED_FILE<br />
Type<br />
Specifies the name of the file from which the partition was last imported. This<br />
assignment is for purely informational purpose only.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name PARTITION_LAST_IMPORTED_FILE -entity -section_id <br />
set_instance_assignment -name PARTITION_LAST_IMPORTED_FILE -to -<br />
entity -section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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5–20 Chapter 5: Incremental Compilation Assignments<br />
PARTITION_NETLIST_TYPE<br />
PARTITION_NETLIST_TYPE<br />
Type<br />
Specifies the type of netlist to use for this partition during the next compilation.<br />
Enumeration<br />
■ Auto<br />
■ EMPTY<br />
■ IMPORTED<br />
■ IMPORT_BASED_POST_FIT<br />
■ POST_FIT<br />
■ POST_FIT_WITH_ROUTING<br />
■ POST_SYNTH<br />
■ SOURCE<br />
Device Support<br />
■ STRICT_POST_FIT<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name PARTITION_NETLIST_TYPE -entity -<br />
section_id <br />
set_instance_assignment -name PARTITION_NETLIST_TYPE -to -entity<br />
-section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 5: Incremental Compilation Assignments 5–21<br />
PARTITION_PRESERVE_HIGH_SPEED_TILES<br />
PARTITION_PRESERVE_HIGH_SPEED_TILES<br />
Type<br />
Specifies whether to preserve the high-speed tiles in the post-fit netlist, if applicable.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES -entity<br />
-section_id <br />
set_instance_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES -to <br />
-entity -section_id <br />
Default Value<br />
On, requires section identifier and entity name<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
5–22 Chapter 5: Incremental Compilation Assignments<br />
PARTITION_PRESERVE_HIGH_SPEED_TILES<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
ACTIVE_SERIAL_CLOCK<br />
Type<br />
© 2012 <strong>Altera</strong> Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos<br />
are trademarks of <strong>Altera</strong> Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as<br />
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. <strong>Altera</strong> warrants performance of its<br />
semiconductor products to current specifications in accordance with <strong>Altera</strong>'s standard warranty, but reserves the right to make changes to any products and<br />
services at any time without notice. <strong>Altera</strong> assumes no responsibility or liability arising out of the application or use of any information, product, or service<br />
described herein except as expressly agreed to in writing by <strong>Altera</strong>. <strong>Altera</strong> customers are advised to obtain the latest version of device specifications before relying<br />
on any published information and before placing orders for products or services.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong><br />
June 2012<br />
6. Fitter Assignments<br />
Specifies the clock source for Fast Active Serial Programming. You can select an<br />
internal oscillator clock or an external clock as the clock source for Fast Active Serial<br />
programming. If you choose an external clock as the source, you can control exactly<br />
when the device enters user mode. The external clock is provided through the CLKUSR<br />
pin and you should enable user-supplied start-up clock (CLKUSR) option. The default is<br />
to use an internal oscillator clock of 40 MHz for Arria <strong>II</strong> GX and Cyclone IV devices,<br />
and 100 MHz for Stratix V and Arria V devices.<br />
Enumeration<br />
■ CLKUSR<br />
Device Support<br />
■ FREQ_100MHz<br />
■ FREQ_12_5MHz<br />
■ FREQ_20MHz<br />
■ FREQ_25MHz<br />
■ FREQ_40MHz<br />
■ FREQ_50MHz<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria V<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name ACTIVE_SERIAL_CLOCK <br />
ISO<br />
9001:2008<br />
Registered<br />
Subscribe
6–2 Chapter 6: Fitter Assignments<br />
ACTIVE_SERIAL_CLOCK<br />
Example<br />
set_global_assignment -name active_serial_clock "CLKUSR"<br />
See Also<br />
■ “USER_START_UP_CLOCK” on page 6–361<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–3<br />
ADCE_ENABLED<br />
ADCE_ENABLED<br />
Type<br />
Disables the Adaptive Dispersion Compensation Engine (ADCE) on a physical media<br />
attachment (PMA) direct channel for RX PMA. Setting this option to Off disables the<br />
ADCE. Setting this option to Auto leaves the ADCE setting unchanged. The default<br />
value is Auto.<br />
Enumeration<br />
■ Auto<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GZ<br />
■ HardCopy IV<br />
■ Stratix IV<br />
Syntax<br />
set_global_assignment -name ADCE_ENABLED <br />
set_instance_assignment -name ADCE_ENABLED -to <br />
Default Value<br />
Auto<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–4 Chapter 6: Fitter Assignments<br />
ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER<br />
ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER<br />
Type<br />
Specifies whether the Fitter allows input pins with LVTTL or LVCMOS I/O standards<br />
to be placed inside an I/O bank with a lower V CCIO voltage than the voltage specified<br />
by the pins. Overdriving the I/O bank results in higher leakage current, which can<br />
cause the design to not function as intended.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_global_assignment -name<br />
ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–5<br />
ALWAYS_ENABLE_INPUT_BUFFERS<br />
ALWAYS_ENABLE_INPUT_BUFFERS<br />
Type<br />
Enables input buffers on all I/O pins including output pins. This option is required<br />
for the SAMPLE/PRELOAD JTAG instruction to function correctly on output pins.<br />
Turning on this option consumes more power.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–6 Chapter 6: Fitter Assignments<br />
ASYNC_PIPELINE_DISABLE_DESTINATION_CHECK<br />
ASYNC_PIPELINE_DISABLE_DESTINATION_CHECK<br />
Type<br />
Allows the automatic asynchronous signal pipelining algorithm to run on the<br />
specified asynchronous signal even if it feeds synchronous inputs. However, turning<br />
this option On can change circuit functionality. This option is intended for advanced<br />
users<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name ASYNC_PIPELINE_DISABLE_DESTINATION_CHECK -<br />
entity <br />
set_instance_assignment -name ASYNC_PIPELINE_DISABLE_DESTINATION_CHECK -to<br />
-entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–7<br />
ASYNC_PIPELINE_REG_REACH<br />
ASYNC_PIPELINE_REG_REACH<br />
Type<br />
Specify the maximum number of LABs that the asynchronous signal sourcing at the<br />
To register can go across before a new pipeline register is inserted. This requirement<br />
might not be met for all pipeline stages, when, due to congestion or over-filled LABs,<br />
the register cannot be placed at the desired location.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name ASYNC_PIPELINE_REG_REACH -entity <br />
<br />
set_instance_assignment -name ASYNC_PIPELINE_REG_REACH -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–8 Chapter 6: Fitter Assignments<br />
AUTO_C3_M9K_BIT_SKIP<br />
AUTO_C3_M9K_BIT_SKIP<br />
Type<br />
Directs the Fitter to skip certain bitlines in Cyclone <strong>II</strong>I (including LS) M9K blocks that<br />
may be susceptible to read bit error when used in affected modes. The Standard<br />
setting reserves the necessary M9K bitlines to ensure correct operation for all devices<br />
within the selected temperature range. The Auto setting applies the necessary bitline<br />
reservation to additional modes (×16 or ×18) to provide extra margin. The Maximum<br />
setting applies the most conservative bitline reservation required for industrial<br />
temperature ranges regardless of the targeted device settings. Enabling any of these<br />
options can increase the number of M9K blocks required to implement the design.<br />
You can override this global setting for each memory instance in the Assignment<br />
Editor to customize the solution. Certain RAM modes may not be supported for<br />
commercial temperature range devices when the Standard or Auto setting is applied.<br />
The Fitter issues an error for these cases. You can implement RAM cells by making an<br />
instance assignment with the Maximum setting, in which case additional M9K blocks<br />
may be used. For more information, refer to the Cyclone <strong>II</strong>I Device Family Errata Sheet.<br />
Enumeration<br />
■ Auto<br />
■ Maximum<br />
■ Off<br />
■ Standard<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–9<br />
AUTO_DELAY_CHAINS<br />
AUTO_DELAY_CHAINS<br />
Type<br />
Allows the Fitter to choose the optimal delay chain to meet tsu and tco timing<br />
requirements for all I/O elements. Turning on this option may reduce the number of<br />
tsu violations while introducing a minimal number of th violations. Turning on this<br />
option does not override delay chain settings on individual nodes.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–10 Chapter 6: Fitter Assignments<br />
AUTO_DELAY_CHAINS<br />
Syntax<br />
set_global_assignment -name AUTO_DELAY_CHAINS <br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–11<br />
AUTO_GLOBAL_CLOCK<br />
AUTO_GLOBAL_CLOCK<br />
Type<br />
Allows the Compiler to choose the signal that feeds the most clock inputs to flipflops<br />
as a global clock signal that is made available throughout the device on the global<br />
routing paths. If you want to prevent the Compiler from automatically selecting a<br />
particular signal as global clock, set the Global Signal option to Off on that signal.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ EPC1<br />
■ EPC2<br />
■ Enhanced Configuration Devices<br />
■ FLEX10KB<br />
■ FLEX8000<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX9000<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–12 Chapter 6: Fitter Assignments<br />
AUTO_GLOBAL_CLOCK<br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name AUTO_GLOBAL_CLOCK <br />
set_global_assignment -name AUTO_GLOBAL_CLOCK -entity <br />
<br />
set_instance_assignment -name AUTO_GLOBAL_CLOCK -to -entity <br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–13<br />
AUTO_GLOBAL_MEMORY_CONTROLS<br />
AUTO_GLOBAL_MEMORY_CONTROLS<br />
Type<br />
Allows the Compiler to choose the signals that feed the most write enable and read<br />
enable inputs to memories as global write enable and read enable signals that are<br />
made available throughout the device on the global routing paths. If you want to<br />
prevent the Compiler from automatically selecting a particular signal as global<br />
memory control signal, set the Global Signal option to Off on that signal.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I LS<br />
■ HardCopy <strong>II</strong><br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS <br />
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS -entity <br />
set_instance_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS -to -entity<br />
<br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–14 Chapter 6: Fitter Assignments<br />
AUTO_GLOBAL_REGISTER_CONTROLS<br />
AUTO_GLOBAL_REGISTER_CONTROLS<br />
Type<br />
Allows the Compiler to choose the signals that feed the most control signal inputs to<br />
flipflops (excluding clock signals) as global signals that are made available<br />
throughout the device on the global routing paths. Depending on the target device<br />
family, these control signals can include asynchronous clear and load, synchronous<br />
clear and load, clock enable, and preset signals.If you want to prevent the Compiler<br />
from automatically selecting a particular signal as global register control signal, set<br />
the Global Signal option to Off on that signal.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ EPC1<br />
■ EPC2<br />
■ Enhanced Configuration Devices<br />
■ FLEX10KB<br />
■ FLEX8000<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX9000<br />
■ Stratix<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–15<br />
AUTO_GLOBAL_REGISTER_CONTROLS<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS <br />
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS -entity <br />
set_instance_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS -to -<br />
entity <br />
Default Value<br />
On<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–16 Chapter 6: Fitter Assignments<br />
AUTO_MERGE_PLLS<br />
AUTO_MERGE_PLLS<br />
Type<br />
Allows the Compiler to automatically find and merge together two compatible phaselocked<br />
loops (PLL) driven by the same clock source, reducing the total number of<br />
PLLs used in a design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name AUTO_MERGE_PLLS <br />
set_global_assignment -name AUTO_MERGE_PLLS -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–17<br />
AUTO_MERGE_PLLS<br />
set_instance_assignment -name AUTO_MERGE_PLLS -to -entity <br />
Default Value<br />
On<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–18 Chapter 6: Fitter Assignments<br />
AUTO_PACKED_REGISTERS_CYCLONE<br />
AUTO_PACKED_REGISTERS_CYCLONE<br />
Type<br />
Allows the Compiler to automatically implement a register and a combinational<br />
function in the same logic cell, or to implement registers using I/O cells or RAM<br />
blocks instead of logic cells. This option controls how aggressively the Fitter combines<br />
registers with other function blocks in order to reduce logic element count. If this<br />
option is set to Off, the Fitter does not attempt to place a pair of logic functions in a<br />
single logic cell; however, logic cells specified during synthesis to perform both a<br />
combinational and a sequential function are maintained. If this option is set to<br />
Normal, the Fitter places both a combinational and a sequential operation in a logic<br />
cell when it is expected that the placement does not affect design performance. When<br />
this option is set to Minimize Area, the Fitter aggressively combines unrelated<br />
sequential and combinational functions that are not part of an arithmetic or register<br />
cascade chain into a single logic cell in order to reduce the logic cell count, even at the<br />
expense of design performance. When this option is set to Minimize Area with<br />
Chains, the Fitter even more aggressively combines sequential and combinational<br />
functions that are part of arithmetic or register cascade chains or that can be converted<br />
to register cascade chains. When this setting is Auto, the fitter attempts to achieve the<br />
best performance while maintaining a fit for the design in the specified device. The<br />
fitter will combine all combinational and sequential functions that are deemed to<br />
benefit circuit speed. In addition, more aggressive combinations of unrelated<br />
combinational and sequential functions are performed to the extent required to<br />
reduce the area of the design in order to achieve a fit in the specified device. If this<br />
option is set to any value but Off, registers are merged with I/O cells to improve I/O<br />
timing, and with RAM blocks to reduce logic cell count or improve timing when<br />
possible.<br />
Enumeration<br />
■ Auto<br />
■ Minimize Area<br />
■ Minimize Area with Chains<br />
■ Normal<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–19<br />
AUTO_PACKED_REGISTERS_CYCLONE<br />
set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE -entity <br />
set_instance_assignment -name AUTO_PACKED_REGISTERS_CYCLONE -to -<br />
entity <br />
Default Value<br />
Auto<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
AUTO_PACKED_REG_CYCLONE<br />
Auto Packed Registers -- Cyclone<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–20 Chapter 6: Fitter Assignments<br />
AUTO_PACKED_REGISTERS_MAX<strong>II</strong><br />
AUTO_PACKED_REGISTERS_MAX<strong>II</strong><br />
Type<br />
Allows the Compiler to automatically implement a register and a combinational<br />
function in the same logic cell. This option controls how aggressively the Fitter<br />
combines registers with other function blocks in order to reduce logic element count.<br />
If this option is set to Off, the Fitter does not attempt to place a pair of logic functions<br />
in a single logic cell; however, logic cells specified during synthesis to perform both a<br />
combinational and a sequential function are maintained. If this option is set to<br />
Normal, the Fitter places both a combinational and a sequential operation in a logic<br />
cell when it is expected that the placement does not affect design performance. When<br />
this option is set to Minimize Area, the Fitter aggressively combines unrelated<br />
sequential and combinational functions into a single logic cell in order to reduce the<br />
logic cell count, even at the expense of design performance. When this option is set to<br />
Minimize Area with Chains, the Fitter even more aggressively combines sequential<br />
and combinational functions that are part of arithmetic or register cascade chains or<br />
that can be converted to register cascade chains. When this setting is Auto, the Fitter<br />
attempts to achieve the best performance while maintaining a fit for the design in the<br />
specified device. The Fitter combines all combinational and sequential functions that<br />
are deemed to benefit circuit speed. In addition, more aggressive combinations of<br />
unrelated combinational and sequential functions are performed to the extent<br />
required to reduce the area of the design in order to achieve a fit in the specified<br />
device.<br />
Enumeration<br />
■ Auto<br />
■ Minimize Area<br />
■ Minimize Area with Chains<br />
■ Normal<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_global_assignment -name AUTO_PACKED_REGISTERS_MAX<strong>II</strong> <br />
set_global_assignment -name AUTO_PACKED_REGISTERS_MAX<strong>II</strong> -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–21<br />
AUTO_PACKED_REGISTERS_MAX<strong>II</strong><br />
set_instance_assignment -name AUTO_PACKED_REGISTERS_MAX<strong>II</strong> -to -entity<br />
<br />
Default Value<br />
Auto<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
AUTO_PACKED_REGISTERS_TSUNAMI<br />
Auto Packed Registers -- MAX <strong>II</strong><br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–22 Chapter 6: Fitter Assignments<br />
AUTO_PACKED_REGISTERS_STRATIX<br />
AUTO_PACKED_REGISTERS_STRATIX<br />
Type<br />
Allows the Compiler to automatically implement a register and a combinational<br />
function in the same logic cell, or to implement registers using I/O cells, RAM blocks,<br />
or DSP blocks instead of logic cells. This option controls how aggressively the Fitter<br />
combines registers with other function blocks in order to reduce logic element count.<br />
If this option is set to Off, the Fitter does not attempt to place a pair of logic functions<br />
in a single logic cell; however, logic cells specified during synthesis to perform both a<br />
combinational and a sequential function are maintained. If this option is set to<br />
Normal, the Fitter places both a combinational and a sequential operation in a logic<br />
cell when it is expected that the placement does not affect design performance. When<br />
this option is set to Minimize Area, the Fitter aggressively combines unrelated<br />
sequential and combinational functions into a single logic cell in order to reduce the<br />
logic cell count, even at the expense of design performance. When this option is set to<br />
Minimize Area with Chains, the Fitter even more aggressively combines sequential<br />
and combinational functions that are part of arithmetic or register cascade chains or<br />
that can be converted to register cascade chains. When this setting is Auto, the fitter<br />
attempts to achieve the best performance while maintaining a fit for the design in the<br />
specified device. The Fitter combines all combinational and sequential functions that<br />
are deemed to benefit circuit speed. In addition, more aggressive combinations of<br />
unrelated combinational and sequential functions are performed to the extent<br />
required to reduce the area of the design in order to achieve a fit in the specified<br />
device. If this option is set to any value but Off, registers are merged with I/O cells to<br />
improve I/O timing, and with DSP blocks and RAM blocks to reduce logic cell count<br />
or improve timing when possible.<br />
Enumeration<br />
■ Auto<br />
■ Minimize Area<br />
■ Minimize Area with Chains<br />
■ Normal<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix<br />
■ Stratix GX<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–23<br />
AUTO_PACKED_REGISTERS_STRATIX<br />
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX -entity <br />
set_instance_assignment -name AUTO_PACKED_REGISTERS_STRATIX -to -<br />
entity <br />
Default Value<br />
Auto<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
AUTO_MODIFIED_PACKED_REGISTERS<br />
Auto Packed Registers -- Stratix/Stratix GX<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–24 Chapter 6: Fitter Assignments<br />
AUTO_PACKED_REGISTERS_STRATIX<strong>II</strong><br />
AUTO_PACKED_REGISTERS_STRATIX<strong>II</strong><br />
Type<br />
Allows the Compiler to combine a register and a combinational function, or to<br />
implement registers using I/O cells, RAM blocks, or DSP blocks instead of logic cells.<br />
This option controls how aggressively the Fitter combines registers with other<br />
function blocks to reduce the area of the design. Generally, the Auto or Sparse Auto<br />
settings should be used for this option. The other options limit the flexibility of the<br />
Fitter to combine registers with other function blocks and can result in no fits. When<br />
Auto, the default setting is selected, the Fitter attempts to achieve the best<br />
performance with good area. If necessary, additional logic is combined to reduce the<br />
area of the design so that it can fit within the selected device. When this setting is<br />
Sparse Auto, the Fitter attempts to achieve the highest performance with possibly<br />
increased area, but without exceeding the logic capacity of the device. If this option is<br />
set to Off, the Fitter does not combine registers with other functions. The Off setting<br />
severely increases the area of the design and may cause a no fit. If this option is set to<br />
Sparse, the Fitter combines functions in a way which improves performance for many<br />
designs. If this option is set to Normal, the Fitter combines functions that are expected<br />
to maximize design performance and reduce area. When this option is set to<br />
Minimize Area, the Fitter aggressively combines unrelated functions to reduce the<br />
area required for placing the design, at the expense of performance. When this option<br />
is set to Minimize Area with Chains, the Fitter even more aggressively combines<br />
functions that are part of register cascade chains or can be converted to register<br />
cascade chains. If this option is set to any value but Off, registers are combined with<br />
I/O cells to improve I/O timing (as long as the Optimize IOC Register Placement<br />
For Timing option allows it), and with DSP blocks and RAM blocks to reduce the area<br />
required for placing the design or to improve timing when possible.<br />
Enumeration<br />
■ Auto<br />
■ Minimize Area<br />
■ Minimize Area with Chains<br />
■ Normal<br />
■ Off<br />
■ Sparse<br />
■ Sparse Auto<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–25<br />
AUTO_PACKED_REGISTERS_STRATIX<strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX<strong>II</strong> <br />
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX<strong>II</strong> -entity<br />
<br />
set_instance_assignment -name AUTO_PACKED_REGISTERS_STRATIX<strong>II</strong> -to -<br />
entity <br />
Default Value<br />
Auto<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
AUTO_PACKED_REGISTERS_ARMSTRONG<br />
Auto Packed Registers -- Stratix <strong>II</strong>/<strong>II</strong> GX/<strong>II</strong>I Cyclone <strong>II</strong>/<strong>II</strong>I Arria GX<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–26 Chapter 6: Fitter Assignments<br />
AUTO_TURBO_BIT<br />
AUTO_TURBO_BIT<br />
Type<br />
Controls the speed versus power usage trade-off for a macrocell. If you set the Turbo<br />
Bit option to on, the speed of the macrocell increases; if you set this option to Off, its<br />
power consumption decreases; if you choose the Auto setting, the Compiler chooses<br />
the most appropriate setting for the design.<br />
Enumeration<br />
■ Auto<br />
■ Off<br />
■ On<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
Notes<br />
This assignment is included in the Analysis & Synthesis report.<br />
Syntax<br />
set_global_assignment -name AUTO_TURBO_BIT <br />
set_global_assignment -name AUTO_TURBO_BIT -entity <br />
set_instance_assignment -name AUTO_TURBO_BIT -to -entity <br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–27<br />
BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE<br />
BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE<br />
Type<br />
Directs the Compiler to base the Pin-Out <strong>File</strong> (.pin) and floorplan package views on<br />
the largest selected SameFrame device.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–28 Chapter 6: Fitter Assignments<br />
BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES<br />
BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES<br />
Type<br />
Controls whether RAMs implemented in MLAB cells must have equivalent pause<br />
read capabilities as RAMs implemented in block RAM. Pausing a read is the ability to<br />
keep around the last read value when reading is disabled. Allowing differences in<br />
paused read capabilities provides the Fitter more flexibility in implementing RAMs<br />
using MLAB cells. If you set this option to Don’t Care, the RAMs may convert RAMs<br />
to MLAB cells even if the Fitter does not have the equivalent paused read capabilities<br />
to a block RAM implementation. The Fitter also sends an information message<br />
notifying you of RAMs with different paused read capabilities. If you set this option<br />
to Care, the Fitter does not convert RAMs to MLAB cells unless the RAMs have the<br />
equivalent paused read capabilities to a block RAM implementation. To allow the<br />
Fitter the most flexibility in deciding which RAMs are implemented using MLAB<br />
cells, set this option to Don’t Care.<br />
Enumeration<br />
■ Care<br />
■ Don’t Care<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name<br />
BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES <br />
set_global_assignment -name<br />
BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–29<br />
BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES<br />
set_instance_assignment -name<br />
BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES -to -entity<br />
<br />
Default Value<br />
Care<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–30 Chapter 6: Fitter Assignments<br />
BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS<br />
BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS<br />
Type<br />
Controls whether RAMs implemented in MLAB cells must have equivalent power up<br />
conditions as RAMs implemented in block RAM. Power up conditions occur when<br />
the device is powered up or globally reset. Allowing non-equivalent power up<br />
conditions provides the Fitter more flexibility in implementing RAMs using MLAB<br />
cells. If you set this option to Auto, the Fitter may convert RAMs to MLAB cells even<br />
if the RAMs do not have the equivalent power up conditions to a block RAM<br />
implementation. The Fitter also sends a warning message notifying you of RAMs with<br />
non-equivalent power up conditions. If you set this option to Don’t Care, the same<br />
behavior as Auto applies, but the warning message is an information message<br />
instead. If you set this option to Care, the Fitter does not convert RAMs to MLAB cells<br />
unless the RAMs have the equivalent power up conditions to a block RAM<br />
implementation. To allow the Fitter the most flexibility in deciding which RAMs are<br />
implemented using MLAB cells, set this option to Auto or Don’t Care.<br />
Enumeration<br />
■ Auto<br />
■ Care<br />
■ Don’t Care<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name<br />
BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS <br />
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Chapter 6: Fitter Assignments 6–31<br />
BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS<br />
set_global_assignment -name<br />
BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS -entity <br />
<br />
set_instance_assignment -name<br />
BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS -to -entity <br />
Default Value<br />
Auto<br />
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6–32 Chapter 6: Fitter Assignments<br />
BLOCK_RAM_TO_MLAB_CELL_CONVERSION<br />
BLOCK_RAM_TO_MLAB_CELL_CONVERSION<br />
Type<br />
Controls whether the fitter is able to convert RAMs to use LAB locations when those<br />
RAMs use Auto as the selected block type. If this option is changed to Off, only<br />
MLAB cells in the design or RAM cells with a block type setting of MLAB uses LAB<br />
locations to implement memory.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION <br />
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION -entity<br />
<br />
set_instance_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION -to -<br />
entity <br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–33<br />
C3_M9K_BIT_SKIP<br />
C3_M9K_BIT_SKIP<br />
Type<br />
Directs the Fitter to skip certain bitlines in Cyclone <strong>II</strong>I M9K blocks when<br />
implementing the specificed RAM or ROM cell. The default remapping behavior is<br />
determined by the overall RAM Bit Reservation Fitter setting, accessible from the<br />
More Fitter <strong>Settings</strong> page of the <strong>Settings</strong> dialog box. This setting can be used to<br />
override that behavior for a specified RAM. For more information about the values for<br />
the setting, refer to the description of the global setting.<br />
Enumeration<br />
■ Auto<br />
■ Maximum<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name C3_M9K_BIT_SKIP -to -entity <br />
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6–34 Chapter 6: Fitter Assignments<br />
CDR_BANDWIDTH_PRESET<br />
CDR_BANDWIDTH_PRESET<br />
Type<br />
Specifies the CDR (clock data recovery) bandwidth preset setting.<br />
Enumeration<br />
■ Auto<br />
■ High<br />
■ Low<br />
■ Medium<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_instance_assignment -name CDR_BANDWIDTH_PRESET -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
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Chapter 6: Fitter Assignments 6–35<br />
CKN_CK_PAIR<br />
CKN_CK_PAIR<br />
Type<br />
Specifies the pairing of a CKn pin to a CK pin. The I/O pin of a CK CKn pair must be<br />
placed on a differential pin pair. This option is ignored if is assigned to anything other<br />
than an I/O pad, input buffer, or output buffer.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name CKN_CK_PAIR -from -to -entity<br />
<br />
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CLAMPING_DIODE<br />
CLAMPING_DIODE<br />
Type<br />
Turns on the clamping diode of a pin. The clamping diode can be turned on to limit<br />
overshoot voltage for a pin in input operation. The clamping diode is turned on by<br />
default for 3.0-V PCI/PCI-X I/O standards. The clamping diode is turned off by<br />
default for 3.3-V LVTTL/LVCMOS I/O standards. This option is ignored if it is<br />
applied to anything other than a pin or a top-level design entity.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name CLAMPING_DIODE -entity <br />
set_instance_assignment -name CLAMPING_DIODE -to -entity <br />
set_global_assignment -name CLAMPING_DIODE <br />
Example<br />
set_instance_assignment -name CLAMPING_DIODE ON -to pin<br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–37<br />
CLOCK_TO_OUTPUT_DELAY<br />
CLOCK_TO_OUTPUT_DELAY<br />
Type<br />
Specifies the propagation delay to the output or bidirectional pin from the output<br />
register implemented in an I/O cell. This is an advanced option that should be used<br />
only after you have compiled a project, checked the I/O timing, and determined that<br />
the timing is unsatisfactory. For detailed information on how to use this option, refer<br />
to the data sheet for the device family. This option is off by default. This option is<br />
ignored if it is applied to anything other than an output or bidirectional pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY -to -entity<br />
<br />
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CONFIGURATION_VCCIO_LEVEL<br />
CONFIGURATION_VCCIO_LEVEL<br />
Type<br />
Specifies the V CCIO voltage of the configuration pins for the current configuration<br />
scheme on the target device.<br />
Some configuration schemes support multiple configuration voltage levels. This<br />
option allows you to specify a configuration voltage level.<br />
The Fitter produces warnings if the configuration voltage level is not consistent with<br />
the V CCIO after the I/O placement.<br />
You can use the FORCE_CONFIGURATION_VCCIO option to force the V CCIO voltage<br />
of the configuration pins to be the same as the configuration device I/O voltage.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL <br />
Example<br />
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 1.8V<br />
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Chapter 6: Fitter Assignments 6–39<br />
CONFIGURATION_VCCIO_LEVEL<br />
Default Value<br />
Auto<br />
See Also<br />
■ “FORCE_CONFIGURATION_VCCIO” on page 6–134<br />
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CRC_ERROR_CHECKING<br />
CRC_ERROR_CHECKING<br />
Type<br />
Specifies error detection CRC usage for the selected device. If error detection CRC is<br />
turned on, the device checks the validity of the programming data in the device. Any<br />
changes in the data while the device is in operation generates an error.<br />
Using this feature in Stratix, Cyclone, or Stratix GX devices causes a reduction in<br />
device speed.<br />
Enabling this option puts the dual-purpose CRCERROR pin into configuration mode.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Syntax<br />
set_global_assignment -name CRC_ERROR_CHECKING <br />
Example<br />
set_global_assignment -name CRC_ERROR_CHECKING ON<br />
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Chapter 6: Fitter Assignments 6–41<br />
CRC_ERROR_CHECKING<br />
Default Value<br />
Off<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
STRATIX_CRC_ERROR_CHECKING<br />
YEAGER_CRC_ERROR_CHECKING<br />
See Also<br />
■ “CRC_ERROR_OPEN_DRAIN” on page 6–42<br />
■ “ERROR_CHECK_FREQUENCY_DIVISOR” on page 6–116<br />
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CRC_ERROR_OPEN_DRAIN<br />
CRC_ERROR_OPEN_DRAIN<br />
Type<br />
Specifies whether the Open-Drain feature on the CRC Error pin should be enabled or<br />
not.<br />
Using this feature decouples the voltage level of the CRCERROR pin from V CCIO.<br />
A pull-up resistor must be connected to the pin when this feature is enabled.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name CRC_ERROR_OPEN_DRAIN <br />
Example<br />
set_global_assignment -name crc_error_open_drain on<br />
set_global_assignment -name crc_error_open_drain off<br />
See Also<br />
■ “CRC_ERROR_OPEN_DRAIN” on page 6–42<br />
■ “ERROR_CHECK_FREQUENCY_DIVISOR” on page 6–116<br />
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Chapter 6: Fitter Assignments 6–43<br />
CURRENT_STRENGTH_NEW<br />
CURRENT_STRENGTH_NEW<br />
Type<br />
Sets the drive strength of a pin. Specify a number (in mA), MIN, or MAX for output or<br />
bidirectional pins that support programmable drive strength. Refer to the family data<br />
sheet for which drive strengths are allowed for each I/O standard. This option is<br />
ignored if it is applied to anything other than an output or bidirectional pin.<br />
This option specifies a current strength setting for the single-ended output buffer of a<br />
pin. Since an input-only pin does not use single-ended output buffer, this option is<br />
ignored on such pin. This option is not supported on a pin with I/O standard which<br />
uses true differential output buffer such as LVDS. Some differential I/O standards are<br />
implemented with two single-ended output buffers and therefore this option may be<br />
supported. Refer to the family data sheet for which I/O standards support<br />
programmable drive strengths. This option can only be supported on pin locations<br />
that support programmable drive strength. Dedicated programming pins, such as<br />
TDO, do not support programmable drive strength. If output termination is enabled<br />
on a pin, then this current strength assignment should not be used on the pin.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
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CURRENT_STRENGTH_NEW<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name CURRENT_STRENGTH_NEW -to -entity<br />
<br />
Example<br />
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to output_pin<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
CURRENT_STRENGTH<br />
See Also<br />
■ “IO_STANDARD” on page 6–186<br />
■ “OUTPUT_TERMINATION” on page 6–231<br />
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CVP_CONFDONE_OPEN_DRAIN<br />
CVP_CONFDONE_OPEN_DRAIN<br />
Type<br />
Specify open drain on the CvP_CONFDONE pin should be enabled or not.<br />
Using this feature decouples the voltage level of the CvP_CONFDONE pin from V CCIO.<br />
A pull-up resistor must be connected to the pin when this feature is enabled.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN <br />
Example<br />
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN on<br />
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN off<br />
Default Value<br />
On<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
CVPCIE_CONFDONE_OPEN_DRAIN<br />
See Also<br />
■ “ENABLE_CVP_CONFDONE” on page 6–104<br />
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CVP_MODE<br />
CVP_MODE<br />
Type<br />
Specifies the configuration mode for Configuration via Protocol (CvP).<br />
Enumeration<br />
■ Off<br />
Device Support<br />
■ Power up and subsequent core configuration<br />
■ Subsequent core reconfiguration<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name CVP_MODE <br />
Example<br />
set_global_assignment -name CVP_MODE "Power up and subsequent core<br />
configuration"<br />
Default Value<br />
Off<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
CVPCIE_MODE<br />
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CYCLONE<strong>II</strong>I_CONFIGURATION_SCHEME<br />
CYCLONE<strong>II</strong>I_CONFIGURATION_SCHEME<br />
Type<br />
The method used to load data into the device. Up to four configuration schemes are<br />
available, depending on the selected device: Passive Serial (PS); Fast Passive Parallel<br />
(FPP), Active Parallel (AP) and Active Serial (AS).<br />
Enumeration<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
Syntax<br />
set_global_assignment -name CYCLONE<strong>II</strong>I_CONFIGURATION_SCHEME <br />
Example<br />
set_global_assignment -name CYCLONE<strong>II</strong>I_CONFIGURATION_SCHEME "Active<br />
Serial"<br />
Default Value<br />
Active Serial<br />
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CYCLONE<strong>II</strong>_CONFIGURATION_SCHEME<br />
CYCLONE<strong>II</strong>_CONFIGURATION_SCHEME<br />
Type<br />
The method used to load data into the device. Two configuration schemes are<br />
available: Passive Serial (PS) and Active Serial (AS).<br />
Enumeration<br />
■ Active Serial<br />
Device Support<br />
■ Passive Serial<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong><br />
Syntax<br />
set_global_assignment -name CYCLONE<strong>II</strong>_CONFIGURATION_SCHEME <br />
Default Value<br />
Active Serial<br />
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CYCLONE<strong>II</strong>_RESERVE_NCEO_AFTER_CONFIGURATION<br />
CYCLONE<strong>II</strong>_RESERVE_NCEO_AFTER_CONFIGURATION<br />
Type<br />
Specifies how the nCEO pin should be used when the device is operating in user mode<br />
after configuration is complete. The nCEO pin can be reserved as dedicated nCEO<br />
programming pin or a regular I/O pin.<br />
Enumeration<br />
Device Support<br />
■ Use as programming pin<br />
■ Use as regular IO<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
Syntax<br />
set_global_assignment -name CYCLONE<strong>II</strong>_RESERVE_NCEO_AFTER_CONFIGURATION<br />
<br />
Example<br />
set_global_assignment -name CYCLONE<strong>II</strong>_RESERVE_NCEO_AFTER_CONFIGURATION<br />
"Use as programming pin"<br />
Default Value<br />
Use as programming pin<br />
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CYCLONE<strong>II</strong>_TERMINATION<br />
CYCLONE<strong>II</strong>_TERMINATION<br />
Type<br />
Allows the Compiler to configure the on-chip termination (OCT) and impedance<br />
matching for an I/O pin. OCT helps to prevent signal reflections and maintain signal<br />
integrity. This option is ignored if it is applied to anything other than an I/O pin.<br />
Enumeration<br />
■ Off<br />
Device Support<br />
■ Series 25 Ohms<br />
■ Series 50 Ohms<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong><br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name CYCLONE<strong>II</strong>_TERMINATION -to -entity<br />
<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
Termination -- CYCLONE <strong>II</strong><br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
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Chapter 6: Fitter Assignments 6–51<br />
CYCLONE_CONFIGURATION_SCHEME<br />
CYCLONE_CONFIGURATION_SCHEME<br />
Type<br />
The method used to load data into the device. Two configuration schemes are<br />
available: Passive Serial (PS) and Active Serial (AS).<br />
Enumeration<br />
■ Active Serial<br />
Device Support<br />
■ Passive Serial<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
Syntax<br />
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME <br />
Default Value<br />
Active Serial<br />
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D1_DELAY<br />
D1_DELAY<br />
Type<br />
Specifies the propagation delay for D1 Delay Cell. This is an advanced option that<br />
should be used only after you have compiled a project, checked the I/O timing, and<br />
determined that the timing is unsatisfactory. For detailed information on how to use<br />
this option, refer to the data sheet for the device family. This option is ignored if it is<br />
applied to anything other than an input or bidirectional pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name D1_DELAY -to -entity <br />
<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
T1_DELAY<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–53<br />
D1_FINE_DELAY<br />
D1_FINE_DELAY<br />
Type<br />
Enable the fine delay resolution on D1 Delay.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name D1_FINE_DELAY -to -entity <br />
<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
T1_FINE_DELAY<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–54 Chapter 6: Fitter Assignments<br />
D2_DELAY<br />
D2_DELAY<br />
Type<br />
Specifies the propagation delay for D2 Delay Cell. This is an advanced option that<br />
should be used only after you have compiled a project, checked the I/O timing, and<br />
determined that the timing is unsatisfactory. For detailed information on how to use<br />
this option, refer to the data sheet for the device family. This option is ignored if it is<br />
applied to anything other than an input or bidirectional pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GZ<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name D2_DELAY -to -entity <br />
<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
T2_DELAY<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–55<br />
D3_DELAY<br />
D3_DELAY<br />
Type<br />
Specifies the propagation delay for D3 Delay Cell. This is an advanced option that<br />
should be used only after you have compiled a project, checked the I/O timing, and<br />
determined that the timing is unsatisfactory. For detailed information on how to use<br />
this option, refer to the data sheet for the device family. This option is ignored if it is<br />
applied to anything other than an input or bidirectional pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name D3_DELAY -to -entity <br />
<br />
set_instance_assignment -name D3_DELAY -from -to -entity<br />
<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
T3_DELAY<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–56 Chapter 6: Fitter Assignments<br />
D4_DELAY<br />
D4_DELAY<br />
Type<br />
Specifies the propagation delay for D4 Delay Cell. This is an advanced option that<br />
should be used only after you have compiled a project, checked the I/O timing, and<br />
determined that the timing is unsatisfactory. For detailed information on how to use<br />
this option, refer to the data sheet for the device family. This option is ignored if it is<br />
applied to anything other than an input or bidirectional pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name D4_DELAY -to -entity <br />
<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
T7_DELAY<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–57<br />
D4_FINE_DELAY<br />
D4_FINE_DELAY<br />
Type<br />
Enable the fine delay resolution on D4 Delay.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name D4_FINE_DELAY -to -entity <br />
<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
T7_FINE_DELAY<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–58 Chapter 6: Fitter Assignments<br />
D5_DELAY<br />
D5_DELAY<br />
Type<br />
Specifies the propagation delay for D5 Delay Cell. This is an advanced option that<br />
should be used only after you have compiled a project, checked the I/O timing, and<br />
determined that the timing is unsatisfactory. For detailed information on how to use<br />
this option, refer to the data sheet for the device family. This option is ignored if it is<br />
applied to anything other than an output or bidirectional pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name D5_DELAY -to -entity <br />
<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
T9_DELAY<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–59<br />
D5_FINE_DELAY<br />
D5_FINE_DELAY<br />
Type<br />
Enable the fine delay resolution on D5 Delay.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name D5_FINE_DELAY -to -entity <br />
<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
T9_FINE_DELAY<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–60 Chapter 6: Fitter Assignments<br />
D5_OCT_DELAY<br />
D5_OCT_DELAY<br />
Type<br />
Specifies the propagation delay for D5 OCT Delay Cell. This is an advanced option<br />
that should be used only after you have compiled a project, checked the I/O timing,<br />
and determined that the timing is unsatisfactory. For detailed information on how to<br />
use this option, refer to the data sheet for the device family. This option is ignored if it<br />
is applied to anything other than an input or bidirectional pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name D5_OCT_DELAY -to -entity <br />
<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
T9_OCT_DELAY<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–61<br />
D5_OE_DELAY<br />
D5_OE_DELAY<br />
Type<br />
Specifies the propagation delay for D5 Output-Enable Delay Cell. Use this advanced<br />
option only after you have compiled a project, checked the I/O timing, and<br />
determined that the timing is unsatisfactory. For more information about this option,<br />
refer to the data sheet for the device family. This option is ignored if it is applied to<br />
anything other than an output or bidirectional pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name D5_OE_DELAY -to -entity <br />
<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
T9_OE_DELAY<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–62 Chapter 6: Fitter Assignments<br />
D6_DELAY<br />
D6_DELAY<br />
Type<br />
Specifies the propagation delay for D6 Delay Cell. This is an advanced option that<br />
should be used only after you have compiled a project, checked the I/O timing, and<br />
determined that the timing is unsatisfactory. For detailed information on how to use<br />
this option, refer to the data sheet for the device family. This option is ignored if it is<br />
applied to anything other than an output or bidirectional pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GZ<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name D6_DELAY -to -entity <br />
<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
T10_DELAY<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–63<br />
D6_FINE_DELAY<br />
D6_FINE_DELAY<br />
Type<br />
Enable the fine delay resolution on D6 Delay.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name D6_FINE_DELAY -to -entity <br />
<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
T10_FINE_DELAY<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–64 Chapter 6: Fitter Assignments<br />
D6_OCT_DELAY<br />
D6_OCT_DELAY<br />
Type<br />
Specifies the propagation delay for D6 OCT Delay Cell. This is an advanced option<br />
that should be used only after you have compiled a project, checked the I/O timing,<br />
and determined that the timing is unsatisfactory. For detailed information on how to<br />
use this option, refer to the data sheet for the device family. This option is ignored if it<br />
is applied to anything other than an input or bidirectional pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GZ<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name D6_OCT_DELAY -to -entity <br />
<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
T10_OCT_DELAY<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–65<br />
D6_OE_DELAY<br />
D6_OE_DELAY<br />
Type<br />
Specifies the propagation delay for D6 Output-Enable Delay Cell. This is an advanced<br />
option that should be used only after you have compiled a project, checked the I/O<br />
timing, and determined that the timing is unsatisfactory. For detailed information on<br />
how to use this option, refer to the data sheet for the device family. This option is<br />
ignored if it is applied to anything other than an output or bidirectional pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name D6_OE_DELAY -to -entity <br />
<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
T10_OE_DELAY<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–66 Chapter 6: Fitter Assignments<br />
D6_OE_FINE_DELAY<br />
D6_OE_FINE_DELAY<br />
Type<br />
Enable the fine delay resolution on D6 Output-Enable Delay.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name D6_OE_FINE_DELAY -to -entity <br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
T10_OE_FINE_DELAY<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–67<br />
DATA0_PIN<br />
DATA0_PIN<br />
Type<br />
Specifies the Data[0] configuration pin.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_instance_assignment -name DATA0_PIN -to <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–68 Chapter 6: Fitter Assignments<br />
DCLK_PIN<br />
DCLK_PIN<br />
Type<br />
Specifies the DCLK configuration pin.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_instance_assignment -name DCLK_PIN -to <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–69<br />
DC_CURRENT_FOR_ELECTROMIGRATION_CHECK<br />
DC_CURRENT_FOR_ELECTROMIGRATION_CHECK<br />
Type<br />
Specifies the maximum amount of DC current, in mA, allowed when the Fitter checks<br />
for electromigration violations.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_instance_assignment -name DC_CURRENT_FOR_ELECTROMIGRATION_CHECK -to <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–70 Chapter 6: Fitter Assignments<br />
DDIO_INPUT_REGISTER<br />
DDIO_INPUT_REGISTER<br />
Type<br />
Directs the Compiler to perform special placement and routing of the specified<br />
register to prevent register packing of the input registers into the IO registers. This is<br />
used for registers involved in DDR memory interfaces. A setting of High designates<br />
the input register that gets set on the rising edge of the clock; a setting of Low<br />
designates the input register that gets set on the falling edge of the clock.<br />
Enumeration<br />
■ High<br />
■ Low<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name DDIO_INPUT_REGISTER -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–71<br />
DDIO_OUTPUT_REGISTER<br />
DDIO_OUTPUT_REGISTER<br />
Type<br />
Directs the Compiler to perform special placement and routing of the specified<br />
register to provide a glitch-free output. This is used for registers involved in DDR<br />
memory interfaces. A setting of High designates the output register used when the<br />
output mux select is 1; a setting of Low designates the output register used when the<br />
output mux select is 0.<br />
Enumeration<br />
■ High<br />
■ Low<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name DDIO_OUTPUT_REGISTER -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–72 Chapter 6: Fitter Assignments<br />
DDIO_OUTPUT_REGISTER_DISTANCE<br />
DDIO_OUTPUT_REGISTER_DISTANCE<br />
Type<br />
Directs the Fitter to place the DDIO output registers (and output mux) that feed this<br />
I/O pin in a location whose LAB distance is specified by this option. This option is<br />
ignored if applied to an input pin or if applied to an output or bidir pin that is not fed<br />
by a DDIO Output configuration.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong><br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name DDIO_OUTPUT_REGISTER_DISTANCE -to -<br />
entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–73<br />
DECREASE_INPUT_DELAY_TO_INPUT_REGISTER<br />
DECREASE_INPUT_DELAY_TO_INPUT_REGISTER<br />
Type<br />
Decreases the propagation delay from an input pin to the data input of the input<br />
register implemented in the I/O cell associated with the pin. This is an advanced<br />
option that should be used only after you have compiled a project, checked the I/O<br />
timing, and determined that the timing is unsatisfactory. For detailed information on<br />
how to use this option, refer to the data sheet for the device family. This option is<br />
ignored if it is applied to anything other than an input or bidirectional pin.<br />
Enumeration<br />
■ Off<br />
■ On<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name DECREASE_INPUT_DELAY_TO_INPUT_REGISTER -to<br />
-entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–74 Chapter 6: Fitter Assignments<br />
DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER<br />
DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER<br />
Type<br />
Decreases the propagation delay from the interior of the device to the data input of<br />
the output register implemented in an I/O cell. This is an advanced option that<br />
should be used only after you have compiled a project, checked the I/O timing, and<br />
determined that the timing is unsatisfactory. For detailed information on how to use<br />
this option, refer to the data sheet for the device family. This option is ignored if it is<br />
applied to anything other an output or bidirectional pin that is associated with an<br />
output register implemented in an I/O cell.<br />
Enumeration<br />
■ Off<br />
■ On<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix<br />
■ Stratix GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER -to<br />
-entity <br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
DELAY_SETTING_TO_CORE_TO_OUTPUT_REGISTER<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–75<br />
DEVICE<br />
DEVICE<br />
Type<br />
Specifies the device to use.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name DEVICE <br />
Default Value<br />
Auto<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–76 Chapter 6: Fitter Assignments<br />
DEVICE_MIGRATION_LIST<br />
DEVICE_MIGRATION_LIST<br />
Type<br />
Specifies the list of devices intended for possible future migration. The Compiler<br />
constrains the resource usage to migratable resources across all devices in the<br />
migration list.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name DEVICE_MIGRATION_LIST <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–77<br />
DEVICE_TECHNOLOGY_MIGRATION_LIST<br />
DEVICE_TECHNOLOGY_MIGRATION_LIST<br />
Type<br />
Specifies the selected technology migration devices for the current device.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name DEVICE_TECHNOLOGY_MIGRATION_LIST <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–78 Chapter 6: Fitter Assignments<br />
DPRIO_CHANNEL_NUM<br />
DPRIO_CHANNEL_NUM<br />
Type<br />
RX or TX channel number for DPRIO logic.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_instance_assignment -name DPRIO_CHANNEL_NUM -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–79<br />
DPRIO_CRUCLK_NUM<br />
DPRIO_CRUCLK_NUM<br />
Type<br />
Logical RX CRU clock number.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_instance_assignment -name DPRIO_CRUCLK_NUM -to -entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–80 Chapter 6: Fitter Assignments<br />
DPRIO_INTERFACE_REG<br />
DPRIO_INTERFACE_REG<br />
Type<br />
Interface I/O register of DPRIO logic.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_instance_assignment -name DPRIO_INTERFACE_REG -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–81<br />
DPRIO_QUAD_NUM<br />
DPRIO_QUAD_NUM<br />
Type<br />
RX/TX quad number for DPRIO logic.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_instance_assignment -name DPRIO_QUAD_NUM -to -entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–82 Chapter 6: Fitter Assignments<br />
DPRIO_QUAD_PLL_NUM<br />
DPRIO_QUAD_PLL_NUM<br />
Type<br />
Logical CMU PLL number in a quad.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_instance_assignment -name DPRIO_QUAD_PLL_NUM -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–83<br />
DPRIO_TX_PLL0_REFCLK_NUM<br />
DPRIO_TX_PLL0_REFCLK_NUM<br />
Type<br />
Logical TX PLL0 REFCLK number.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_instance_assignment -name DPRIO_TX_PLL0_REFCLK_NUM -to -entity<br />
<br />
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6–84 Chapter 6: Fitter Assignments<br />
DPRIO_TX_PLL1_REFCLK_NUM<br />
DPRIO_TX_PLL1_REFCLK_NUM<br />
Type<br />
Logical TX PLL1 REFCLK number.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_instance_assignment -name DPRIO_TX_PLL1_REFCLK_NUM -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–85<br />
DPRIO_TX_PLL_NUM<br />
DPRIO_TX_PLL_NUM<br />
Type<br />
Logical TX PLL number.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_instance_assignment -name DPRIO_TX_PLL_NUM -to -entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–86 Chapter 6: Fitter Assignments<br />
DQSB_DQS_PAIR<br />
DQSB_DQS_PAIR<br />
Type<br />
Specifies the pairing of a DQSn pin to a DQS pin. The I/O pin of a DQS must be placed<br />
in the DQS pin location of a DQS group; the I/O pin of a DQSn must be placed in the DQSn<br />
pin location of the same DQS group. This option is ignored if is assigned to anything<br />
other than an I/O pad, input buffer, or output buffer.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name DQSB_DQS_PAIR -from -to -entity<br />
<br />
Example<br />
set_instance_assignment -name DQSB_DQS_PAIR ON -from mem_dqs_n[0] -to<br />
mem_dqs[0]<br />
See Also<br />
■ “DQ_GROUP” on page 6–90<br />
■ “MEMORY_INTERFACE_DATA_PIN_GROUP” on page 6–205<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–87<br />
DQSOUT_DELAY_CHAIN<br />
DQSOUT_DELAY_CHAIN<br />
Type<br />
Set the propagation delay on the DQSBUS signal from the DQS pin. This is an advanced<br />
option that should be used only after you have compiled a project, checked the I/O<br />
timing, and determined that the timing is unsatisfactory. For detailed information on<br />
how to use this option, refer to the data sheet for the device family. This option is<br />
ignored if it is applied to anything other than a DQ pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ HardCopy <strong>II</strong><br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name DQSOUT_DELAY_CHAIN -to -entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–88 Chapter 6: Fitter Assignments<br />
DQS_ENABLE_DELAY_CHAIN<br />
DQS_ENABLE_DELAY_CHAIN<br />
Type<br />
Set the propagation delay on the DQS enable signal for the DQS pin. This is an advanced<br />
option that should be used only after you have compiled a project, checked the I/O<br />
timing, and determined that the timing is unsatisfactory. For detailed information on<br />
how to use this option, refer to the data sheet for the device family. This option is<br />
ignored if it is applied to anything other than a DQS pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name DQS_ENABLE_DELAY_CHAIN -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–89<br />
DQS_LOCAL_CLOCK_DELAY_CHAIN<br />
DQS_LOCAL_CLOCK_DELAY_CHAIN<br />
Type<br />
Set the propagation delay on the DQS signal to the input register of the target pin. This<br />
is an advanced option that should be used only after you have compiled a project,<br />
checked the I/O timing, and determined that the timing is unsatisfactory. For detailed<br />
information on how to use this option, refer to the data sheet for the device family.<br />
This option is ignored if it is applied to anything other than a DQ or DQS pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ HardCopy <strong>II</strong><br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name DQS_LOCAL_CLOCK_DELAY_CHAIN -to -entity<br />
<br />
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6–90 Chapter 6: Fitter Assignments<br />
DQ_GROUP<br />
DQ_GROUP<br />
Type<br />
Specifies the grouping from a DQS pin to its associated DQ pins and the width (4, 9, 18,<br />
or 36) of the group. Setting this option allows the Fitter to view the pins as a DQS/DQ<br />
pin group. I/O pins of a DQ pin group must be placed in the DQ pin locations of a single<br />
DQS group. This option is ignored if is assigned to anything other than an I/O pad,<br />
input buffer, or output buffer.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name DQ_GROUP -from -to -entity<br />
<br />
Example<br />
set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[0..7]<br />
See Also<br />
■ “DQSB_DQS_PAIR” on page 6–86<br />
■ “MEMORY_INTERFACE_DATA_PIN_GROUP” on page 6–205<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–91<br />
DQ_PIN<br />
DQ_PIN<br />
Type<br />
Designates the specified pin as an DQ I/O pin.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong><br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name DQ_PIN -to -entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–92 Chapter 6: Fitter Assignments<br />
DUAL_PURPOSE_CLOCK_PIN_DELAY<br />
DUAL_PURPOSE_CLOCK_PIN_DELAY<br />
Type<br />
Specifies the propagation delay from a dual-purpose clock pin to its fan-out<br />
destinations that are routed on the global clock network. Legal integer values range<br />
from 0 through 63 for Cyclone and Cyclone <strong>II</strong> device families and from 0 through 11<br />
for Cyclone <strong>II</strong>I, where 0 is the setting with the least delay and 63 is the setting with the<br />
most delay. This is an advanced option that should be used only after you have<br />
compiled a project, checked the I/O timing, and determined that the timing is<br />
unsatisfactory. For detailed information on how to use this option, refer to the data<br />
sheet for the device family. This option is ignored if it is applied to anything other<br />
than an input or bidirectional pin, or if the pin is user assigned to a non-dual-purpose<br />
clock pin location.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name DUAL_PURPOSE_CLOCK_PIN_DELAY -to -<br />
entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–93<br />
DUPLICATE_ATOM<br />
DUPLICATE_ATOM<br />
Type<br />
Directs the Compiler to duplicate the source node, and uses the new duplicate node to<br />
fan out to the destination node; the original source node no longer fans out to the<br />
destination node. Use the Value field to specify the name of the duplicate node.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment supports wildcards.<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–94 Chapter 6: Fitter Assignments<br />
DUPLICATE_ATOM<br />
The value of this assignment must be a node name.<br />
Syntax<br />
set_instance_assignment -name DUPLICATE_ATOM -from -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–95<br />
DYNAMIC_OCT_CONTROL_GROUP<br />
DYNAMIC_OCT_CONTROL_GROUP<br />
Type<br />
Assigns a dynamic termination control group number for the specified node. Turning<br />
on this option directs the Fitter to view the specified nodes as a dynamic termination<br />
control group so as to place them next to each other to share the termination control<br />
routing resource. This is only applicable for bidirectional pins.<br />
This option is deprecated and should no longer be used.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GZ<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name DYNAMIC_OCT_CONTROL_GROUP -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–96 Chapter 6: Fitter Assignments<br />
ECO_ALLOW_ROUTING_CHANGES<br />
ECO_ALLOW_ROUTING_CHANGES<br />
Type<br />
This option controls whether the Fitter moves items in a design to ensure that new<br />
ECO signals get routed.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–97<br />
ECO_OPTIMIZE_TIMING<br />
ECO_OPTIMIZE_TIMING<br />
Type<br />
Controls whether the fitter optimizes to meet the user's maximum delay timing<br />
requirements (for example, clock cycle time, T SU, T CO) during ECO compiles. By<br />
default, this option is set to off. Turning it on can improve timing performance at the<br />
cost of compilation time.<br />
Enumeration<br />
■ Off<br />
■ On<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name ECO_OPTIMIZE_TIMING <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–98 Chapter 6: Fitter Assignments<br />
ECO_REGENERATE_REPORT<br />
ECO_REGENERATE_REPORT<br />
Type<br />
Controls whether the fitter report is regenerated during ECO compiles. By default,<br />
this option is set to off.<br />
Enumeration<br />
■ Off<br />
■ On<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name ECO_REGENERATE_REPORT <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–99<br />
ENABLE_ASMI_FOR_FLASH_LOADER<br />
ENABLE_ASMI_FOR_FLASH_LOADER<br />
Type<br />
Enables Active Serial Memory Interface (ASMI) for Flash Loader IP blocks.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong><br />
Syntax<br />
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–100 Chapter 6: Fitter Assignments<br />
ENABLE_BENEFICIAL_SKEW_OPTIMIZATION<br />
ENABLE_BENEFICIAL_SKEW_OPTIMIZATION<br />
Type<br />
Allows the Fitter to insert skew on globally routed clock signals to improve the<br />
performance of the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION <br />
set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION -to <br />
-entity <br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–101<br />
ENABLE_BUS_HOLD_CIRCUITRY<br />
ENABLE_BUS_HOLD_CIRCUITRY<br />
Type<br />
Enables bus-hold circuitry during device operation. If you turn this option on, a pin<br />
retains its last logic level when it is not driven, and does not go to a high impedance<br />
logic level. The Enable Bus-Hold Circuitry option should not be simultaneously with<br />
the Weak Pull-Up Resistor option. This option is ignored if it is applied to anything<br />
other than a pin.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–102 Chapter 6: Fitter Assignments<br />
ENABLE_BUS_HOLD_CIRCUITRY<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY <br />
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY -entity <br />
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY -to -entity<br />
<br />
Example<br />
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to pin<br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–103<br />
ENABLE_CRC_ERROR_PIN<br />
ENABLE_CRC_ERROR_PIN<br />
Type<br />
Specifies error detection CRC and CRC_ERROR pin usage for the selected device. If<br />
error detection CRC is turned on, the device checks the validity of the programming<br />
data in the device. Any changes in the data while the device is in operation generates<br />
an error.<br />
Enabling this option would put the dual-purpose CRCERROR pin into configuration<br />
mode.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name ENABLE_CRC_ERROR_PIN <br />
Example<br />
set_global_assignment -name ENABLE_CRC_ERROR_PIN ON<br />
Default Value<br />
Off<br />
See Also<br />
■ “CRC_ERROR_OPEN_DRAIN” on page 6–42<br />
■ “ERROR_CHECK_FREQUENCY_DIVISOR” on page 6–116<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–104 Chapter 6: Fitter Assignments<br />
ENABLE_CVP_CONFDONE<br />
ENABLE_CVP_CONFDONE<br />
Type<br />
Enable the CvP_CONFDONE pin, which indicates that the device finished core<br />
programming in Configuration via Protocol mode. If this option is turned off, the<br />
CvP_CONFDONE pin is disabled when the device operates in user mode and is available<br />
as a user I/O pin.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name ENABLE_CVP_CONFDONE <br />
Example<br />
set_global_assignment -name ENABLE_CVP_CONFDONE ON<br />
Default Value<br />
Off<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
ENABLE_CVPCIE_CONFDONE<br />
See Also<br />
■ “CVP_CONFDONE_OPEN_DRAIN” on page 6–45<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–105<br />
ENABLE_DEVICE_WIDE_OE<br />
ENABLE_DEVICE_WIDE_OE<br />
Type<br />
Enables the DEV_OE pin when the device is in user mode. If this option is turned on, all<br />
outputs on the chip operate normally. When the pin is disabled, all outputs are tristated.<br />
If this option is turned off, the DEV_OE pin is disabled when the device operates<br />
in user mode and is available as a user I/O pin.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name ENABLE_DEVICE_WIDE_OE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–106 Chapter 6: Fitter Assignments<br />
ENABLE_DEVICE_WIDE_OE<br />
Example<br />
set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON<br />
Default Value<br />
Off<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
ENABLE_CHIP_WIDE_OE<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–107<br />
ENABLE_DEVICE_WIDE_RESET<br />
ENABLE_DEVICE_WIDE_RESET<br />
Type<br />
Enables the DEV_CLRn pin, which allows all registers of the device to be reset by an<br />
external source. If this option is turned off, the DEV_CLRn pin is disabled when the<br />
device operates in user mode and is available as a user I/O pin.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET <br />
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6–108 Chapter 6: Fitter Assignments<br />
ENABLE_DEVICE_WIDE_RESET<br />
Example<br />
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON<br />
Default Value<br />
Off<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
ENABLE_CHIP_WIDE_RESET<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–109<br />
ENABLE_HOLD_BACK_OFF<br />
ENABLE_HOLD_BACK_OFF<br />
Type<br />
Enables the Fitter to successfully fit a design despite infeasible hold constraints.<br />
Enumeration<br />
■ Off<br />
■ On<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ HardCopy <strong>II</strong><br />
Syntax<br />
set_global_assignment -name ENABLE_HOLD_BACK_OFF <br />
Default Value<br />
On<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–110 Chapter 6: Fitter Assignments<br />
ENABLE_INIT_DONE_OUTPUT<br />
ENABLE_INIT_DONE_OUTPUT<br />
Type<br />
Enables the INIT_DONE pin, which allows you to externally monitor when<br />
initialization is completed and the device is in user mode. If this option is turned off,<br />
the INIT_DONE pin is disabled when the device operates in user mode and is available<br />
as a user I/O pin.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–111<br />
ENABLE_INIT_DONE_OUTPUT<br />
Example<br />
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF<br />
Default Value<br />
Off<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
Enable INIT_DONE Output<br />
See Also<br />
■ “INIT_DONE_OPEN_DRAIN” on page 6–177<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–112 Chapter 6: Fitter Assignments<br />
ENABLE_NCEO_OUTPUT<br />
ENABLE_NCEO_OUTPUT<br />
Type<br />
Enables the nCEO pin. This pin should be connected to the nCE of the succeeding device<br />
when multiple devices are being programmed. If this option is turned off, the nCEO<br />
pin is disabled when the device operates in user mode and is available as a user I/O<br />
pin.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name ENABLE_NCEO_OUTPUT <br />
Example<br />
set_global_assignment -name ENABLE_NCEO_OUTPUT OFF<br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–113<br />
ENABLE_PR_PINS<br />
ENABLE_PR_PINS<br />
Type<br />
Enable the PR_REQUEST, PR_READY, PR_ERROR and PR_DONE pins. These pins are needed<br />
for supporting partial reconfiguration with external host or external scrubbing. An<br />
external host uses the PR_REQUEST pin to request partial reconfiguration or external<br />
scrubbing, the PR_READY pin to determine if the device is ready to receive<br />
programming data, the PR_ERROR pin to externally monitor programming error, and<br />
the PR_DONE pin to indicate that the device has finished programming. If this option is<br />
turned off, these functionalities are disabled when the device operates in user mode<br />
and these pins are available as user I/O pins.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name ENABLE_PR_PINS <br />
Example<br />
set_global_assignment -name ENABLE_PR_PINS ON<br />
Default Value<br />
Off<br />
See Also<br />
■ “PR_READY_OPEN_DRAIN” on page 6–281<br />
■ “PR_ERROR_OPEN_DRAIN” on page 6–280<br />
■ “PR_DONE_OPEN_DRAIN” on page 6–279<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–114 Chapter 6: Fitter Assignments<br />
ENABLE_VREFA_PIN<br />
ENABLE_VREFA_PIN<br />
Type<br />
Enable the circuitry for input voltage reference pins A.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX7000B<br />
Syntax<br />
set_global_assignment -name ENABLE_VREFA_PIN <br />
Default Value<br />
Off<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
Enable VREFA pin<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–115<br />
ENABLE_VREFB_PIN<br />
ENABLE_VREFB_PIN<br />
Type<br />
Enables the circuitry for input voltage reference pins B.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX7000B<br />
Syntax<br />
set_global_assignment -name ENABLE_VREFB_PIN <br />
Default Value<br />
Off<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
Enable VREFB pin<br />
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6–116 Chapter 6: Fitter Assignments<br />
ERROR_CHECK_FREQUENCY_DIVISOR<br />
ERROR_CHECK_FREQUENCY_DIVISOR<br />
Type<br />
Specifies the divide value of the internal clock, which determines the frequency of the<br />
CRC. The divide value must be a power of two. Refer to the device handbook to find<br />
the frequency of the internal clock for the selected device.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR <br />
Example<br />
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 16<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–117<br />
ERROR_CHECK_FREQUENCY_DIVISOR<br />
See Also<br />
■ “CRC_ERROR_CHECKING” on page 6–40<br />
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6–118 Chapter 6: Fitter Assignments<br />
EXCLUSIVE_IO_GROUP<br />
EXCLUSIVE_IO_GROUP<br />
Type<br />
Assigns an exclusive group number for the specified I/O. I/Os with the different<br />
exclusive group number cannot share the same bank.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name EXCLUSIVE_IO_GROUP -to -entity <br />
Example<br />
set_instance_assignment -name "EXCLUSIVE_IO_GROUP" -to pin<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–119<br />
EXTERNAL_LVDS_RX_USES_DPA<br />
EXTERNAL_LVDS_RX_USES_DPA<br />
Type<br />
Indicates that this LVDS Transmitter pin is connected to an external LVDS Receiver<br />
that uses DPA.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_instance_assignment -name EXTERNAL_LVDS_RX_USES_DPA -to -entity<br />
<br />
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6–120 Chapter 6: Fitter Assignments<br />
FINAL_PLACEMENT_OPTIMIZATION<br />
FINAL_PLACEMENT_OPTIMIZATION<br />
Type<br />
Specifies whether the Fitter performs final placement optimizations. Performing final<br />
placement optimizations may improve timing and routability, but may also require<br />
longer compilation time. The default setting of Automatically can be used with the<br />
Auto Fit Fitter Effort Level (also the default) to let the Fitter decide whether these<br />
optimizations should run based on the routability and timing requirements of the<br />
design.<br />
Enumeration<br />
■ Always<br />
■ Automatically<br />
■ Never<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–121<br />
FINAL_PLACEMENT_OPTIMIZATION<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION <br />
Default Value<br />
Automatically<br />
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6–122 Chapter 6: Fitter Assignments<br />
FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND<br />
FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND<br />
Type<br />
Allows timing analysis to add extra short path guardband on a specific node during<br />
fitting.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
Syntax<br />
set_global_assignment -name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND <br />
set_global_assignment -name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND -entity<br />
<br />
set_instance_assignment -name FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND -to<br />
-entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–123<br />
FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION<br />
FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION<br />
Type<br />
Specifies whether the Fitter aggressively optimizes for routability. Performing<br />
aggressive routability optimizations may decrease design speed, but may also reduce<br />
routing wire usage and routing time. The default setting of Automatically lets the<br />
Fitter decide whether to perform these optimizations based on the routability and<br />
timing requirements of the design.<br />
Enumeration<br />
■ Always<br />
■ Automatically<br />
■ Never<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–124 Chapter 6: Fitter Assignments<br />
FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION<br />
<br />
Default Value<br />
Automatically<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–125<br />
FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN<br />
FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN<br />
Type<br />
Specifies the amount of worst-case slack margin the Fitter should try to maintain<br />
when the FITTER_EFFORT option is set to Auto Fit. If the design is likely to have at<br />
least this much slack on every path, the Fitter reduces optimization effort to reduce<br />
compilation time. Otherwise, its behavior is the same as it is with the Standard Fit<br />
setting for the FITTER_EFFORT option.<br />
Time<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
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6–126 Chapter 6: Fitter Assignments<br />
FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN<br />
Syntax<br />
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN<br />
<br />
Default Value<br />
0ns<br />
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FITTER_EARLY_TIMING_ESTIMATE_MODE<br />
FITTER_EARLY_TIMING_ESTIMATE_MODE<br />
Type<br />
Controls the type of early timing estimate produced by the Early Timing Estimate<br />
feature. The Realistic setting estimates the average results expected from a Standard<br />
Fit compile, the Optimistic setting estimates the best case final timing, and the<br />
Pessimistic setting estimates the worst case final timing.<br />
Enumeration<br />
■ Optimistic<br />
■ Pessimistic<br />
■ Realistic<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Syntax<br />
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE <br />
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FITTER_EARLY_TIMING_ESTIMATE_MODE<br />
Default Value<br />
Realistic<br />
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FITTER_EFFORT<br />
FITTER_EFFORT<br />
Type<br />
Controls the trade-off between performance and compilation speed of the Fitter. The<br />
Auto Fit setting adjusts the Fitter optimization effort to minimize compilation time<br />
while still achieving the design timing requirements. The<br />
FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN option can be used to<br />
request that Auto Fit apply sufficient optimization effort to achieve additional timing<br />
margin. The Standard Fit setting uses maximum effort regardless of the requirements<br />
of the design, leading to higher compilation time and more margin on easier designs.<br />
For difficult designs, the Auto Fit and Standard Fit settings both use maximum effort.<br />
The Fast Fit setting decreases optimization effort to reduce compilation time, which<br />
may degrade design performance.<br />
Enumeration<br />
■ Auto Fit<br />
■ Fast Fit<br />
■ Standard Fit<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name FITTER_EFFORT <br />
Default Value<br />
Auto Fit<br />
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FIT_ATTEMPTS_TO_SKIP<br />
FIT_ATTEMPTS_TO_SKIP<br />
Type<br />
Controls how many fit attempts the Fitter skips. In subsequent fit attempts, the Fitter<br />
uses higher effort to improve design routability at the expense of longer compilation<br />
times. Use this setting to force the Fitter directly into a second or third fit attempt,<br />
which will save time when it is known that multiple attempts are needed. This setting<br />
causes the same amount of additional effort to be applied but does not guarantee an<br />
identical result to what would be achieved if all fit attempts were performed. For<br />
some families, the Fitter will not perform a third fit attempt automatically due to the<br />
long compilation time and possible timing quality degradation. However, a third fit<br />
attempt can still be forced to run by setting this value to 2.<br />
Integer<br />
Device Support<br />
The value must be between these two numbers, inclusive: 0, 2<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
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FIT_ATTEMPTS_TO_SKIP<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP <br />
Default Value<br />
0.0<br />
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FIT_ONLY_ONE_ATTEMPT<br />
FIT_ONLY_ONE_ATTEMPT<br />
Type<br />
Controls how many fitting attempts the Fitter tries to get a fit. When this option is off<br />
(default), the Fitter tries a maximum of three placement and routing attempts, with<br />
each successive attempt increasing the placement effort and hence increasing<br />
compilation times. These additional attempts are used only if previous attempts failed<br />
to fit the design. Setting this option restricts the Fitter to using only the first of these<br />
three attempts.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT <br />
Default Value<br />
Off<br />
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FLEX10K_MAX_PERIPHERAL_OE<br />
FLEX10K_MAX_PERIPHERAL_OE<br />
Type<br />
Sets the limit on the number of peripheral OE buses that can be used.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name FLEX10K_MAX_PERIPHERAL_OE <br />
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FORCE_CONFIGURATION_VCCIO<br />
FORCE_CONFIGURATION_VCCIO<br />
Type<br />
Forces the V CCIO voltage of the configuration pins to be the same as the configuration<br />
device I/O voltage.<br />
In some device families, the V CCIO of some banks power both general purpose I/Os<br />
and configuration pins.<br />
Turning on this option forces the Fitter to produce an I/O placement in such a way<br />
that the V CCIO would be consistent with the selected configuration voltage.<br />
Fitter produces placement errors if such I/O placement cannot be found.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name FORCE_CONFIGURATION_VCCIO <br />
Example<br />
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON<br />
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Chapter 6: Fitter Assignments 6–135<br />
FORCE_CONFIGURATION_VCCIO<br />
Default Value<br />
Off<br />
See Also<br />
■ “CONFIGURATION_VCCIO_LEVEL” on page 6–38<br />
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FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS<br />
FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS<br />
Type<br />
Directs the Fitter to treat periphery placement warnings as errors. As a result, the<br />
Fitter attempts to find a placement for the design that corrects these warnings. If the<br />
Fitter cannot fit the design, an error message is displayed instead of the original<br />
warning message.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name<br />
FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS <br />
Default Value<br />
Off<br />
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FORCE_FRACTURED_MODE_ALM_IMPLEMENTATION<br />
FORCE_FRACTURED_MODE_ALM_IMPLEMENTATION<br />
Type<br />
Directs the Fitter to implement the specified node using the fractured mode of the<br />
ALM. This assignment only applies to nodes with a specific location assignment.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name FORCE_FRACTURED_MODE_ALM_IMPLEMENTATION -to<br />
-entity <br />
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FORCE_MERGE_PLL<br />
FORCE_MERGE_PLL<br />
Type<br />
Forces the slave PLL to be merged with the master PLL. This option should be used<br />
only for two compatible PLLs driven by the same clock source.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_instance_assignment -name FORCE_MERGE_PLL -from -to -<br />
entity <br />
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FORCE_MERGE_PLL_FANOUTS<br />
FORCE_MERGE_PLL_FANOUTS<br />
Type<br />
Forces the fanouts of the slave PLL clock output to be merged into the master PLL<br />
clock output. This option should be used only for static PLL clock outputs.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_instance_assignment -name FORCE_MERGE_PLL_FANOUTS -from -to<br />
-entity <br />
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FORCE_NON_FRACTURED_MODE_ALM_IMPLEMENTATION<br />
FORCE_NON_FRACTURED_MODE_ALM_IMPLEMENTATION<br />
Type<br />
Directs the Fitter to implement the specified node using the non-fractured mode of the<br />
ALM. This assignment only applies to nodes with a specific location assignment.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name FORCE_NON_FRACTURED_MODE_ALM_IMPLEMENTATION<br />
-to -entity <br />
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GENERATE_GXB_RECONFIG_MIF<br />
GENERATE_GXB_RECONFIG_MIF<br />
Type<br />
Generates a gigabit transceiver block reconfiguration Memory Initialization <strong>File</strong> (.mif)<br />
for each used gigabit transceiver block Transmitter and Receiver channel pair (Stratix<br />
<strong>II</strong> GX and Arria GX) or each ALTGX megafunction instance (Stratix IV, Arria <strong>II</strong> GX<br />
and Cyclone IV GX). Reprogramming using this Memory Initialization <strong>File</strong> (.mif)<br />
reconfigures the gigabit transceiver block channel.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone IV GX<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix IV<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF <br />
Default Value<br />
Off<br />
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GENERATE_GXB_RECONFIG_MIF_WITH_PLL<br />
GENERATE_GXB_RECONFIG_MIF_WITH_PLL<br />
Type<br />
Generates a gigabit transceiver block reconfiguration Memory Initialization <strong>File</strong> (.mif)<br />
with PLL data for each used gigabit transceiver block Transmitter and Receiver<br />
channel pair. Reprogramming using this Memory Initialization <strong>File</strong> (.mif)<br />
reconfigures the entire gigabit transceiver block channel.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL <br />
Default Value<br />
Off<br />
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GLOBAL_SIGNAL<br />
GLOBAL_SIGNAL<br />
Type<br />
Specifies whether the signal should be routed using global routing paths. Global<br />
signals can be both pin- and logic-driven, and can be any signal in the design. Turning<br />
this option on for a pin or a single-output logic function signal is equivalent to feeding<br />
the signal through a GLOBAL buffer. Turning this option off for a particular signal<br />
will prevent any of the Auto Global options from using the signal as an automatic<br />
global signal.<br />
Enumeration<br />
■ Dual-Fast Regional Clock<br />
■ Dual-Regional Clock<br />
■ Fast Regional Clock<br />
■ Global Clock<br />
■ Off<br />
■ On<br />
Device Support<br />
■ Periphery Clock<br />
■ Regional Clock<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ EPC1<br />
■ EPC2<br />
■ Enhanced Configuration Devices<br />
■ FLEX10KB<br />
■ FLEX8000<br />
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GLOBAL_SIGNAL<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
■ MAX9000<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name GLOBAL_SIGNAL -to -entity <br />
<br />
set_instance_assignment -name GLOBAL_SIGNAL -from -to -entity<br />
<br />
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GLOBAL_SIGNAL_CLKCTRL_LOCATION<br />
GLOBAL_SIGNAL_CLKCTRL_LOCATION<br />
Type<br />
Specifies the CLKCTRL that the signal should be routed using global routing paths. The<br />
value to use is the same as that used for location assignments of Clock Control/Clock<br />
Enable Blocks.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name GLOBAL_SIGNAL_CLKCTRL_LOCATION -to -<br />
entity <br />
set_instance_assignment -name GLOBAL_SIGNAL_CLKCTRL_LOCATION -from <br />
-to -entity <br />
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GNDIO_CURRENT_1PT8V<br />
GNDIO_CURRENT_1PT8V<br />
Type<br />
For user to override GNDIO current of 1.8-V I/O standard. The original current is<br />
2mA.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name GNDIO_CURRENT_1PT8V <br />
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GNDIO_CURRENT_2PT5V<br />
GNDIO_CURRENT_2PT5V<br />
Type<br />
For user to override GNDIO current of 2.5-V I/O standard. The original current is<br />
2mA.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name GNDIO_CURRENT_2PT5V <br />
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GNDIO_CURRENT_GTL<br />
GNDIO_CURRENT_GTL<br />
Type<br />
Overrides the GNDIO current of a GTL I/O standard. Not supported in MAX7000.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name GNDIO_CURRENT_GTL <br />
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Chapter 6: Fitter Assignments 6–149<br />
GNDIO_CURRENT_GTL_PLUS<br />
GNDIO_CURRENT_GTL_PLUS<br />
Type<br />
Overrides the GNDIO current of a GTL+ I/O standard. The original current is 50 mA.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name GNDIO_CURRENT_GTL_PLUS <br />
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6–150 Chapter 6: Fitter Assignments<br />
GNDIO_CURRENT_LVCMOS<br />
GNDIO_CURRENT_LVCMOS<br />
Type<br />
Overrides the GNDIO current of an LVCMOS I/O standard. The original current is 2<br />
mA.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name GNDIO_CURRENT_LVCMOS <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–151<br />
GNDIO_CURRENT_LVTTL<br />
GNDIO_CURRENT_LVTTL<br />
Type<br />
Overrides the GNDIO current of an LVTTL I/O standard. The original current is 4<br />
mA.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name GNDIO_CURRENT_LVTTL <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–152 Chapter 6: Fitter Assignments<br />
GNDIO_CURRENT_PCI<br />
GNDIO_CURRENT_PCI<br />
Type<br />
Overrides the GNDIO current of a PCI I/O standard. The original current is 4 mA.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name GNDIO_CURRENT_PCI <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–153<br />
GNDIO_CURRENT_SSTL2_CLASS1<br />
GNDIO_CURRENT_SSTL2_CLASS1<br />
Type<br />
Overrides the GNDIO current of a SSTL2_CLASS1 I/O standard. The original current<br />
is 14 mA.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name GNDIO_CURRENT_SSTL2_CLASS1 <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–154 Chapter 6: Fitter Assignments<br />
GNDIO_CURRENT_SSTL2_CLASS2<br />
GNDIO_CURRENT_SSTL2_CLASS2<br />
Type<br />
Overrides the GNDIO current of a SSTL2_CLASS2 I/O standard. The original current<br />
is 21 mA.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name GNDIO_CURRENT_SSTL2_CLASS2 <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–155<br />
GNDIO_CURRENT_SSTL3_CLASS1<br />
GNDIO_CURRENT_SSTL3_CLASS1<br />
Type<br />
Overrides the GNDIO current of a SSTL3_CLASS1 I/O standard. The original current<br />
is 18 mA.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name GNDIO_CURRENT_SSTL3_CLASS1 <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–156 Chapter 6: Fitter Assignments<br />
GNDIO_CURRENT_SSTL3_CLASS2<br />
GNDIO_CURRENT_SSTL3_CLASS2<br />
Type<br />
Overrides the GNDIO current of a SSTL3_CLASS2 I/O standard. The original current<br />
is 25 mA.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name GNDIO_CURRENT_SSTL3_CLASS2 <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–157<br />
GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME<br />
GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME<br />
Type<br />
Controls whether the Fitter tries to achieve a zero hold time for I/O pins that feed<br />
globally clocked registers at the fast corner and in stringent operating conditions even<br />
if a design does not contain timing assignments. When this option is set to On, the<br />
Fitter preserves zero hold time for I/O pins feeding globally clocked registers at the<br />
fast corner and in stringent operating conditions. This setting may cause violations of<br />
t SU or t PD timing constraints. When this option is set to Off, the Fitter optimizes a<br />
design to meet user timing assignments only. When this option is set to When Tsu and<br />
Tpd Constraints Permit, the Fitter preserves zero hold time for I/O pins feeding<br />
globally clocked registers at the fast corner and in stringent operating conditions only<br />
if this can be done without violating tSU or tPD timing constraints. You can use this<br />
option to automatically meet I/O hold time requirements in the fast corner without<br />
specifying any extra timing constraints.<br />
Enumeration<br />
■ Off<br />
■ On<br />
Device Support<br />
■ When Tsu and Tpd Constraints Permit<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME<br />
<br />
Default Value<br />
On<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–158 Chapter 6: Fitter Assignments<br />
GXB_0PPM_CLOCK_GROUP<br />
GXB_0PPM_CLOCK_GROUP<br />
Type<br />
Specifies a group of gigabit transceiver block core clocks that have zero parts per<br />
million (ppm) difference. The clock driver source specified in the gigabit transceiver<br />
block 0 ppm clock group driver must have a difference of 0 ppm compared with all<br />
clocks specified in the gigabit transceiver block 0 ppm clock group. You must connect<br />
the specified clock driver to all specified destinations in the gigabit transceiver block 0<br />
ppm clock group. Do not reconfigure the gigabit transceiver block 0 PPM clock group<br />
driver differently from other clocks in the gigabit transceiver block 0 ppm clock<br />
group, and do not disable the gigabit transceiver block 0 ppm clock group driver<br />
source when the destination gigabit transceiver block receiver or transmitter is<br />
listening to the signal. Follow the <strong>Altera</strong> High Speed I/O Applications Technical<br />
Support recommendations when using this assignment.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name GXB_0PPM_CLOCK_GROUP -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–159<br />
GXB_0PPM_CLOCK_GROUP_DRIVER<br />
GXB_0PPM_CLOCK_GROUP_DRIVER<br />
Type<br />
Specifies core clocks that have zero PPM difference. Follow the <strong>Altera</strong> High Speed I/O<br />
Applications Technical Support recommendations when using this assignment.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name GXB_0PPM_CLOCK_GROUP_DRIVER -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–160 Chapter 6: Fitter Assignments<br />
GXB_0PPM_CORECLK<br />
GXB_0PPM_CORECLK<br />
Type<br />
Specifies core clocks that have zero PPM difference. Follow the <strong>Altera</strong> High Speed I/O<br />
Applications Technical Support recommendations when using this assignment.<br />
Boolean<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name GXB_0PPM_CORECLK -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–161<br />
GXB_0PPM_CORE_CLOCK<br />
GXB_0PPM_CORE_CLOCK<br />
Type<br />
Specifies two GXB core clocks that have zero (0) PPM difference. The core clock driver<br />
for the assignment source GXB must have a difference of 0 PPM compared with the<br />
core clock of the assignment destination GXB. Do not reconfigure the GXB 0 PPM<br />
clock group driver differently from other clocks it is 0 PPM-linked to and do not bring<br />
down the GXB 0 PPM clock source when the destination GXB receiver or transmitter<br />
is listening to the signal. Follow the <strong>Altera</strong> High Speed I/O Applications Technical<br />
Support recommendations when using this assignment.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone IV GX<br />
■ HardCopy IV<br />
■ Stratix IV<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name GXB_0PPM_CORE_CLOCK -from -to -<br />
entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–162 Chapter 6: Fitter Assignments<br />
GXB_CLOCK_GROUP<br />
GXB_CLOCK_GROUP<br />
Type<br />
Specifies gigabit transceiver block core clock groups to be merged after compilation.<br />
All specified gigabit transceiver block transmitters in the gigabit transceiver block<br />
shared clock group are driven by the clock source specified in the gigabit transceiver<br />
block shared clock group driver. All clocks in the gigabit transceiver block shared<br />
clock group and gigabit transceiver block clock group driver must be configured in<br />
the same manner. When the destination GXB transmitter is listening to a signal such<br />
as gxb_powerdown, do not disable the gigabit transceiver block shared clock group<br />
driver source. Follow the <strong>Altera</strong> High Speed I/O Applications Technical Support<br />
recommendations when using this assignment.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name GXB_CLOCK_GROUP -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–163<br />
GXB_CLOCK_GROUP_DRIVER<br />
GXB_CLOCK_GROUP_DRIVER<br />
Type<br />
Specifies the gigabit transceiver block core clock driver that drives all core clocks in a<br />
gigabit transceiver block shared clock group after compilation. All gigabit transceiver<br />
block transmitters specified in the gigabit transceiver block shared clock group are<br />
driven by the clock source specified in the gigabit transceiver block shared clock<br />
group driver. Do not reconfigure the gigabit transceiver block shared clock group<br />
driver differently from other clocks in the gigabit transceiver block shared clock<br />
group, and do not bring down the gigabit transceiver block shared clock group driver<br />
source when the destination gigabit transceiver block transmitter is listening to the<br />
signal. Follow the <strong>Altera</strong> High Speed I/O Applications Technical Support<br />
recommendations when using this assignment.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name GXB_CLOCK_GROUP_DRIVER -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–164 Chapter 6: Fitter Assignments<br />
GXB_RECONFIG_GROUP<br />
GXB_RECONFIG_GROUP<br />
Type<br />
Specifies whether gigabit transceiver block transceiver channels with Dynamic<br />
Reconfiguration can be placed in the same physical channel. Gigabit transceiver block<br />
receivers and transmitters are not placed into the same physical channel when<br />
Dynamic Reconfiguration setting is turned On unless they are in the same<br />
reconfiguration group. Gigabit transceiver block receivers and transmitters can be<br />
assigned to the same group if the following conditions are met: the gigabit transceiver<br />
block receivers and transmitters are dynamically reconfigured at the same time, and<br />
the gigabit transceiver block receivers and transmitters are kept in reset until the<br />
dynamic reconfiguration of both is complete.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name GXB_RECONFIG_GROUP -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–165<br />
GXB_RECONFIG_MIF_PLL<br />
GXB_RECONFIG_MIF_PLL<br />
Type<br />
Includes PLL information in the gigabit transceiver block reconfiguration channel<br />
data.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name GXB_RECONFIG_MIF_PLL -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–166 Chapter 6: Fitter Assignments<br />
GXB_REFCLK_COUPLING_TERMINATION_SETTING<br />
GXB_REFCLK_COUPLING_TERMINATION_SETTING<br />
Type<br />
Allows the Compiler to configure the AC/DC coupling and on-chip termination<br />
(OCT) for a Stratix <strong>II</strong> GX gigabit transceiver block REFCLK input pin. Use DC coupling<br />
external termination value only with the HCSL I/O standard on the PCI-Express<br />
protocol. This option is ignored if it is applied to anything other than an input pin.<br />
Enumeration<br />
Device Support<br />
■ DC coupling external termination<br />
■ OCT 100 Ohms<br />
■ Use as regular IO<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name GXB_REFCLK_COUPLING_TERMINATION_SETTING -to<br />
-entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–167<br />
HPS_IO<br />
HPS_IO<br />
Type<br />
Flags an I/O in the user netlist as one that is intended to be owned by a HPS block.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name HPS_IO -to -entity <br />
Example<br />
set_instance_assignment -name HPS_IO ON -to output_pin<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–168 Chapter 6: Fitter Assignments<br />
IGNORE_MODE_FOR_MERGE<br />
IGNORE_MODE_FOR_MERGE<br />
Type<br />
Ignores the mode of the PLL when the Fitter attempts to merge PLLs, therefore<br />
allowing PLLs with different modes to be merged.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong><br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name IGNORE_MODE_FOR_MERGE <br />
set_global_assignment -name IGNORE_MODE_FOR_MERGE -entity <br />
<br />
set_instance_assignment -name IGNORE_MODE_FOR_MERGE -to -entity<br />
<br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–169<br />
IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE<br />
IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE<br />
Type<br />
Allows you to specify the MLAB memory blocks implementation mode. MLAB<br />
memory blocks are implemented in 32-bit deep mode or 64-bit deep mode. Turning<br />
on this option forces MLAB memory blocks to be implemented in 16-bit deep mode.<br />
This leads to significantly shorter delays and may speed up the overall design<br />
performance if the MLAB memory block is on the critical path. However, it also<br />
requires twice as many MLAB blocks to implement a given logical memory.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE -entity<br />
<br />
set_instance_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE -to <br />
-entity <br />
set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–170 Chapter 6: Fitter Assignments<br />
INCREASE_DELAY_TO_OUTPUT_ENABLE_PIN<br />
INCREASE_DELAY_TO_OUTPUT_ENABLE_PIN<br />
Type<br />
Increases the propagation delay to the output enable pin from internal logic or the<br />
output enable register implemented in an I/O cell. This is an advanced option that<br />
should be used only after you have compiled a project, checked the I/O timing, and<br />
determined that the timing is unsatisfactory. For detailed information on how to use<br />
this option, refer to the data sheet for the device family. This option is ignored if it is<br />
applied to anything other than an output enable pin.<br />
Enumeration<br />
■ Off<br />
■ On<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix<br />
■ Stratix GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name INCREASE_DELAY_TO_OUTPUT_ENABLE_PIN -to <br />
-entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–171<br />
INCREASE_DELAY_TO_OUTPUT_PIN<br />
INCREASE_DELAY_TO_OUTPUT_PIN<br />
Type<br />
Increases the propagation delay to the output or bidirectional pin from the output<br />
register implemented in an I/O cell. This is an advanced option that should be used<br />
only after you have compiled a project, checked the I/O timing, and determined that<br />
the timing is unsatisfactory. For detailed information on how to use this option, refer<br />
to the data sheet for the device family. This option is off by default. This option is<br />
ignored if it is applied to anything other than an output or bidirectional pin.<br />
Enumeration<br />
■ Off<br />
■ On<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ Stratix<br />
■ Stratix GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name INCREASE_DELAY_TO_OUTPUT_PIN -to -<br />
entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–172 Chapter 6: Fitter Assignments<br />
INCREASE_INPUT_CLOCK_ENABLE_DELAY<br />
INCREASE_INPUT_CLOCK_ENABLE_DELAY<br />
Type<br />
Increases the propagation delay from the interior of the device to the clock enable<br />
input of an output register. This is an advanced option that should be used only after<br />
you compile a project, check the I/O timing, and determine that the timing is<br />
unsatisfactory. This option is ignored if it is applied to anything other than an I/O cell<br />
that has an input register with a clock enable signal. For detailed information on how<br />
to use this option, refer to the respective device family data sheet.<br />
Enumeration<br />
■ Large<br />
■ Off<br />
■ On<br />
■ Small<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix<br />
■ Stratix GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name INCREASE_INPUT_CLOCK_ENABLE_DELAY -to -<br />
entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–173<br />
INCREASE_OUTPUT_CLOCK_ENABLE_DELAY<br />
INCREASE_OUTPUT_CLOCK_ENABLE_DELAY<br />
Type<br />
Increases the propagation delay from the interior of the device to the clock enable<br />
input of an output register. This is an advanced option that should be used only after<br />
you compile a project, check the I/O timing, and determine that the timing is<br />
unsatisfactory. This option is ignored if it is applied to anything other than an I/O cell<br />
that has an output register with a clock enable signal. For detailed information on<br />
how to use this option, refer to the respective device family data sheet.<br />
Enumeration<br />
■ Large<br />
■ Off<br />
■ On<br />
■ Small<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix<br />
■ Stratix GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name INCREASE_OUTPUT_CLOCK_ENABLE_DELAY -to <br />
-entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–174 Chapter 6: Fitter Assignments<br />
INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY<br />
INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY<br />
Type<br />
Increases the propagation delay from the interior of the device to the clock enable<br />
input of an output enable register. This is an advanced option that should be used<br />
only after you compile a project, check the I/O timing, and determine that the timing<br />
is unsatisfactory. This option is ignored if it is applied to anything other than an I/O<br />
cell that has an output enable register with a clock enable signal. For detailed<br />
information on how to use this option, refer to the respective device family data sheet.<br />
Enumeration<br />
■ Large<br />
■ Off<br />
■ On<br />
■ Small<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix<br />
■ Stratix GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY -<br />
to -entity <br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAYR<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–175<br />
INCREASE_TZX_DELAY_TO_OUTPUT_PIN<br />
INCREASE_TZX_DELAY_TO_OUTPUT_PIN<br />
Type<br />
Supports zero bus-turnaround (ZBT) by increasing the propagation delay of the<br />
falling edge of the output enable signal. This option allows a device to quickly release<br />
control and slowly take control of a bus. Turning the Increase tzx Delay to Output<br />
Pin option on prevents bus contention between ZBT SRAM devices. This option is<br />
ignored if it is applied to anything other than an output or bidirectional pin.<br />
Enumeration<br />
■ Off<br />
■ On<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix<br />
■ Stratix GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name INCREASE_TZX_DELAY_TO_OUTPUT_PIN -to -<br />
entity <br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
ZBT_OE_FALLING_EDGE_DELAY<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–176 Chapter 6: Fitter Assignments<br />
INC_PLC_MODE<br />
INC_PLC_MODE<br />
Type<br />
Directs the <strong>Quartus</strong> <strong>II</strong> software to run in Incremental Placement Mode.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name INC_PLC_MODE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–177<br />
INIT_DONE_OPEN_DRAIN<br />
INIT_DONE_OPEN_DRAIN<br />
Type<br />
Specifies whether the Open-Drain feature on the INIT_DONE pin should be enabled or<br />
not.<br />
Using this feature decouples the voltage level of the INIT_DONE pin from V CCIO.<br />
A pull-up resistor must be connected to the pin when this feature is enabled.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name INIT_DONE_OPEN_DRAIN <br />
Example<br />
set_global_assignment -name init_done_open_drain on<br />
set_global_assignment -name init_done_open_drain off<br />
Default Value<br />
On<br />
See Also<br />
■ “ENABLE_INIT_DONE_OUTPUT” on page 6–110<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–178 Chapter 6: Fitter Assignments<br />
INPUT_REFERENCE<br />
INPUT_REFERENCE<br />
Type<br />
Allows you to specify the VREF pin for the I/O standard being used by an I/O pin.<br />
This option is ignored if it is applied to anything other than the I/O standard being<br />
used by an I/O pin.<br />
Enumeration<br />
■ As VREFA<br />
■ As VREFB<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX7000B<br />
Syntax<br />
set_instance_assignment -name INPUT_REFERENCE -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–179<br />
INPUT_TERMINATION<br />
INPUT_TERMINATION<br />
Type<br />
Allows the Compiler to configure the on-chip termination (OCT) and impedance<br />
matching for an I/O pin. OCT helps to prevent signal reflections and maintain signal<br />
integrity. This option is ignored if it is applied to anything other than an I/O pad,<br />
input buffer, or output buffer. This option should be applied to an I/O pad or input<br />
buffer of an I/O in bidirectional or input mode. A bidirectional I/O may also have an<br />
output termination assignment.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name INPUT_TERMINATION -to -entity <br />
Example<br />
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH<br />
CALIBRATION" -to pin_name<br />
See Also<br />
■ “IO_STANDARD” on page 6–186<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–180 Chapter 6: Fitter Assignments<br />
INSERT_ADDITIONAL_LOGIC_CELL<br />
INSERT_ADDITIONAL_LOGIC_CELL<br />
Type<br />
Allows the Compiler to insert an additional logic cell after the output(s) of the logic<br />
function to which it is applied, provided that the function is implemented as one logic<br />
cell. This option allows you to insert logic cells for routing purposes without adding<br />
LCELL primitives to the design. If this option is applied to a mega- or macrofunction,<br />
it operates on all outputs of the function. This option is ignored if it is applied to a<br />
logic function that is not already implemented in a macrocell(s). For example, if it is<br />
applied to an AND gate, it does not force the AND gate to be the output of a logic cell.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
Syntax<br />
set_instance_assignment -name INSERT_ADDITIONAL_LOGIC_CELL -to -<br />
entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–181<br />
INTERNAL_SCRUBBING<br />
INTERNAL_SCRUBBING<br />
Type<br />
Specifies internal scrubbing usage for the selected device. If internal scrubbing is<br />
turned on, the device corrects single error or double adjacent error within the core<br />
configuration memory while the device is still running.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name INTERNAL_SCRUBBING <br />
Example<br />
set_global_assignment -name INTERNAL_SCRUBBING ON<br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–182 Chapter 6: Fitter Assignments<br />
IO_MAXIMUM_TOGGLE_RATE<br />
IO_MAXIMUM_TOGGLE_RATE<br />
Type<br />
Specifies the toggle rate of this node. You can specify the desired frequency setting.<br />
This option is ignored if it is applied to anything other than pins. This option can be<br />
used to direct the Fitter in its toggle-rate checking while allowing a single-ended pin<br />
to be placed closer to a differential pin. This assignment is used to analyze signal<br />
integrity under worst case conditions (highest possible toggle rate). A different<br />
assignment, Power Toggle Rate, is used to specify the expected time-averaged toggle<br />
rate rather than worst-case toggle rate, and is used by the Power Analyzer to estimate<br />
time-averaged power consumption. Use the Synchronizer Toggle Rate if you want to<br />
configure the data rates used for Metastability Reporting in the TimeQuest timing<br />
analyzer.<br />
Frequency<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–183<br />
IO_MAXIMUM_TOGGLE_RATE<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE -to -entity<br />
<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
TOGGLE RATE<br />
TOGGLE_RATE<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–184 Chapter 6: Fitter Assignments<br />
IO_PLACEMENT_OPTIMIZATION<br />
IO_PLACEMENT_OPTIMIZATION<br />
Type<br />
Specifies whether the Fitter optimizes the location of I/Os that do not already have<br />
pin locations assigned to them. Performing IO placement optimizations may improve<br />
I/O timing, f MAX, and fitting, but may also require longer compilation time.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–185<br />
IO_PLACEMENT_OPTIMIZATION<br />
Default Value<br />
On<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–186 Chapter 6: Fitter Assignments<br />
IO_STANDARD<br />
IO_STANDARD<br />
Type<br />
Specifies the I/O standard of a pin. Different device families support different I/O<br />
standards, and restrictions apply to placing pins with different I/O standards<br />
together. For more information, refer to the respective device family data sheet. This<br />
option is ignored if it is applied to anything other than a pin or a top-level design<br />
entity.<br />
This option specifies an I/O standard of a pin. If a pin does not have this option, the<br />
<strong>Quartus</strong> <strong>II</strong> software automatically assigns an I/O standard to the pin, based on the<br />
global device option STRATIX_DEVICE_IO_STANDARD (or its device value), or<br />
derived from the netlist (for example, using differential output buffer implies that<br />
differential I/O standard is used). You should specify this option explicitly because<br />
I/O standard affects placement, timing and power. This option also implies what<br />
other I/O options are supported such as current strength, slew rate, termination, preemphasis<br />
and VOD. This option is always honored.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–187<br />
IO_STANDARD<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name IO_STANDARD -to <br />
Example<br />
set_instance_assignment -name IO_STANDARD LVDS -to pin<br />
See Also<br />
■ “STRATIX_DEVICE_IO_STANDARD” on page 6–341<br />
■ “CURRENT_STRENGTH_NEW” on page 6–43<br />
■ “SLEW_RATE” on page 6–313<br />
■ “OUTPUT_TERMINATION” on page 6–231<br />
■ “INPUT_TERMINATION” on page 6–179<br />
■ “PROGRAMMABLE_PREEMPHASIS” on page 6–275<br />
■ “PROGRAMMABLE_VOD” on page 6–277<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–188 Chapter 6: Fitter Assignments<br />
LVDS_DIRECT_LOOPBACK_MODE<br />
LVDS_DIRECT_LOOPBACK_MODE<br />
Type<br />
Enable the LVDS Direct Loop Mode on a True Differential output pin. This assignment<br />
should only apply from an input pin to an output pin and both of them should have<br />
True Differential I/O standard. When this feature is enabled, data coming in from the<br />
adjacent RX pair gets looped back to the TX pair. This feature can be used to verify the<br />
Tx and Rx buffer by checking the data transmit and received. This option is ignored if<br />
it is applied to anything other than a pin or a top-level design entity.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_instance_assignment -name LVDS_DIRECT_LOOPBACK_MODE -from -to<br />
-entity <br />
Example<br />
set_instance_assignment -name LVDS_DIRECT_LOOPBACK_MODE ON -from<br />
true_diff_in_pin_p -to true_diff_out_pin_p<br />
See Also<br />
■ “IO_STANDARD” on page 6–186<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–189<br />
LVDS_RX_REGISTER<br />
LVDS_RX_REGISTER<br />
Type<br />
Directs the Compiler to perform special placement and routing of the specified<br />
register for LVDS receiver interfaces.<br />
Enumeration<br />
■ High<br />
■ Low<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name LVDS_RX_REGISTER -to -entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–190 Chapter 6: Fitter Assignments<br />
M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY<br />
M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY<br />
Type<br />
Allows you to specify whether the M144K memory block read operations depend<br />
upon the read clock’s duty cycle. When M144K memory blocks are driven by a read<br />
clock with a very narrow pulse, they can go into a locked, inactive state. Turning on<br />
this option allows the M144K memory blocks to operate dependent upon the read<br />
clock’s duty cycle to prevent the memory blocks from going into to an inactive state;<br />
however, turning on this option may degrade the performance of the M144K blocks.<br />
Enumeration<br />
■ Off<br />
■ On<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GZ<br />
■ HardCopy IV<br />
■ Stratix IV<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY -<br />
entity <br />
set_instance_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY<br />
-to -entity <br />
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY<br />
<br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–191<br />
MATCH_PLL_COMPENSATION_CLOCK<br />
MATCH_PLL_COMPENSATION_CLOCK<br />
Type<br />
Allows you to specify a PLL output clock feeding a clock network as a compensation<br />
target for a PLL in NORMAL or SOURCE_SYNCHRONOUS mode. This configures<br />
the PLL to match its feedback path to the target’s clock network. This option is<br />
ignored if it is applied to anything other than a PLL output clock.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_instance_assignment -name MATCH_PLL_COMPENSATION_CLOCK -to -<br />
entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–192 Chapter 6: Fitter Assignments<br />
MAX7000B_VCCIO_IOBANK1<br />
MAX7000B_VCCIO_IOBANK1<br />
Type<br />
Specifies the default I/O Bank1 Voltage to be used for pins on the target device.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX7000B<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name MAX7000B_VCCIO_IOBANK1 <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–193<br />
MAX7000B_VCCIO_IOBANK2<br />
MAX7000B_VCCIO_IOBANK2<br />
Type<br />
Specifies the default I/O Bank2 Voltage to be used for pins on the target device.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX7000B<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name MAX7000B_VCCIO_IOBANK2 <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–194 Chapter 6: Fitter Assignments<br />
MAX7000_DEVICE_IO_STANDARD<br />
MAX7000_DEVICE_IO_STANDARD<br />
Type<br />
Specifies the default I/O standard to be used for pins on the target device.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–195<br />
MAX7000_ENABLE_JTAG_BST_SUPPORT<br />
MAX7000_ENABLE_JTAG_BST_SUPPORT<br />
Type<br />
Enables JTAG boundary-scan test (BST) support.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
Syntax<br />
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT <br />
Default Value<br />
On<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–196 Chapter 6: Fitter Assignments<br />
MAX7000_INDIVIDUAL_TURBO_BIT<br />
MAX7000_INDIVIDUAL_TURBO_BIT<br />
Type<br />
Controls the speed versus power usage trade-off for a macrocell. If the Turbo Bit is on,<br />
the macrocell’s speed increases; if it is off, its power consumption decreases.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT -entity <br />
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT -to -<br />
entity <br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
Turbo Bit -- MAX 7000B/7000AE/3000A/7000S/7000A<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–197<br />
MAX_CLOCKS_ALLOWED<br />
MAX_CLOCKS_ALLOWED<br />
Type<br />
Specifies the maximum number of clocks of any type (for example, global clock,<br />
regional clock) that can be used by the design. A value of -1 means that the Fitter can<br />
use all the clocks supported by the device.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name MAX_CLOCKS_ALLOWED <br />
Default Value<br />
-1 (Unlimited)<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–198 Chapter 6: Fitter Assignments<br />
MAX_CONSECUTIVE_OUTPUTS_FOR_ELECTROMIGRATION<br />
MAX_CONSECUTIVE_OUTPUTS_FOR_ELECTROMIGRATION<br />
Type<br />
Specifies the number of consecutive horizontal output or bidirectional pins<br />
considered in the current-density computation for electromigration when the Fitter<br />
checks for electromigration violations.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_global_assignment -name MAX_CONSECUTIVE_OUTPUTS_FOR_ELECTROMIGRATION<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–199<br />
MAX_CONSECUTIVE_VIO_OUTPUTS_FOR_ELECTROMIGRATION<br />
MAX_CONSECUTIVE_VIO_OUTPUTS_FOR_ELECTROMIGRATION<br />
Type<br />
Specifies the number of consecutive vertical output or bidirectional pins considered in<br />
the current-density computation for electromigration when the Fitter checks for<br />
electromigration violations.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_global_assignment -name<br />
MAX_CONSECUTIVE_VIO_OUTPUTS_FOR_ELECTROMIGRATION <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–200 Chapter 6: Fitter Assignments<br />
MAX_CURRENT_FOR_ELECTROMIGRATION<br />
MAX_CURRENT_FOR_ELECTROMIGRATION<br />
Type<br />
Specifies the maximum amount of DC current, in mA, allowed on horizontal output<br />
or bidirectional pins when the Fitter checks for electromigration violations.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_global_assignment -name MAX_CURRENT_FOR_ELECTROMIGRATION <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–201<br />
MAX_CURRENT_FOR_VIO_ELECTROMIGRATION<br />
MAX_CURRENT_FOR_VIO_ELECTROMIGRATION<br />
Type<br />
Specifies the maximum amount of DC current, in mA, allowed on vertical output or<br />
bidirectional pins when the Fitter checks for electromigration violations.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_global_assignment -name MAX_CURRENT_FOR_VIO_ELECTROMIGRATION <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–202 Chapter 6: Fitter Assignments<br />
MAX_GLOBAL_CLOCKS_ALLOWED<br />
MAX_GLOBAL_CLOCKS_ALLOWED<br />
Type<br />
Specifies the maximum number of global clocks that can be used by the design. A<br />
value of -1 means that the Fitter can use all the global clocks supported by the device.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED <br />
Default Value<br />
-1 (Unlimited)<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–203<br />
MAX_PERIPHERY_CLOCKS_ALLOWED<br />
MAX_PERIPHERY_CLOCKS_ALLOWED<br />
Type<br />
Specifies the maximum number of periphery clocks that can be used by the design. A<br />
value of -1 means that the Fitter can use all the periphery clocks supported by the<br />
device.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED <br />
Default Value<br />
-1 (Unlimited)<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–204 Chapter 6: Fitter Assignments<br />
MAX_REGIONAL_CLOCKS_ALLOWED<br />
MAX_REGIONAL_CLOCKS_ALLOWED<br />
Type<br />
Specifies the maximum number of regional clocks that can be used by the design. A<br />
value of -1 means that the Fitter can use all the regional clocks supported by the<br />
device.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED <br />
Default Value<br />
-1 (Unlimited)<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–205<br />
MEMORY_INTERFACE_DATA_PIN_GROUP<br />
MEMORY_INTERFACE_DATA_PIN_GROUP<br />
Type<br />
Specifies the group width (4, 9, 18, or 36), and associates a pin with another pin.<br />
Turning on this option allows the Fitter to view the pins as part of the same memory<br />
interface pin group. I/O pins of this pin group must be placed in the DQ pin locations<br />
of a single DQS group. This option is ignored if is assigned to anything other than an<br />
I/O pad, input buffer, or output buffer.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name MEMORY_INTERFACE_DATA_PIN_GROUP -from <br />
-to -entity <br />
Example<br />
set_instance_assignment -name MEMORY_INTERFACE_DATA_PIN_GROUP 4 -from<br />
mem_clk[0] -to mem_clk_n[0]<br />
See Also<br />
■ “DQSB_DQS_PAIR” on page 6–86<br />
■ “DQ_GROUP” on page 6–90<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–206 Chapter 6: Fitter Assignments<br />
MEM_INTERFACE_DELAY_CHAIN_CONFIG<br />
MEM_INTERFACE_DELAY_CHAIN_CONFIG<br />
Type<br />
Changes <strong>Quartus</strong> <strong>II</strong> Fitter behavior regarding delay chain configurations on memory<br />
interface pins. This option is ignored if is assigned to anything other than an I/O pad,<br />
input buffer, or output buffer.<br />
Enumeration<br />
Device Support<br />
■ Fitter_optimized<br />
■ Flexible_timing<br />
■ Macro_timing<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG -to -<br />
entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–207<br />
MERGE_TX_PLL_DRIVEN_BY_REGISTERS_WITH_SAME_CLEAR<br />
MERGE_TX_PLL_DRIVEN_BY_REGISTERS_WITH_SAME_CLEAR<br />
Type<br />
Allows merging of HSSI TX PLLs if their reset input are driven by registers that have<br />
the same asynchronous clear input.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_instance_assignment -name<br />
MERGE_TX_PLL_DRIVEN_BY_REGISTERS_WITH_SAME_CLEAR -to -entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–208 Chapter 6: Fitter Assignments<br />
MIGRATION_CONSTRAIN_CORE_RESOURCES<br />
MIGRATION_CONSTRAIN_CORE_RESOURCES<br />
Type<br />
Limits the Compiler to only use those core resources which are also available in the<br />
target migration device.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES <br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–209<br />
MIGRATION_DEVICES<br />
MIGRATION_DEVICES<br />
Type<br />
Shows the selected migration devices for the target device.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name MIGRATION_DEVICES <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–210 Chapter 6: Fitter Assignments<br />
NCEO_OPEN_DRAIN<br />
NCEO_OPEN_DRAIN<br />
Type<br />
Specify whether the Open-Drain feature on the nCEO pin should be enabled or not.<br />
Using this feature decouples the voltage level of the nCEO pin from V CCIO.<br />
You must connect a pull-up resistor to the pin when this feature is enabled.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name NCEO_OPEN_DRAIN <br />
Example<br />
set_global_assignment -name nceo_open_drain on<br />
set_global_assignment -name nceo_open_drain off<br />
Default Value<br />
On<br />
See Also<br />
■ “ENABLE_NCEO_OUTPUT” on page 6–112<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–211<br />
NDQS_LOCAL_CLOCK_DELAY_CHAIN<br />
NDQS_LOCAL_CLOCK_DELAY_CHAIN<br />
Type<br />
Sets the propagation delay on the NDQS signal to the input register of the target pin.<br />
This is an advanced option that should be used only after you have compiled a<br />
project, checked the I/O timing, and determined that the timing is unsatisfactory. For<br />
detailed information on how to use this option, refer to the data sheet for the device<br />
family. This option is ignored if it is applied to anything other than a DQ or DQS pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ HardCopy <strong>II</strong><br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name NDQS_LOCAL_CLOCK_DELAY_CHAIN -to -<br />
entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–212 Chapter 6: Fitter Assignments<br />
OPTIMIZE_FOR_METASTABILITY<br />
OPTIMIZE_FOR_METASTABILITY<br />
Type<br />
Improves the reliability of the design by increasing its Mean Time Between Failures<br />
(MTBF). When this setting is enabled, the Fitter aims to increase the output setup<br />
slacks of synchronizer registers in the design, which can exponentially increase the<br />
design MTBF. This option takes effect only if the TimeQuest timing analyzer is being<br />
used for timing-driven compilation. Use the TimeQuest analyzer<br />
report_metastability command to review the synchronizers detected in your design<br />
and to produce MTBF estimates.<br />
Enumeration<br />
■ Off<br />
■ On<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY <br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–213<br />
OPTIMIZE_HOLD_TIMING<br />
OPTIMIZE_HOLD_TIMING<br />
Type<br />
Allows the Fitter to optimize hold time by adding delay to the appropriate paths. The<br />
Optimize Timing option must be turned on in order for this option to work. If you<br />
use the TimeQuest timing analyzer and specify the I/O Paths and Minimum tpd<br />
Paths setting, all assignments involving I/O pins are optimized. Specifying the All<br />
Paths setting directs the Fitter to optimize the hold time of all paths. Turning off this<br />
option directs the Fitter not to optimize the hold time of any paths.<br />
Enumeration<br />
■ All Paths<br />
■ IO Paths and Minimum TPD Paths<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–214 Chapter 6: Fitter Assignments<br />
OPTIMIZE_HOLD_TIMING<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name OPTIMIZE_HOLD_TIMING <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–215<br />
OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING<br />
OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING<br />
Type<br />
Controls whether the Fitter optimizes I/O pin timing by automatically packing<br />
registers into I/Os to minimize I/O -> register and register -> I/O delays. If you<br />
enable the Normal option, the Fitter opportunistically packs registers into I/Os that<br />
should improve I/O timing. If you enable the Pack All I/O Registers, the Fitter<br />
aggressively tries to pack any registers connected to input, output or output enable<br />
pins into I/Os unless prevented by user constraints or other legality restrictions. By<br />
default, this option is set to Normal. This option requires the Optimize Timing option<br />
to be enabled for it to work.<br />
Enumeration<br />
■ Normal<br />
■ Off<br />
Device Support<br />
■ Pack All IO Registers<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING<br />
<br />
Default Value<br />
Normal<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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OPTIMIZE_MULTI_CORNER_TIMING<br />
OPTIMIZE_MULTI_CORNER_TIMING<br />
Type<br />
Controls whether the Fitter optimizes a design to meet timing requirements at all<br />
process corners and operating conditions. The Optimize Timing logic option must be<br />
enabled for this option to work. If you turn this setting off, designs are optimized to<br />
meet timing only at the slow timing process corner and operating condition. When<br />
you turn this option on, designs are optimized to meet timing at all corners and<br />
operating conditions; as a result, turning on this option helps create a design<br />
implementation that is more robust across process, temperature, and voltage<br />
variations. Turning on this option does not enable multi-corner timing analysis. To<br />
enable multi-corner timing analysis, go to the TimeQuest Timing Analyzer page of<br />
the <strong>Settings</strong> dialog box.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ EPC1<br />
■ EPC2<br />
■ Enhanced Configuration Devices<br />
■ FLEX10KB<br />
■ FLEX8000<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–217<br />
OPTIMIZE_MULTI_CORNER_TIMING<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
■ MAX9000<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING <br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
OPTIMIZE_FAST_CORNER_TIMING<br />
Optimize Fast-Corner Timing<br />
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OPTIMIZE_POWER_DURING_FITTING<br />
OPTIMIZE_POWER_DURING_FITTING<br />
Type<br />
Controls the power-driven compilation setting of the Fitter. This option determines<br />
how aggressively the Fitter optimizes the design for power. If you set this option to<br />
Off, the Fitter does not perform any power optimizations. If you set this option to<br />
Normal compilation, the Fitter performs power optimizations which should not<br />
impact design performance or increase compile time. If you set this option to Extra<br />
effort, the Fitter performs additional power optimizations which may affect design<br />
performance and/or increase compile time. For the best results with Extra Effort<br />
power optimization during fitting, you should specify a Signal Activity <strong>File</strong> (.saf) that<br />
lists the toggle rate of each signal in the design. To generate the most accurate .saf, use<br />
a gate-level simulation, with glitch filtering, of the compiled design. Specify this .saf<br />
as an input to the Power Analyzer in the PowerPlay Power Analysis <strong>Settings</strong>, and<br />
recompile the design with Extra Effort PowerPlay Power Optimization during fitting.<br />
The signal activities (toggle rates) in the .saf help guide the Fitter to reduce power.<br />
Enumeration<br />
■ Extra effort<br />
■ Normal compilation<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix <strong>II</strong><br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–219<br />
OPTIMIZE_POWER_DURING_FITTING<br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING <br />
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING -entity <br />
set_instance_assignment -name OPTIMIZE_POWER_DURING_FITTING -to -<br />
entity <br />
Default Value<br />
Normal compilation<br />
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OPTIMIZE_SSN<br />
OPTIMIZE_SSN<br />
Type<br />
Controls the Simultaneous Switching Noise (SSN) optimization setting of the Fitter.<br />
This option determines how aggressively the Fitter optimizes the design for SSN. If<br />
this option is set to Off, the Fitter does not perform any SSN optimizations. If this<br />
option is set to Normal compilation, the Fitter performs SSN optimizations which<br />
should not impact design performance. When this option is set to Extra effort, the<br />
Fitter performs aggressive SSN optimizations which may affect design performance.<br />
Enumeration<br />
■ Extra effort<br />
■ Normal compilation<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name OPTIMIZE_SSN <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–221<br />
OPTIMIZE_SSN<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
OPTIMIZE_SIGNAL_INTEGRITY<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–222 Chapter 6: Fitter Assignments<br />
OPTIMIZE_TIMING<br />
OPTIMIZE_TIMING<br />
Type<br />
Controls whether the Fitter optimizes to meet maximum delay timing requirements<br />
(for example, clock cycle time). By default, this option is set to Normal compilation.<br />
Turning it off can help fit designs that have extremely high interconnect requirements<br />
and can also reduce compilation time, although at the expense of significant timing<br />
performance (since the Fitter ignores the timing requirements of the design). If this<br />
option is off, other Fitter timing optimization options have no effect (such as<br />
Optimize Hold Timing).<br />
Enumeration<br />
■ Normal compilation<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–223<br />
OPTIMIZE_TIMING<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name OPTIMIZE_TIMING <br />
Default Value<br />
Normal compilation<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
OPTIMIZE_INTERNAL_TIMING<br />
USE_TIMING_DRIVEN_COMPILATION<br />
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6–224 Chapter 6: Fitter Assignments<br />
OUTPUT_BUFFER_DELAY<br />
OUTPUT_BUFFER_DELAY<br />
Type<br />
Specifies the delay value (in ps) for the Programmable Output Buffer Delay. Turning<br />
on this feature should improve the output duty cycle at the cost of worse timing<br />
across the output buffer.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name OUTPUT_BUFFER_DELAY -to -entity <br />
Example<br />
set_instance_assignment -name OUTPUT_BUFFER_DELAY 50 -to pin<br />
set_instance_assignment -name OUTPUT_BUFFER_DELAY 100 -to pin<br />
set_instance_assignment -name OUTPUT_BUFFER_DELAY 150 -to pin<br />
See Also<br />
■ “OUTPUT_BUFFER_DELAY_CONTROL” on page 6–225<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–225<br />
OUTPUT_BUFFER_DELAY_CONTROL<br />
OUTPUT_BUFFER_DELAY_CONTROL<br />
Type<br />
Specifies the edges for the Programmable Output Buffer Delay. Turning on this<br />
feature should improve the output duty cycle at the cost of worse timing across the<br />
output buffer.<br />
Enumeration<br />
■ Both Edges<br />
■ Negative Edge<br />
■ Off<br />
Device Support<br />
■ Positive Edge<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name OUTPUT_BUFFER_DELAY_CONTROL -to -entity<br />
<br />
Example<br />
set_instance_assignment -name OUTPUT_BUFFER_DELAY_CONTROL "Both Edges" -to<br />
pin<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
STRATIX<strong>II</strong>_OUTPUT_DUTY_CYCLE_CONTROL<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–226 Chapter 6: Fitter Assignments<br />
OUTPUT_BUFFER_DELAY_CONTROL<br />
See Also<br />
■ “OUTPUT_BUFFER_DELAY” on page 6–224<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–227<br />
OUTPUT_ENABLE_DELAY<br />
OUTPUT_ENABLE_DELAY<br />
Type<br />
Specifies the propagation delay to the output enable pin from internal logic or the<br />
output enable register implemented in an I/O cell. This is an advanced option that<br />
should be used only after you have compiled a project, checked the I/O timing, and<br />
determined that the timing is unsatisfactory. For detailed information on how to use<br />
this option, refer to the data sheet for the device family. This option is ignored if it is<br />
applied to anything other than an output pin or bidirectional pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name OUTPUT_ENABLE_DELAY -to -entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–228 Chapter 6: Fitter Assignments<br />
OUTPUT_ENABLE_GROUP<br />
OUTPUT_ENABLE_GROUP<br />
Type<br />
Assigns an output enable group number for the specified node. Turning on this option<br />
directs the Fitter to view the specified nodes as an output enable group so as not to<br />
violate the requirements for the maximum number of pins driving out of a VREF<br />
group when a voltage-referenced input pin or bidirectional pin is present. For<br />
bidirectional pins, the Fitter determines all possible pins that may potentially drive<br />
out when any bidirectional pin is driving in by looking at the output enable of all the<br />
bidirectional pins in the VREF group. This behavior can result in the VREF group<br />
exceeding the maximum number of outputs and result in a no fit. Turning on the<br />
Output Enable Group option allows you to specify an output enable group for<br />
specific pins, thus allowing you to specify which pins in the design are driving in and<br />
out at the same time. The Fitter only considers pins as potential outputs when they are<br />
in separate output enable groups or when they are not in an output enable group; by<br />
specifying an output enable group, you can lower the total number of outputs in the<br />
VREF group when any pin is driving in. As a result, the Fitter does not count all of the<br />
potential outputs of the bidirectional pins and the number of outputs in the VREF<br />
group remains in the legal range. You should turn on this option when the Fitter<br />
cannot detect the output enable group of the pins in the VREF group, for example<br />
when the output enables come from a state machine or complex logic. For detailed<br />
information on the number of outputs supported by a VREF group, refer to the<br />
respective device family data sheet.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–229<br />
OUTPUT_ENABLE_GROUP<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name OUTPUT_ENABLE_GROUP -to -entity <br />
Example<br />
set_instance_assignment -name OUTPUT_ENABLE_GROUP 2 -to output_pin[0]<br />
set_instance_assignment -name OUTPUT_ENABLE_GROUP 2 -to output_pin[1]<br />
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6–230 Chapter 6: Fitter Assignments<br />
OUTPUT_PIN_LOAD<br />
OUTPUT_PIN_LOAD<br />
Type<br />
Specifies the capacitive load, in picofarads (pF), on output pins for each I/O standard.<br />
These settings affect FPGA pins only. To specify board trace, termination, and<br />
capacitive load parameters for use with Advanced I/O Timing, use the Board Trace<br />
Model tab. Capacitive loading is ignored if applied to anything other than an output<br />
or bidirectional pin, or if Advanced I/O Timing is enabled.<br />
Integer<br />
Device Support<br />
The value must be between these two numbers, inclusive: 0, 10000<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment is copied to any duplicated nodes<br />
Syntax<br />
set_instance_assignment -name OUTPUT_PIN_LOAD -to -entity <br />
set_global_assignment -name OUTPUT_PIN_LOAD -section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–231<br />
OUTPUT_TERMINATION<br />
OUTPUT_TERMINATION<br />
Type<br />
Allows the Compiler to configure the on-chip termination (OCT) and impedance<br />
matching for an I/O pin. OCT helps to prevent signal reflections and maintain signal<br />
integrity. This option is ignored if it is applied to anything other than an I/O pad,<br />
input buffer, or output buffer. This option should be applied to an I/O pad or output<br />
buffer of an I/O in bidirectional or output mode. A bidirectional I/O may also have<br />
an input termination assignment.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name OUTPUT_TERMINATION -to -entity <br />
Example<br />
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH<br />
CALIBRATION" -to pin_name<br />
See Also<br />
■ “IO_STANDARD” on page 6–186<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–232 Chapter 6: Fitter Assignments<br />
OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS<br />
OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS<br />
Type<br />
Specifies whether you want the Fitter to use default electromigration values, or if you<br />
want to specify maximum consecutive output and maximum current values.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS<br />
<br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–233<br />
PAD_TO_CORE_DELAY<br />
PAD_TO_CORE_DELAY<br />
Type<br />
Specifies the propagation delay from an input or bidirectional pin to logic and<br />
embedded cells within the device. This is an advanced option that should be used<br />
only after you have compiled a project, checked the I/O timing, and determined that<br />
the timing is unsatisfactory. For detailed information on how to use this option, refer<br />
to the data sheet for the device family. This option is ignored if it is applied to<br />
anything other than an input or bidirectional pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name PAD_TO_CORE_DELAY -to -entity <br />
set_instance_assignment -name PAD_TO_CORE_DELAY -from -to -<br />
entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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PAD_TO_DDIO_REGISTER_DELAY<br />
PAD_TO_DDIO_REGISTER_DELAY<br />
Type<br />
Specifies the propagation delay from an input pin to the data input of the DDIO low<br />
capture input register in the I/O cell associated with the pin. This is an advanced<br />
option that should be used only after you have compiled a project, checked the I/O<br />
timing, and determined that the timing is unsatisfactory. For detailed information on<br />
how to use this option, refer to the data sheet for the device family. This option is<br />
ignored if it is applied to anything other than an input or bidirectional pin that uses<br />
DDIO functionality.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name PAD_TO_DDIO_REGISTER_DELAY -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–235<br />
PAD_TO_INPUT_REGISTER_DELAY<br />
PAD_TO_INPUT_REGISTER_DELAY<br />
Type<br />
Specifies the propagation delay from an input pin to the data input of the input<br />
register implemented in the I/O cell associated with the pin. This is an advanced<br />
option that should be used only after you have compiled a project, checked the I/O<br />
timing, and determined that the timing is unsatisfactory. For detailed information on<br />
how to use this option, refer to the data sheet for the device family. This option is<br />
ignored if it is applied to anything other than an input or bidirectional pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name PAD_TO_INPUT_REGISTER_DELAY -to -entity<br />
<br />
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PCI_IO<br />
PCI_IO<br />
Type<br />
Turns on PCI compatibility for a pin. For example, when the VCCIO of an EP20K400<br />
device operates at 3.3 V and PCI I/O is turned on for a pin, the Compiler clamps the<br />
pin’s signal to the VCCIO value, thus making the pin 3.3-V PCI-compliant. This<br />
option is ignored if it is applied to anything other than a pin or a top-level design<br />
entity.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name PCI_IO -entity <br />
set_instance_assignment -name PCI_IO -to -entity <br />
set_global_assignment -name PCI_IO <br />
Example<br />
set_instance_assignment -name PCI_IO ON -to pin<br />
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Chapter 6: Fitter Assignments 6–237<br />
PCI_IO<br />
Default Value<br />
Off<br />
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6–238 Chapter 6: Fitter Assignments<br />
PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING<br />
PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING<br />
Type<br />
Specifies that the <strong>Quartus</strong> <strong>II</strong> software should perform automatic insertion of pipeline<br />
stages for asynchronous clear and asynchronous load signals during fitting to increase<br />
circuit performance. This option is useful for asynchronous signals that are failing<br />
recovery and removal timing because they feed registers using a high-speed clock.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
This assignment supports wildcards.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–239<br />
PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING<br />
Syntax<br />
set_global_assignment -name<br />
PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING <br />
set_global_assignment -name<br />
PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING -entity <br />
<br />
set_instance_assignment -name<br />
PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING -to -entity <br />
Default Value<br />
Off<br />
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6–240 Chapter 6: Fitter Assignments<br />
PHYSICAL_SYNTHESIS_COMBO_LOGIC<br />
PHYSICAL_SYNTHESIS_COMBO_LOGIC<br />
Type<br />
Specifies that the <strong>Quartus</strong> <strong>II</strong> software should perform physical synthesis<br />
optimizations on combinational logic during synthesis and fitting to increase circuit<br />
performance.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
This assignment supports wildcards.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–241<br />
PHYSICAL_SYNTHESIS_COMBO_LOGIC<br />
Syntax<br />
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC <br />
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC -entity <br />
set_instance_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC -to -<br />
entity <br />
Default Value<br />
Off<br />
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6–242 Chapter 6: Fitter Assignments<br />
PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA<br />
PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA<br />
Type<br />
Specifies that the Fitter should perform physical synthesis optimizations on<br />
combinational logic during fitting to achieve a fit.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
This assignment supports wildcards.<br />
Syntax<br />
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA<br />
<br />
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA -<br />
entity <br />
set_instance_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA -to<br />
-entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–243<br />
PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA<br />
Default Value<br />
Off<br />
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PHYSICAL_SYNTHESIS_EFFORT<br />
PHYSICAL_SYNTHESIS_EFFORT<br />
Type<br />
Specifies the amount of effort, in terms of compile time, physical synthesis should use.<br />
Compared to the Default setting, a setting of Extra uses extra compile time to try to<br />
gain extra circuit performance. Conversely, a setting of Fast uses less compile time<br />
but may reduce the performance gain that physical synthesis is able to achieve.<br />
Enumeration<br />
■ Extra<br />
■ Fast<br />
■ Normal<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
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Chapter 6: Fitter Assignments 6–245<br />
PHYSICAL_SYNTHESIS_EFFORT<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT <br />
Default Value<br />
Normal<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
PHYSICAL_SYNTHESIS_EXTRA_EFFORT<br />
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6–246 Chapter 6: Fitter Assignments<br />
PHYSICAL_SYNTHESIS_LOG_FILE<br />
PHYSICAL_SYNTHESIS_LOG_FILE<br />
Type<br />
Specifies the log file that lists all the physical synthesis operations performed in a<br />
previous compile that need to be reproduced. This log should be generated during a<br />
Stratix <strong>II</strong> compile with physical synthesis on, and in which a Hardcopy <strong>II</strong> device is<br />
specified for migration. When the design is migrated to Hardcopy <strong>II</strong>, this log file<br />
allows the original physical synthesis operations performed on the Stratix <strong>II</strong> device to<br />
be replicated on the Hardcopy <strong>II</strong> device.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ HardCopy <strong>II</strong><br />
■ Stratix <strong>II</strong>I<br />
Syntax<br />
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–247<br />
PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA<br />
PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA<br />
Type<br />
Specifies that the Fitter should perform physical synthesis optimizations on logic and<br />
registers, specifically allowing the mapping of logic and registers into unused<br />
memory blocks during fitting to achieve a fit.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Notes<br />
This assignment is included in the Fitter report.<br />
This assignment supports wildcards.<br />
Syntax<br />
set_global_assignment -name<br />
PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA <br />
set_global_assignment -name<br />
PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA -entity <br />
<br />
set_instance_assignment -name<br />
PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA -to -entity <br />
Default Value<br />
Off<br />
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6–248 Chapter 6: Fitter Assignments<br />
PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION<br />
PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION<br />
Type<br />
Specifies that the Fitter should perform physical synthesis optimizations on registers,<br />
specifically allowing register duplication, during fitting to increase circuit<br />
performance.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
This assignment supports wildcards.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–249<br />
PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION<br />
Syntax<br />
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION<br />
<br />
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION -<br />
entity <br />
set_instance_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION -to<br />
-entity <br />
Default Value<br />
Off<br />
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6–250 Chapter 6: Fitter Assignments<br />
PHYSICAL_SYNTHESIS_REGISTER_RETIMING<br />
PHYSICAL_SYNTHESIS_REGISTER_RETIMING<br />
Type<br />
Specifies that the <strong>Quartus</strong> <strong>II</strong> software should perform physical synthesis<br />
optimizations on registers, specifically allowing register retiming, during synthesis<br />
and fitting to increase circuit performance.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
This assignment supports wildcards.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–251<br />
PHYSICAL_SYNTHESIS_REGISTER_RETIMING<br />
Syntax<br />
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING <br />
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING -entity<br />
<br />
set_instance_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING -to<br />
-entity <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–252 Chapter 6: Fitter Assignments<br />
PLACEMENT_EFFORT_MULTIPLIER<br />
PLACEMENT_EFFORT_MULTIPLIER<br />
Type<br />
Controls how much time the Fitter spends in placement. The default value is 1.0 and<br />
legal values must be greater than 0. Specifying a floating-point number allows you to<br />
control the placement effort. A higher value increases CPU time but may improve<br />
placement quality. For example, a value of 4 increases fitting time by approximately 2<br />
to 4 times but may increase quality.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ EPC1<br />
■ EPC2<br />
■ Enhanced Configuration Devices<br />
■ FLEX10KB<br />
■ FLEX8000<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX9000<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–253<br />
PLACEMENT_EFFORT_MULTIPLIER<br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER <br />
Default Value<br />
1.0<br />
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6–254 Chapter 6: Fitter Assignments<br />
PLL_AUTO_RESET<br />
PLL_AUTO_RESET<br />
Type<br />
Causes the PLL to self-reset automatically on loss of lock. The lock time of a PLL is<br />
defined as the amount of time required by the PLL to attain the target frequency and<br />
phase relationship after device power-up, after a change in the PLL output frequency,<br />
or after resetting the PLL.<br />
A PLL might lose lock for a number of reasons, such as the following causes:<br />
■ Excessive jitter on the reference clock. For PLL input jitter specification, refer to the<br />
DC and Switching Characteristics chapter in the relevant device handbook.<br />
■ Excessive switching noise on the clock inputs of the PLL.<br />
■ Excessive noise from the power supply can cause high output jitter and possible<br />
loss of lock.<br />
■ A glitch or stopping of the input clock to the PLL.<br />
■ Resetting the PLL by asserting the reset port of the PLL.<br />
■ An attempt to reconfigure the PLL might cause the M counter, N counter, or phase<br />
shift to change, which causes the PLL to lose lock. However, changes to the postscale<br />
counters do not affect the PLL locked signal.<br />
■ PLL reference clock frequency drifts outside the lock range specification.<br />
Boolean<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_instance_assignment -name PLL_AUTO_RESET -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–255<br />
PLL_BANDWIDTH_PRESET<br />
PLL_BANDWIDTH_PRESET<br />
Type<br />
Specifies the PLL bandwidth preset setting.<br />
Enumeration<br />
■ Auto<br />
■ High<br />
■ Low<br />
■ Medium<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_instance_assignment -name PLL_BANDWIDTH_PRESET -to -entity<br />
<br />
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PLL_CHANNEL_SPACING<br />
PLL_CHANNEL_SPACING<br />
Type<br />
Specifies the PLL channel spacing. The PLL channel spacing is the frequency<br />
difference between successive oscillations of the feedback clock into the phase<br />
frequency detector.<br />
Frequency<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_instance_assignment -name PLL_CHANNEL_SPACING -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–257<br />
PLL_COMPENSATE<br />
PLL_COMPENSATE<br />
Type<br />
Allows you to specify an output pin as a compensation target for a PLL in<br />
ZERO_DELAY_BUFFER or EXTERNAL_FEEDBACK mode, or an input pin or a<br />
group of input pins as compensation targets for a PLL in SOURCE_SYNCHRONOUS<br />
mode. If assigned to an output pin, the pin must be fed by the external clock output<br />
port of a PLL in a Stratix, Hardcopy Stratix or Cyclone device, or the compensated<br />
clock output port of a PLL in other devices. Any other output pins fed by the same<br />
PLL generally are not delay compensated, especially if they have different I/O<br />
standards. If assigned to an input pin or a group of input pins, the input pins must<br />
drive input registers that are clocked by the compensated clock output port of a PLL<br />
in SOURCE_SYNCHRONOUS mode. This option is ignored if it is applied to<br />
anything other than an output or input pin as described previously.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–258 Chapter 6: Fitter Assignments<br />
PLL_COMPENSATE<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name PLL_COMPENSATE -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–259<br />
PLL_COMPENSATION_MODE<br />
PLL_COMPENSATION_MODE<br />
Specifies the routing path of the PLL feedback clock and adjusts the delay chains in<br />
the PLL.<br />
■ Direct—The aim of this setting is to produce the smallest possible jitter at the PLL<br />
output. You can perform this by minimizing the length of the feedback path by not<br />
compensating for anything.<br />
■ External Feedback—The goal is to have the clock edge at the clock output pin to<br />
occur earlier than the clock edge at the clock input (reference) pin, by the amount<br />
of board trace delay placed between the clock output pin and the external<br />
feedback input pin. In this mode what needs to be compensated for within the<br />
FPGA is any difference in delay between the two paths:<br />
■ Clock Input Pin to the PLL PFD input<br />
■ External Feedback Input Pin to the PLL PFD input<br />
■ LVDS—The aim of this setting is to maintain the same data and clock timing<br />
relationship seen at the pins at the internal SERDES capture register. Thus, this<br />
mode ideally compensates for the delay of the LVDS clock network, plus any<br />
differences in delay between the following two paths:<br />
■ Data Pin to SERDES capture register<br />
■ Clock Input Pin to SERDES capture register<br />
The compensation mimic path is designed to mimic the clock and data delay of the<br />
receiver side.<br />
■ Normal—The aim of this setting is to have the clock edge at an IOE or LE register<br />
to occur at the same time that it does at the Clock Input Pin. Thus, this mode<br />
ideally compensates for the clock network used and the delay from the Clock<br />
Input Pin to the PLL PFD input. Since you are unable to compensate for the delay<br />
in the first stage of the input buffer, you must use a delay chain for compensation.<br />
■ Source Synchronous—The aim of this setting is to maintain the same data and<br />
clock timing relationship seen at the pins at any IOE register. Thus, this mode<br />
ideally compensates for the delay of the clock network used, including any<br />
differences in delay between the following two paths:<br />
■ Data Pin to IOE register input<br />
■ Clock Input Pin to PLL PFD input<br />
There is a delay cell block in the feedback path to compensate for the timing<br />
differences between the SE and DIFF input delay in the IO register and wire delay.<br />
■ Zero Delay Buffer—The goal is to have zero delay between a clock edge at the<br />
clock input pin and the clock output pin. This consumes a clock output pin to<br />
provide the output buffer delay compensation. Thus this mode ideally<br />
compensates for the delay from the clock input pin to the PLL PFD input, plus the<br />
delay from the PLL output to the clock output pin.<br />
If the input clock and feedback buffers use different IO standard, we need to<br />
compensate the delay different by using delay chain.<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–260 Chapter 6: Fitter Assignments<br />
PLL_COMPENSATION_MODE<br />
Type<br />
Enumeration<br />
■ Direct<br />
■ External Feedback<br />
■ LVDS<br />
■ Normal<br />
Device Support<br />
■ Source Synchronous<br />
■ Zero Delay Buffer<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_instance_assignment -name PLL_COMPENSATION_MODE -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–261<br />
PLL_ENFORCE_USER_PHASE_SHIFT<br />
PLL_ENFORCE_USER_PHASE_SHIFT<br />
Type<br />
Ensures that phase shift requirements are given higher priority.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name PLL_ENFORCE_USER_PHASE_SHIFT -to -<br />
entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–262 Chapter 6: Fitter Assignments<br />
PLL_FEEDBACK_CLOCK_SIGNAL<br />
PLL_FEEDBACK_CLOCK_SIGNAL<br />
Type<br />
Allows you to specify whether PLL feedback clock signal should be routed using<br />
global or regional routing paths in the PLL conversion code to fractional PLL.<br />
Enumeration<br />
Device Support<br />
■ Global Clock<br />
■ Regional Clock<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_instance_assignment -name PLL_FEEDBACK_CLOCK_SIGNAL -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–263<br />
PLL_FORCE_OUTPUT_COUNTER<br />
PLL_FORCE_OUTPUT_COUNTER<br />
Type<br />
Forces which counter to use for a particular PLL clock output. By default, the<br />
Compiler automatically determines the best counter to use based on clock usage and<br />
other routing conflicts, but can be overridden with this option. Using this option can<br />
cause clock routing problems, as the clock router cannot rotate counters to resolve<br />
conflicts. Also refer to option “PRESERVE_PLL_COUNTER_ORDER” on page 6–272.<br />
Enumeration<br />
■ C0<br />
■ C1<br />
■ C2<br />
■ C3<br />
■ C4<br />
■ C5<br />
■ C6<br />
■ C7<br />
■ C8<br />
■ C9<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–264 Chapter 6: Fitter Assignments<br />
PLL_FORCE_OUTPUT_COUNTER<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name PLL_FORCE_OUTPUT_COUNTER -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–265<br />
PLL_FORCE_OUTPUT_COUNTER_HARDCOPY_REPLAY<br />
PLL_FORCE_OUTPUT_COUNTER_HARDCOPY_REPLAY<br />
Type<br />
Forces which counter to use for a particular PLL clock output. By default, the<br />
Compiler automatically determines the best counter to use based on clock usage and<br />
other routing conflicts, but can be overridden with this option. Using this option can<br />
cause clock routing problems, as the clock router cannot rotate counters to resolve<br />
conflicts. Also refer to option “PRESERVE_PLL_COUNTER_ORDER” on page 6–272.<br />
Enumeration<br />
■ C0<br />
■ C1<br />
■ C2<br />
■ C3<br />
■ C4<br />
■ C5<br />
■ C6<br />
■ C7<br />
■ C8<br />
■ C9<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GZ<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name PLL_FORCE_OUTPUT_COUNTER_HARDCOPY_REPLAY -to<br />
-entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–266 Chapter 6: Fitter Assignments<br />
PLL_IGNORE_MIGRATION_DEVICES<br />
PLL_IGNORE_MIGRATION_DEVICES<br />
Type<br />
Forces the Compiler to ignore the migration devices when calculating the PLL<br />
settings. Normally, the PLL is configured to work for all migration devices in addition<br />
to the current device. When this option is enabled, the Compiler ignores the PLL<br />
constraints for the migration devices, and only considers the PLL constraints from the<br />
current device.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name PLL_IGNORE_MIGRATION_DEVICES -to -<br />
entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–267<br />
PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING<br />
PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING<br />
Type<br />
Allows the Fitter to set the phase shift of a PLL output counter, and hence the phase<br />
shift of its generated clock, to improve timing for all edges affected by this clock.<br />
Apply multicycle timing exceptions to paths between the generated clock and other<br />
clocks in the design to avoid timing violations.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_instance_assignment -name PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING -to <br />
-entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–268 Chapter 6: Fitter Assignments<br />
PLL_OUTPUT_CLOCK_FREQUENCY<br />
PLL_OUTPUT_CLOCK_FREQUENCY<br />
Type<br />
Specifies the output clock frequency of the PLL.<br />
Frequency<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_instance_assignment -name PLL_OUTPUT_CLOCK_FREQUENCY -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–269<br />
PLL_PFD_CLOCK_FREQUENCY<br />
PLL_PFD_CLOCK_FREQUENCY<br />
Type<br />
Specifies the phase frequency detector (PFD) clock frequency.<br />
Frequency<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_instance_assignment -name PLL_PFD_CLOCK_FREQUENCY -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–270 Chapter 6: Fitter Assignments<br />
PLL_TYPE<br />
PLL_TYPE<br />
Type<br />
Specifies a specific PLL implementation to target.<br />
Enumeration<br />
■ ATX<br />
■ CMU<br />
■ fPLL<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_instance_assignment -name PLL_TYPE -to -entity <br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–271<br />
PLL_VCO_CLOCK_FREQUENCY<br />
PLL_VCO_CLOCK_FREQUENCY<br />
Type<br />
Specifies the voltage controlled oscillator (VCO) output clock frequency.<br />
Frequency<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_instance_assignment -name PLL_VCO_CLOCK_FREQUENCY -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–272 Chapter 6: Fitter Assignments<br />
PRESERVE_PLL_COUNTER_ORDER<br />
PRESERVE_PLL_COUNTER_ORDER<br />
Type<br />
Preserves the order of PLL clock outputs used when selecting corresponding output<br />
counters. For example, a clk0 output uses a C0 counter and a clk2 output uses a C2<br />
counter. Turning this option can cause clock routing problems, as the clock router<br />
cannot rotate counters to resolve conflicts.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name PRESERVE_PLL_COUNTER_ORDER -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–273<br />
PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_ FRACTION_OF_USED_LAB_TILES<br />
PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_<br />
FRACTION_OF_USED_LAB_TILES<br />
Type<br />
Sets an upper limit on the fraction of the LAB tiles used by your design that can be<br />
high-speed. Legal values must be between 0.0 and 1.0. The default value is 1.0. A<br />
value of 1.0 means that there is no restriction on the number of high-speed tiles, and<br />
the Fitter uses the minimum number needed to meet the timing requirements of your<br />
design. Specifying a value lower than 1.0 might degrade timing quality, because some<br />
timing critical resources might be forced into low-power mode.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GZ<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name<br />
PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES <br />
Default Value<br />
1.0<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–274 Chapter 6: Fitter Assignments<br />
PROGRAMMABLE_POWER_TECHNOLOGY_SETTING<br />
PROGRAMMABLE_POWER_TECHNOLOGY_SETTING<br />
Type<br />
Controls how the Fitter configures tiles to operate in high-speed mode or low-power<br />
mode. Automatic specifies that the Fitter should try to minimize power without<br />
sacrificing timing performance. Minimize Power Only specifies that the Fitter should<br />
set the maximum number of tiles to operate in low-power mode. Force All Tiles with<br />
Failing Timing Paths to High Speed specifies that the Fitter should ensure that all<br />
paths that are failing timing are set to high-speed mode. For designs that meet timing,<br />
the behavior of this setting should be similar to the Automatic setting. For designs<br />
that fail timing, all paths with negative slack is put in high-speed mode. This does not<br />
likely increase the speed of the design. Although it may increase static power<br />
consumption, it may assist in determining which logic paths need to be re-designed in<br />
order to close timing.<br />
Enumeration<br />
■ Automatic<br />
Device Support<br />
■ Force All Tiles with Failing Timing Paths to High Speed<br />
■ Minimize Power Only<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GZ<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING <br />
Default Value<br />
Force All Tiles with Failing Timing Paths to High Speed<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–275<br />
PROGRAMMABLE_PREEMPHASIS<br />
PROGRAMMABLE_PREEMPHASIS<br />
Type<br />
Implements control of programmable pre-emphasis, which helps compensate for high<br />
frequency losses. This option is ignored if it is applied to anything other than an<br />
output or bidirectional pin, or a top-level design entity containing output or<br />
bidirectional pins.<br />
This option specifies a pre-emphasis setting for the true differential output buffer of a<br />
pin. Since an input-only pin does not use true differential output buffer, this option is<br />
ignored on such pin. This option is not supported on a pin with I/O standard which<br />
uses single-ended output buffer such as LVTTL. Some differential I/O standards are<br />
implemented with two single-ended output buffers and therefore this option cannot<br />
be supported. Please refer to the family data sheet for which I/O standards support<br />
programmable pre-emphasis. This option can only be supported on pin locations that<br />
support programmable pre-emphasis. Dedicated programming pins, such as TDO,<br />
do not support programmable pre-emphasis. 0 is the slowest pre-emphasis value.<br />
The higher the value the stronger the pre-emphasis. The highest pre-emphasis value is<br />
family dependent. A pin using this option should also use IO_STANDARD option.<br />
Integer<br />
Device Support<br />
The value must be between these two numbers, inclusive: 0, 3<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–276 Chapter 6: Fitter Assignments<br />
PROGRAMMABLE_PREEMPHASIS<br />
Syntax<br />
set_global_assignment -name PROGRAMMABLE_PREEMPHASIS -entity <br />
<br />
set_instance_assignment -name PROGRAMMABLE_PREEMPHASIS -to -entity<br />
<br />
set_global_assignment -name PROGRAMMABLE_PREEMPHASIS <br />
Example<br />
set_instance_assignment -name PROGRAMMABLE_PREEMPHASIS 0 -to pin<br />
See Also<br />
■ “IO_STANDARD” on page 6–186<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–277<br />
PROGRAMMABLE_VOD<br />
PROGRAMMABLE_VOD<br />
Type<br />
Implements control of programmable VOD. This option is ignored if it is applied to<br />
anything other than an output or bidirectional pin, or a top-level design entity<br />
containing output or bidirectional pins.<br />
This option specifies a VOD setting for the true differential output buffer of a pin.<br />
Since an input-only pin does not use true differential output buffer, this option is<br />
ignored on such pin. This option is not supported on a pin with I/O standard which<br />
uses single-ended output buffer such as LVTTL. Some differential I/O standards are<br />
implemented with two single-ended output buffers and therefore this option cannot<br />
be supported. Please refer to the family data sheet for which I/O standards support<br />
programmable VOD. This option can only be supported on pin locations that support<br />
programmable VOD. Dedicated programming pins, such as TDO, do not support<br />
programmable VOD. 0 is the slowest VOD value. The higher the value the higher the<br />
differential output voltage. The highest VOD value is family dependent. A pin using<br />
this option should also use IO_STANDARD option.<br />
Integer<br />
Device Support<br />
The value must be between these two numbers, inclusive: 0, 3<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name PROGRAMMABLE_VOD -entity <br />
set_instance_assignment -name PROGRAMMABLE_VOD -to -entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–278 Chapter 6: Fitter Assignments<br />
PROGRAMMABLE_VOD<br />
set_global_assignment -name PROGRAMMABLE_VOD <br />
Example<br />
set_instance_assignment -name PROGRAMMABLE_PREEMPHASIS 0 -to pin<br />
See Also<br />
■ “IO_STANDARD” on page 6–186<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–279<br />
PR_DONE_OPEN_DRAIN<br />
PR_DONE_OPEN_DRAIN<br />
Type<br />
Specifies whether the Open-Drain feature on the PR_DONE pin should be enabled or<br />
not.<br />
Using this feature decouples the voltage level of the PR_DONE pin from V CCIO.<br />
You must connect a pull-up resistor to the pin when this feature is enabled.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name PR_DONE_OPEN_DRAIN <br />
Example<br />
set_global_assignment -name pr_done_open_drain on<br />
set_global_assignment -name pr_done_open_drain off<br />
Default Value<br />
On<br />
See Also<br />
■ “ENABLE_PR_PINS” on page 6–113<br />
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PR_ERROR_OPEN_DRAIN<br />
PR_ERROR_OPEN_DRAIN<br />
Type<br />
Specifies whether the Open-Drain feature on the PR_ERROR pin should be enabled or<br />
not.<br />
Using this feature decouples the voltage level of the PR_ERROR pin from V CCIO.<br />
You must connect a pull-up resistor to the pin when this feature is enabled.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name PR_ERROR_OPEN_DRAIN <br />
Example<br />
set_global_assignment -name pr_error_open_drain on<br />
set_global_assignment -name pr_error_open_drain off<br />
Default Value<br />
On<br />
See Also<br />
■ “ENABLE_PR_PINS” on page 6–113<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–281<br />
PR_READY_OPEN_DRAIN<br />
PR_READY_OPEN_DRAIN<br />
Type<br />
Specifies whether the Open-Drain feature on the PR_READY pin should be enabled or<br />
not.<br />
Using this feature decouples the voltage level of the PR_READY pin from V CCIO.<br />
You must connect a pull-up resistor to the pin when this feature is enabled.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name PR_READY_OPEN_DRAIN <br />
Example<br />
set_global_assignment -name pr_ready_open_drain on<br />
set_global_assignment -name pr_ready_open_drain off<br />
Default Value<br />
On<br />
See Also<br />
■ “ENABLE_PR_PINS” on page 6–113<br />
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QDR_D_PIN_GROUP<br />
QDR_D_PIN_GROUP<br />
Type<br />
Assigns a quad data rate (QDR) D (data) output pin group number to a specified pin.<br />
Turning on this option allows the Fitter to view pins as a QDR D output pin group.<br />
I/O pins of a QDR D output pin group must be placed in the DQ pin locations of a<br />
single DQS group. This option is ignored if is assigned to anything other than an I/O<br />
pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong><br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name QDR_D_PIN_GROUP -to -entity <br />
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RESERVE_ALL_UNUSED_PINS<br />
RESERVE_ALL_UNUSED_PINS<br />
Type<br />
Reserves all unused pins on the target device in one of 5 states: as inputs that are tristated,<br />
as outputs that drive ground, as outputs that drive an unspecified signal, as<br />
input tri-stated with bus-hold, or as input tri-stated with weak pull-up.<br />
Enumeration<br />
Device Support<br />
■ As input tri-stated<br />
■ As input tri-stated with bus-hold<br />
■ As input tri-stated with weak pull-up<br />
■ As output driving an unspecified signal<br />
■ As output driving ground<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_global_assignment -name RESERVE_ALL_UNUSED_PINS <br />
Default Value<br />
As output driving ground<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
RESERVED_ALL_UNUSED_PINS<br />
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RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP<br />
RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP<br />
Type<br />
Reserves all unused pins on the target device in one of 5 states: as inputs that are tristated,<br />
as outputs that drive ground, as outputs that drive an unspecified signal, as<br />
input tri-stated with bus-hold, or as input tri-stated with weak pull-up.<br />
Enumeration<br />
Device Support<br />
■ As input tri-stated<br />
■ As input tri-stated with bus-hold<br />
■ As input tri-stated with weak pull-up<br />
■ As output driving an unspecified signal<br />
■ As output driving ground<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP <br />
Default Value<br />
As input tri-stated with weak pull-up<br />
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RESERVE_ASDO_AFTER_CONFIGURATION<br />
RESERVE_ASDO_AFTER_CONFIGURATION<br />
Type<br />
Specifies how the ASDO pin should be used when the device is operating in user<br />
mode after configuration is complete. Depending on the current device and<br />
configuration scheme, the ASDO pin can be reserved as a regular I/O pin, as an input<br />
that is tri-stated, as an output that drives ground, or as an output that drives an<br />
unspecified signal. If this pin is reserved as a regular I/O pin, the ASDO pin can be<br />
used as an ordinary I/O pin after configuration.<br />
Enumeration<br />
Device Support<br />
■ As input tri-stated<br />
■ Use as regular IO<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION <br />
Example<br />
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS<br />
REGULAR IO"<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
RESERVE_SDO_AFTER_CONFIGURATION<br />
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RESERVE_DATA0_AFTER_CONFIGURATION<br />
RESERVE_DATA0_AFTER_CONFIGURATION<br />
Type<br />
Specifies how the Data[0] pin should be used when the device is operating in user<br />
mode after configuration is complete. Depending on the current device and<br />
configuration scheme, the Data[0] pin can be reserved as a regular I/O pin, as an<br />
input that is tri-stated, as an output that drives ground, as an output that drives an<br />
unspecified signal, or compiler configured. If the Data[0] pin is reserved as a regular<br />
I/O pin, the Data[0] pin can be used as an ordinary I/O pin after configuration. If the<br />
Data[0] pin is only used to interface with external memory for configuration, the<br />
Data[0] pin should be reserved as compiler configured.<br />
Enumeration<br />
Device Support<br />
■ As input tri-stated<br />
■ As output driving an unspecified signal<br />
■ As output driving ground<br />
■ Compiler configured<br />
■ Use as regular IO<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
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RESERVE_DATA0_AFTER_CONFIGURATION<br />
Syntax<br />
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION <br />
Example<br />
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS<br />
REGULAR IO"<br />
Default Value<br />
As input tri-stated<br />
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RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION<br />
RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION<br />
Type<br />
Specifies how the Data[15..8] pins should be used when the device is operating in user<br />
mode after configuration is complete.<br />
Depending on the current device and configuration scheme, these pins can be<br />
reserved as regular I/O pins, as inputs that are tri-stated, as outputs that drive<br />
ground, or as outputs that drive an unspecified signal. If this pin is reserved as a<br />
regular I/O pin, the Data[15..8] pins can be used as ordinary I/O pins after<br />
configuration.<br />
Enumeration<br />
Device Support<br />
■ As input tri-stated<br />
■ As output driving an unspecified signal<br />
■ As output driving ground<br />
■ Use as regular IO<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name<br />
RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION <br />
Example<br />
set_global_assignment -name<br />
RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "USE AS REGULAR IO"<br />
Default Value<br />
Use as regular IO<br />
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RESERVE_DATA1_AFTER_CONFIGURATION<br />
RESERVE_DATA1_AFTER_CONFIGURATION<br />
Type<br />
Specifies how the Data[1]/ASDO pin should be used when the device is operating in<br />
user mode after configuration is complete. Depending on the current device and<br />
configuration scheme, this pin can be reserved as a regular I/O pin, as an input that is<br />
tri-stated, as an output that drives ground, as an output that drives an unspecified<br />
signal, or compiler configured. If the Data[1]/ASDO pin is reserved as a regular I/O<br />
pin, the Data[1]/ASDO pin can be used as an ordinary I/O pin after configuration. If<br />
the Data[1]/ASDO pin is only used to interface with external memory for<br />
configuration, the Data[1]/ASDO pin should be reserved as compiler configured.<br />
Enumeration<br />
Device Support<br />
■ As input tri-stated<br />
■ As output driving an unspecified signal<br />
■ As output driving ground<br />
■ Compiler configured<br />
■ Use as regular IO<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
Syntax<br />
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION <br />
Example<br />
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS<br />
REGULAR IO"<br />
Default Value<br />
As input tri-stated<br />
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RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION<br />
RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION<br />
Type<br />
Specifies how the Data[31..16] pins should be used when the device is operating in<br />
user mode after configuration is complete.<br />
Depending on the current device and configuration scheme, these pins can be<br />
reserved as regular I/O pins, as inputs that are tri-stated, as outputs that drive<br />
ground, or as outputs that drive an unspecified signal. If this pin is reserved as a<br />
regular I/O pin, the Data[31..16] pins can be used as ordinary I/O pins after<br />
configuration.<br />
Enumeration<br />
Device Support<br />
■ As input tri-stated<br />
■ As output driving an unspecified signal<br />
■ As output driving ground<br />
■ Use as regular IO<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name<br />
RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION <br />
Example<br />
set_global_assignment -name<br />
RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "USE AS REGULAR IO"<br />
Default Value<br />
Use as regular IO<br />
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RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION<br />
RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION<br />
Type<br />
Specifies how the Data[7..1] pins should be used when the device is operating in user<br />
mode after configuration is complete. Depending on the current device and<br />
configuration scheme, these pins can be reserved as regular I/O pins, as inputs that<br />
are tri-stated, as outputs that drive ground, or as outputs that drive an unspecified<br />
signal. If this pin is reserved as a regular I/O pin, the Data[7..1] pins can be used as<br />
ordinary I/O pins after configuration.<br />
Enumeration<br />
Device Support<br />
■ As input tri-stated<br />
■ As output driving an unspecified signal<br />
■ As output driving ground<br />
■ Use as regular IO<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name<br />
RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION <br />
Example<br />
set_global_assignment -name<br />
RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"<br />
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RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION<br />
Default Value<br />
Use as regular IO<br />
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RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION<br />
RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION<br />
Type<br />
Specifies how the Data[7..2] pins should be used when the device is operating in user<br />
mode after configuration is complete. Depending on the current device and<br />
configuration scheme, these pins can be reserved as regular I/O pins, as inputs that<br />
are tri-stated, as outputs that drive ground, as outputs that drive an unspecified<br />
signal, or compiler configured. If the Data[7..2] pins are reserved as a regular I/O<br />
pins, the Data[7..2] pins can be used as ordinary I/O pins after configuration. If<br />
Data[7..2] pins are only used to interface with external memory for configuration, the<br />
Data[7..2] pins should be reserved as compiler configured.<br />
Enumeration<br />
Device Support<br />
■ As input tri-stated<br />
■ As output driving an unspecified signal<br />
■ As output driving ground<br />
■ Compiler configured<br />
■ Use as regular IO<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
Syntax<br />
set_global_assignment -name<br />
RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION <br />
Example<br />
set_global_assignment -name<br />
RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "USE AS REGULAR IO"<br />
Default Value<br />
Use as regular IO<br />
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RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION<br />
RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION<br />
Type<br />
Specifies how the Data[7..5] pins should be used when the device is operating in user<br />
mode after configuration is complete. Depending on the current device and<br />
configuration scheme, these pins can be reserved as regular I/O pins, as inputs that<br />
are tri-stated, as outputs that drive ground, as outputs that drive an unspecified<br />
signal. If the Data[7..5] pins are reserved as a regular I/O pins, the Data[7..5] pins can<br />
be used as ordinary I/O pins after configuration.<br />
Enumeration<br />
Device Support<br />
■ As input tri-stated<br />
■ As output driving an unspecified signal<br />
■ As output driving ground<br />
■ Use as regular IO<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
Syntax<br />
set_global_assignment -name<br />
RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION <br />
Example<br />
set_global_assignment -name<br />
RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "USE AS REGULAR IO"<br />
Default Value<br />
Use as regular IO<br />
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RESERVE_DCLK_AFTER_CONFIGURATION<br />
RESERVE_DCLK_AFTER_CONFIGURATION<br />
Type<br />
Specifies how the DCLK pin should be used when the device is operating in user<br />
mode after configuration is complete. Depending on the current device and<br />
configuration scheme, the DCLK pin can be reserved as a regular I/O pin, as a<br />
dedicated programming pin, or compiler configured. If this pin is reserved as a<br />
regular I/O pin, the DCLK pin can be used as an ordinary output pin after<br />
configuration. If the DCLK pin is only used to interface with external memory for<br />
configuration, the DCLK pin should be reserved as compiler configured.<br />
Enumeration<br />
Device Support<br />
■ Compiler configured<br />
■ Use as programming pin<br />
■ Use as regular IO<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
Syntax<br />
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION <br />
Example<br />
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS<br />
REGULAR IO"<br />
Default Value<br />
Use as programming pin<br />
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RESERVE_FLASH_NCE_AFTER_CONFIGURATION<br />
RESERVE_FLASH_NCE_AFTER_CONFIGURATION<br />
Type<br />
Specifies how the FLASH_nCE/nCSO pin should be used when the device is<br />
operating in user mode after configuration is complete. Depending on the current<br />
device and configuration scheme, this pin can be reserved as a regular I/O pin, as an<br />
input that is tri-stated, as an output that drives ground, as an output that drives an<br />
unspecified signal, or compiler configured. If the FLASH_nCE/nCSO pin is reserved<br />
as a regular I/O pin, the FLASH_nCE/nCSO pin can be used as an ordinary I/O pin<br />
after configuration. If the FLASH_nCE/nCSO pin is only used to interface with<br />
external memory for configuration, the FLASH_nCE/nCSO pin should be reserved as<br />
compiler configured.<br />
Enumeration<br />
Device Support<br />
■ As input tri-stated<br />
■ As output driving an unspecified signal<br />
■ As output driving ground<br />
■ Compiler configured<br />
■ Use as regular IO<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
Syntax<br />
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION <br />
Example<br />
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS<br />
REGULAR IO"<br />
Default Value<br />
As input tri-stated<br />
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RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION<br />
RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION<br />
Type<br />
Specifies how the nWS, nRS, nCS, and CS pins should be used when the device is<br />
operating in user mode after configuration is complete. Depending on the current<br />
device and configuration scheme, these pins can be reserved as regular I/O pins, as<br />
inputs that are tri-stated, as outputs that drive ground, or as outputs that drive an<br />
unspecified signal. If this pin is reserved as a regular I/O pin, the nWS, nRS, nCS, and<br />
CS pins can be used as ordinary I/O pins after configuration.<br />
Enumeration<br />
Device Support<br />
■ As input tri-stated<br />
■ As output driving an unspecified signal<br />
■ As output driving ground<br />
■ Use as regular IO<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ HardCopy <strong>II</strong><br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION<br />
<br />
Default Value<br />
Use as regular IO<br />
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RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION<br />
RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION<br />
Type<br />
Specifies how the Data[15..8], PADD[23..0], NRESET, NAVD, NOE and NWE pins<br />
should be used when the device is operating in user mode after configuration is<br />
complete. Depending on the current device and configuration scheme, these pins can<br />
be reserved as regular I/O pins, as inputs that are tri-stated, as outputs that drive<br />
ground, as outputs that drive an unspecified signal, or compiler configured. If these<br />
pins are reserved as regular I/O pins, they can be used as ordinary I/O pins after<br />
configuration. If these pins are only used to interface with external memory for<br />
configuration, these pins should be reserved as compiler configured.<br />
Enumeration<br />
Device Support<br />
■ As input tri-stated<br />
■ As output driving an unspecified signal<br />
■ As output driving ground<br />
■ Compiler configured<br />
■ Use as regular IO<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone IV E<br />
Syntax<br />
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION<br />
<br />
Example<br />
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "USE<br />
AS REGULAR IO"<br />
Default Value<br />
Use as regular IO<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
RESERVE_OTHER_APF_PINS_AFTER_CONFIGURATION<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
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Chapter 6: Fitter Assignments 6–299<br />
RESERVE_RDYNBUSY_AFTER_CONFIGURATION<br />
RESERVE_RDYNBUSY_AFTER_CONFIGURATION<br />
Type<br />
Specifies how the RDYnBUSY pin should be used when the device is operating in user<br />
mode after configuration is complete. Depending on the current device and<br />
configuration scheme, the RDYnBUSY pin can be reserved as a regular I/O pin, as an<br />
input that is tri-stated, as an output that drives ground, or as an output that drives an<br />
unspecified signal. If this pin is reserved as a regular I/O pin, the RDYnBUSY pin can<br />
be used as an ordinary I/O pin after configuration.<br />
Enumeration<br />
Device Support<br />
■ As input tri-stated<br />
■ As output driving an unspecified signal<br />
■ As output driving ground<br />
■ Use as regular IO<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ HardCopy <strong>II</strong><br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION <br />
Default Value<br />
Use as regular IO<br />
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ROUTER_CLOCKING_TOPOLOGY_ANALYSIS<br />
ROUTER_CLOCKING_TOPOLOGY_ANALYSIS<br />
Type<br />
Directs the router to perform an analysis of the design's clocking topology and adjust<br />
the optimization approach on paths with significant clock skew. Enabling this option<br />
may improve hold timing at the cost of increased compile time.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
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Chapter 6: Fitter Assignments 6–301<br />
ROUTER_EFFORT_MULTIPLIER<br />
ROUTER_EFFORT_MULTIPLIER<br />
Type<br />
Controls how quickly the router tries to find a valid solution. The default value is 1.0<br />
and legal values must be greater than or equal to 0.25. Values higher than 1.0 may<br />
improve routing quality at the expense of run-time on difficult-to-route circuits.<br />
Values lower than 1.0 can reduce router run-time, but usually reduces routing quality<br />
slightly.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ EPC1<br />
■ EPC2<br />
■ Enhanced Configuration Devices<br />
■ FLEX10KB<br />
■ FLEX8000<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX9000<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–302 Chapter 6: Fitter Assignments<br />
ROUTER_EFFORT_MULTIPLIER<br />
■ Stratix V<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER <br />
Default Value<br />
1.0<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
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ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION<br />
ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION<br />
Type<br />
Allows the Fitter to automatically insert buffer logic cells between two nodes without<br />
altering the functionality of the design. Buffer logic cells are created from unused logic<br />
cells in the device. This option also allows the Fitter to duplicate a logic cell within a<br />
LAB when there are unused logic cells available in a LAB. Using this option can<br />
increase compilation time. The default setting of Auto allows these operations to run<br />
when the design requires them to fit the design, or the performance of the design can<br />
be improved by this optimization with a nominal compilation time increase.<br />
Enumeration<br />
■ Auto<br />
■ Off<br />
■ On<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–304 Chapter 6: Fitter Assignments<br />
ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION<br />
<br />
Default Value<br />
Auto<br />
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ROUTER_REGISTER_DUPLICATION<br />
ROUTER_REGISTER_DUPLICATION<br />
Type<br />
Allows the Fitter to automatically duplicate registers within a LAB containing empty<br />
logic cells. This option does not alter the functionality of the design. The Auto<br />
Register Duplication option is also ignored if you select OFF as the setting for the<br />
Logic Cell Insertion -- Logic Duplication logic option. Turning on this option can<br />
allow the Logic Cell Insertion -- Logic Duplication logic option to improve a design's<br />
routability, but can make formal verification of a design more difficult.<br />
Enumeration<br />
■ Auto<br />
■ Off<br />
■ On<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–306 Chapter 6: Fitter Assignments<br />
ROUTER_REGISTER_DUPLICATION<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name ROUTER_REGISTER_DUPLICATION <br />
Default Value<br />
Auto<br />
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ROUTER_TIMING_OPTIMIZATION_LEVEL<br />
ROUTER_TIMING_OPTIMIZATION_LEVEL<br />
Type<br />
Controls how aggressively the router tries to meet timing requirements. Setting this<br />
option to Maximum can increase design speed slightly, at the cost of increased<br />
compile time. Setting this option to Minimum can reduce compile time, at the cost of<br />
slightly reduced design speed. The default value is Normal.<br />
Enumeration<br />
■ Maximum<br />
■ Minimum<br />
■ Normal<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ EPC1<br />
■ EPC2<br />
■ Enhanced Configuration Devices<br />
■ FLEX10KB<br />
■ FLEX8000<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX9000<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–308 Chapter 6: Fitter Assignments<br />
ROUTER_TIMING_OPTIMIZATION_LEVEL<br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL <br />
Default Value<br />
Normal<br />
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ROUTING_BACK_ANNOTATION_MODE<br />
ROUTING_BACK_ANNOTATION_MODE<br />
Type<br />
If this option is turned on, that is, Normal, it allows the router to read routing<br />
constraints for the design from a Routing Constraints <strong>File</strong> (.rcf).<br />
Enumeration<br />
■ Advanced<br />
■ Normal<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–310 Chapter 6: Fitter Assignments<br />
SCE_PIN<br />
SCE_PIN<br />
Type<br />
Specifies the SCE configuration pin.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_instance_assignment -name SCE_PIN -to <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–311<br />
SDO_PIN<br />
SDO_PIN<br />
Type<br />
Specifies the SDO configuration pin.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_instance_assignment -name SDO_PIN -to <br />
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SEED<br />
SEED<br />
Type<br />
Specifies the starting value the Fitter uses when randomly determining the initial<br />
placement for the current design. The value can be any non-negative integer value.<br />
Changing the starting value may or may not produce better fitting. Specify a starting<br />
value only if the Fitter is not meeting timing requirements by a small amount. The<br />
Design Space Explorer tool lets you sweep many seed values easily to find the best<br />
value for a given project. Modifying the design or the <strong>Quartus</strong> <strong>II</strong> software settings<br />
even slightly usually changes which seed is best for the design.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name SEED <br />
Default Value<br />
1<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
INITIAL_PLACEMENT_CONFIGURATION<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
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Chapter 6: Fitter Assignments 6–313<br />
SLEW_RATE<br />
SLEW_RATE<br />
Type<br />
Implements control of low-to-high/high-to-low transitions on output pins to help<br />
reduce switching noise. When a large number of output pins switch simultaneously,<br />
pins that use the lower Slew Rate option help reduce switching noise. This option is<br />
ignored if it is applied to anything other than an output or bidirectional pin, or a toplevel<br />
design entity containing output or bidirectional pins. Note that using this option<br />
may increase the delay for output or bidir pins, which can affect slack on t CO paths for<br />
the pins this is applied to.<br />
This option specifies a slew rate setting for the single-ended output buffer of a pin.<br />
Since an input-only pin does not use single-ended output buffer, this option is ignored<br />
on such pin. This option is not supported on a pin with I/O standard which uses true<br />
differential output buffer such as LVDS. Some differential I/O standards are<br />
implemented with two single-ended output buffers and therefore this option may be<br />
supported. Please refer to the family data sheet for which I/O standards support<br />
programmable slew rate. This option can only be supported on pin locations that<br />
support programmable slew rate. Dedicated programming pins, such as TDO, do not<br />
support programmable slew rate. Please refer to the family data sheet for which<br />
current strength and output termination settings support programmable slew rate.<br />
Output termination with Calibration usually requires highest slew rate setting. 0 is<br />
the slowest slew rate value. The higher the value the faster the slew rate. The highest<br />
slew rate value is family dependent. A pin using this option should also use<br />
IO_STANDARD option.<br />
Integer<br />
Device Support<br />
The value must be between these two numbers, inclusive: 0, 3<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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6–314 Chapter 6: Fitter Assignments<br />
SLEW_RATE<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name SLEW_RATE -entity <br />
set_instance_assignment -name SLEW_RATE -to -entity <br />
<br />
set_global_assignment -name SLEW_RATE <br />
Example<br />
set_instance_assignment -name SLEW_RATE 0 -to pin<br />
See Also<br />
■ “IO_STANDARD” on page 6–186<br />
■ “CURRENT_STRENGTH_NEW” on page 6–43<br />
■ “OUTPUT_TERMINATION” on page 6–231<br />
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SLOW_SLEW_RATE<br />
SLOW_SLEW_RATE<br />
Type<br />
Implements slow low-to-high or high-to-low transitions on output pins to help reduce<br />
switching noise. When a large number of output pins switch simultaneously, pins that<br />
use the Slow Slew Rate option help reduce switching noise. This option is ignored if<br />
it is applied to anything other than an output or bidirectional pin, or a top-level<br />
design entity containing output or bidirectional pins. Note that using this option<br />
increases the delay for output or bidir pins, which can affect slack on t CO paths for the<br />
pins to which you apply this option.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ EPC1<br />
■ EPC2<br />
■ Enhanced Configuration Devices<br />
■ FLEX10KB<br />
■ FLEX8000<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
■ MAX9000<br />
■ Stratix<br />
■ Stratix GX<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name SLOW_SLEW_RATE -entity <br />
set_instance_assignment -name SLOW_SLEW_RATE -to -entity <br />
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SLOW_SLEW_RATE<br />
set_global_assignment -name SLOW_SLEW_RATE <br />
Default Value<br />
Off<br />
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Chapter 6: Fitter Assignments 6–317<br />
STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET<br />
STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET<br />
Type<br />
Allows the Compiler to enable netlist placements and routing where the dedicated<br />
reference clock pad in a quad, that has a gigabit transceiver block Transmitter PLL<br />
with its pll_reset or pllenable signal connected or has only Receivers which have<br />
their rxanalogreset signals connected, to feed other quads or core logic. Also allows<br />
the Compiler to enable netlist placements where a gigabit transceiver block<br />
Transmitter PLL exists in a quad that has only receivers which have their<br />
rxanalogreset signals connected.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET<br />
<br />
Default Value<br />
Off<br />
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STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE<br />
STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE<br />
Type<br />
Enables the double data width (channel widths of 16 and 20) GIGE mode operation of<br />
gigabit transceiver block Receiver and Transmitter channels.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE<br />
<br />
Default Value<br />
Off<br />
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STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE<br />
STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE<br />
Type<br />
Enables GIGE configurations of gigabit transceiver block Receiver and Transmitter<br />
channels to operate at other data rates than 1.25 Gbps.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE<br />
<br />
Default Value<br />
Off<br />
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STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B<br />
STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B<br />
Type<br />
Enables GIGE configurations of gigabit transceiver block Receiver and Transmitter<br />
channels where the 8B10B decoder and encoder are not used<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B <br />
Default Value<br />
Off<br />
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STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER<br />
STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCH<br />
ER<br />
Type<br />
Enables GIGE configurations of gigabit transceiver block Receiver channels with the<br />
coreclk selected at the rate matching FIFO.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name<br />
STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER <br />
Default Value<br />
Off<br />
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STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE<br />
STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOU<br />
RCE<br />
Type<br />
Allows GIGE configurations of gigabit transceiver block Receiver channels where the<br />
coreclk input is fed from another source than the gigabit transceiver block Transmitter<br />
PLL in the same quad.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name<br />
STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE <br />
Default Value<br />
Off<br />
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STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE<br />
STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_M<br />
ODE<br />
Type<br />
Enables the double data width (channel widths of 16 and 20) parallel loopback mode<br />
operation of gigabit transceiver block Receiver and Transmitter channels.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name<br />
STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE <br />
Default Value<br />
Off<br />
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STRATIXGX_ALLOW_POST8B10B_LOOPBACK<br />
STRATIXGX_ALLOW_POST8B10B_LOOPBACK<br />
Type<br />
Allows Post 8B10B parallel loopback configurations of gigabit transceiver block<br />
Receiver and Transmitter channels.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK <br />
Default Value<br />
Off<br />
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STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK<br />
STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK<br />
Type<br />
Allows reverse parallel loopback configurations of gigabit transceiver block Receiver<br />
and Transmitter channels.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK<br />
<br />
Default Value<br />
Off<br />
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STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_ SOURCE_IN_DOUBLE_DATA_WIDTH_MODE<br />
STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_<br />
SOURCE_IN_DOUBLE_DATA_WIDTH_MODE<br />
Type<br />
Enables the gigabit transceiver block Receiver coreclk input to be sourced from a<br />
different signal than the clkout output from the same gigabit transceiver block<br />
Receiver channel, while in double data width mode (channel widths of 16 or 20).<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name<br />
STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_<br />
MODE <br />
Default Value<br />
Off<br />
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STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS<br />
STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS<br />
Type<br />
Directs the Compiler to allow the use of I/O pins that couple onto the gigabit<br />
transceiver block I/O banks.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS <br />
Default Value<br />
Off<br />
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STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE<br />
STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE<br />
Type<br />
Enables single data width (channel width of 8) XAUI mode operation of gigabit<br />
transceiver block Receiver and Transmitter channels<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE<br />
<br />
Default Value<br />
Off<br />
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STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER<br />
STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCH<br />
ER<br />
Type<br />
Enables XAUI configurations of gigabit transceiver block Receiver channels with the<br />
coreclk selected at the rate matching FIFO.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name<br />
STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER <br />
Default Value<br />
Off<br />
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STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE<br />
STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOU<br />
RCE<br />
Type<br />
Allows XAUI configurations of gigabit transceiver block Receiver channels where the<br />
coreclk input is fed from another source than the gigabit transceiver block<br />
Transmitter PLL in the same quad.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name<br />
STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE <br />
Default Value<br />
Off<br />
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STRATIXGX_TERMINATION_VALUE<br />
STRATIXGX_TERMINATION_VALUE<br />
Type<br />
Allows the Compiler to configure the on-chip termination (OCT) for a Stratix GX<br />
gigabit transceiver block receiver channel input pin, gigabit transceiver block<br />
transmitter channel output pin, gigabit transceiver block transmitter PLL clock input<br />
pin, or gigabit transceiver block receiver channel clock input pin.<br />
Enumeration<br />
■ OCT 100 Ohms<br />
■ OCT 120 Ohms<br />
■ OCT 150 Ohms<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name STRATIXGX_TERMINATION_VALUE -to -entity<br />
<br />
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STRATIX<strong>II</strong>GX_TERMINATION_VALUE<br />
STRATIX<strong>II</strong>GX_TERMINATION_VALUE<br />
Type<br />
Allows the Compiler to configure the on-chip termination (OCT) for a Stratix <strong>II</strong> GX<br />
gigabit transceiver block receiver channel input pin or gigabit transceiver block<br />
transmitter channel output pin.<br />
Enumeration<br />
■ OCT 100 Ohms<br />
■ OCT 120 Ohms<br />
■ OCT 150 Ohms<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name STRATIX<strong>II</strong>GX_TERMINATION_VALUE -to -<br />
entity <br />
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STRATIX<strong>II</strong>I_CONFIGURATION_SCHEME<br />
STRATIX<strong>II</strong>I_CONFIGURATION_SCHEME<br />
Type<br />
The method used to load data into the device. Three configuration schemes are<br />
available: Passive Serial (PS); Fast Passive Parallel (FPP) and Active Serial (AS).<br />
Enumeration<br />
■ Active Serial<br />
Device Support<br />
■ Fast Passive Parallel<br />
■ Passive Serial<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Syntax<br />
set_global_assignment -name STRATIX<strong>II</strong>I_CONFIGURATION_SCHEME <br />
Example<br />
set_global_assignment -name STRATIX<strong>II</strong>I_CONFIGURATION_SCHEME "Active<br />
Serial"<br />
Default Value<br />
Passive Serial<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
STRATIXIV_CONFIGURATION_SCHEME<br />
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STRATIX<strong>II</strong>I_MRAM_COMPATIBILITY<br />
STRATIX<strong>II</strong>I_MRAM_COMPATIBILITY<br />
Type<br />
Directs the <strong>Quartus</strong> <strong>II</strong> software to produce programming files that are compatible<br />
with all silicon revisions. Refer to the Stratix <strong>II</strong>I Device Handbook for more details.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix <strong>II</strong>I<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name STRATIX<strong>II</strong>I_MRAM_COMPATIBILITY <br />
Default Value<br />
On<br />
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STRATIX<strong>II</strong>I_UPDATE_MODE<br />
STRATIX<strong>II</strong>I_UPDATE_MODE<br />
Type<br />
Specifies the configuration mode used with the configuration scheme for configuring<br />
the device.<br />
Enumeration<br />
■ Remote<br />
■ Standard<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name STRATIX<strong>II</strong>I_UPDATE_MODE <br />
Example<br />
set_global_assignment -name STRATIX<strong>II</strong>I_UPDATE_MODE REMOTE<br />
Default Value<br />
Standard<br />
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STRATIX<strong>II</strong>_CONFIGURATION_SCHEME<br />
STRATIX<strong>II</strong>_CONFIGURATION_SCHEME<br />
Type<br />
The method used to load data into the device. Four configuration schemes are<br />
available: Passive Parallel Asynchronous (PPA); Passive Serial (PS); Fast Passive<br />
Parallel (FPP) and Active Serial (AS).<br />
Enumeration<br />
■ Active Serial<br />
Device Support<br />
■ Fast Passive Parallel<br />
■ Passive Parallel Asynchronous<br />
■ Passive Serial<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ HardCopy <strong>II</strong><br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_global_assignment -name STRATIX<strong>II</strong>_CONFIGURATION_SCHEME <br />
Default Value<br />
Passive Serial<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
STRATIX_<strong>II</strong>_CONFIGURATION_SCHEME<br />
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STRATIX<strong>II</strong>_TERMINATION<br />
STRATIX<strong>II</strong>_TERMINATION<br />
Type<br />
Allows the Compiler to configure the on-chip termination (OCT) and impedance<br />
matching for an I/O pin. OCT helps to prevent signal reflections and maintain signal<br />
integrity. This option is ignored if it is applied to anything other than an I/O pin.<br />
Enumeration<br />
■ Differential<br />
■ Off<br />
Device Support<br />
■ Parallel 50 Ohms with Calibration<br />
■ Series 25 Ohms with Calibration<br />
■ Series 25 Ohms without Calibration<br />
■ Series 50 Ohms with Calibration<br />
■ Series 50 Ohms without Calibration<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ HardCopy <strong>II</strong><br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name STRATIX<strong>II</strong>_TERMINATION -to -entity<br />
<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
Termination -- Stratix <strong>II</strong>/Stratix <strong>II</strong> GX/HardCopy <strong>II</strong><br />
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STRATIXV_CONFIGURATION_SCHEME<br />
STRATIXV_CONFIGURATION_SCHEME<br />
Type<br />
The method used to configure a device with a design. Up to six configuration schemes<br />
are available, depending on the selected device: Passive Serial (PS), Passive Parallel x8<br />
(PPx8), Passive Parallel ×16 (PP×16), Passive Parallel ×32 (PP×32), Active Serial ×1<br />
(AS×1) and Active Serial ×4 (AS×4).<br />
Enumeration<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME <br />
Example<br />
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Active Serial"<br />
Default Value<br />
Passive Serial<br />
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STRATIX_CONFIGURATION_SCHEME<br />
STRATIX_CONFIGURATION_SCHEME<br />
Type<br />
The method used to load data into the device. Three configuration schemes are<br />
available: Passive Parallel Asynchronous (PPA); Passive Serial (PS); and Fast Passive<br />
Parallel (FPP).<br />
Enumeration<br />
Device Support<br />
■ Fast Passive Parallel<br />
■ Passive Parallel Asynchronous<br />
■ Passive Serial<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME <br />
Default Value<br />
Passive Serial<br />
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STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS<br />
STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS<br />
Type<br />
Decreases the propagation delay from an input or bidirectional pin to logic and<br />
embedded cells within the device. This is an advanced option that should be used<br />
only after you have compiled a project, checked the I/O timing, and determined that<br />
the timing is unsatisfactory. For detailed information on how to use this option, refer<br />
to the data sheet for the device family. This option is ignored if it is applied to<br />
anything other than an input or bidirectional pin.<br />
Enumeration<br />
■ Large<br />
■ Medium<br />
■ Off<br />
■ On<br />
■ Small<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ Stratix<br />
■ Stratix GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name<br />
STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS -to -entity <br />
set_instance_assignment -name<br />
STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS -from -to -<br />
entity <br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
Decrease Input Delay to Internal Cells -- Stratix/Stratix GX/Cyclone<br />
YEAGER_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS<br />
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STRATIX_DEVICE_IO_STANDARD<br />
STRATIX_DEVICE_IO_STANDARD<br />
Type<br />
Specifies the default I/O standard to be used for pins on the target device. This option<br />
is ignored on a pin with IO_STANDARD assignment. This option is also ignored if<br />
the netlist disagrees with the option. You should specify the IO_STANARD<br />
assignment for all pins in the design.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
The value of this assignment is case sensitive.<br />
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STRATIX_DEVICE_IO_STANDARD<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD <br />
Example<br />
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "1.2 V"<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
YEAGER_DEVICE_IO_STANDARD<br />
See Also<br />
■ “IO_STANDARD” on page 6–186<br />
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STRATIX_UPDATE_MODE<br />
STRATIX_UPDATE_MODE<br />
Type<br />
Specifies the configuration mode used with the configuration scheme for configuring<br />
the device.<br />
Enumeration<br />
■ Local<br />
■ Remote<br />
■ Standard<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ HardCopy <strong>II</strong><br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_global_assignment -name STRATIX_UPDATE_MODE <br />
Default Value<br />
Standard<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
YEAGER_UPDATE_MODE<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–344 Chapter 6: Fitter Assignments<br />
SYNCHRONIZER_IDENTIFICATION<br />
SYNCHRONIZER_IDENTIFICATION<br />
Type<br />
Specifies how the TimeQuest timing analyzer identifies registers as being part of a<br />
synchronization register chain for metastability analysis. A synchronization register<br />
chain is a sequence of registers with the same clock with no fan-out in between, which<br />
is driven by a pin or logic from another clock domain. If you set this option to Off, the<br />
TimeQuest analyzer does not identify the specified registers, or the registers in the<br />
specified entity, as synchronization registers. If you set the option to Auto, the<br />
TimeQuest analyzer identifies valid synchronization registers that are part of a chain<br />
with more than one register that contains no combinational logic. If you set this option<br />
to Forced if Asynchronous, the TimeQuest analyzer identifies synchronization<br />
register chains if the software detects an asynchronous signal transfer, even if there is<br />
combinational logic or only one register in the chain. If you set this option to Forced,<br />
then the specified register, or all registers within the specified entity, are identified as<br />
synchronizers. You should not apply the Forced option to the entire design, because<br />
doing so identifies all registers in the design as synchronizers. Registers that are<br />
identified as synchronizers are optimized for improved Mean Time Between Failure<br />
(MTBF) as long as the Optimize Design for the Metastability option is turned on. If a<br />
synchronization register chain is identified with the Forced or Forced if<br />
Asynchronous option, then the TimeQuest analyzer reports the metastability MTBF<br />
for the chain. MTBF is not reported for automatically-detected register chains; you can<br />
use the Auto setting to generate a report of possible synchronization chains in your<br />
design. If a synchronization register chain is identified with the Forced or Forced if<br />
Asynchronous option, then the TimeQuest analyzer reports the metastability MTBF<br />
for the chain when it meets the design timing requirements.<br />
Enumeration<br />
■ Auto<br />
■ Forced<br />
■ Forced If Asynchronous<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–345<br />
SYNCHRONIZER_IDENTIFICATION<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION <br />
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION -entity <br />
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION -to -entity<br />
<br />
Default Value<br />
Off<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
ANALYZE_METASTABILITY<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–346 Chapter 6: Fitter Assignments<br />
SYNCHRONIZER_TOGGLE_RATE<br />
SYNCHRONIZER_TOGGLE_RATE<br />
Type<br />
Specifies the toggle rate of this register. The units for this value are in transitions per<br />
second, and must be positive. This is used when calculating the Mean Time Between<br />
Failures (MTBF) of a synchronizer chain in the Metastability Report. This only applies<br />
when the TimeQuest analyzer is used. You can specify the desired frequency setting<br />
on the first register of a synchronizer chain, and this will determine the data rate used<br />
in the MTBF estimation. There are two other assignments associated with toggle<br />
rates. The I/O Maximum Toggle Rate is only used for pins, and specifies the worstcase<br />
toggle rates used for signal integrity purposes. The Power Toggle Rate<br />
assignment is used to specify the expected time-averaged toggle rate, and is used by<br />
the Power Analyzer to estimate time-averaged power consumption.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name SYNCHRONIZER_TOGGLE_RATE -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–347<br />
T11_0_DELAY<br />
T11_0_DELAY<br />
Type<br />
Specifies the propagation delay for the gated T11 delay cell. Use this advanced option<br />
only after you have compiled a project, checked the I/O timing, and determined that<br />
the timing is unsatisfactory. For more information about using this advanced option,<br />
refer to the data sheet for the targeted device family. The software ignores this option<br />
if you apply the option to other pins other than an input or bidirectional pin.<br />
Integer<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name T11_0_DELAY -to -entity <br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–348 Chapter 6: Fitter Assignments<br />
T11_1_DELAY<br />
T11_1_DELAY<br />
Type<br />
Specifies the propagation delay for the ungated T11 delay cell. Use this advanced<br />
option only after you have compiled a project, checked the I/O timing, and<br />
determined that the timing is unsatisfactory. For more information about using this<br />
option, refer to the data sheet for the device family. The software ignores this option if<br />
you apply this option to any pins other than an input or bidirectional pin.<br />
Integer<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name T11_1_DELAY -to -entity <br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–349<br />
T11_DELAY<br />
T11_DELAY<br />
Type<br />
Specifies the propagation delay for T11 Delay Cell. This is an advanced option that<br />
should be used only after you have compiled a project, checked the I/O timing, and<br />
determined that the timing is unsatisfactory. For detailed information on how to use<br />
this option, refer to the data sheet for the device family. This option is ignored if it is<br />
applied to anything other than an input or bidirectional pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GZ<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name T11_DELAY -to -entity <br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–350 Chapter 6: Fitter Assignments<br />
T11_FINE_DELAY<br />
T11_FINE_DELAY<br />
Type<br />
Enable the fine delay resolution on T11 Delay (DQS post-amble delay cell).<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name T11_FINE_DELAY -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–351<br />
T4_DELAY<br />
T4_DELAY<br />
Type<br />
Specifies the propagation delay for T4 Delay Cell (output register to switch mux). This<br />
is an advanced option that should be used only after you have compiled a project,<br />
checked the I/O timing, and determined that the timing is unsatisfactory. For detailed<br />
information on how to use this option, refer to the data sheet for the device family.<br />
This option is ignored if it is applied to anything other than an input or bidirectional<br />
pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GZ<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name T4_DELAY -to -entity <br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–352 Chapter 6: Fitter Assignments<br />
T8_DELAY0<br />
T8_DELAY0<br />
Type<br />
Specifies the propagation delay for T8 Delay Cell. This is an advanced option that<br />
should be used only after you have compiled a project, checked the I/O timing, and<br />
determined that the timing is unsatisfactory. For detailed information on how to use<br />
this option, refer to the data sheet for the device family. This option is ignored if it is<br />
applied to anything other than an input or bidirectional pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GZ<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name T8_DELAY0 -to -entity <br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–353<br />
T8_DELAY1<br />
T8_DELAY1<br />
Type<br />
Specifies the propagation delay for T8 Delay Cell. This is an advanced option that<br />
should be used only after you have compiled a project, checked the I/O timing, and<br />
determined that the timing is unsatisfactory. For detailed information on how to use<br />
this option, refer to the data sheet for the device family. This option is ignored if it is<br />
applied to anything other than an input or bidirectional pin.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GZ<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name T8_DELAY1 -to -entity <br />
<br />
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<strong>Reference</strong> <strong>Manual</strong>
6–354 Chapter 6: Fitter Assignments<br />
TERMINATION<br />
TERMINATION<br />
Type<br />
Allows the Compiler to configure the on-chip termination (OCT) and impedance<br />
matching for an I/O pin. OCT helps to prevent signal reflections and maintain signal<br />
integrity. This option is ignored if it is applied to anything other than an I/O pin.<br />
Enumeration<br />
■ Differential<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix<br />
■ Stratix GX<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name TERMINATION -to -entity <br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
Termination -- Stratix / Stratix GX / HardCopy Stratix / Mercury<br />
YEAGER_OCT_AND_IMPEDANCE_MATCHING<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–355<br />
TERMINATION_CONTROL_BLOCK<br />
TERMINATION_CONTROL_BLOCK<br />
Type<br />
Specifies the control block used for calibrated on-chip termination (OCT) and<br />
impedance matching for an I/O pin. OCT helps to prevent signal reflections and<br />
maintain signal integrity. This option is ignored if it is applied to anything other than<br />
an I/O pad, input buffer, or output buffer. This option should only be used on I/O<br />
pins which have a calibrated termination assignment.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is copied to any duplicated nodes<br />
This assignment supports wildcards.<br />
The value of this assignment must be a node name.<br />
Syntax<br />
set_instance_assignment -name TERMINATION_CONTROL_BLOCK -to -entity<br />
<br />
Example<br />
set_instance_assignment -name TERMINATION_CONTROL_BLOCK<br />
"my_oct:inst|my_oct_alt_oct_toq:my_oct_alt_oct_toq_component|sd1a_0" -to<br />
pin_name<br />
See Also<br />
■ “IO_STANDARD” on page 6–186<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–356 Chapter 6: Fitter Assignments<br />
TREAT_BIDIR_AS_OUTPUT<br />
TREAT_BIDIR_AS_OUTPUT<br />
Type<br />
Directs the bidirectional pin to be essentially treated as an output pin meaning that<br />
the input path is used for feedback from the output path. This option is a modifier of<br />
IO_STANDARD option with Differential HSTL/SSTL I/O standard setting. The<br />
<strong>Quartus</strong> <strong>II</strong> software implements a legality check that requires differental HSTL/SSTL<br />
bi-directional pin connecting to a differential input buffer. This option disables this<br />
legality check if the output enable of the two single-ended output buffers of the pins<br />
are set to V CC.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT <br />
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT -entity <br />
<br />
set_instance_assignment -name TREAT_BIDIR_AS_OUTPUT -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–357<br />
TREAT_BIDIR_AS_OUTPUT<br />
Example<br />
set_instance_assignment -name TREAT_BIDIR_AS_OUTPUT ON -to bidir_pin<br />
Default Value<br />
Off<br />
See Also<br />
■ “IO_STANDARD” on page 6–186<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–358 Chapter 6: Fitter Assignments<br />
TRI_STATE_SPI_PINS<br />
TRI_STATE_SPI_PINS<br />
Type<br />
This option controls Active Configuration Controller to tri-state the Active<br />
Configuration pins in user mode. This option is ignored if the selected configuration<br />
scheme is not an Active Configuration scheme.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name TRI_STATE_SPI_PINS <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–359<br />
TXPMA_SLEW_RATE<br />
TXPMA_SLEW_RATE<br />
Type<br />
Overwrites TX PMA slew rate to 4 options: Off, Low, Medium, High.<br />
Enumeration<br />
■ High<br />
■ Low<br />
■ Medium<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GZ<br />
■ Stratix IV<br />
Syntax<br />
set_global_assignment -name TXPMA_SLEW_RATE <br />
set_instance_assignment -name TXPMA_SLEW_RATE -to <br />
Default Value<br />
Low<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–360 Chapter 6: Fitter Assignments<br />
UNUSED_TSD_PINS_GND<br />
UNUSED_TSD_PINS_GND<br />
Type<br />
If this option is turned on, unused temperature sensing diode (TSD) pins,<br />
TEMPDIODEp/TEMPDIODEn, on the device are automatically set to GND in the<br />
Pin-Out <strong>File</strong> (.pin) file. By default, the TSD pins are available for connection to an<br />
external temperature sensing device; however, you must manually connect the pins to<br />
GND if they are not connected. Turning on this option only updates the information<br />
in the .pin file, it does not affect FPGA behavior.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix IV<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name UNUSED_TSD_PINS_GND <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–361<br />
USER_START_UP_CLOCK<br />
USER_START_UP_CLOCK<br />
Type<br />
Directs the device to use a user-supplied clock on the CLKUSR pin for initialization. You<br />
can select which clock source to use for initialization, either the internal oscillator or<br />
external clocks provided on the CLKUSR pin. This clock can synchronize the<br />
initialization of multiple devices. The default setting is to make CLKUSR pin available<br />
as a user I/O pin.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name USER_START_UP_CLOCK <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–362 Chapter 6: Fitter Assignments<br />
USER_START_UP_CLOCK<br />
Example<br />
set_global_assignment -name USER_START_UP_CLOCK ON<br />
set_global_assignment -name USER_START_UP_CLOCK OFF<br />
Default Value<br />
Off<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
User Specified Start-up clock<br />
See Also<br />
■ “ACTIVE_SERIAL_CLOCK” on page 6–1<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–363<br />
VCCIO_CURRENT_1PT8V<br />
VCCIO_CURRENT_1PT8V<br />
Type<br />
Overrides VCCIO current of 1.8-V I/O standard. The original current is 2 mA.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name VCCIO_CURRENT_1PT8V <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–364 Chapter 6: Fitter Assignments<br />
VCCIO_CURRENT_2PT5V<br />
VCCIO_CURRENT_2PT5V<br />
Type<br />
Overrides VCCIO current of 2.5-V I/O standard. The original current is 2 mA.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name VCCIO_CURRENT_2PT5V <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–365<br />
VCCIO_CURRENT_GTL<br />
VCCIO_CURRENT_GTL<br />
Type<br />
Overrides VCCIO current of GTL I/O standard. Not supported in MAX7000.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name VCCIO_CURRENT_GTL <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–366 Chapter 6: Fitter Assignments<br />
VCCIO_CURRENT_GTL_PLUS<br />
VCCIO_CURRENT_GTL_PLUS<br />
Type<br />
Overrides VCCIO current of GTL+ I/O standard. The original current is 0 mA.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name VCCIO_CURRENT_GTL_PLUS <br />
Fitter Assignments<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–367<br />
VCCIO_CURRENT_LVCMOS<br />
VCCIO_CURRENT_LVCMOS<br />
Type<br />
Overrides VCCIO current of LVCMOS I/O standard. The original current is 2 mA.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name VCCIO_CURRENT_LVCMOS <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–368 Chapter 6: Fitter Assignments<br />
VCCIO_CURRENT_LVTTL<br />
VCCIO_CURRENT_LVTTL<br />
Type<br />
Overrides VCCIO current of LVTTL I/O standard. The original current is 4 mA.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name VCCIO_CURRENT_LVTTL <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–369<br />
VCCIO_CURRENT_PCI<br />
VCCIO_CURRENT_PCI<br />
Type<br />
Overrides VCCIO current of PCI I/O standard. The original current is 4 mA.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name VCCIO_CURRENT_PCI <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–370 Chapter 6: Fitter Assignments<br />
VCCIO_CURRENT_SSTL2_CLASS1<br />
VCCIO_CURRENT_SSTL2_CLASS1<br />
Type<br />
Overrides VCCIO current of SSTL2_CLASS1 I/O standard. The original current is 14<br />
mA.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name VCCIO_CURRENT_SSTL2_CLASS1 <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–371<br />
VCCIO_CURRENT_SSTL2_CLASS2<br />
VCCIO_CURRENT_SSTL2_CLASS2<br />
Type<br />
Overrides VCCIO current of SSTL2_CLASS2 I/O standard. The original current is 21<br />
mA.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name VCCIO_CURRENT_SSTL2_CLASS2 <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–372 Chapter 6: Fitter Assignments<br />
VCCIO_CURRENT_SSTL3_CLASS1<br />
VCCIO_CURRENT_SSTL3_CLASS1<br />
Type<br />
Overrides VCCIO currentof SSTL3_CLASS1 I/O standard. The original current is 18<br />
mA.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name VCCIO_CURRENT_SSTL3_CLASS1 <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–373<br />
VCCIO_CURRENT_SSTL3_CLASS2<br />
VCCIO_CURRENT_SSTL3_CLASS2<br />
Type<br />
Overrides VCCIO current of SSTL3_CLASS2 I/O standard. The original current is 25<br />
mA.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name VCCIO_CURRENT_SSTL3_CLASS2 <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–374 Chapter 6: Fitter Assignments<br />
VCCPD_VOLTAGE<br />
VCCPD_VOLTAGE<br />
Type<br />
Specifies the default I/O Bank VCCPD voltage to be used for pins on the target device.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ HardCopy <strong>II</strong><br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_global_assignment -name VCCPD_VOLTAGE -section_id <br />
<br />
Default Value<br />
3.3 V, requires section identifier<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–375<br />
WEAK_PULL_UP_RESISTOR<br />
WEAK_PULL_UP_RESISTOR<br />
Type<br />
Enables the weak pull-up resistor when the device is operating in user mode. This<br />
option pulls a high-impedance bus signal to VCC. The Weak Pull-Up Resistor option<br />
should not be used at the same time as the Enable Bus-Hold Circuitry option. This<br />
option is ignored if it is applied to anything other than a pin.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–376 Chapter 6: Fitter Assignments<br />
WEAK_PULL_UP_RESISTOR<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name WEAK_PULL_UP_RESISTOR <br />
set_global_assignment -name WEAK_PULL_UP_RESISTOR -entity <br />
<br />
set_instance_assignment -name WEAK_PULL_UP_RESISTOR -to -entity<br />
<br />
Example<br />
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to pin<br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–377<br />
XCVR_ANALOG_SETTINGS_PROTOCOL<br />
XCVR_ANALOG_SETTINGS_PROTOCOL<br />
Type<br />
Specify protocol and its variant that are used to determine electrical analog settings<br />
for the transceiver.<br />
Enumeration<br />
■ BASIC<br />
■ CEI<br />
■ CPRI<br />
■ GIGE<br />
■ INTERLAKEN<br />
■ PCIE_GEN1<br />
■ PCIE_GEN2<br />
■ PCIE_GEN3<br />
■ QPI<br />
■ SATA1_I<br />
■ SATA1_M<br />
■ SATA1_X<br />
■ SATA2_I<br />
■ SATA2_M<br />
■ SATA2_X<br />
■ SFIS<br />
■ SONET<br />
■ SRIO<br />
■ TENG_BASER<br />
■ TENG_SDI<br />
■ XAUI<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–378 Chapter 6: Fitter Assignments<br />
XCVR_ANALOG_SETTINGS_PROTOCOL<br />
Syntax<br />
set_instance_assignment -name XCVR_ANALOG_SETTINGS_PROTOCOL -to -<br />
entity <br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
HSSI_ANALOG_SETTINGS_PROTOCOL<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–379<br />
XCVR_GT_IO_PIN_TERMINATION<br />
XCVR_GT_IO_PIN_TERMINATION<br />
Type<br />
Allows the Compiler to configure the GT transceiver termination value.<br />
Integer<br />
Device Support<br />
The value must be between these two numbers, inclusive: 0, 15<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Note<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_GT_IO_PIN_TERMINATION -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–380 Chapter 6: Fitter Assignments<br />
XCVR_GT_RX_COMMON_MODE_VOLTAGE<br />
XCVR_GT_RX_COMMON_MODE_VOLTAGE<br />
Type<br />
Specifies the GT receiver buffer common-mode voltage.<br />
Enumeration<br />
■ VTT_0P35V<br />
■ VTT_0P50V<br />
■ VTT_0P55V<br />
■ VTT_0P60V<br />
■ VTT_0P65V<br />
■ VTT_0P70V<br />
■ VTT_0P75V<br />
■ VTT_0P80V<br />
Device Support<br />
■ VTT_VCMOFF0<br />
■ VTT_VCMOFF1<br />
■ VTT_VCMOFF2<br />
■ VTT_VCMOFF3<br />
■ VTT_VCMOFF4<br />
■ VTT_VCMOFF5<br />
■ VTT_VCMOFF6<br />
■ VTT_VCMOFF7<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Note<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_GT_RX_COMMON_MODE_VOLTAGE -to -<br />
entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–381<br />
XCVR_GT_RX_CTLE<br />
XCVR_GT_RX_CTLE<br />
Type<br />
Specifies the static control for the continuous time equalizer in the receiver buffer.<br />
Integer<br />
Device Support<br />
The value must be between these two numbers, inclusive: 0, 8<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Note<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_GT_RX_CTLE -to -entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–382 Chapter 6: Fitter Assignments<br />
XCVR_GT_RX_DC_GAIN<br />
XCVR_GT_RX_DC_GAIN<br />
Type<br />
Controls the amount of the receiver buffer DC gain at a stage.<br />
Integer<br />
Device Support<br />
The value must be between these two numbers, inclusive: 0, 19<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Note<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_GT_RX_DC_GAIN -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–383<br />
XCVR_GT_TX_COMMON_MODE_VOLTAGE<br />
XCVR_GT_TX_COMMON_MODE_VOLTAGE<br />
Type<br />
Specifies the GT transmitter common-mode driver voltage.<br />
Enumeration<br />
■ GROUNDED<br />
■ PULL_DN<br />
■ PULL_UP<br />
Device Support<br />
■ PULL_UP_TO_VCCELA<br />
■ TRISTATED1<br />
■ TRISTATED2<br />
■ TRISTATED3<br />
■ TRISTATED4<br />
■ VOLT_0P35V<br />
■ VOLT_0P50V<br />
■ VOLT_0P55V<br />
■ VOLT_0P60V<br />
■ VOLT_0P65V<br />
■ VOLT_0P70V<br />
■ VOLT_0P75V,<br />
■ VOLT_0P80V<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Note<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_GT_TX_COMMON_MODE_VOLTAGE -to -<br />
entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–384 Chapter 6: Fitter Assignments<br />
XCVR_GT_TX_PRE_EMP_1ST_POST_TAP<br />
XCVR_GT_TX_PRE_EMP_1ST_POST_TAP<br />
Type<br />
Specifies the GT transmitter preemphasis first post-tap setting value.<br />
Integer<br />
Device Support<br />
The value must be between these two numbers, inclusive: 0, 31<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Note<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_GT_TX_PRE_EMP_1ST_POST_TAP -to -<br />
entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–385<br />
XCVR_GT_TX_PRE_EMP_INV_PRE_TAP<br />
XCVR_GT_TX_PRE_EMP_INV_PRE_TAP<br />
Type<br />
Inverts the GT transmitter preemphasis pre-tap setting value.<br />
Boolean<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Note<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_GT_TX_PRE_EMP_INV_PRE_TAP -to -<br />
entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–386 Chapter 6: Fitter Assignments<br />
XCVR_GT_TX_PRE_EMP_PRE_TAP<br />
XCVR_GT_TX_PRE_EMP_PRE_TAP<br />
Type<br />
Specifies the GT transmitter preemphasis pre-tap setting value.<br />
Integer<br />
Device Support<br />
The value must be between these two numbers, inclusive: 0, 31<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Note<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_GT_TX_PRE_EMP_PRE_TAP -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–387<br />
XCVR_GT_TX_VOD_MAIN_TAP<br />
XCVR_GT_TX_VOD_MAIN_TAP<br />
Type<br />
Specifies the GT differential output voltage setting.<br />
Integer<br />
Device Support<br />
The value must be between these two numbers, inclusive: 0, 5<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Note<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_GT_TX_VOD_MAIN_TAP -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–388 Chapter 6: Fitter Assignments<br />
XCVR_IO_PIN_TERMINATION<br />
XCVR_IO_PIN_TERMINATION<br />
Type<br />
Allows the Compiler to configure the Transceiver Termination value for a gigabit<br />
transceiver block I/O pin. It specifies the intended Transceiver Termination value for<br />
the specified gigabit transceiver block I/O pin.<br />
Enumeration<br />
■ 100_OHMS<br />
■ 120_OHMS<br />
■ 150_OHMS<br />
■ 85_OHMS<br />
Device Support<br />
■ EXTERNAL_RESISTOR<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_IO_PIN_TERMINATION -to -entity<br />
<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
GXB_IO_PIN_TERMINATION<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–389<br />
XCVR_REFCLK_PIN_TERMINATION<br />
XCVR_REFCLK_PIN_TERMINATION<br />
Type<br />
Allows the Compiler to configure the Termination value for a dedicated refclk pin. It<br />
specifies the intended Termination value for the specified refclk pin.<br />
Enumeration<br />
Device Support<br />
■ AC_COUPLING<br />
■ DC_COUPLING_EXTERNAL_RESISTOR<br />
■ DC_COUPLING_INTERNAL_100_OHMS<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION -to -entity<br />
<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
GXB_REFCLK_PIN_TERMINATION<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–390 Chapter 6: Fitter Assignments<br />
XCVR_RX_ACGAIN_A<br />
XCVR_RX_ACGAIN_A<br />
Type<br />
Sets reference voltage on EQA.<br />
Enumeration<br />
Device Support<br />
■ AREF_VOLT_0<br />
■ AREF_VOLT_0P5<br />
■ AREF_VOLT_0P75<br />
■ AREF_VOLT_1P0<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_RX_ACGAIN_A -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–391<br />
XCVR_RX_ACGAIN_V<br />
XCVR_RX_ACGAIN_V<br />
Type<br />
Sets reference voltage on EQV.<br />
Enumeration<br />
Device Support<br />
■ VREF_VOLT_0<br />
■ VREF_VOLT_0P5<br />
■ VREF_VOLT_0P75<br />
■ VREF_VOLT_1P0<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_RX_ACGAIN_V -to -entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–392 Chapter 6: Fitter Assignments<br />
XCVR_RX_BYPASS_EQ_STAGES_234<br />
XCVR_RX_BYPASS_EQ_STAGES_234<br />
Type<br />
Bypasses continuous time equalizer stages 2, 3, and 4 to save power. This assignment<br />
eliminates significant AC gain on the equalizer and is appropriate for chip-to-chip<br />
short range communication on a PCB.<br />
Enumeration<br />
Device Support<br />
■ ALL_STAGES_ENABLED<br />
■ BYYPASS_STAGES_234<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_RX_BYPASS_EQ_STAGES_234 -to -<br />
entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–393<br />
XCVR_RX_COMMON_MODE_VOLTAGE<br />
XCVR_RX_COMMON_MODE_VOLTAGE<br />
Type<br />
Receiver buffer common-mode voltage.<br />
Enumeration<br />
■ TRISTATE1<br />
■ TRISTATE2<br />
■ TRISTATE3<br />
■ TRISTATE4<br />
■ VTT_0P35V<br />
■ VTT_0P50V<br />
■ VTT_0P55V<br />
■ VTT_0P60V<br />
■ VTT_0P65V<br />
■ VTT_0P70V<br />
■ VTT_0P75V<br />
■ VTT_0P80V<br />
Device Support<br />
■ VTT_PDN_STRONG<br />
■ VTT_PDN_WEAK<br />
■ VTT_PUP_STRONG<br />
■ VTT_PUP_WEAK<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_RX_COMMON_MODE_VOLTAGE -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–394 Chapter 6: Fitter Assignments<br />
XCVR_RX_DC_GAIN<br />
XCVR_RX_DC_GAIN<br />
Type<br />
Controls the amount of a stage receive-buffer DC gain.<br />
Integer<br />
Device Support<br />
The value must be between these two numbers, inclusive: 0, 19<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_RX_DC_GAIN -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–395<br />
XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE<br />
XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE<br />
Type<br />
If enabled, equalizer gain control is driven by the PCS block for PCI Express. If<br />
disabled, equalizer gain control is determined by the<br />
XCVR_RX_LINEAR_EQUALIZER_SETTING assignment.<br />
Boolean<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE -to<br />
-entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–396 Chapter 6: Fitter Assignments<br />
XCVR_RX_EQ_BW_SEL<br />
XCVR_RX_EQ_BW_SEL<br />
Type<br />
Sets the gain peaking frequency for the equalizer. For data rates lesser than 6.5 Gbps,<br />
set to HALF. For data rates greater than 6.5 Gbps, set to FULL.<br />
Enumeration<br />
Device Support<br />
■ BW_FULL_12P5<br />
■ BW_HALF_6P5<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_RX_EQ_BW_SEL -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–397<br />
XCVR_RX_INPUT_VCM_SEL<br />
XCVR_RX_INPUT_VCM_SEL<br />
Type<br />
When set to LOW_VCM, this assignment enables PMOS equalizer on stage 1 of the<br />
input buffer and disables the NMOS stage for QPI and other modes in which the DC<br />
coupled connection common voltage is at approximately 0.25 V.<br />
Enumeration<br />
■ HIGH_VCM<br />
■ LOW_VCM<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_RX_INPUT_VCM_SEL -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–398 Chapter 6: Fitter Assignments<br />
XCVR_RX_LINEAR_EQUALIZER_CONTROL<br />
XCVR_RX_LINEAR_EQUALIZER_CONTROL<br />
Type<br />
Static control for the continuous time equalizer in the receiver buffer. The equalizer<br />
has 16 distinct settings from 0 to 15 corresponding to the increasing AC gain.<br />
Integer<br />
The value must be between these two numbers, inclusive: 1, 16<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_RX_LINEAR_EQUALIZER_CONTROL -to -<br />
entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–399<br />
XCVR_RX_SD_ENABLE<br />
XCVR_RX_SD_ENABLE<br />
Type<br />
Enables or disables the receiver signal detection unit.<br />
Boolean<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_RX_SD_ENABLE -to -entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–400 Chapter 6: Fitter Assignments<br />
XCVR_RX_SD_OFF<br />
XCVR_RX_SD_OFF<br />
Type<br />
Number of parallel cycles to wait before the signal detect block declares loss of signal.<br />
Integer<br />
Device Support<br />
The value must be between these two numbers, inclusive: 0, 29<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_RX_SD_OFF -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–401<br />
XCVR_RX_SD_ON<br />
XCVR_RX_SD_ON<br />
Type<br />
Number of parallel cycles to wait before the signal detect block declares presence of<br />
signal.<br />
Integer<br />
Device Support<br />
The value must be between these two numbers, inclusive: 0, 16<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_RX_SD_ON -to -entity <br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–402 Chapter 6: Fitter Assignments<br />
XCVR_RX_SD_THRESHOLD<br />
XCVR_RX_SD_THRESHOLD<br />
Type<br />
Specifies signal detection voltage threshold level.<br />
Integer<br />
Device Support<br />
The value must be between these two numbers, inclusive: 0, 7<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_RX_SD_THRESHOLD -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–403<br />
XCVR_RX_SEL_HALF_BW<br />
XCVR_RX_SEL_HALF_BW<br />
Type<br />
Enable half bandwidth mode. For BW=3.25GHZ, select FULL_BW. For BW=1.5GHz,<br />
select HALF_BW.<br />
Enumeration<br />
■ FULL_BW<br />
■ HALF_BW<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_RX_SEL_HALF_BW -to -entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–404 Chapter 6: Fitter Assignments<br />
XCVR_TX_COMMON_MODE_VOLTAGE<br />
XCVR_TX_COMMON_MODE_VOLTAGE<br />
Type<br />
Transmitter common-mode driver voltage.<br />
Enumeration<br />
■ GROUNDED<br />
■ PULL_DN<br />
■ PULL_UP<br />
Device Support<br />
■ PULL_UP_TO_VCCELA<br />
■ TRISTATED1<br />
■ TRISTATED2<br />
■ TRISTATED3<br />
■ TRISTATED4<br />
■ VOLT_0P35V<br />
■ VOLT_0P50V<br />
■ VOLT_0P55V<br />
■ VOLT_0P60V<br />
■ VOLT_0P65V<br />
■ VOLT_0P70V<br />
■ VOLT_0P75V<br />
■ VOLT_0P80V<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_TX_COMMON_MODE_VOLTAGE -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–405<br />
XCVR_TX_PLL_RECONFIG_GROUP<br />
XCVR_TX_PLL_RECONFIG_GROUP<br />
Type<br />
Specifies whether gigabit transceiver block transceiver channels with Dynamic TX<br />
PLL Reconfiguration can be placed in the same physical gigabit transceiver block<br />
quad. If the gigabit transceiver block transceivers have 2 dynamically reconfigured TX<br />
PLLs, the gigabit transceiver block transceivers are not placed into the same physical<br />
quad when the Dynamic TX PLL Reconfiguration setting is turned on unless they are<br />
in the same TX PLL reconfiguration group. If the gigabit transceiver block<br />
transceivers have one dynamically reconfigured TX PLL, gigabit transceiver block<br />
transceivers from two TX PLL reconfiguration groups can be placed into the same<br />
physical quad if the logical number of the TX PLLs are different.<br />
Gigabit transceiver block transceivers can be assigned to the same group if the<br />
following conditions are met:<br />
■ Gigabit transceiver block transmitters in the same group can only listen to 2 TX<br />
PLLs at one time<br />
■ You must maintain proper data rates on TX PLLs according to <strong>Altera</strong> user<br />
guidelines<br />
■ You must wait until the pll_locked signal is asserted for dynamic PLL<br />
reconfiguration completion, and the gigabit transceiver block receivers and<br />
transmitters are kept in reset until the dynamic reconfiguration of both is complete<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name GXB_TX_PLL_RECONFIG_GROUP -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–406 Chapter 6: Fitter Assignments<br />
XCVR_TX_PRE_EMP_1ST_POST_TAP<br />
XCVR_TX_PRE_EMP_1ST_POST_TAP<br />
Type<br />
Specifies the transmitter pre-emphasis first post-tap setting value.<br />
Integer<br />
Device Support<br />
The value must be between these two numbers, inclusive: 0, 31<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_TX_PRE_EMP_1ST_POST_TAP -to -<br />
entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–407<br />
XCVR_TX_PRE_EMP_2ND_POST_TAP<br />
XCVR_TX_PRE_EMP_2ND_POST_TAP<br />
Type<br />
Specifies the transmitter pre-emphasis second post-tap setting.<br />
Integer<br />
Device Support<br />
The value must be between 0 and15, inclusive.<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_TX_PRE_EMP_2ND_POST_TAP -to -<br />
entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–408 Chapter 6: Fitter Assignments<br />
XCVR_TX_PRE_EMP_2ND_POST_TAP_USER<br />
XCVR_TX_PRE_EMP_2ND_POST_TAP_USER<br />
Type<br />
Specifies the transmitter preemphasis second post-tap setting value, including<br />
inversion.<br />
Integer<br />
Device Support<br />
The value must be between 0 and31, inclusive.<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_TX_PRE_EMP_2ND_POST_TAP_USER -to -<br />
entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–409<br />
XCVR_TX_PRE_EMP_INV_2ND_TAP<br />
XCVR_TX_PRE_EMP_INV_2ND_TAP<br />
Type<br />
Inverts the transmitter pre-emphasis second post-tap setting value.<br />
Boolean<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_TX_PRE_EMP_INV_2ND_TAP -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–410 Chapter 6: Fitter Assignments<br />
XCVR_TX_PRE_EMP_INV_PRE_TAP<br />
XCVR_TX_PRE_EMP_INV_PRE_TAP<br />
Type<br />
Inverts the transmitter pre-emphasis, pre-tap setting value.<br />
Boolean<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_TX_PRE_EMP_INV_PRE_TAP -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–411<br />
XCVR_TX_PRE_EMP_PRE_TAP<br />
XCVR_TX_PRE_EMP_PRE_TAP<br />
Type<br />
Specifies the transmitter pre-emphasis, pre-tap setting value.<br />
Integer<br />
Device Support<br />
The value must be between these two numbers, inclusive: 0, 15<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_TX_PRE_EMP_PRE_TAP -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–412 Chapter 6: Fitter Assignments<br />
XCVR_TX_PRE_EMP_PRE_TAP_USER<br />
XCVR_TX_PRE_EMP_PRE_TAP_USER<br />
Type<br />
Specifies the transmitter preemphasis pre-tap setting value, including inversion.<br />
Integer<br />
Device Support<br />
The value must be between these two numbers, inclusive: 0, 31<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_TX_PRE_EMP_PRE_TAP_USER -to -<br />
entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–413<br />
XCVR_TX_RX_DET_ENABLE<br />
XCVR_TX_RX_DET_ENABLE<br />
Type<br />
Enables or disables the receiver detector circuit at the transmitter.<br />
Boolean<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_TX_RX_DET_ENABLE -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–414 Chapter 6: Fitter Assignments<br />
XCVR_TX_RX_DET_MODE<br />
XCVR_TX_RX_DET_MODE<br />
Type<br />
Sets the mode for the receiver detect block function.<br />
Integer<br />
Device Support<br />
The value must be between 0 and 15, inclusive.<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_TX_RX_DET_MODE -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–415<br />
XCVR_TX_RX_DET_OUTPUT_SEL<br />
XCVR_TX_RX_DET_OUTPUT_SEL<br />
Type<br />
Determines QPI or PCI Express mode for the Receiver Detect block.<br />
Enumeration<br />
Device Support<br />
■ RX_DET_PCIE_OUT<br />
■ RX_DET_QPI_OUT<br />
You can use this setting in projects targeting the following device families:<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_TX_RX_DET_OUTPUT_SEL -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–416 Chapter 6: Fitter Assignments<br />
XCVR_TX_SLEW_RATE_CTRL<br />
XCVR_TX_SLEW_RATE_CTRL<br />
Type<br />
Specifies the slew rate of the output signal. The valid values span from the slowest<br />
rate to fastest rate.<br />
Integer<br />
Device Support<br />
The value must be between these two numbers, inclusive: 1, 5<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_TX_SLEW_RATE_CTRL -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–417<br />
XCVR_TX_VCM_CTRL_SRC<br />
XCVR_TX_VCM_CTRL_SRC<br />
Type<br />
Controls the VCM driver (pulldown/pullup) dynamically from user signals when<br />
you set this assignment to DYNAMIC_CTL for QPI protocol. The default setting<br />
(RAM_CTL) causes the XCVR_TX_COMMON_MODE_VOLTAGE assignment to<br />
determine the state of the VCM driver.<br />
Enumeration<br />
■ DYNAMIC_CTL<br />
■ RAM_CTL<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_TX_VCM_CTRL_SRC -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–418 Chapter 6: Fitter Assignments<br />
XCVR_TX_VOD<br />
XCVR_TX_VOD<br />
Type<br />
Differential output voltage setting. The values are monotonically increasing with the<br />
driver main tap current strength.<br />
Integer<br />
Device Support<br />
The value must be between these two numbers, inclusive: 0, 63<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_TX_VOD -to -entity <br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–419<br />
XCVR_TX_VOD_PRE_EMP_CTRL_SRC<br />
XCVR_TX_VOD_PRE_EMP_CTRL_SRC<br />
Type<br />
When you set this assignment to DYNAMIC_CTL for PCI Express, the PCS block<br />
controls the VOD and preemphasis coefficients. When you set this assignment to<br />
RAM_CTL, the VOD and preemphasis are controlled by other assignments (for<br />
example, XCVR_TX_PRE_EMP_1ST_POST_TAP).<br />
Enumeration<br />
■ DYNAMIC_CTL<br />
■ RAM_CTL<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_TX_VOD_PRE_EMP_CTRL_SRC -to -<br />
entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–420 Chapter 6: Fitter Assignments<br />
XCVR_VCCA_VOLTAGE<br />
XCVR_VCCA_VOLTAGE<br />
Type<br />
Configures the VCCA_GXB voltage for a GXB I/O pin by specifying the intended<br />
VCCA_GXB voltage for a GXB I/O pin. If you do not set this option, the Compiler<br />
automatically sets the correct VCCA_GXB voltage.<br />
Enumeration<br />
■ 2_5V<br />
■ 3_0V<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_VCCA_VOLTAGE -to -entity <br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
GXB_VCCA_VOLTAGE<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–421<br />
XCVR_VCCR_VCCT_VOLTAGE<br />
XCVR_VCCR_VCCT_VOLTAGE<br />
Type<br />
Configures the VCCR_GXB and VCCT_GXB voltage for a GXB I/O pin by specifying<br />
the intended supply voltages for a GXB I/O pin. If you do not set this option, the<br />
Compiler automatically sets the correct VCCR_GXB and VCCT_GXB voltage.<br />
Enumeration<br />
■ 0_85V<br />
■ 1_0V<br />
■ 1_1V<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE -to -entity<br />
<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
GXB_VCCR_VCCT_VOLTAGE<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–422 Chapter 6: Fitter Assignments<br />
XSTL_INPUT_ALLOW_SE_BUFFER<br />
XSTL_INPUT_ALLOW_SE_BUFFER<br />
Type<br />
Allows the pin with a Differential-XSTL IO-standard to be used with a single-ended<br />
input buffer.<br />
This option is a modifier of IO_STANDARD option with Differential HSTL/SSTL<br />
I/O standards setting. This option is only available for families which implement<br />
differential HSTL/SSTL input with true differential input buffer. If this option is on,<br />
the <strong>Quartus</strong> <strong>II</strong> software implements differential HSTL/SSTL input with single-ended<br />
input buffer with voltage reference. This option affects placment because it allows a<br />
differential HSTL/SSTL input to be placed on a pin location which does not have<br />
differential input buffer, but it also requires its reference voltage to be consistent with<br />
other pins shared the same VREF pin.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER <br />
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER -entity <br />
set_instance_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 6: Fitter Assignments 6–423<br />
XSTL_INPUT_ALLOW_SE_BUFFER<br />
Example<br />
set_instance_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER ON -to pin<br />
Default Value<br />
Off<br />
See Also<br />
■ “IO_STANDARD” on page 6–186<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
6–424 Chapter 6: Fitter Assignments<br />
XSTL_INPUT_ALLOW_SE_BUFFER<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
POWER_AUTO_COMPUTE_TJ<br />
Type<br />
© 2012 <strong>Altera</strong> Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos<br />
are trademarks of <strong>Altera</strong> Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as<br />
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. <strong>Altera</strong> warrants performance of its<br />
semiconductor products to current specifications in accordance with <strong>Altera</strong>'s standard warranty, but reserves the right to make changes to any products and<br />
services at any time without notice. <strong>Altera</strong> assumes no responsibility or liability arising out of the application or use of any information, product, or service<br />
described herein except as expressly agreed to in writing by <strong>Altera</strong>. <strong>Altera</strong> customers are advised to obtain the latest version of device specifications before relying<br />
on any published information and before placing orders for products or services.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong><br />
June 2012<br />
7. Power Estimation Assignments<br />
Specifies whether the junction temperature is auto-computed during power<br />
estimation. If the junction temperature is not auto-computed, you must specify the<br />
junction temperature.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
ISO<br />
9001:2008<br />
Registered<br />
Subscribe
7–2 Chapter 7: Power Estimation Assignments<br />
POWER_AUTO_COMPUTE_TJ<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_AUTO_COMPUTE_TJ <br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–3<br />
POWER_BOARD_TEMPERATURE<br />
POWER_BOARD_TEMPERATURE<br />
Type<br />
Specifies the board temperature, in degrees Celsius, used during power estimation.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_BOARD_TEMPERATURE <br />
Default Value<br />
25<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–4 Chapter 7: Power Estimation Assignments<br />
POWER_BOARD_THERMAL_MODEL<br />
POWER_BOARD_THERMAL_MODEL<br />
Type<br />
Specifies the board thermal model used during power estimation.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_BOARD_THERMAL_MODEL <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–5<br />
POWER_DEFAULT_INPUT_IO_TOGGLE_RATE<br />
POWER_DEFAULT_INPUT_IO_TOGGLE_RATE<br />
Type<br />
Specifies the default toggle rate to be used on input I/O pins during power<br />
estimation. This value is only used if a toggle rate has not been specified for a node<br />
either through a Signal Activity <strong>File</strong> (.saf), Value Change Dump <strong>File</strong> (.vcd), or user<br />
assignment.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–6 Chapter 7: Power Estimation Assignments<br />
POWER_DEFAULT_INPUT_IO_TOGGLE_RATE<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE <br />
Default Value<br />
12.5%<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–7<br />
POWER_DEFAULT_TOGGLE_RATE<br />
POWER_DEFAULT_TOGGLE_RATE<br />
Type<br />
Specifies the default toggle rate to be used on all nodes except input I/O pins during<br />
power estimation. This value is only used if a toggle rate has not been specified for a<br />
node either through a Signal Activity <strong>File</strong> (.saf), Value Change Dump <strong>File</strong> (.vcd), or<br />
user assignment.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–8 Chapter 7: Power Estimation Assignments<br />
POWER_DEFAULT_TOGGLE_RATE<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE <br />
Default Value<br />
12.5%<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–9<br />
POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR<br />
POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR<br />
Type<br />
Specifies the external supply voltage applied to the on-chip voltage regulator. This<br />
option applies only to devices which have an on-chip voltage regulator.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–10 Chapter 7: Power Estimation Assignments<br />
POWER_HPS_ENABLE<br />
POWER_HPS_ENABLE<br />
Type<br />
Specifies whether or not you must include the HPS processor subsystem for SoC<br />
power estimation.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_HPS_ENABLE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–11<br />
POWER_HPS_ENABLE<br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–12 Chapter 7: Power Estimation Assignments<br />
POWER_HPS_DYNAMIC_POWER_DUAL<br />
POWER_HPS_DYNAMIC_POWER_DUAL<br />
Tyoe<br />
Specifies the dynamic power of the dual processor core when HPS is active.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–13<br />
POWER_HPS_DYNAMIC_POWER_DUAL<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_HPS_DYNAMIC_POWER_DUAL <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–14 Chapter 7: Power Estimation Assignments<br />
POWER_HPS_DYNAMIC_POWER_SINGLE<br />
POWER_HPS_DYNAMIC_POWER_SINGLE<br />
Type<br />
Specifies the dynamic power of the single processor core when HPS is active.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–15<br />
POWER_HPS_DYNAMIC_POWER_SINGLE<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_HPS_DYNAMIC_POWER_SINGLE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–16 Chapter 7: Power Estimation Assignments<br />
POWER_HPS_JUNCTION_TEMPERATURE<br />
POWER_HPS_JUNCTION_TEMPERATURE<br />
Type<br />
Specifies the junction temperature when HPS is active.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–17<br />
POWER_HPS_JUNCTION_TEMPERATURE<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_HPS_JUNCTION_TEMPERATURE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–18 Chapter 7: Power Estimation Assignments<br />
POWER_HPS_PROC_FREQ<br />
POWER_HPS_PROC_FREQ<br />
Type<br />
Specifies the processor frequency of the HPS assumed by power estimation. The units<br />
for this value are in MHz and the value must be positive. The value provided must be<br />
within 0 to 1000.<br />
Double<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–19<br />
POWER_HPS_PROC_FREQ<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_HPS_PROC_FREQ <br />
Default Value<br />
0.0<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–20 Chapter 7: Power Estimation Assignments<br />
POWER_HPS_STATIC_POWER<br />
POWER_HPS_STATIC_POWER<br />
Type<br />
Specifies the static power when HPS is active.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–21<br />
POWER_HPS_STATIC_POWER<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_HPS_STATIC_POWER <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–22 Chapter 7: Power Estimation Assignments<br />
POWER_HPS_TOTAL_POWER<br />
POWER_HPS_TOTAL_POWER<br />
Type<br />
Specifies the total power when HPS is active.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–23<br />
POWER_HPS_TOTAL_POWER<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_HPS_TOTAL_POWER <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–24 Chapter 7: Power Estimation Assignments<br />
POWER_HSSI<br />
POWER_HSSI<br />
Type<br />
If the transceivers are unused, setting this option to Opportunistically power off<br />
directs the <strong>Quartus</strong> <strong>II</strong> software to consider the transceivers as powered down. Setting<br />
this option to Power on directs the <strong>Quartus</strong> <strong>II</strong> software to consider the transceivers<br />
powered regardless of their use. This setting affects the VCCA, VCCH_GXB, and VCCL_GXB<br />
power rails<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_HSSI <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–25<br />
POWER_HSSI_LEFT<br />
POWER_HSSI_LEFT<br />
Type<br />
If the transceivers on the left side of the device are unused, setting this option to<br />
Opportunistically power off directs the <strong>Quartus</strong> <strong>II</strong> software to consider the<br />
transceivers on the left side of the device powered down. Setting this option to Power<br />
on directs the <strong>Quartus</strong> <strong>II</strong> software to consider the transceivers on the left side powered<br />
regardless of their use. This setting affects the VCCA_L, VCCH_GXBL, VCCL_GXBL, VCCR_L,<br />
and VCCT_L power rails.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_HSSI_LEFT <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–26 Chapter 7: Power Estimation Assignments<br />
POWER_HSSI_RIGHT<br />
POWER_HSSI_RIGHT<br />
Type<br />
If the transceivers on the right side of the device are unused, setting this option to<br />
Opportunistically power off directs the <strong>Quartus</strong> <strong>II</strong> software to consider the<br />
transceivers on the right side of the device powered down. Setting this option to<br />
Power on directs the <strong>Quartus</strong> <strong>II</strong> software to consider the transceivers on the right side<br />
powered regardless of their use. This setting affects the VCCA_R, VCCH_GXBR, VCCL_GXBR,<br />
VCCR_R, and VCCT_R power rails.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_HSSI_RIGHT <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–27<br />
POWER_HSSI_VCCHIP_LEFT<br />
POWER_HSSI_VCCHIP_LEFT<br />
Type<br />
If the PCI Express hard IP blocks on the left side of the device are unused, setting this<br />
option to Opportunistically power off directs the <strong>Quartus</strong> <strong>II</strong> software to consider the<br />
PCI Express hard IP blocks on the left side of the device powered down. Setting this<br />
option to Power on directs the <strong>Quartus</strong> <strong>II</strong> software to consider the PCI Express hard IP<br />
blocks on the left side powered regardless of their use.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_HSSI_VCCHIP_LEFT <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–28 Chapter 7: Power Estimation Assignments<br />
POWER_HSSI_VCCHIP_RIGHT<br />
POWER_HSSI_VCCHIP_RIGHT<br />
Type<br />
If the PCI Express hard IP blocks on the right side of the device are unused, setting<br />
this option to Opportunistically power off directs the <strong>Quartus</strong> <strong>II</strong> software to consider<br />
the PCI Express hard IP blocks on the right side of the device powered down. Setting<br />
this option to Power on directs the <strong>Quartus</strong> <strong>II</strong> software to consider the PCI Express<br />
hard IP blocks on the right side powered regardless of their use.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_HSSI_VCCHIP_RIGHT <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–29<br />
POWER_INPUT_FILE_NAME<br />
POWER_INPUT_FILE_NAME<br />
Type<br />
Specifies the name of the Value Change Dump <strong>File</strong> (.vcd) or Signal Activity <strong>File</strong> (.saf)<br />
which should be used to initialize the toggle rates and static probabilities that are used<br />
during power estimation.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–30 Chapter 7: Power Estimation Assignments<br />
POWER_INPUT_FILE_NAME<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name POWER_INPUT_FILE_NAME -entity -<br />
section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–31<br />
POWER_INPUT_FILE_TYPE<br />
POWER_INPUT_FILE_TYPE<br />
Type<br />
Specifies whether the input power file is a Value Change Dump <strong>File</strong> (.vcd) or Signal<br />
Activity <strong>File</strong> (.saf).<br />
Enumeration<br />
■ SAF<br />
■ VCD<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–32 Chapter 7: Power Estimation Assignments<br />
POWER_INPUT_FILE_TYPE<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name POWER_INPUT_FILE_TYPE -entity -<br />
section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–33<br />
POWER_INPUT_SAF_NAME<br />
POWER_INPUT_SAF_NAME<br />
Type<br />
Specifies the name of the Signal Activity <strong>File</strong> (.saf) which should be used to initialize<br />
the toggle rates and static probabilities that are used during power estimation.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name POWER_INPUT_SAF_NAME <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–34 Chapter 7: Power Estimation Assignments<br />
POWER_INPUT_VCD_FILE_NAME<br />
POWER_INPUT_VCD_FILE_NAME<br />
Type<br />
Specifies the names of the Value Change Dump <strong>File</strong>s (.vcd) which should be used to<br />
initialize the toggle rates and static probabilities that are used during power<br />
estimation.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name POWER_INPUT_VCD_FILE_NAME <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–35<br />
POWER_OCS_VALUE<br />
POWER_OCS_VALUE<br />
Type<br />
Specifies the case-to-heat sink thermal resistance, in degrees Celsius per Watt, used<br />
during power estimation.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_OCS_VALUE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–36 Chapter 7: Power Estimation Assignments<br />
POWER_OJB_VALUE<br />
POWER_OJB_VALUE<br />
Type<br />
Specifies the junction-to-board thermal resistance, in degrees Celsius per Watt, used<br />
during power estimation.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_OJB_VALUE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–37<br />
POWER_OJC_VALUE<br />
POWER_OJC_VALUE<br />
Type<br />
Specifies the junction-to-case sink thermal resistance, in degrees Celsius per Watt,<br />
used during power estimation.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_OJC_VALUE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–38 Chapter 7: Power Estimation Assignments<br />
POWER_OSA_VALUE<br />
POWER_OSA_VALUE<br />
Type<br />
Specifies the heat sink-to-ambient thermal resistance, in degrees Celsius per Watt,<br />
used during power estimation.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_OSA_VALUE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–39<br />
POWER_OUTPUT_SAF_NAME<br />
POWER_OUTPUT_SAF_NAME<br />
Type<br />
Specifies the name the Signal Activity <strong>File</strong> (.saf) should be written to containing the<br />
toggle rates and static probabilities used during power estimation.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–40 Chapter 7: Power Estimation Assignments<br />
POWER_OUTPUT_SAF_NAME<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_OUTPUT_SAF_NAME <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–41<br />
POWER_PRESET_COOLING_SOLUTION<br />
POWER_PRESET_COOLING_SOLUTION<br />
Type<br />
Specifies the preset cooling solution used during power estimation.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–42 Chapter 7: Power Estimation Assignments<br />
POWER_READ_INPUT_FILE<br />
POWER_READ_INPUT_FILE<br />
Type<br />
Assigns user-defined power input file characteristics to an entity. To specify a power<br />
input file, you must define a named group of power input file settings and assign<br />
them to an entity with this option. You can create these settings using the PowerPlay<br />
Power Analyzer <strong>Settings</strong> page.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–43<br />
POWER_READ_INPUT_FILE<br />
■ Stratix V<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_instance_assignment -name POWER_READ_INPUT_FILE -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–44 Chapter 7: Power Estimation Assignments<br />
POWER_REPORT_POWER_DISSIPATION<br />
POWER_REPORT_POWER_DISSIPATION<br />
Type<br />
Specifies whether the PowerPlay Power Analyzer should report the thermal power<br />
dissipation calculated during power analysis in the Thermal Power Dissipation By<br />
Block report panel.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–45<br />
POWER_REPORT_POWER_DISSIPATION<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION <br />
set_instance_assignment -name POWER_REPORT_POWER_DISSIPATION -to -<br />
entity <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–46 Chapter 7: Power Estimation Assignments<br />
POWER_REPORT_SIGNAL_ACTIVITY<br />
POWER_REPORT_SIGNAL_ACTIVITY<br />
Type<br />
Specifies whether the PowerPlay Power Analyzer should report the signal activities<br />
assumed for power analysis, and the sources for those activities. Signal activity<br />
consists of both the static probability and the toggle rate for the signals generated by<br />
the node or entity.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–47<br />
POWER_REPORT_SIGNAL_ACTIVITY<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY <br />
set_instance_assignment -name POWER_REPORT_SIGNAL_ACTIVITY -to -<br />
entity <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–48 Chapter 7: Power Estimation Assignments<br />
POWER_SIGNAL_ACTIVITY_END_TIME<br />
POWER_SIGNAL_ACTIVITY_END_TIME<br />
Type<br />
Specifies the time at which toggle rates and static probabilities should stop being<br />
calculated for the output signals contained in the Value Change Dump <strong>File</strong>s (.vcd).<br />
Time<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_global_assignment -name POWER_SIGNAL_ACTIVITY_END_TIME <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–49<br />
POWER_SIGNAL_ACTIVITY_START_TIME<br />
POWER_SIGNAL_ACTIVITY_START_TIME<br />
Type<br />
Specifies the time at which toggle rates and static probabilities should start to be<br />
calculated for the output signals contained in the Value Change Dump <strong>File</strong>s (.vcd).<br />
Time<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_global_assignment -name POWER_SIGNAL_ACTIVITY_START_TIME <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–50 Chapter 7: Power Estimation Assignments<br />
POWER_STATIC_PROBABILITY<br />
POWER_STATIC_PROBABILITY<br />
Type<br />
Specifies the fraction of time the signals generated by the node or entity are expected<br />
to be at VCC. Allowable values range from and include 0.0 through 1.0.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–51<br />
POWER_STATIC_PROBABILITY<br />
Syntax<br />
set_instance_assignment -name POWER_STATIC_PROBABILITY -to <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–52 Chapter 7: Power Estimation Assignments<br />
POWER_TJ_VALUE<br />
POWER_TJ_VALUE<br />
Type<br />
Specifies the junction temperature value, in degrees Celsius, used during power<br />
estimation.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_TJ_VALUE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–53<br />
POWER_TJ_VALUE<br />
Default Value<br />
25<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–54 Chapter 7: Power Estimation Assignments<br />
POWER_TOGGLE_RATE<br />
POWER_TOGGLE_RATE<br />
Type<br />
Specifies the toggle rate assumed by power estimation for the signals generated by<br />
this node or entity. The units for this value are transitions per second and the value<br />
must be positive. The value provided should be the expected time-averaged toggle<br />
rate, rather than worst case (highest possible) toggle rate. A different assignment,<br />
Toggle Rate, applies to I/O pins only and is used by the Fitter and by I/O<br />
Assignment Analysis to verify signal integrity under worst case conditions (highest<br />
possible toggle rate). Use the Synchronizer Toggle Rate if you want to configure the<br />
data rates used for Metastability Reporting in the TimeQuest timing analyzer.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–55<br />
POWER_TOGGLE_RATE<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Syntax<br />
set_instance_assignment -name POWER_TOGGLE_RATE -to <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–56 Chapter 7: Power Estimation Assignments<br />
POWER_TOGGLE_RATE_PERCENTAGE<br />
POWER_TOGGLE_RATE_PERCENTAGE<br />
Type<br />
Specifies the toggle rate, as a percentage of clock domain frequency, assumed by<br />
power estimation for the signals generated by this node or entity. This percentage acts<br />
as a multiplier for the clock domain frequency of the given node. For example, a<br />
toggle rate percentage of 12.5 on a node with a clock domain frequency of 96 MHz<br />
would result in a toggle rate of 12 million transitions per second. The percentage<br />
value must be positive and can take on values greater than 100. The value provided<br />
should be representative of the expected time-averaged toggle rate, rather than worst<br />
case (highest possible) toggle rate.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–57<br />
POWER_TOGGLE_RATE_PERCENTAGE<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Syntax<br />
set_instance_assignment -name POWER_TOGGLE_RATE_PERCENTAGE -to <br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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7–58 Chapter 7: Power Estimation Assignments<br />
POWER_USE_CUSTOM_COOLING_SOLUTION<br />
POWER_USE_CUSTOM_COOLING_SOLUTION<br />
Type<br />
Specifies whether a custom cooling solution is used during power estimation. For a<br />
custom cooling solution, you must specify the case-to-heat sink, junction-to-case and<br />
heat sink-to-ambient thermal resistances.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–59<br />
POWER_USE_CUSTOM_COOLING_SOLUTION<br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–60 Chapter 7: Power Estimation Assignments<br />
POWER_USE_DEVICE_CHARACTERISTICS<br />
POWER_USE_DEVICE_CHARACTERISTICS<br />
Type<br />
Specifies the device characteristics to be used during power estimation.<br />
Estimates are based on average power consumed by typical silicon at nominal<br />
operating conditions. For FPGA board power supply design, change to MAXIMUM<br />
to get worst-case values.<br />
Enumeration<br />
■ MAXIMUM<br />
■ TYPICAL<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–61<br />
POWER_USE_DEVICE_CHARACTERISTICS<br />
Syntax<br />
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS <br />
Default Value<br />
TYPICAL<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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7–62 Chapter 7: Power Estimation Assignments<br />
POWER_USE_INPUT_FILE<br />
POWER_USE_INPUT_FILE<br />
Type<br />
Specifies whether or not Signal Activity <strong>File</strong>s (.saf) or Value Change Dump <strong>File</strong>s (.vcd)<br />
should be used to initialize the toggle rates and static probabilities that will be used<br />
during power estimation.<br />
Enumeration<br />
■ No <strong>File</strong><br />
■ Signal Activity <strong>File</strong><br />
■ VCD <strong>File</strong><br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_global_assignment -name POWER_USE_INPUT_FILE <br />
Default Value<br />
No <strong>File</strong><br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–63<br />
POWER_USE_INPUT_FILES<br />
POWER_USE_INPUT_FILES<br />
Type<br />
Specifies whether or not Signal Activity <strong>File</strong>s (.saf) or Value Change Dump <strong>File</strong>s (.vcd)<br />
should be used to initialize the toggle rates and static probabilities that will be used<br />
during power estimation.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–64 Chapter 7: Power Estimation Assignments<br />
POWER_USE_INPUT_FILES<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_USE_INPUT_FILES <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–65<br />
POWER_USE_PVA<br />
POWER_USE_PVA<br />
Type<br />
Specifies whether or not Power Vectorless Activity should be used to fill in undefined<br />
toggle rates and static probabilities.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_USE_PVA <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–66 Chapter 7: Power Estimation Assignments<br />
POWER_USE_PVA<br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–67<br />
POWER_USE_TA_VALUE<br />
POWER_USE_TA_VALUE<br />
Type<br />
Specifies the ambient temperature value, in degrees Celsius, used during power<br />
estimation.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_USE_TA_VALUE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–68 Chapter 7: Power Estimation Assignments<br />
POWER_USE_TA_VALUE<br />
Default Value<br />
25<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–69<br />
POWER_VCCAUX_USER_OPTION<br />
POWER_VCCAUX_USER_OPTION<br />
Type<br />
Allows you to specify settings for the VCCAUX power rail supply. For more information,<br />
refer to the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_VCCAUX_USER_OPTION <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–70 Chapter 7: Power Estimation Assignments<br />
POWER_VCCA_GXB_USER_OPTION<br />
POWER_VCCA_GXB_USER_OPTION<br />
Type<br />
Allows you to specify settings for the VCCA_GXB power rail supply. For more<br />
information, refer to the device datasheet for the current device family.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_VCCA_GXB_USER_OPTION <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–71<br />
POWER_VCCA_L_USER_OPTION<br />
POWER_VCCA_L_USER_OPTION<br />
Type<br />
Allows you to specify settings for the VCCA_L power rail supply. For more information,<br />
refer to the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_VCCA_L_USER_OPTION <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–72 Chapter 7: Power Estimation Assignments<br />
POWER_VCCA_R_USER_OPTION<br />
POWER_VCCA_R_USER_OPTION<br />
Type<br />
Allows you to specify settings for the VCCA_R power rail supply. For more information,<br />
refer to the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_VCCA_R_USER_OPTION <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–73<br />
POWER_VCCCB_USER_OPTION<br />
POWER_VCCCB_USER_OPTION<br />
Type<br />
Allows you to specify settings for the VCCCB power rail supply. For more information,<br />
refer to the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_VCCCB_USER_OPTION <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–74 Chapter 7: Power Estimation Assignments<br />
POWER_VCCH_GXBL_USER_OPTION<br />
POWER_VCCH_GXBL_USER_OPTION<br />
Type<br />
Allows you to specify settings for the VCCH_GXBL power rail supply. For more<br />
information, refer to the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_VCCH_GXBL_USER_OPTION <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–75<br />
POWER_VCCH_GXBR_USER_OPTION<br />
POWER_VCCH_GXBR_USER_OPTION<br />
Type<br />
Allows you to specify settings for the VCCH_GXBR power rail supply. For more<br />
information, refer to the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_VCCH_GXBR_USER_OPTION <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–76 Chapter 7: Power Estimation Assignments<br />
POWER_VCCH_GXB_USER_OPTION<br />
POWER_VCCH_GXB_USER_OPTION<br />
Type<br />
Allows you to specify settings for the VCCH_GXB power rail supply. For more<br />
information, refer to the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_VCCH_GXB_USER_OPTION <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–77<br />
POWER_VCCIO_USER_OPTION<br />
POWER_VCCIO_USER_OPTION<br />
Type<br />
Allows you to specify settings for the VCCIO power rail supply. For more information,<br />
refer to the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_VCCIO_USER_OPTION <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–78 Chapter 7: Power Estimation Assignments<br />
POWER_VCCL_GXB_USER_OPTION<br />
POWER_VCCL_GXB_USER_OPTION<br />
Type<br />
Allows you to specify settings for the VCCL_GXB power rail supply. For more<br />
information, refer to the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_VCCL_GXB_USER_OPTION <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–79<br />
POWER_VCCPD_USER_OPTION<br />
POWER_VCCPD_USER_OPTION<br />
Type<br />
Allows you to specify settings for the VCCPD power rail supply. For more information,<br />
refer to the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_VCCPD_USER_OPTION <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–80 Chapter 7: Power Estimation Assignments<br />
POWER_VCCR_GXBL_USER_OPTION<br />
POWER_VCCR_GXBL_USER_OPTION<br />
Type<br />
Allows you to specify settings for the VCCR_GXBL power rail supply. For more<br />
information, refer to the device datasheet for the current device family.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_VCCR_GXBL_USER_OPTION <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–81<br />
POWER_VCCR_GXBR_USER_OPTION<br />
POWER_VCCR_GXBR_USER_OPTION<br />
Type<br />
Allows you to specify settings for the VCCR_GXBR power rail supply. For more<br />
information, refer to the device datasheet for the current device family.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_VCCR_GXBR_USER_OPTION <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–82 Chapter 7: Power Estimation Assignments<br />
POWER_VCCR_GXB_USER_OPTION<br />
POWER_VCCR_GXB_USER_OPTION<br />
Type<br />
Allows you to specify settings for the VCCR_GXB power rail supply. For more<br />
information, refer to the device datasheet for the current device family.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_VCCR_GXB_USER_OPTION <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–83<br />
POWER_VCCT_GXBL_USER_OPTION<br />
POWER_VCCT_GXBL_USER_OPTION<br />
Type<br />
Allows you to specify settings for the VCCT_GXBL power rail supply. For more<br />
information, refer to the device datasheet for the current device family.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_VCCT_GXBL_USER_OPTION <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–84 Chapter 7: Power Estimation Assignments<br />
POWER_VCCT_GXBR_USER_OPTION<br />
POWER_VCCT_GXBR_USER_OPTION<br />
Type<br />
Allows you to specify settings for the VCCT_GXBR power rail supply. Refer to the<br />
device datasheet for the current device family for more details.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_VCCT_GXBR_USER_OPTION <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–85<br />
POWER_VCCT_GXB_USER_OPTION<br />
POWER_VCCT_GXB_USER_OPTION<br />
Type<br />
Allows you to specify settings for the VCCT_GXB power rail supply. For more<br />
information, refer to the device datasheet for the current device family.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name POWER_VCCT_GXB_USER_OPTION <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–86 Chapter 7: Power Estimation Assignments<br />
POWER_VCD_FILE_END_TIME<br />
POWER_VCD_FILE_END_TIME<br />
Type<br />
Specifies the time at which toggle rates and static probabilities should stop being<br />
calculated for the output signals contained in the Value Change Dump <strong>File</strong>s (.vcd).<br />
Time<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–87<br />
POWER_VCD_FILE_END_TIME<br />
Syntax<br />
set_global_assignment -name POWER_VCD_FILE_END_TIME -entity <br />
-section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–88 Chapter 7: Power Estimation Assignments<br />
POWER_VCD_FILE_START_TIME<br />
POWER_VCD_FILE_START_TIME<br />
Type<br />
Specifies the time at which toggle rates and static probabilities should start to be<br />
calculated for the output signals contained in the Value Change Dump <strong>File</strong>s (.vcd).<br />
Time<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–89<br />
POWER_VCD_FILE_START_TIME<br />
Syntax<br />
set_global_assignment -name POWER_VCD_FILE_START_TIME -entity -section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–90 Chapter 7: Power Estimation Assignments<br />
POWER_VCD_FILTER_GLITCHES<br />
POWER_VCD_FILTER_GLITCHES<br />
Type<br />
Specifies whether or not glitch filtering should be used when reading in Value Change<br />
Dump <strong>File</strong>s (.vcd).<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–91<br />
POWER_VCD_FILTER_GLITCHES<br />
Syntax<br />
set_global_assignment -name POWER_VCD_FILTER_GLITCHES <br />
Default Value<br />
On<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–92 Chapter 7: Power Estimation Assignments<br />
VCCAUX_USER_VOLTAGE<br />
VCCAUX_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCAUX power rail supply. For more information, refer to<br />
the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCAUX_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–93<br />
VCCA_GXBL_USER_VOLTAGE<br />
VCCA_GXBL_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCA_GXBL power rail supply. For more information,<br />
refer to the device datasheet for the current device family.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCA_GXBL_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–94 Chapter 7: Power Estimation Assignments<br />
VCCA_GXBR_USER_VOLTAGE<br />
VCCA_GXBR_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCA_GXBR power rail supply. For more information,<br />
refer to the device datasheet for the current device family.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCA_GXBR_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–95<br />
VCCA_GXB_USER_VOLTAGE<br />
VCCA_GXB_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCA_GXB power rail supply. For more information, refer to<br />
the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCA_GXB_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–96 Chapter 7: Power Estimation Assignments<br />
VCCA_L_USER_VOLTAGE<br />
VCCA_L_USER_VOLTAGE<br />
Type<br />
Specifies the default voltage of the VCCA_L power rail supply, which is applied if all<br />
transceivers on the left side of the device are powered and unused. To configure a<br />
transceiver for your intended protocol, use the ALTGX MegaWizard. For more<br />
information, refer to the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCA_L_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–97<br />
VCCA_PLL_USER_VOLTAGE<br />
VCCA_PLL_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCA_PLL power rail supply. For more information, refer to<br />
the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCA_PLL_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–98 Chapter 7: Power Estimation Assignments<br />
VCCA_R_USER_VOLTAGE<br />
VCCA_R_USER_VOLTAGE<br />
Type<br />
Specifies the default voltage of the VCCA_R power rail supply, which is applied if all<br />
transceivers on the right side of the device are powered and unused. To configure a<br />
transceiver for your intended protocol, use the ALTGX MegaWizard. For more<br />
information, refer to the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCA_R_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–99<br />
VCCA_USER_VOLTAGE<br />
VCCA_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCA power rail supply. For devices in the Arria <strong>II</strong> family,<br />
this voltage is applied if the transceivers are powered. For more information, refer to<br />
the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCA_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–100 Chapter 7: Power Estimation Assignments<br />
VCCCB_USER_VOLTAGE<br />
VCCCB_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCCB power rail supply. For more information, refer to the<br />
respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCCB_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–101<br />
VCCD_PLL_USER_VOLTAGE<br />
VCCD_PLL_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCD_PLL power rail supply. For more information, refer to<br />
the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCD_PLL_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–102 Chapter 7: Power Estimation Assignments<br />
VCCD_USER_VOLTAGE<br />
VCCD_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCD power rail supply. For more information, refer to the<br />
respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCD_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–103<br />
VCCE_GXBL_USER_VOLTAGE<br />
VCCE_GXBL_USER_VOLTAGE<br />
Type<br />
Specifies the default voltage of the VCCE_GXBL power rail supplies, which is applied<br />
if all transceivers in the corresponding transceiver block are powered and unused. To<br />
configure a transceiver for your intended protocol, use the ALTGX MegaWizard Plug-<br />
In Manager. For more information, refer to the device datasheet for the current device<br />
family.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCE_GXBL_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–104 Chapter 7: Power Estimation Assignments<br />
VCCE_GXBR_USER_VOLTAGE<br />
VCCE_GXBR_USER_VOLTAGE<br />
Type<br />
Specifies the default voltage of the VCCE_GXBR power rail supplies, which is applied<br />
if all transceivers in the corresponding transceiver block are powered and unused. To<br />
configure a transceiver for your intended protocol, use the ALTGX MegaWizard Plug-<br />
In Manager. For more information, refer to the device datasheet for the current device<br />
family.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCE_GXBR_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–105<br />
VCCE_GXB_USER_VOLTAGE<br />
VCCE_GXB_USER_VOLTAGE<br />
Type<br />
Specifies the default voltage of the VCCE_GXB power rail supplies, which is applied<br />
if all transceivers in the corresponding transceiver block are powered and unused. To<br />
configure a transceiver for your intended protocol, use the ALTGX MegaWizard Plug-<br />
In Manager. For more information, refer to the device datasheet for the current device<br />
family.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCE_GXB_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–106 Chapter 7: Power Estimation Assignments<br />
VCCE_USER_VOLTAGE<br />
VCCE_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCE power rail supply. For more information, refer to<br />
the device datasheet for the current device family.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCE_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–107<br />
VCCEH_GXBL_USER_VOLTAGE<br />
VCCEH_GXBL_USER_VOLTAGE<br />
Type<br />
Specifies the default voltage of the VCCEH_GXBL power rail supplies, which is<br />
applied if all transceivers in the corresponding transceiver block are powered and<br />
unused. To configure a transceiver for your intended protocol, use the ALTGX<br />
MegaWizard Plug-In Manager. For more information, refer to the device datasheet for<br />
the current device family.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCEH_GXBL_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–108 Chapter 7: Power Estimation Assignments<br />
VCCEH_GXBR_USER_VOLTAGE<br />
VCCEH_GXBR_USER_VOLTAGE<br />
Type<br />
Specifies the default voltage of the VCCEH_GXBR power rail supplies, which is<br />
applied if all transceivers in the corresponding transceiver block are powered and<br />
unused. To configure a transceiver for your intended protocol, use the ALTGX<br />
MegaWizard Plug-In Manager. For more information, refer to the device datasheet for<br />
the current device family.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCEH_GXBR_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–109<br />
VCCEH_GXB_USER_VOLTAGE<br />
VCCEH_GXB_USER_VOLTAGE<br />
Type<br />
Specifies the default voltage of the VCCEH_GXB power rail supplies, which is<br />
applied if all transceivers in the corresponding transceiver block are powered and<br />
unused. To configure a transceiver for your intended protocol, use the ALTGX<br />
MegaWizard Plug-In Manager. For more information, refer to the device datasheet for<br />
the current device family.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCEH_GXB_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–110 Chapter 7: Power Estimation Assignments<br />
VCCHIP_L_USER_VOLTAGE<br />
VCCHIP_L_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCHIP_L power rail supply. For more information, refer to<br />
the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCHIP_L_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–111<br />
VCCHIP_R_USER_VOLTAGE<br />
VCCHIP_R_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCHIP_R power rail supply. For more information, refer to<br />
the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCHIP_R_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–112 Chapter 7: Power Estimation Assignments<br />
VCCHIP_USER_VOLTAGE<br />
VCCHIP_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCHIP power rail supply. For more information, refer to<br />
the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCHIP_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–113<br />
VCCHSSI_L_USER_VOLTAGE<br />
VCCHSSI_L_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCHSSI_L power rail supply. For more information,<br />
refer to the device datasheet for the current device family.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCHSSI_L_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–114 Chapter 7: Power Estimation Assignments<br />
VCCHSSI_R_USER_VOLTAGE<br />
VCCHSSI_R_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCHSSI_R power rail supply. For more information,<br />
refer to the device datasheet for the current device family.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCHSSI_R_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–115<br />
VCCH_GXBL_USER_VOLTAGE<br />
VCCH_GXBL_USER_VOLTAGE<br />
Type<br />
Specifies the default voltage of the VCCH_GXBL power rail supplies, which is applied if<br />
all transceivers in the corresponding transceiver block are powered and unused. To<br />
configure a transceiver for your intended protocol, use the ALTGX MegaWizard. For<br />
more information, refer to the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCH_GXBL_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–116 Chapter 7: Power Estimation Assignments<br />
VCCH_GXBR_USER_VOLTAGE<br />
VCCH_GXBR_USER_VOLTAGE<br />
Type<br />
Specifies the default voltage of the VCCH_GXBR power rail supplies, which is applied if<br />
all transceivers in the corresponding transceiver block are powered and unused. To<br />
configure a transceiver for your intended protocol, use the ALTGX MegaWizard. For<br />
more information, refer to the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCH_GXBR_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–117<br />
VCCH_GXB_USER_VOLTAGE<br />
VCCH_GXB_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCH_GXB power rail supply. For more information, refer to<br />
the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCH_GXB_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–118 Chapter 7: Power Estimation Assignments<br />
VCCH_L_USER_VOLTAGE<br />
VCCH_L_USER_VOLTAGE<br />
Type<br />
Specifies the default voltage of the VCCH_L power rail supplies, which is applied if<br />
all transceivers in the corresponding transceiver block are powered and unused. To<br />
configure a transceiver for your intended protocol, use the ALTGX MegaWizard Plug-<br />
In Manager. For more information, refer to the device datasheet for the current device<br />
family.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCH_L_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–119<br />
VCCH_R_USER_VOLTAGE<br />
VCCH_R_USER_VOLTAGE<br />
Type<br />
Specifies the default voltage of the VCCH_R power rail supplies, which is applied if<br />
all transceivers in the corresponding transceiver block are powered and unused. To<br />
configure a transceiver for your intended protocol, use the ALTGX MegaWizard Plug-<br />
In Manager. For more information, refer to the device datasheet for the current device<br />
family.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCH_R_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–120 Chapter 7: Power Estimation Assignments<br />
VCCINT_USER_VOLTAGE<br />
VCCINT_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCINT power rail supply. For more information, refer to<br />
the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCINT_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–121<br />
VCCIO_USER_VOLTAGE<br />
VCCIO_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCIO power rail supply. For more information, refer to the<br />
respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCIO_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–122 Chapter 7: Power Estimation Assignments<br />
VCCL_GXBL_USER_VOLTAGE<br />
VCCL_GXBL_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCL_GXBL power rail supply. For more information, refer<br />
to the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCL_GXBL_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–123<br />
VCCL_GXBR_USER_VOLTAGE<br />
VCCL_GXBR_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCL_GXBR power rail supply. For more information, refer<br />
to the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCL_GXBR_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–124 Chapter 7: Power Estimation Assignments<br />
VCCL_GXB_USER_VOLTAGE<br />
VCCL_GXB_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCL_GXB power rail supply. For more information, refer to<br />
the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCL_GXB_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–125<br />
VCCL_USER_VOLTAGE<br />
VCCL_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCL power rail supply. For more information, refer to the<br />
respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCL_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–126 Chapter 7: Power Estimation Assignments<br />
VCCPD_USER_VOLTAGE<br />
VCCPD_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCPD power rail supply. For more information, refer to the<br />
respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCPD_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–127<br />
VCCPT_USER_VOLTAGE<br />
VCCPT_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCPT power rail supply. For more information, refer to the<br />
respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCPT_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–128 Chapter 7: Power Estimation Assignments<br />
VCCP_USER_VOLTAGE<br />
VCCP_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCP power rail supply. For more information, refer to<br />
the device datasheet for the current device family.<br />
String<br />
Device Families<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCP_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–129<br />
VCCR_GXBL_USER_VOLTAGE<br />
VCCR_GXBL_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCR_GXBL power rail supply. For more information,<br />
refer to the device datasheet for the current device family.<br />
String<br />
Device Families<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCR_GXBL_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–130 Chapter 7: Power Estimation Assignments<br />
VCCR_GXBR_USER_VOLTAGE<br />
VCCR_GXBR_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCR_GXBR power rail supply. For more information,<br />
refer to the device datasheet for the current device family.<br />
String<br />
Device Families<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCR_GXBR_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–131<br />
VCCR_GXB_USER_VOLTAGE<br />
VCCR_GXB_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCR_GXB power rail supply. For more information, refer<br />
to the device datasheet for the current device family.<br />
String<br />
Device Families<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCR_GXB_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–132 Chapter 7: Power Estimation Assignments<br />
VCCR_L_USER_VOLTAGE<br />
VCCR_L_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCR_L power rail supply. For more information, refer to<br />
the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCR_L_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–133<br />
VCCR_R_USER_VOLTAGE<br />
VCCR_R_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCR_R power rail supply. For more information, refer to<br />
the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCR_R_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–134 Chapter 7: Power Estimation Assignments<br />
VCCR_USER_VOLTAGE<br />
VCCR_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCR power rail supply. For more information, refer to the<br />
respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCR_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–135<br />
VCCT_GXBL_USER_VOLTAGE<br />
VCCT_GXBL_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCT_GXBL power rail supply. For more information,<br />
refer to the device datasheet for the current device family.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCT_GXBL_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–136 Chapter 7: Power Estimation Assignments<br />
VCCT_GXBR_USER_VOLTAGE<br />
VCCT_GXBR_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCT_GXBR power rail supply. For more information,<br />
refer to the device datasheet for the current device family.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCT_GXBR_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–137<br />
VCCT_GXB_USER_VOLTAGE<br />
VCCT_GXB_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCT_GXB power rail supply. For more information, refer<br />
to the device datasheet for the current device family.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCT_GXB_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–138 Chapter 7: Power Estimation Assignments<br />
VCCT_L_USER_VOLTAGE<br />
VCCT_L_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCT_L power rail supply. For more information, refer to<br />
the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCT_L_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–139<br />
VCCT_R_USER_VOLTAGE<br />
VCCT_R_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCT_R power rail supply. For more information, refer to<br />
the respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCT_R_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–140 Chapter 7: Power Estimation Assignments<br />
VCCT_USER_VOLTAGE<br />
VCCT_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCCT power rail supply. For more information, refer to the<br />
respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCCT_USER_VOLTAGE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 7: Power Estimation Assignments 7–141<br />
VCC_USER_VOLTAGE<br />
VCC_USER_VOLTAGE<br />
Type<br />
Specifies the voltage of the VCC power rail supply. For more information, refer to the<br />
respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
C<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name VCC_USER_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
7–142 Chapter 7: Power Estimation Assignments<br />
VCC_USER_VOLTAGE<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
EDA_BOARD_BOUNDARY_SCAN_OPERATION<br />
Type<br />
© 2012 <strong>Altera</strong> Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos<br />
are trademarks of <strong>Altera</strong> Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as<br />
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. <strong>Altera</strong> warrants performance of its<br />
semiconductor products to current specifications in accordance with <strong>Altera</strong>'s standard warranty, but reserves the right to make changes to any products and<br />
services at any time without notice. <strong>Altera</strong> assumes no responsibility or liability arising out of the application or use of any information, product, or service<br />
described herein except as expressly agreed to in writing by <strong>Altera</strong>. <strong>Altera</strong> customers are advised to obtain the latest version of device specifications before relying<br />
on any published information and before placing orders for products or services.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong><br />
June 2012<br />
8. EDA Netlist Writer Assignments<br />
Specifies the Boundary-Scan Description Language (BSDL) file operation either for<br />
pre-configuration or post-configuration<br />
Enumeration<br />
Device Support<br />
■ POST_CONFIG<br />
■ PRE_CONFIG<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION -section_id<br />
<br />
Default Value<br />
PRE_CONFIG, requires section identifier<br />
ISO<br />
9001:2008<br />
Registered<br />
Subscribe
8–2 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL<br />
EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL<br />
Type<br />
Specifies the boundary scan format used for board level boundary scan testing.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL <br />
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL -entity<br />
<br />
Default Value<br />
None<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–3<br />
EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL<br />
EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL<br />
Type<br />
Specifies the EDA third-party tool used for board level signal integrity analysis.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL <br />
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL -entity<br />
<br />
Default Value<br />
None<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–4 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_BOARD_DESIGN_SYMBOL_TOOL<br />
EDA_BOARD_DESIGN_SYMBOL_TOOL<br />
Type<br />
Specifies the EDA third-party tool used for board level schematic design.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL <br />
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL -entity <br />
Default Value<br />
None<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–5<br />
EDA_BOARD_DESIGN_TIMING_TOOL<br />
EDA_BOARD_DESIGN_TIMING_TOOL<br />
Type<br />
Specifies the EDA third-party tool used for board level timing analysis.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL <br />
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL -entity <br />
Default Value<br />
None<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–6 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_BOARD_DESIGN_TOOL<br />
EDA_BOARD_DESIGN_TOOL<br />
Type<br />
Specifies the EDA third-party tool used for board level design and analysis.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_BOARD_DESIGN_TOOL <br />
set_global_assignment -name EDA_BOARD_DESIGN_TOOL -entity <br />
<br />
Default Value<br />
None<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–7<br />
EDA_DESIGN_EXTRA_ALTERA_SIM_LIB<br />
EDA_DESIGN_EXTRA_ALTERA_SIM_LIB<br />
Type<br />
Specifies additional <strong>Altera</strong> simulation model libraries used by the design files.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDA_DESIGN_EXTRA_ALTERA_SIM_LIB -section_id<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–8 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_DESIGN_INSTANCE_NAME<br />
EDA_DESIGN_INSTANCE_NAME<br />
Type<br />
Specifies the instance name of the design in the test bench.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME -section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–9<br />
EDA_ENABLE_GLITCH_FILTERING<br />
EDA_ENABLE_GLITCH_FILTERING<br />
Type<br />
Writes logic to filter glitches in the simulation netlist.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING -section_id<br />
<br />
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING -entity -section_id <br />
Default Value<br />
Off, requires section identifier<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–10 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_ENABLE_IPUTF_MODE<br />
EDA_ENABLE_IPUTF_MODE<br />
Type<br />
Allows you to simulate designs containing hw.tcl based IP cores. This may require<br />
adding .sip files to your <strong>Quartus</strong> <strong>II</strong> project. This variable may be removed in future<br />
releases<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_ENABLE_IPUTF_MODE -section_id <br />
set_global_assignment -name EDA_ENABLE_IPUTF_MODE -entity -<br />
section_id <br />
Default Value<br />
On, requires section identifier<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–11<br />
EDA_EXTRA_ELAB_OPTION<br />
EDA_EXTRA_ELAB_OPTION<br />
Type<br />
Additional custom simulation elaboration options for one or more simulators.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_EXTRA_ELAB_OPTION -section_id <br />
set_global_assignment -name EDA_EXTRA_ELAB_OPTION -entity -<br />
section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–12 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_FLATTEN_BUSES<br />
EDA_FLATTEN_BUSES<br />
Type<br />
Flattens all buses when creating the VHDL Output <strong>File</strong> (.vho). You should turn on this<br />
option if your third-party EDA environment does not support buses.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_FLATTEN_BUSES -section_id <br />
set_global_assignment -name EDA_FLATTEN_BUSES -entity -<br />
section_id <br />
Default Value<br />
Off, requires section identifier<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–13<br />
EDA_FORMAL_VERIFICATION_ALLOW_RETIMING<br />
EDA_FORMAL_VERIFICATION_ALLOW_RETIMING<br />
Type<br />
Allows register retiming to be turned on for formal verification.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING -<br />
section_id <br />
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING -entity<br />
-section_id <br />
Default Value<br />
Off, requires section identifier<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–14 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_FORMAL_VERIFICATION_TOOL<br />
EDA_FORMAL_VERIFICATION_TOOL<br />
Type<br />
Specifies the EDA third-party tool used for formal verification.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL <br />
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL -entity <br />
Default Value<br />
None<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–15<br />
EDA_FV_HIERARCHY<br />
EDA_FV_HIERARCHY<br />
Type<br />
Determines how the hierarchy of design entities is to be processed during<br />
compilation. The BLACKBOX setting causes the entity to be handled as a black-box in<br />
the EDA flow. The NONE setting is the default and means that no special handling<br />
needs to be done. This option applies only to the design entity to which it is assigned;<br />
lower-level entities do not inherit the setting of their parent entity for this option.<br />
Enumeration<br />
■ BLACKBOX<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name EDA_FV_HIERARCHY -entity <br />
set_instance_assignment -name EDA_FV_HIERARCHY -to -entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–16 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_GENERATE_FUNCTIONAL_NETLIST<br />
EDA_GENERATE_FUNCTIONAL_NETLIST<br />
Type<br />
Generates the Verilog or VHDL netlist for functional simulation with EDA simulation<br />
tools. The Standard Delay Format Output <strong>File</strong> (.sdo) is not generated for the project.<br />
This option is not available for the VCS MX simulation tool.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST -section_id<br />
<br />
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST -entity<br />
-section_id <br />
Default Value<br />
Off, requires section identifier<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–17<br />
EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT<br />
EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT<br />
Type<br />
Directs the EDA Netlist Writer to generate a command script to run gate-level<br />
simulation with a third-party EDA tool.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name<br />
EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT -section_id <br />
set_global_assignment -name<br />
EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT -entity -<br />
section_id <br />
Default Value<br />
Off, requires section identifier<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–18 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_GENERATE_POWER_INPUT_FILE<br />
EDA_GENERATE_POWER_INPUT_FILE<br />
Type<br />
Generates a Power Input <strong>File</strong> (.pwf) to perform power analysis in the <strong>Quartus</strong> <strong>II</strong><br />
software when using third-party simulation tools.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE -section_id<br />
<br />
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE -entity -section_id <br />
Default Value<br />
Off, requires section identifier<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–19<br />
EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT<br />
EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT<br />
Type<br />
Directs the EDA Netlist Writer to generate a command script to run RTL functional<br />
simulation with a third-party EDA tool.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT -<br />
section_id <br />
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT -<br />
entity -section_id <br />
Default Value<br />
Off, requires section identifier<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–20 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_GENERATE_TIMING_CLOSURE_DATA<br />
EDA_GENERATE_TIMING_CLOSURE_DATA<br />
Type<br />
Generates back-annotation data for performing in-place optimization with the<br />
LeonardoSpectrum software.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA -section_id<br />
<br />
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA -entity<br />
-section_id <br />
Default Value<br />
Off, requires section identifier<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–21<br />
EDA_IBIS_MODEL_SELECTOR<br />
EDA_IBIS_MODEL_SELECTOR<br />
Type<br />
Enable or disable model selector feature for IBIS Writer.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR -section_id <br />
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR -entity <br />
-section_id <br />
Default Value<br />
Off, requires section identifier<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–22 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_IBIS_MUTUAL_COUPLING<br />
EDA_IBIS_MUTUAL_COUPLING<br />
Type<br />
Allows you to print the per pin RLC package model with mutual coupling when<br />
generating IBIS Output <strong>File</strong>s (.ibs) with the EDA Netlist Writer. The lumped RLC<br />
package model information appears in the IBIS Output <strong>File</strong> (.ibs).<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING -section_id <br />
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING -entity <br />
-section_id <br />
Default Value<br />
Off, requires section identifier<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–23<br />
EDA_IBIS_SPECIFICATION_VERSION<br />
EDA_IBIS_SPECIFICATION_VERSION<br />
Type<br />
Specifies the IBIS Specification version.<br />
Enumeration<br />
■ 4p1<br />
■ 4p2<br />
■ 5p0<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION -section_id<br />
<br />
Default Value<br />
4p1, requires section identifier<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–24 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_IPFS_FILE<br />
EDA_IPFS_FILE<br />
Type<br />
Specifies the library to which IPFS file should be compiled.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDA_IPFS_FILE -section_id <br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–25<br />
EDA_LAUNCH_CMD_LINE_TOOL<br />
EDA_LAUNCH_CMD_LINE_TOOL<br />
Type<br />
Allows you to launch third-party EDA tools in the command-line mode rather than<br />
opening the graphical user interface.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL -section_id <br />
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL -entity <br />
-section_id <br />
Default Value<br />
Off, requires section identifier<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–26 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_MAINTAIN_DESIGN_HIERARCHY<br />
EDA_MAINTAIN_DESIGN_HIERARCHY<br />
Type<br />
Maintain the original user design hierarchy when generating Verilog or VHDL<br />
simulation netlist for the project.<br />
Enumeration<br />
■ OFF<br />
■ ON<br />
Device Support<br />
■ PARTITION_ONLY<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY -section_id<br />
<br />
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY -entity -section_id <br />
Default Value<br />
OFF, requires section identifier<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–27<br />
EDA_MAP_ILLEGAL_CHARACTERS<br />
EDA_MAP_ILLEGAL_CHARACTERS<br />
Type<br />
Maps the vertical bar (|), tilde (~), and colon (:) characters in <strong>Quartus</strong> <strong>II</strong> hierarchical<br />
node names to the legal Verilog HDL characters z, x, and underscore (_), respectively,<br />
in Verilog Output <strong>File</strong>s. Turning on this option also maps other illegal nonalphanumeric<br />
characters, including brackets [], parentheses, (), angle brackets , and<br />
braces {} to underscores (_).<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS -section_id<br />
<br />
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS -entity -section_id <br />
Default Value<br />
Off, requires section identifier<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–28 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_NATIVELINK_GENERATE_SCRIPT_ONLY<br />
EDA_NATIVELINK_GENERATE_SCRIPT_ONLY<br />
Type<br />
Allows you to generate the script for a third-party EDA tool without running the EDA<br />
tool.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY -<br />
section_id <br />
Default Value<br />
Off, requires section identifier<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–29<br />
EDA_NATIVELINK_PORTABLE_FILE_PATHS<br />
EDA_NATIVELINK_PORTABLE_FILE_PATHS<br />
Type<br />
Specifies that the file paths in the generated third-party EDA tool command scripts<br />
should be written out using relative paths for design and testbench files, and by using<br />
a variable to refer to <strong>Quartus</strong> <strong>II</strong> simulation library path.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS -section_id<br />
<br />
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS -entity<br />
-section_id <br />
Default Value<br />
Off, requires section identifier<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–30 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT<br />
EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT<br />
Type<br />
Specifies the script for EDA Tool. After compiling models, design files and test bench<br />
files, Native Link uses this script to set up the simulation.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT -<br />
section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–31<br />
EDA_NATIVELINK_SIMULATION_TEST_BENCH<br />
EDA_NATIVELINK_SIMULATION_TEST_BENCH<br />
Type<br />
Specifies the active logical name of the test bench, that will be used to perform<br />
NativeLink Simulation.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH -<br />
section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–32 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_NETLIST_WRITER_OUTPUT_DIR<br />
EDA_NETLIST_WRITER_OUTPUT_DIR<br />
Type<br />
Specifies the output directory for EDA Netlist Writer.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR -section_id<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–33<br />
EDA_RESYNTHESIS_TOOL<br />
EDA_RESYNTHESIS_TOOL<br />
Type<br />
Specifies the EDA tool used for resynthesis.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_RESYNTHESIS_TOOL <br />
set_global_assignment -name EDA_RESYNTHESIS_TOOL -entity <br />
<br />
Default Value<br />
None<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–34 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_RTL_SIMULATION_RUN_SCRIPT<br />
EDA_RTL_SIMULATION_RUN_SCRIPT<br />
Type<br />
Specifies the script file for performing RTL simulation using third-party simulation<br />
software.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDA_RTL_SIMULATION_RUN_SCRIPT -section_id<br />
<br />
set_global_assignment -name EDA_RTL_SIMULATION_RUN_SCRIPT -entity -section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–35<br />
EDA_RTL_SIM_MODE<br />
EDA_RTL_SIM_MODE<br />
Type<br />
Enables the Advanced Options—VHDL or Verilog Simulation options for Test Bench<br />
mode, or Command or macro mode.<br />
Enumeration<br />
■ COMMAND_MACRO_MODE<br />
■ NOT_USED<br />
Device Support<br />
■ TEST_BENCH_MODE<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name EDA_RTL_SIM_MODE -section_id <br />
set_global_assignment -name EDA_RTL_SIM_MODE -entity -<br />
section_id <br />
Default Value<br />
NOT_USED, requires section identifier<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–36 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_RTL_TEST_BENCH_FILE_NAME<br />
EDA_RTL_TEST_BENCH_FILE_NAME<br />
Type<br />
Specifies the RTL simulation test bench file name for Test Bench Mode. <strong>File</strong> type can<br />
be a VHDL Test Bench <strong>File</strong> (.vht), VHDL <strong>File</strong> (.vhd), Verilog HDL Test Bench <strong>File</strong> (.vt),<br />
or Verilog HDL file (.v).<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDA_RTL_TEST_BENCH_FILE_NAME -section_id<br />
<br />
set_global_assignment -name EDA_RTL_TEST_BENCH_FILE_NAME -entity -section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–37<br />
EDA_RTL_TEST_BENCH_NAME<br />
EDA_RTL_TEST_BENCH_NAME<br />
Type<br />
Specifies the name of top-level test bench in RTL simulation test bench file.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDA_RTL_TEST_BENCH_NAME -section_id <br />
set_global_assignment -name EDA_RTL_TEST_BENCH_NAME -entity <br />
-section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–38 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_RTL_TEST_BENCH_RUN_FOR<br />
EDA_RTL_TEST_BENCH_RUN_FOR<br />
Type<br />
Specifies the time duration for RTL simulation using third-party simulation.<br />
Time<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name EDA_RTL_TEST_BENCH_RUN_FOR -section_id<br />
<br />
set_global_assignment -name EDA_RTL_TEST_BENCH_RUN_FOR -entity -section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–39<br />
EDA_SDC_FILE_NAME<br />
EDA_SDC_FILE_NAME<br />
Type<br />
Name of Design Constraints file to be sourced in scripts generated for third party<br />
tools<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDA_SDC_FILE_NAME -section_id <br />
set_global_assignment -name EDA_SDC_FILE_NAME -entity -<br />
section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–40 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED<br />
EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLE<br />
D<br />
Type<br />
Disables setup and hold time violations detection in input registers of bi-directional<br />
pins.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name<br />
EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED -section_id<br />
<br />
Default Value<br />
Off, requires section identifier<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–41<br />
EDA_SIMULATION_RUN_SCRIPT<br />
EDA_SIMULATION_RUN_SCRIPT<br />
Type<br />
Specifies the script file for running a third-party simulation in Command/macro<br />
mode.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDA_SIMULATION_RUN_SCRIPT -section_id <br />
set_global_assignment -name EDA_SIMULATION_RUN_SCRIPT -entity -section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–42 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_SIMULATION_TOOL<br />
EDA_SIMULATION_TOOL<br />
Type<br />
Specifies the third-party EDA tool used for simulation.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_SIMULATION_TOOL <br />
set_global_assignment -name EDA_SIMULATION_TOOL -entity <br />
<br />
Default Value<br />
None<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–43<br />
EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE<br />
EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE<br />
Type<br />
Specifies which type of output signals should be written out to the Tcl file which can<br />
be used in a third-party EDA simulation tool to generate a Value Change Dump <strong>File</strong><br />
(.vcd). Writing out all output signals to the Tcl file may result in a very large Value<br />
Change Dump <strong>File</strong> (.vcd) being generated by the third-party simulation tool.<br />
Enumeration<br />
■ All<br />
Device Support<br />
■ All Except Combinational Logic Element Outputs<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE<br />
-section_id <br />
Default Value<br />
All Except Combinational Logic Element Outputs, requires section identifier<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–44 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_SIMULATION_VCD_OUTPUT_TCL_FILE<br />
EDA_SIMULATION_VCD_OUTPUT_TCL_FILE<br />
Type<br />
Specifies whether or not a Tcl file should be written out which can be used in a thirdparty<br />
EDA simulation tool to generate a Value Change Dump <strong>File</strong> (.vcd).<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE -section_id<br />
<br />
Default Value<br />
Off, requires section identifier<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–45<br />
EDA_SIMULATION_VCD_OUTPUT_TCL_FILE_NAME<br />
EDA_SIMULATION_VCD_OUTPUT_TCL_FILE_NAME<br />
Type<br />
Specifies the name the Tcl file should be written to which can be used in a third-party<br />
EDA simulation tool to generate a Value Change Dump <strong>File</strong> (.vcd).<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE_NAME -<br />
section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–46 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_TEST_BENCH_DESIGN_INSTANCE_NAME<br />
EDA_TEST_BENCH_DESIGN_INSTANCE_NAME<br />
Type<br />
Specifies the instance name of the design entity in the test bench file.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME -<br />
section_id <br />
set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME -entity<br />
-section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–47<br />
EDA_TEST_BENCH_ENABLE_STATUS<br />
EDA_TEST_BENCH_ENABLE_STATUS<br />
Type<br />
Enables the Advanced Options—VHDL or Verilog Simulation options for Test Bench<br />
mode or Command/macro mode.<br />
Enumeration<br />
■ COMMAND_MACRO_MODE<br />
■ NOT_USED<br />
Device Support<br />
■ TEST_BENCH_MODE<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS -section_id<br />
<br />
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS -entity -section_id <br />
Default Value<br />
NOT_USED, requires section identifier<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–48 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_TEST_BENCH_ENTITY_MODULE_NAME<br />
EDA_TEST_BENCH_ENTITY_MODULE_NAME<br />
Type<br />
Specifies the top-level design entity in the test bench file.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDA_TEST_BENCH_ENTITY_MODULE_NAME -section_id<br />
<br />
set_global_assignment -name EDA_TEST_BENCH_ENTITY_MODULE_NAME -entity<br />
-section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–49<br />
EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB<br />
EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB<br />
Type<br />
Directs NativeLink to add extra simulation libraries to the specified module. This is<br />
required by the memory controllers (both new and legacy).<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB -<br />
section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–50 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_TEST_BENCH_FILE<br />
EDA_TEST_BENCH_FILE<br />
Type<br />
Associates a test bench file with the logical test bench name.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDA_TEST_BENCH_FILE -section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–51<br />
EDA_TEST_BENCH_FILE_NAME<br />
EDA_TEST_BENCH_FILE_NAME<br />
Type<br />
Specifies the test bench file name for Test Bench Mode. <strong>File</strong> type can be a VHDL Test<br />
Bench <strong>File</strong> (.vht), Verilog HDL Test Bench <strong>File</strong> (.vt), or another design file type.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDA_TEST_BENCH_FILE_NAME -section_id <br />
set_global_assignment -name EDA_TEST_BENCH_FILE_NAME -entity <br />
-section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–52 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY<br />
EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY<br />
Type<br />
Specifies the simulation library to which the gate level netlist is compiled.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY -<br />
section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–53<br />
EDA_TEST_BENCH_MODULE_NAME<br />
EDA_TEST_BENCH_MODULE_NAME<br />
Type<br />
Associates a test bench file with the logical test bench name.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME -section_id<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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8–54 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_TEST_BENCH_NAME<br />
EDA_TEST_BENCH_NAME<br />
Type<br />
Defines a logical name for test bench. Each test bench logical name has associated<br />
section, containing test bench information, and section_id being the logical test bench<br />
name.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDA_TEST_BENCH_NAME -section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–55<br />
EDA_TEST_BENCH_RUN_FOR<br />
EDA_TEST_BENCH_RUN_FOR<br />
Type<br />
Specifies the simulation run time for a third-party simulation in test bench mode.<br />
Time<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name EDA_TEST_BENCH_RUN_FOR -section_id <br />
set_global_assignment -name EDA_TEST_BENCH_RUN_FOR -entity -<br />
section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–56 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_TEST_BENCH_RUN_SIM_FOR<br />
EDA_TEST_BENCH_RUN_SIM_FOR<br />
Type<br />
Specifies the time interval for running EDA Simulation.<br />
Time<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR -section_id<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–57<br />
EDA_TIME_SCALE<br />
EDA_TIME_SCALE<br />
Type<br />
Specifies the time unit used to represent timing delays in each Verilog Output <strong>File</strong><br />
(.vo). The value for the Time Scale option may be between 0.001 ns and 10ns, and<br />
should be a multiple of 10.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_TIME_SCALE -section_id <br />
set_global_assignment -name EDA_TIME_SCALE -entity -<br />
section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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8–58 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_TIMING_ANALYSIS_TOOL<br />
EDA_TIMING_ANALYSIS_TOOL<br />
Type<br />
Specifies the EDA third-party tool used for timing analysis.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL <br />
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL -entity <br />
<br />
Default Value<br />
None<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–59<br />
EDA_TRUNCATE_LONG_HIERARCHY_PATHS<br />
EDA_TRUNCATE_LONG_HIERARCHY_PATHS<br />
Type<br />
Truncates hierarchical node names to 80 characters.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS -section_id<br />
<br />
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS -entity<br />
-section_id <br />
Default Value<br />
Off, requires section identifier<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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8–60 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY<br />
EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY<br />
Type<br />
Specifies the directory in which you store the library generated with the EDA<br />
Simulation Library Compiler tool. You should not use this option to specify the<br />
directory for ModelSim-<strong>Altera</strong> precompiled libraries or Active-HDL precompiled<br />
libraries.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY<br />
-section_id <br />
Default Value<br />
None, requires section identifier<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–61<br />
EDA_VHDL_ARCH_NAME<br />
EDA_VHDL_ARCH_NAME<br />
Type<br />
Specifies the name of Architecture in the generated VHDL simulation netlist.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_VHDL_ARCH_NAME -section_id <br />
Default Value<br />
Structure, requires section identifier<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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8–62 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_WAIT_FOR_GUI_TOOL_COMPLETION<br />
EDA_WAIT_FOR_GUI_TOOL_COMPLETION<br />
Type<br />
Specifies that NativeLink should wait for the EDA tool GUI launched by it to finish.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION -section_id<br />
<br />
Default Value<br />
Off, requires section identifier<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–63<br />
EDA_WRITER_DONT_WRITE_TOP_ENTITY<br />
EDA_WRITER_DONT_WRITE_TOP_ENTITY<br />
Type<br />
Do not write top-level entity in VHDL Output <strong>File</strong> (.vho).<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY -section_id<br />
<br />
Default Value<br />
Off, requires section identifier<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–64 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_WRITE_DEVICE_CONTROL_PORTS<br />
EDA_WRITE_DEVICE_CONTROL_PORTS<br />
Type<br />
Adds the devpor, devclrn, and devoe signals in the design as input ports in the toplevel<br />
design hierarchy in the Verilog or VHDL simulation netlist for the project.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS -section_id<br />
<br />
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS -entity -section_id <br />
Default Value<br />
Off, requires section identifier<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 8: EDA Netlist Writer Assignments 8–65<br />
EDA_WRITE_NODES_FOR_POWER_ESTIMATION<br />
EDA_WRITE_NODES_FOR_POWER_ESTIMATION<br />
Type<br />
Writes the script for the simulation tool to generate a Value Change Dump <strong>File</strong> (.vcd)<br />
for outputs for power estimation.<br />
Enumeration<br />
■ ALL_NODES<br />
■ NO_COMBINATIONAL_OUTPUT<br />
■ Off<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION -<br />
section_id <br />
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION -entity<br />
-section_id <br />
Default Value<br />
Off, requires section identifier<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
8–66 Chapter 8: EDA Netlist Writer Assignments<br />
EDA_WRITE_NODES_FOR_POWER_ESTIMATION<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
ARRIA<strong>II</strong>GX_RX_CDR_LOCKUP_FIX_OVERRIDE<br />
Type<br />
© 2012 <strong>Altera</strong> Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos<br />
are trademarks of <strong>Altera</strong> Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as<br />
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. <strong>Altera</strong> warrants performance of its<br />
semiconductor products to current specifications in accordance with <strong>Altera</strong>'s standard warranty, but reserves the right to make changes to any products and<br />
services at any time without notice. <strong>Altera</strong> assumes no responsibility or liability arising out of the application or use of any information, product, or service<br />
described herein except as expressly agreed to in writing by <strong>Altera</strong>. <strong>Altera</strong> customers are advised to obtain the latest version of device specifications before relying<br />
on any published information and before placing orders for products or services.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong><br />
June 2012<br />
9. Assembler Assignments<br />
Allows signaldetect to propagate from PCS to the core, which will be blocked if you<br />
fix the CDR lockup issue. This is because a PMA direct route is unavailable in Arria <strong>II</strong><br />
GX devices.<br />
Boolean<br />
Device Support<br />
You can use this setting in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name ARRIA<strong>II</strong>GX_RX_CDR_LOCKUP_FIX_OVERRIDE <br />
set_instance_assignment -name ARRIA<strong>II</strong>GX_RX_CDR_LOCKUP_FIX_OVERRIDE -to<br />
<br />
Default Value<br />
Off<br />
ISO<br />
9001:2008<br />
Registered<br />
Subscribe
9–2 Chapter 9: Assembler Assignments<br />
AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE<br />
AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE<br />
Type<br />
Automatically increments the JTAG user code in the second and subsequent<br />
configuration devices if the target device requires multiple configuration devices.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ Stratix<br />
■ Stratix GX<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE<br />
<br />
Default Value<br />
On<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
AUTO_INCREMENT_USER_JTAG_CODE<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 9: Assembler Assignments 9–3<br />
AUTO_RESTART_CONFIGURATION<br />
AUTO_RESTART_CONFIGURATION<br />
Type<br />
Directs the device to restart the configuration process automatically if a data error is<br />
encountered. If this option is turned off, you must externally direct the device to<br />
restart the configuration process if an error occurs.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name AUTO_RESTART_CONFIGURATION <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
9–4 Chapter 9: Assembler Assignments<br />
AUTO_RESTART_CONFIGURATION<br />
Default Value<br />
On<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
Auto restart on configuration error<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 9: Assembler Assignments 9–5<br />
CLOCK_SOURCE<br />
CLOCK_SOURCE<br />
Type<br />
Specifies whether the configuration device generates an internal clock or applies an<br />
external clock.<br />
Enumeration<br />
■ External<br />
■ Internal<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name CLOCK_SOURCE <br />
Default Value<br />
Internal<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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9–6 Chapter 9: Assembler Assignments<br />
COMPRESSION_MODE<br />
COMPRESSION_MODE<br />
Type<br />
Allows you to compress SRAM Object <strong>File</strong>s (.sof) stored in a Programmer Object <strong>File</strong><br />
(.pof) for a configuration device.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name COMPRESSION_MODE <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 9: Assembler Assignments 9–7<br />
CONFIGURATION_CLOCK_DIVISOR<br />
CONFIGURATION_CLOCK_DIVISOR<br />
Type<br />
Specifies the clock frequency divisor, which is used to determine the period of the<br />
system clock.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR <br />
Default Value<br />
1<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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9–8 Chapter 9: Assembler Assignments<br />
CONFIGURATION_CLOCK_FREQUENCY<br />
CONFIGURATION_CLOCK_FREQUENCY<br />
Type<br />
Specifies the clock frequency of the configuration device.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY <br />
Default Value<br />
10 MHz<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 9: Assembler Assignments 9–9<br />
CYCLONE<strong>II</strong>I_CONFIGURATION_DEVICE<br />
CYCLONE<strong>II</strong>I_CONFIGURATION_DEVICE<br />
Type<br />
Specifies the configuration device that you want to use as the means of configuring<br />
the target device.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name CYCLONE<strong>II</strong>I_CONFIGURATION_DEVICE <br />
Default Value<br />
Auto<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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9–10 Chapter 9: Assembler Assignments<br />
CYCLONE<strong>II</strong>_M4K_COMPATIBILITY<br />
CYCLONE<strong>II</strong>_M4K_COMPATIBILITY<br />
Type<br />
Directs the <strong>Quartus</strong> <strong>II</strong> software to produce programming files that are compatible<br />
with both rev A and rev B silicon. This option applies only to the Cyclone <strong>II</strong> device<br />
family. For more information, refer to the Cyclone <strong>II</strong> FPGA Family Errata Sheet.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong><br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name CYCLONE<strong>II</strong>_M4K_COMPATIBILITY <br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 9: Assembler Assignments 9–11<br />
CYCLONE_CONFIGURATION_DEVICE<br />
CYCLONE_CONFIGURATION_DEVICE<br />
Type<br />
Specifies the configuration device that you want to use as the means of configuring<br />
the target Cyclone device.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE <br />
Default Value<br />
Auto<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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9–12 Chapter 9: Assembler Assignments<br />
DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE<br />
DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE<br />
Type<br />
Disables the nCS and OE internal pull-ups on the configuration device(s).<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix<br />
■ Stratix GX<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE<br />
<br />
Default Value<br />
Off<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
DISABLE_CONF_DONE_AND_NSTATUS_PULLUPS_ON_CONFIG_DEVICE<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 9: Assembler Assignments 9–13<br />
ENABLE_AUTONOMOUS_PCIE_HIP<br />
ENABLE_AUTONOMOUS_PCIE_HIP<br />
Type<br />
Directs the device to release the PCIe HIP after the periphery is configured and before<br />
core configuration is completed. This option only takes effect if CvP mode is disabled.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP <br />
Default Value<br />
Off<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
AUTO_RESTART_ON_CONFIGURATION_ERROR<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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9–14 Chapter 9: Assembler Assignments<br />
ENABLE_OCT_DONE<br />
ENABLE_OCT_DONE<br />
Type<br />
This option controls whether the INIT_DONE signal is gated by the OCT_DONE signal<br />
which indicates the Power-Up OCT calibration is completed. If this option is turned<br />
off, the INIT_DONE signal is not gated by the OCT_DONE signal.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name ENABLE_OCT_DONE <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 9: Assembler Assignments 9–15<br />
EPROM_USE_CHECKSUM_AS_USERCODE<br />
EPROM_USE_CHECKSUM_AS_USERCODE<br />
Type<br />
Uses the checksum value from the Programmer Object <strong>File</strong> (.pof) as the JTAG user<br />
code.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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9–16 Chapter 9: Assembler Assignments<br />
GENERATE_HEX_FILE<br />
GENERATE_HEX_FILE<br />
Type<br />
Generates a Hexadecimal (Intel-format) Output <strong>File</strong> (.hexout) containing<br />
configuration data that can be programmed into a parallel data source, such as an<br />
EPROM or a mass storage device, which then in turn configures the target device.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name GENERATE_HEX_FILE <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 9: Assembler Assignments 9–17<br />
GENERATE_RBF_FILE<br />
GENERATE_RBF_FILE<br />
Type<br />
Generates a Raw Binary <strong>File</strong> (.rbf) containing configuration data that an intelligent<br />
external controller can use to configure the target device.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name GENERATE_RBF_FILE <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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9–18 Chapter 9: Assembler Assignments<br />
GENERATE_TTF_FILE<br />
GENERATE_TTF_FILE<br />
Type<br />
Generates a Tabular Text <strong>File</strong> (.ttf) containing configuration data that an intelligent<br />
external controller can use to configure the target device.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name GENERATE_TTF_FILE <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 9: Assembler Assignments 9–19<br />
HARDCOPY<strong>II</strong>_POWER_ON_EXTRA_DELAY<br />
HARDCOPY<strong>II</strong>_POWER_ON_EXTRA_DELAY<br />
Type<br />
Directs the HardCopy chip to wait before the INIT_DONE pin goes high and before the<br />
chip is in user mode.<br />
Enumeration<br />
■ Off<br />
■ Wait 1 ms<br />
■ Wait 2 ms<br />
■ Wait 4 ms<br />
■ Wait 50 ms<br />
■ Wait 8 ms<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name HARDCOPY<strong>II</strong>_POWER_ON_EXTRA_DELAY <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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9–20 Chapter 9: Assembler Assignments<br />
HEXOUT_FILE_COUNT_DIRECTION<br />
HEXOUT_FILE_COUNT_DIRECTION<br />
Type<br />
Specifies the count direction for the data in a Hexadecimal (Intel-Format) Output <strong>File</strong><br />
(.hexout) as up or down.<br />
Enumeration<br />
■ Down<br />
■ Up<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION <br />
Default Value<br />
Up<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
HEX_FILE_COUNT_UP_DOWN<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 9: Assembler Assignments 9–21<br />
HEXOUT_FILE_START_ADDRESS<br />
HEXOUT_FILE_START_ADDRESS<br />
Type<br />
Specifies the starting memory address for a Hexadecimal (Intel-Format) Output <strong>File</strong><br />
(.hexout).<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name HEXOUT_FILE_START_ADDRESS <br />
Default Value<br />
0<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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9–22 Chapter 9: Assembler Assignments<br />
MAX7000S_JTAG_USER_CODE<br />
MAX7000S_JTAG_USER_CODE<br />
Type<br />
Specifies user-defined information about the target device. The JTAG user code is an<br />
extension of the option register. This data can be read with the JTAG USERCODE<br />
instruction.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX7000A<br />
■ MAX7000S<br />
Syntax<br />
set_global_assignment -name MAX7000S_JTAG_USER_CODE <br />
Default Value<br />
FFFF<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 9: Assembler Assignments 9–23<br />
MAX7000_JTAG_USER_CODE<br />
MAX7000_JTAG_USER_CODE<br />
Type<br />
Specifies user-defined information about the target device. The JTAG user code is an<br />
extension of the option register. This data can be read with the JTAG USERCODE<br />
instruction.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
Syntax<br />
set_global_assignment -name MAX7000_JTAG_USER_CODE <br />
Default Value<br />
FFFFFFFF<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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9–24 Chapter 9: Assembler Assignments<br />
MAX7000_USE_CHECKSUM_AS_USERCODE<br />
MAX7000_USE_CHECKSUM_AS_USERCODE<br />
Type<br />
Sets the JTAG user code to match the checksum value of the device programming file.<br />
The programming file is a Programmer Object <strong>File</strong> (.pof) for non-volatile devices,<br />
such as MAX <strong>II</strong> devices, or an SRAM Object <strong>File</strong> (.sof) for SRAM-based devices. If you<br />
turn this option on, the JTAG user code option is not available.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 9: Assembler Assignments 9–25<br />
ON_CHIP_BITSTREAM_DECOMPRESSION<br />
ON_CHIP_BITSTREAM_DECOMPRESSION<br />
Type<br />
Allows the device to accept and decompress bitstreams during configuration.<br />
Produces compressed bitstreams and enables bitstream decompression.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION <br />
Default Value<br />
On<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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9–26 Chapter 9: Assembler Assignments<br />
RELEASE_CLEARS_BEFORE_TRI_STATES<br />
RELEASE_CLEARS_BEFORE_TRI_STATES<br />
Type<br />
Directs the device to release the clear signal on registered logic cells and I/O cells<br />
before releasing the output enable override on tri-state buffers. If this option is turned<br />
off, the output enable signals are released before the clear overrides are released.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 9: Assembler Assignments 9–27<br />
RELEASE_CLEARS_BEFORE_TRI_STATES<br />
Default Value<br />
Off<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
Release clears before tri-states<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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9–28 Chapter 9: Assembler Assignments<br />
RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND<br />
RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND<br />
Type<br />
Reserves all unused pins on the target device in one of three states: as inputs that are<br />
tri-stated, or as outputs that drive an unspecified signal.<br />
Enumeration<br />
Device Support<br />
■ As input tri-stated<br />
■ As output driving an unspecified signal<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000S<br />
Syntax<br />
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND <br />
Default Value<br />
As output driving an unspecified signal<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
RESERVED_ALL_UNUSED_PINS_NO_OUTPUT_GND<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 9: Assembler Assignments 9–29<br />
SECURITY_BIT<br />
SECURITY_BIT<br />
Type<br />
Enables the security bit support, which prevents a device from being examined and<br />
reprogrammed.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name SECURITY_BIT <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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9–30 Chapter 9: Assembler Assignments<br />
STRATIX<strong>II</strong>_CONFIGURATION_DEVICE<br />
STRATIX<strong>II</strong>_CONFIGURATION_DEVICE<br />
Type<br />
Specifies the configuration device that you want to use as the means of configuring<br />
the target device.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name STRATIX<strong>II</strong>_CONFIGURATION_DEVICE <br />
Default Value<br />
Auto<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
STRATIX_<strong>II</strong>_CONFIGURATION_DEVICE<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 9: Assembler Assignments 9–31<br />
STRATIX<strong>II</strong>_MRAM_COMPATIBILITY<br />
STRATIX<strong>II</strong>_MRAM_COMPATIBILITY<br />
Directs the <strong>Quartus</strong> <strong>II</strong> software to produce programming files that are compatible with both rev A and<br />
rev B silicon. This option applies only to EP2S30, EP2S90, EP2S130, EP2S180. For more information, refer to<br />
the Stratix <strong>II</strong> FPGA Family Errata Sheet.<br />
Boolean<br />
Type<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Stratix <strong>II</strong><br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name STRATIX<strong>II</strong>_MRAM_COMPATIBILITY <br />
Default Value<br />
Off<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
STRATIX<strong>II</strong>_SILICON_VERSION<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
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9–32 Chapter 9: Assembler Assignments<br />
STRATIX_CONFIGURATION_DEVICE<br />
STRATIX_CONFIGURATION_DEVICE<br />
Type<br />
Specifies the configuration device that you want to use as the means of configuring<br />
the target device.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE <br />
Default Value<br />
Auto<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
YEAGER_CONFIGURATION_DEVICE<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 9: Assembler Assignments 9–33<br />
STRATIX_CONFIG_DEVICE_JTAG_USER_CODE<br />
STRATIX_CONFIG_DEVICE_JTAG_USER_CODE<br />
Type<br />
Specifies user-defined information about the configuration device. The JTAG user<br />
code is an extension of the option register. This data can be read with the JTAG<br />
USERCODE instruction.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE <br />
Default Value<br />
FFFFFFFF<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
9–34 Chapter 9: Assembler Assignments<br />
STRATIX_JTAG_USER_CODE<br />
STRATIX_JTAG_USER_CODE<br />
Type<br />
Specifies user-defined information about the target device. The JTAG user code is an<br />
extension of the option register. This data can be read with the JTAG USERCODE<br />
instruction.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name STRATIX_JTAG_USER_CODE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 9: Assembler Assignments 9–35<br />
STRATIX_JTAG_USER_CODE<br />
Default Value<br />
FFFFFFFF<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
9–36 Chapter 9: Assembler Assignments<br />
USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT<br />
USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT<br />
Type<br />
Loads a checkered pattern as initial RAM content into all RAM blocks without<br />
specified RAM content that supports content initialization. Turning on this option<br />
does not affect simulation, which may cause on-chip behavior to differ from<br />
simulation results.<br />
Enumeration<br />
■ 0000<br />
■ 0101<br />
■ 1010<br />
■ 1111<br />
■ OFF<br />
■ ON<br />
■ RANDOM<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone V<br />
■ Stratix<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name<br />
USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT <br />
Default Value<br />
OFF<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 9: Assembler Assignments 9–37<br />
USE_CHECKSUM_AS_USERCODE<br />
USE_CHECKSUM_AS_USERCODE<br />
Type<br />
Sets the JTAG user code to match the checksum value of the device programming file.<br />
The programming file is a Programmer Object <strong>File</strong> (.pof) for non-volatile devices,<br />
such as MAX <strong>II</strong> devices, or an SRAM Object <strong>File</strong> (.sof) for SRAM-based devices. If you<br />
turn this option on, the JTAG user code option is not available.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
9–38 Chapter 9: Assembler Assignments<br />
USE_CHECKSUM_AS_USERCODE<br />
Syntax<br />
set_global_assignment -name USE_CHECKSUM_AS_USERCODE <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 9: Assembler Assignments 9–39<br />
USE_CONFIGURATION_DEVICE<br />
USE_CONFIGURATION_DEVICE<br />
Type<br />
Specifies that you intend to use a configuration device(s) such as the EPC2 as the<br />
means of configuring the target device. This option directs the Compiler to create a<br />
Programmer Output <strong>File</strong> (.pof) for programming the configuration device. If multiple<br />
configuration devices are needed, one Programmer Output <strong>File</strong> (.pof) is created for<br />
each device, with names of the following format: name.pof, name_1.pof, name_2.pof,<br />
and so on.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ EPC1<br />
■ EPC2<br />
■ Enhanced Configuration Devices<br />
■ FLEX10KB<br />
■ FLEX8000<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
9–40 Chapter 9: Assembler Assignments<br />
USE_CONFIGURATION_DEVICE<br />
■ MAX9000<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name USE_CONFIGURATION_DEVICE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
ACLK_CAT<br />
Type<br />
© 2012 <strong>Altera</strong> Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos<br />
are trademarks of <strong>Altera</strong> Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as<br />
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. <strong>Altera</strong> warrants performance of its<br />
semiconductor products to current specifications in accordance with <strong>Altera</strong>'s standard warranty, but reserves the right to make changes to any products and<br />
services at any time without notice. <strong>Altera</strong> assumes no responsibility or liability arising out of the application or use of any information, product, or service<br />
described herein except as expressly agreed to in writing by <strong>Altera</strong>. <strong>Altera</strong> customers are advised to obtain the latest version of device specifications before relying<br />
on any published information and before placing orders for products or services.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong><br />
June 2012<br />
10. Design Assistant Assignments<br />
Directs the Design Assistant to detect asynchronous clock domains on the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name ACLK_CAT <br />
ISO<br />
9001:2008<br />
Registered<br />
Subscribe
10–2 Chapter 10: Design Assistant Assignments<br />
ACLK_RULE_IMSZER_ADOMAIN<br />
ACLK_RULE_IMSZER_ADOMAIN<br />
Type<br />
Directs the Design Assistant to detect improper synchronizer which moves data<br />
across asynchronous domain boundaries on the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–3<br />
ACLK_RULE_NO_SZER_ACLK_DOMAIN<br />
ACLK_RULE_NO_SZER_ACLK_DOMAIN<br />
Type<br />
Directs the Design Assistant to detect synchronizer between asynchronous clock<br />
domains on the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–4 Chapter 10: Design Assistant Assignments<br />
ACLK_RULE_SZER_BTW_ACLK_DOMAIN<br />
ACLK_RULE_SZER_BTW_ACLK_DOMAIN<br />
Type<br />
Directs the Design Assistant to detect synchronizer for every signal between<br />
asynchronous clock domains on the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–5<br />
CLK_CAT<br />
CLK_CAT<br />
Type<br />
Directs the Design Assistant to check all clock-related violations on the design.<br />
Expand the items to turn off the rule checking if irrelevant.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name CLK_CAT <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–6 Chapter 10: Design Assistant Assignments<br />
CLK_RULE_CLKNET_CLKSPINES<br />
CLK_RULE_CLKNET_CLKSPINES<br />
Type<br />
Directs the Design Assistant to check clock net not mapped to clock spines used on the<br />
design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–7<br />
CLK_RULE_CLKNET_CLKSPINES_THRESHOLD<br />
CLK_RULE_CLKNET_CLKSPINES_THRESHOLD<br />
Type<br />
Specifies the Threshold value for clock net not mapped to clock spines rule.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD <br />
Default Value<br />
25<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–8 Chapter 10: Design Assistant Assignments<br />
CLK_RULE_COMB_CLOCK<br />
CLK_RULE_COMB_CLOCK<br />
Type<br />
Directs the Design Assistant to check combinatorial logic output used as on-chip clock<br />
on the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name CLK_RULE_COMB_CLOCK <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–9<br />
CLK_RULE_GATED_CLK_FANOUT<br />
CLK_RULE_GATED_CLK_FANOUT<br />
Type<br />
Directs the Design Assistant to check gated clock have feed to certain number of clock<br />
port to effectively save power.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name CLK_RULE_GATED_CLK_FANOUT <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–10 Chapter 10: Design Assistant Assignments<br />
CLK_RULE_INPINS_CLKNET<br />
CLK_RULE_INPINS_CLKNET<br />
Type<br />
Directs the Design Assistant to check illegal input pins connected to clock net used on<br />
the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name CLK_RULE_INPINS_CLKNET <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–11<br />
CLK_RULE_INV_CLOCK<br />
CLK_RULE_INV_CLOCK<br />
Type<br />
Directs the Design Assistant to check inverted clock used on the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name CLK_RULE_INV_CLOCK <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–12 Chapter 10: Design Assistant Assignments<br />
CLK_RULE_MIX_EDGES<br />
CLK_RULE_MIX_EDGES<br />
Type<br />
Directs the Design Assistant to check mixed-clock edges used on the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name CLK_RULE_MIX_EDGES <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–13<br />
DA_CUSTOM_RULE_FILE<br />
DA_CUSTOM_RULE_FILE<br />
Type<br />
Sets the path for the Design Assistant custom rule file.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name DA_CUSTOM_RULE_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–14 Chapter 10: Design Assistant Assignments<br />
DISABLE_DA_GX_RULE<br />
DISABLE_DA_GX_RULE<br />
Type<br />
Prevents Design Assistant from running when the Fitter is running.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name DISABLE_DA_GX_RULE <br />
set_instance_assignment -name DISABLE_DA_GX_RULE -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–15<br />
DISABLE_DA_RULE<br />
DISABLE_DA_RULE<br />
Type<br />
Suppresses the Design Assistant rule locally, or turns off the Design Assistant rule<br />
globally for the general user<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name DISABLE_DA_RULE <br />
set_instance_assignment -name DISABLE_DA_RULE -to -entity <br />
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<strong>Reference</strong> <strong>Manual</strong>
10–16 Chapter 10: Design Assistant Assignments<br />
DRC_DEADLOCK_STATE_LIMIT<br />
DRC_DEADLOCK_STATE_LIMIT<br />
Type<br />
Specifies the maximum number of states that you want the Design Assistant to detect<br />
as a deadlock condition. A larger number results in longer processing time.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT <br />
Default Value<br />
2<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–17<br />
DRC_DETAIL_MESSAGE_LIMIT<br />
DRC_DETAIL_MESSAGE_LIMIT<br />
Type<br />
Specifies the maximum number of detail messages that you want the Design Assistant<br />
to report.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT <br />
Default Value<br />
10<br />
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<strong>Reference</strong> <strong>Manual</strong>
10–18 Chapter 10: Design Assistant Assignments<br />
DRC_FANOUT_EXCEEDING<br />
DRC_FANOUT_EXCEEDING<br />
Type<br />
Specifies the minimum amount of fan-out that a node must have to be reported by the<br />
Design Assistant.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name DRC_FANOUT_EXCEEDING <br />
Default Value<br />
30<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–19<br />
DRC_GATED_CLOCK_FEED<br />
DRC_GATED_CLOCK_FEED<br />
Type<br />
Specifies the minimum amount of clock port a gated clock must feed so that it's an<br />
acceptable gated clock.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name DRC_GATED_CLOCK_FEED <br />
Default Value<br />
30<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–20 Chapter 10: Design Assistant Assignments<br />
DRC_REPORT_FANOUT_EXCEEDING<br />
DRC_REPORT_FANOUT_EXCEEDING<br />
Type<br />
Directs the Design Assistant to report all nodes with more than the specified amount<br />
of fan-out.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–21<br />
DRC_REPORT_TOP_FANOUT<br />
DRC_REPORT_TOP_FANOUT<br />
Type<br />
Directs the Design Assistant to report the specified number of nodes with the highest<br />
fan-out.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name DRC_REPORT_TOP_FANOUT <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–22 Chapter 10: Design Assistant Assignments<br />
DRC_TOP_FANOUT<br />
DRC_TOP_FANOUT<br />
Type<br />
Specifies the number of nodes with the highest fan-out that you want the Design<br />
Assistant to report.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name DRC_TOP_FANOUT <br />
Default Value<br />
50<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–23<br />
DRC_VIOLATION_MESSAGE_LIMIT<br />
DRC_VIOLATION_MESSAGE_LIMIT<br />
Type<br />
Specifies the maximum number of violation messages that you want the Design<br />
Assistant to report.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT <br />
Default Value<br />
30<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–24 Chapter 10: Design Assistant Assignments<br />
ENABLE_DA_RULE<br />
ENABLE_DA_RULE<br />
Type<br />
Desuppresses the Design Assistant rule locally, or turns on the Design Assistant rule<br />
globally for the general user.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name ENABLE_DA_RULE <br />
set_instance_assignment -name ENABLE_DA_RULE -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–25<br />
ENABLE_DRC_SETTINGS<br />
ENABLE_DRC_SETTINGS<br />
Type<br />
Directs the Design Assistant to run during a compilation based on user settings.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name ENABLE_DRC_SETTINGS <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–26 Chapter 10: Design Assistant Assignments<br />
FSM_CAT<br />
FSM_CAT<br />
Type<br />
Directs the Design Assistant to detect finite state machine rules in your design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name FSM_CAT <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–27<br />
FSM_RULE_DEADLOCK_STATE<br />
FSM_RULE_DEADLOCK_STATE<br />
Type<br />
Directs the Design Assistant to detect deadlock states in state machine in your design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name FSM_RULE_DEADLOCK_STATE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–28 Chapter 10: Design Assistant Assignments<br />
FSM_RULE_NO_RESET_STATE<br />
FSM_RULE_NO_RESET_STATE<br />
Type<br />
Directs the Design Assistant to detect if the reset state is specified for the state<br />
machine in your design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name FSM_RULE_NO_RESET_STATE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–29<br />
FSM_RULE_NO_SZER_ACLK_DOMAIN<br />
FSM_RULE_NO_SZER_ACLK_DOMAIN<br />
Type<br />
Directs the Design Assistant to detect the synchronizer between asynchronous clock<br />
domains feeding to the state machine in your design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name FSM_RULE_NO_SZER_ACLK_DOMAIN <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–30 Chapter 10: Design Assistant Assignments<br />
FSM_RULE_UNREACHABLE_STATE<br />
FSM_RULE_UNREACHABLE_STATE<br />
Type<br />
Directs the Design Assistant to detect an unreachable state in the state machine in<br />
your design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name FSM_RULE_UNREACHABLE_STATE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–31<br />
FSM_RULE_UNUSED_TRANSITION<br />
FSM_RULE_UNUSED_TRANSITION<br />
Type<br />
Directs the Design Assistant to detect an unused transition in the state machine in<br />
your design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name FSM_RULE_UNUSED_TRANSITION <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–32 Chapter 10: Design Assistant Assignments<br />
HARDCOPY_FLOW_AUTOMATION<br />
HARDCOPY_FLOW_AUTOMATION<br />
Type<br />
Specifies which HardCopy flow is run in the HardCopy timing wizard<br />
Enumeration<br />
Device Support<br />
■ COMPILE_NEW_PROJECT<br />
■ FULL_COMPILATION<br />
■ MIGRATION_ONLY<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION <br />
Default Value<br />
MIGRATION_ONLY<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–33<br />
HARDCOPY_NEW_PROJECT_PATH<br />
HARDCOPY_NEW_PROJECT_PATH<br />
Type<br />
Specifies the directory path for the new or migrated HardCopy project.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name HARDCOPY_NEW_PROJECT_PATH <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–34 Chapter 10: Design Assistant Assignments<br />
HCPY_CAT<br />
HCPY_CAT<br />
Type<br />
Directs the Design Assistant to detect HardCopy rules in your design. All HardCopy<br />
rules apply to HardCopy devices only.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name HCPY_CAT <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–35<br />
NONSYNCHSTRUCT_CAT<br />
NONSYNCHSTRUCT_CAT<br />
Type<br />
Directs the Design Assistant to check for non-synchronous design structures on the<br />
design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name NONSYNCHSTRUCT_CAT <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–36 Chapter 10: Design Assistant Assignments<br />
NONSYNCHSTRUCT_RULE_COMBLOOP<br />
NONSYNCHSTRUCT_RULE_COMBLOOP<br />
Type<br />
Directs the Design Assistant to check for combinatorial loop with unidentified<br />
function on the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–37<br />
NONSYNCHSTRUCT_RULE_DELAY_CHAIN<br />
NONSYNCHSTRUCT_RULE_DELAY_CHAIN<br />
Type<br />
Directs the Design Assistant to check for delay chain with unidentified function on<br />
the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–38 Chapter 10: Design Assistant Assignments<br />
NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN<br />
NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN<br />
Type<br />
Directs the Design Assistant to check illegal pulse generator on the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–39<br />
NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED<br />
NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED<br />
Type<br />
Directs the Design Assistant to detect latch of unidentified type on the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–40 Chapter 10: Design Assistant Assignments<br />
NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR<br />
NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR<br />
Type<br />
Directs the Design Assistant to check multi-vibrator on the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–41<br />
NONSYNCHSTRUCT_RULE_REG_LOOP<br />
NONSYNCHSTRUCT_RULE_REG_LOOP<br />
Type<br />
Directs the Design Assistant to check for combinatorial loop with output of register<br />
feeding its own control signal on the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–42 Chapter 10: Design Assistant Assignments<br />
NONSYNCHSTRUCT_RULE_RIPPLE_CLK<br />
NONSYNCHSTRUCT_RULE_RIPPLE_CLK<br />
Type<br />
Directs the Design Assistant to check ripple clock structure on the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–43<br />
NONSYNCHSTRUCT_RULE_SRLATCH<br />
NONSYNCHSTRUCT_RULE_SRLATCH<br />
Type<br />
Directs the Design Assistant to detect SR-latch on the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–44 Chapter 10: Design Assistant Assignments<br />
RESET_CAT<br />
RESET_CAT<br />
Type<br />
Directs the Design Assistant to check reset-related violations on the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name RESET_CAT <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–45<br />
RESET_RULE_COMB_ASYNCH_RESET<br />
RESET_RULE_COMB_ASYNCH_RESET<br />
Type<br />
Directs the Design Assistant to check combinatorial logic output used as on-chip<br />
asynchronous reset on the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–46 Chapter 10: Design Assistant Assignments<br />
RESET_RULE_IMSYNCH_ASYNCH_DOMAIN<br />
RESET_RULE_IMSYNCH_ASYNCH_DOMAIN<br />
Type<br />
Directs the Design Assistant to check for reset which is improperly synchronized in<br />
receiving asynchronous domain on the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–47<br />
RESET_RULE_IMSYNCH_EXRESET<br />
RESET_RULE_IMSYNCH_EXRESET<br />
Type<br />
Directs the Design Assistant to check improper synchronization of external reset on<br />
the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–48 Chapter 10: Design Assistant Assignments<br />
RESET_RULE_UNSYNCH_ASYNCH_DOMAIN<br />
RESET_RULE_UNSYNCH_ASYNCH_DOMAIN<br />
Type<br />
Directs the Design Assistant to check for reset which is not synchronized in receiving<br />
asynchronous domain on the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–49<br />
RESET_RULE_UNSYNCH_EXRESET<br />
RESET_RULE_UNSYNCH_EXRESET<br />
Type<br />
Suppresses unsynchronized external reset rule.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–50 Chapter 10: Design Assistant Assignments<br />
SIGNALRACE_CAT<br />
SIGNALRACE_CAT<br />
Type<br />
Directs the Design Assistant to check signal race on the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name SIGNALRACE_CAT <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–51<br />
SIGNALRACE_RULE_CLK_PORT_RACE<br />
SIGNALRACE_RULE_CLK_PORT_RACE<br />
Type<br />
Directs the Design Assistant to check race condition between clock port and any other<br />
port of the same register.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name SIGNALRACE_RULE_CLK_PORT_RACE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–52 Chapter 10: Design Assistant Assignments<br />
SIGNALRACE_RULE_RESET_RACE<br />
SIGNALRACE_RULE_RESET_RACE<br />
Type<br />
Directs the Design Assistant to detect synchronous port and asynchronous port of<br />
same register driven by same signal source<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name SIGNALRACE_RULE_RESET_RACE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–53<br />
SIGNALRACE_RULE_SECOND_SIGNAL_RACE<br />
SIGNALRACE_RULE_SECOND_SIGNAL_RACE<br />
Type<br />
Directs the Design Assistant to detect more than one secondary signal of same register<br />
driven by same signal source<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name SIGNALRACE_RULE_SECOND_SIGNAL_RACE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–54 Chapter 10: Design Assistant Assignments<br />
SIGNALRACE_RULE_TRISTATE<br />
SIGNALRACE_RULE_TRISTATE<br />
Type<br />
Directs the Design Assistant to detect Tri-state signal race condition.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name SIGNALRACE_RULE_TRISTATE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 10: Design Assistant Assignments 10–55<br />
TIMING_CAT<br />
TIMING_CAT<br />
Type<br />
Directs the Design Assistant to check timing closure related violations on the design.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Cyclone<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
Syntax<br />
set_global_assignment -name TIMING_CAT <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
10–56 Chapter 10: Design Assistant Assignments<br />
TIMING_CAT<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
EXCALIBUR_HEX_FILE<br />
Type<br />
© 2012 <strong>Altera</strong> Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos<br />
are trademarks of <strong>Altera</strong> Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as<br />
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. <strong>Altera</strong> warrants performance of its<br />
semiconductor products to current specifications in accordance with <strong>Altera</strong>'s standard warranty, but reserves the right to make changes to any products and<br />
services at any time without notice. <strong>Altera</strong> assumes no responsibility or liability arising out of the application or use of any information, product, or service<br />
described herein except as expressly agreed to in writing by <strong>Altera</strong>. <strong>Altera</strong> customers are advised to obtain the latest version of device specifications before relying<br />
on any published information and before placing orders for products or services.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong><br />
June 2012<br />
11. Programmer Assignments<br />
Specifies the Hexadecimal (Intel-Format) <strong>File</strong> (.hex) to be used with the e<br />
Programmable Logic Partial SRAM Object <strong>File</strong> (.psof) to generate passive<br />
programming files.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name EXCALIBUR_HEX_FILE <br />
ISO<br />
9001:2008<br />
Registered<br />
Subscribe
11–2 Chapter 11: Programmer Assignments<br />
GENERATE_CONFIG_HEXOUT_FILE<br />
GENERATE_CONFIG_HEXOUT_FILE<br />
Type<br />
Generates a Hexadecimal (Intel-format) Output <strong>File</strong> (.hexout) containing<br />
configuration data that can be programmed into a parallel data source, such as an<br />
EPROM or a mass storage device, which then in turn configures the target device.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Enhanced Configuration Devices<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 11: Programmer Assignments 11–3<br />
GENERATE_CONFIG_ISC_FILE<br />
GENERATE_CONFIG_ISC_FILE<br />
Type<br />
Generates an In System Configuration <strong>File</strong> (.isc) containing configuration data that an<br />
intelligent external controller can use to configure the target device.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Enhanced Configuration Devices<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name GENERATE_CONFIG_ISC_FILE <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
11–4 Chapter 11: Programmer Assignments<br />
GENERATE_CONFIG_JAM_FILE<br />
GENERATE_CONFIG_JAM_FILE<br />
Type<br />
Generates a JEDEC STAPL Format <strong>File</strong> (.jam) containing configuration data that an<br />
intelligent external controller can use to configure the target device.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ EPC2<br />
■ Enhanced Configuration Devices<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name GENERATE_CONFIG_JAM_FILE <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 11: Programmer Assignments 11–5<br />
GENERATE_CONFIG_JBC_FILE<br />
GENERATE_CONFIG_JBC_FILE<br />
Type<br />
Directs the programmer to generate a compressed JAM Byte Code <strong>File</strong> (.jbc)<br />
containing configuration data that an intelligent external controller can use to<br />
configure the target device.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ EPC2<br />
■ Enhanced Configuration Devices<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name GENERATE_CONFIG_JBC_FILE <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
11–6 Chapter 11: Programmer Assignments<br />
GENERATE_CONFIG_JBC_FILE_COMPRESSED<br />
GENERATE_CONFIG_JBC_FILE_COMPRESSED<br />
Type<br />
Directs the programmer to generate a compressed JAM Byte Codec <strong>File</strong> (.jbc)<br />
containing configuration data that an intelligent external controller can use to<br />
configure the target device.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ EPC2<br />
■ Enhanced Configuration Devices<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED <br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 11: Programmer Assignments 11–7<br />
GENERATE_CONFIG_SVF_FILE<br />
GENERATE_CONFIG_SVF_FILE<br />
Type<br />
Generates a Serial Vector Format <strong>File</strong> (.svf) containing configuration data that an<br />
intelligent external controller can use to configure the target device.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ EPC2<br />
■ Enhanced Configuration Devices<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name GENERATE_CONFIG_SVF_FILE <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
11–8 Chapter 11: Programmer Assignments<br />
GENERATE_ISC_FILE<br />
GENERATE_ISC_FILE<br />
Type<br />
Directs the programmer to generate an In System Configuration <strong>File</strong> (.isc) containing<br />
configuration data that an intelligent external controller can use to configure the<br />
target device.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX3000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
Notes<br />
This assignment is included in the Assembler report.<br />
Syntax<br />
set_global_assignment -name GENERATE_ISC_FILE <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 11: Programmer Assignments 11–9<br />
GENERATE_JAM_FILE<br />
GENERATE_JAM_FILE<br />
Type<br />
Directs the programmer to generate a JEDEC JESD71 STAPL Format <strong>File</strong> (.jam)<br />
containing configuration data that an intelligent external controller can use to<br />
configure the target device.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
11–10 Chapter 11: Programmer Assignments<br />
GENERATE_JAM_FILE<br />
Notes<br />
This assignment is included in the Assembler report.<br />
Syntax<br />
set_global_assignment -name GENERATE_JAM_FILE <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 11: Programmer Assignments 11–11<br />
GENERATE_JBC_FILE<br />
GENERATE_JBC_FILE<br />
Type<br />
Directs the programmer to generate a compressed JAM Byte Code <strong>File</strong> (.jbc)<br />
containing configuration data that an intelligent external controller can use to<br />
configure the target device.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
11–12 Chapter 11: Programmer Assignments<br />
GENERATE_JBC_FILE<br />
Notes<br />
This assignment is included in the Assembler report.<br />
Syntax<br />
set_global_assignment -name GENERATE_JBC_FILE <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 11: Programmer Assignments 11–13<br />
GENERATE_JBC_FILE_COMPRESSED<br />
GENERATE_JBC_FILE_COMPRESSED<br />
Type<br />
Generates a compressed JAM Byte Code <strong>File</strong> (.jbc) containing configuration data that<br />
an intelligent external controller can use to configure the target device.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
11–14 Chapter 11: Programmer Assignments<br />
GENERATE_JBC_FILE_COMPRESSED<br />
Notes<br />
This assignment is included in the Assembler report.<br />
Syntax<br />
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED <br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 11: Programmer Assignments 11–15<br />
GENERATE_SVF_FILE<br />
GENERATE_SVF_FILE<br />
Type<br />
Directs the programmer to generate a Serial Vector Format <strong>File</strong> (.svf) containing<br />
configuration data that an intelligent external controller can use to configure the<br />
target device.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
11–16 Chapter 11: Programmer Assignments<br />
GENERATE_SVF_FILE<br />
Notes<br />
This assignment is included in the Assembler report.<br />
Syntax<br />
set_global_assignment -name GENERATE_SVF_FILE <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 11: Programmer Assignments 11–17<br />
ISP_CLAMP_STATE<br />
ISP_CLAMP_STATE<br />
Type<br />
Specifies the pin state during in-system programming. This option is ignored if it is<br />
assigned to anything other than pins.<br />
Enumeration<br />
■ High<br />
■ Low<br />
■ Sample and Sustain<br />
■ Tri-state<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX7000B<br />
Syntax<br />
set_instance_assignment -name ISP_CLAMP_STATE -to -entity <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
11–18 Chapter 11: Programmer Assignments<br />
ISP_CLAMP_STATE_DEFAULT<br />
ISP_CLAMP_STATE_DEFAULT<br />
Type<br />
For used pins that do not have an in-system programming clamp state assignment,<br />
this option allows you to specify the state that the pins take during in-system<br />
programming. Unused pins and dedicated inputs must always be tri-stated for insystem<br />
programming.<br />
Enumeration<br />
■ High<br />
■ Low<br />
■ Sample and Sustain<br />
■ Tri-state<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX7000B<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT <br />
Default Value<br />
Tri-state<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 11: Programmer Assignments 11–19<br />
MERGE_HEX_FILE<br />
MERGE_HEX_FILE<br />
Type<br />
Uses the Hexadecimal (Intel-Format) <strong>File</strong> (.hex) and the programmable logic Partial<br />
SRAM Object <strong>File</strong> (.psof) to create passive programming files.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name MERGE_HEX_FILE <br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
11–20 Chapter 11: Programmer Assignments<br />
MERGE_HEX_FILE<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
ENABLE_LOGIC_ANALYZER_INTERFACE<br />
Type<br />
© 2012 <strong>Altera</strong> Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos<br />
are trademarks of <strong>Altera</strong> Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as<br />
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. <strong>Altera</strong> warrants performance of its<br />
semiconductor products to current specifications in accordance with <strong>Altera</strong>'s standard warranty, but reserves the right to make changes to any products and<br />
services at any time without notice. <strong>Altera</strong> assumes no responsibility or liability arising out of the application or use of any information, product, or service<br />
described herein except as expressly agreed to in writing by <strong>Altera</strong>. <strong>Altera</strong> customers are advised to obtain the latest version of device specifications before relying<br />
on any published information and before placing orders for products or services.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong><br />
June 2012<br />
Enables the Logic Analyzer Interface for compilation.<br />
Boolean<br />
Device Support<br />
12. SignalTap <strong>II</strong> Assignments<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name ENABLE_LOGIC_ANALYZER_INTERFACE <br />
ISO<br />
9001:2008<br />
Registered<br />
Subscribe
12–2 Chapter 12: SignalTap <strong>II</strong> Assignments<br />
ENABLE_SIGNALTAP<br />
ENABLE_SIGNALTAP<br />
Type<br />
Enables the SignalTap <strong>II</strong> Logic Analyzer for compilation.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name ENABLE_SIGNALTAP <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 12: SignalTap <strong>II</strong> Assignments 12–3<br />
STP_FILE<br />
STP_FILE<br />
Type<br />
Associates a SignalTap <strong>II</strong> Logic Analyzer <strong>File</strong> with this project.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name STP_FILE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
12–4 Chapter 12: SignalTap <strong>II</strong> Assignments<br />
USE_LOGIC_ANALYZER_INTERFACE_FILE<br />
USE_LOGIC_ANALYZER_INTERFACE_FILE<br />
Type<br />
Specifies the Logic Analyzer Interface <strong>File</strong> (.lai) to be used for compilation.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name USE_LOGIC_ANALYZER_INTERFACE_FILE <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 12: SignalTap <strong>II</strong> Assignments 12–5<br />
USE_SIGNALTAP_FILE<br />
USE_SIGNALTAP_FILE<br />
Type<br />
Specifies the SignalTap <strong>II</strong> Logic Analyzer <strong>File</strong> to be used for compilation.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
C<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name USE_SIGNALTAP_FILE <br />
SignalTap <strong>II</strong> Assignments<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
12–6 Chapter 12: SignalTap <strong>II</strong> Assignments<br />
USE_SIGNALTAP_FILE<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
LL_AUTO_SIZE<br />
Type<br />
© 2012 <strong>Altera</strong> Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos<br />
are trademarks of <strong>Altera</strong> Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as<br />
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. <strong>Altera</strong> warrants performance of its<br />
semiconductor products to current specifications in accordance with <strong>Altera</strong>'s standard warranty, but reserves the right to make changes to any products and<br />
services at any time without notice. <strong>Altera</strong> assumes no responsibility or liability arising out of the application or use of any information, product, or service<br />
described herein except as expressly agreed to in writing by <strong>Altera</strong>. <strong>Altera</strong> customers are advised to obtain the latest version of device specifications before relying<br />
on any published information and before placing orders for products or services.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong><br />
June 2012<br />
13. LogicLock Region Assignments<br />
Specifies whether the LogicLock region is auto-sized. The Compiler determines an<br />
appropriate size for auto-sized regions during compilation. If this keyword is set to<br />
On, LL_STATE must be set to Floating.<br />
Enumeration<br />
■ Off<br />
■ On<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name LL_AUTO_SIZE -entity -section_id<br />
<br />
ISO<br />
9001:2008<br />
Registered<br />
Subscribe
13–2 Chapter 13: LogicLock Region Assignments<br />
LL_ENABLED<br />
LL_ENABLED<br />
Type<br />
Specifies whether the region is enabled.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name LL_ENABLED -entity -section_id<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 13: LogicLock Region Assignments 13–3<br />
LL_HEIGHT<br />
LL_HEIGHT<br />
Type<br />
Specifies the height of the LogicLock region in rows.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name LL_HEIGHT -entity -section_id<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
13–4 Chapter 13: LogicLock Region Assignments<br />
LL_MEMBER_EXCEPTIONS<br />
LL_MEMBER_EXCEPTIONS<br />
Type<br />
If specified, the Fitter assigns all nodes under the target design entity or path to be<br />
members of the LogicLock region, except for nodes of the specified types.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name LL_MEMBER_EXCEPTIONS -entity -<br />
section_id <br />
set_instance_assignment -name LL_MEMBER_EXCEPTIONS -to -entity<br />
-section_id <br />
set_instance_assignment -name LL_MEMBER_EXCEPTIONS -from -to -<br />
entity -section_id <br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
LL_MEMBER_RESOURCE_EXCLUDE<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 13: LogicLock Region Assignments 13–5<br />
LL_MEMBER_OF<br />
LL_MEMBER_OF<br />
Type<br />
Assigns the current node(s) to a LogicLock region.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
The value of this assignment must be a node name.<br />
Syntax<br />
set_global_assignment -name LL_MEMBER_OF -entity -section_id<br />
<br />
set_instance_assignment -name LL_MEMBER_OF -to -entity -<br />
section_id <br />
set_instance_assignment -name LL_MEMBER_OF -from -to -entity<br />
-section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
13–6 Chapter 13: LogicLock Region Assignments<br />
LL_MEMBER_OF_SECURITY_ROUTING_INTERFACE<br />
LL_MEMBER_OF_SECURITY_ROUTING_INTERFACE<br />
Type<br />
Assigns the current signal to a security routing interface.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
The value of this assignment must be a node name.<br />
Syntax<br />
set_instance_assignment -name LL_MEMBER_OF_SECURITY_ROUTING_INTERFACE -to<br />
-entity -section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 13: LogicLock Region Assignments 13–7<br />
LL_ORIGIN<br />
LL_ORIGIN<br />
Type<br />
Specifies the location of the origin of the LogicLock region. For APEX 20K and APEX<br />
<strong>II</strong> devices, the origin is the top left corner of the region. For newer devices, the origin<br />
is the bottom left corner of the region. The origin of a LogicLock region is specified as<br />
an absolute location on the device, regardless of whether the region is a top-level<br />
LogicLock region or a child LogicLock region. However, if the region is a child<br />
LogicLock region, the <strong>Quartus</strong> <strong>II</strong> software interprets the origin as a relative offset from<br />
the origin of the parent region. If LL_STATE is set to Locked, the Compiler places the<br />
LogicLock region at this location. If LL_STATE is set to Floating, the Compiler is free<br />
to determine an appropriate location for the region during compilation.<br />
Location<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name LL_ORIGIN -entity -section_id<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
13–8 Chapter 13: LogicLock Region Assignments<br />
LL_PARENT<br />
LL_PARENT<br />
Type<br />
Specifies the name of the LogicLock region's parent LogicLock region.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name LL_PARENT -entity -section_id<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 13: LogicLock Region Assignments 13–9<br />
LL_PRIORITY<br />
LL_PRIORITY<br />
Type<br />
Indicates the priority of a wildcard or path-based LL_MEMBER_OF assignment<br />
relative to other wildcard or path-based LL_MEMBER_OF assignments. If a node<br />
matches more than one wildcard or path-based LL_MEMBER_OF assignment target,<br />
the assignment of which the target has the highest LL_PRIORITY value wins.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_instance_assignment -name LL_PRIORITY -to -entity -<br />
section_id <br />
set_instance_assignment -name LL_PRIORITY -from -to -entity<br />
-section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
13–10 Chapter 13: LogicLock Region Assignments<br />
LL_RESERVED<br />
LL_RESERVED<br />
Type<br />
If set to On, the setting prevents the Fitter from placing non-member logic in the<br />
region.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name LL_RESERVED -entity -section_id<br />
<br />
Old Names<br />
This variable also has the following name(s) in some earlier versions of the <strong>Quartus</strong> <strong>II</strong><br />
software:<br />
LL_RESERVE<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 13: LogicLock Region Assignments 13–11<br />
LL_ROOT_REGION<br />
LL_ROOT_REGION<br />
Type<br />
Indicates that the LogicLock region is a root region.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name LL_ROOT_REGION -entity -<br />
section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
13–12 Chapter 13: LogicLock Region Assignments<br />
LL_STATE<br />
LL_STATE<br />
Type<br />
Specifies whether the location of the LogicLock region is locked or floating. The<br />
Compiler determines an appropriate location for floating regions during compilation.<br />
If this keyword is set to Locked, LL_AUTO_SIZE must be set to Off.<br />
Enumeration<br />
■ Floating<br />
■ Locked<br />
■ Soft<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name LL_STATE -entity -section_id<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 13: LogicLock Region Assignments 13–13<br />
LL_WIDTH<br />
LL_WIDTH<br />
Type<br />
Specifies the width of the LogicLock region in logic array blocks (LABs) or embedded<br />
system blocks (ESBs).<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment is not copied when you create a companion revision for HardCopy <strong>II</strong><br />
devices.<br />
Syntax<br />
set_global_assignment -name LL_WIDTH -entity -section_id<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
13–14 Chapter 13: LogicLock Region Assignments<br />
LL_WIDTH<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
MIGRATION_AUTO_PACKED_REGISTERS<br />
Type<br />
© 2012 <strong>Altera</strong> Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos<br />
are trademarks of <strong>Altera</strong> Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as<br />
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. <strong>Altera</strong> warrants performance of its<br />
semiconductor products to current specifications in accordance with <strong>Altera</strong>'s standard warranty, but reserves the right to make changes to any products and<br />
services at any time without notice. <strong>Altera</strong> assumes no responsibility or liability arising out of the application or use of any information, product, or service<br />
described herein except as expressly agreed to in writing by <strong>Altera</strong>. <strong>Altera</strong> customers are advised to obtain the latest version of device specifications before relying<br />
on any published information and before placing orders for products or services.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong><br />
June 2012<br />
14. Migration Assignments<br />
Register Packings that have been performed on a prototype device and that must be<br />
reproduced on the target migration device.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_instance_assignment -name MIGRATION_AUTO_PACKED_REGISTERS -to -<br />
entity <br />
set_instance_assignment -name MIGRATION_AUTO_PACKED_REGISTERS -from <br />
-to -entity <br />
ISO<br />
9001:2008<br />
Registered<br />
Subscribe
14–2 Chapter 14: Migration Assignments<br />
MIGRATION_AUTO_PORT_SWAP<br />
MIGRATION_AUTO_PORT_SWAP<br />
Type<br />
Port Swappings that have been performed on a prototype device and that must be<br />
reproduced on the target migration device.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_instance_assignment -name MIGRATION_AUTO_PORT_SWAP -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 14: Migration Assignments 14–3<br />
MIGRATION_RAM_INFORMATION<br />
MIGRATION_RAM_INFORMATION<br />
Type<br />
RAMs that have been created on a prototype device and that must be reproduced on<br />
the target migration device.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_instance_assignment -name MIGRATION_RAM_INFORMATION -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
14–4 Chapter 14: Migration Assignments<br />
MIGRATION_RAM_INFORMATION<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
RTLV_GROUP_COMB_LOGIC_IN_CLOUD<br />
Type<br />
© 2012 <strong>Altera</strong> Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos<br />
are trademarks of <strong>Altera</strong> Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as<br />
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. <strong>Altera</strong> warrants performance of its<br />
semiconductor products to current specifications in accordance with <strong>Altera</strong>'s standard warranty, but reserves the right to make changes to any products and<br />
services at any time without notice. <strong>Altera</strong> assumes no responsibility or liability arising out of the application or use of any information, product, or service<br />
described herein except as expressly agreed to in writing by <strong>Altera</strong>. <strong>Altera</strong> customers are advised to obtain the latest version of device specifications before relying<br />
on any published information and before placing orders for products or services.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong><br />
June 2012<br />
15. Netlist Viewer Assignments<br />
Allows the RTL Viewer to group combinational logic in a logic cloud.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD <br />
Default Value<br />
Off<br />
ISO<br />
9001:2008<br />
Registered<br />
Subscribe
15–2 Chapter 15: Netlist Viewer Assignments<br />
RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV<br />
RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV<br />
Type<br />
Allows the Technology Map Viewer to group combinational logic in a logic cloud.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 15: Netlist Viewer Assignments 15–3<br />
RTLV_GROUP_RELATED_NODES<br />
RTLV_GROUP_RELATED_NODES<br />
Type<br />
Allows the RTL Viewer to group all related nodes into a single bus node.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name RTLV_GROUP_RELATED_NODES <br />
Default Value<br />
On<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
15–4 Chapter 15: Netlist Viewer Assignments<br />
RTLV_GROUP_RELATED_NODES_TMV<br />
RTLV_GROUP_RELATED_NODES_TMV<br />
Type<br />
Allows the Technology Map Viewer to group all related nodes into a single bus node.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV <br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 15: Netlist Viewer Assignments 15–5<br />
RTLV_REMOVE_FANOUT_FREE_REGISTERS<br />
RTLV_REMOVE_FANOUT_FREE_REGISTERS<br />
Type<br />
Allows the RTL Viewer to remove fanout free registers.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS <br />
Default Value<br />
On<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
15–6 Chapter 15: Netlist Viewer Assignments<br />
RTLV_SIMPLIFIED_LOGIC<br />
RTLV_SIMPLIFIED_LOGIC<br />
Type<br />
Allows the RTL Viewer to remove wire nodes and merge chain of equivalent<br />
combinatorial gates.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC <br />
Default Value<br />
On<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
BOARD_MODEL_EBD_FAR_END<br />
Type<br />
© 2012 <strong>Altera</strong> Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos<br />
are trademarks of <strong>Altera</strong> Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as<br />
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. <strong>Altera</strong> warrants performance of its<br />
semiconductor products to current specifications in accordance with <strong>Altera</strong>'s standard warranty, but reserves the right to make changes to any products and<br />
services at any time without notice. <strong>Altera</strong> assumes no responsibility or liability arising out of the application or use of any information, product, or service<br />
described herein except as expressly agreed to in writing by <strong>Altera</strong>. <strong>Altera</strong> customers are advised to obtain the latest version of device specifications before relying<br />
on any published information and before placing orders for products or services.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong><br />
June 2012<br />
16. Advanced I/O Timing Assignments<br />
Specifies the far-end node to be used in the Electronic Board Description (EBD) path<br />
description.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_instance_assignment -name BOARD_MODEL_EBD_FAR_END -to -entity<br />
<br />
ISO<br />
9001:2008<br />
Registered<br />
Subscribe
16–2 Chapter 16: Advanced I/O Timing Assignments<br />
BOARD_MODEL_EBD_FILE_NAME<br />
BOARD_MODEL_EBD_FILE_NAME<br />
Type<br />
Specifies the Electronic Board Description (EBD) file that contains the path description<br />
for an I/O pin.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment supports wildcards.<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_instance_assignment -name BOARD_MODEL_EBD_FILE_NAME -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 16: Advanced I/O Timing Assignments 16–3<br />
BOARD_MODEL_EBD_SIGNAL_NAME<br />
BOARD_MODEL_EBD_SIGNAL_NAME<br />
Type<br />
Specifies the Electronic Board Description (EBD) path description to be used with an<br />
I/O pin. You must specify the EBD file name.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_instance_assignment -name BOARD_MODEL_EBD_SIGNAL_NAME -to -entity<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
16–4 Chapter 16: Advanced I/O Timing Assignments<br />
BOARD_MODEL_FAR_C<br />
BOARD_MODEL_FAR_C<br />
Type<br />
Specifies, in farads, the board trace model far capacitance.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name BOARD_MODEL_FAR_C -to -entity <br />
set_global_assignment -name BOARD_MODEL_FAR_C -section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 16: Advanced I/O Timing Assignments 16–5<br />
BOARD_MODEL_FAR_DIFFERENTIAL_R<br />
BOARD_MODEL_FAR_DIFFERENTIAL_R<br />
Type<br />
Specifies, in ohms, the board trace model far differential resistance.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name BOARD_MODEL_FAR_DIFFERENTIAL_R -to -<br />
entity <br />
set_global_assignment -name BOARD_MODEL_FAR_DIFFERENTIAL_R -section_id<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
16–6 Chapter 16: Advanced I/O Timing Assignments<br />
BOARD_MODEL_FAR_PULLDOWN_R<br />
BOARD_MODEL_FAR_PULLDOWN_R<br />
Type<br />
Specifies, in ohms, the board trace model far pull-down resistance.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name BOARD_MODEL_FAR_PULLDOWN_R -to -entity<br />
<br />
set_global_assignment -name BOARD_MODEL_FAR_PULLDOWN_R -section_id<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 16: Advanced I/O Timing Assignments 16–7<br />
BOARD_MODEL_FAR_PULLUP_R<br />
BOARD_MODEL_FAR_PULLUP_R<br />
Type<br />
Specifies, in ohms, the board trace model far pull-up resistance.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name BOARD_MODEL_FAR_PULLUP_R -to -entity<br />
<br />
set_global_assignment -name BOARD_MODEL_FAR_PULLUP_R -section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
16–8 Chapter 16: Advanced I/O Timing Assignments<br />
BOARD_MODEL_FAR_SERIES_R<br />
BOARD_MODEL_FAR_SERIES_R<br />
Type<br />
Specifies, in ohms, the board trace model far series resistance.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R -to -entity<br />
<br />
set_global_assignment -name BOARD_MODEL_FAR_SERIES_R -section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 16: Advanced I/O Timing Assignments 16–9<br />
BOARD_MODEL_NEAR_C<br />
BOARD_MODEL_NEAR_C<br />
Type<br />
Specifies, in farads, the board trace model near capacitance.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name BOARD_MODEL_NEAR_C -to -entity <br />
set_global_assignment -name BOARD_MODEL_NEAR_C -section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
16–10 Chapter 16: Advanced I/O Timing Assignments<br />
BOARD_MODEL_NEAR_DIFFERENTIAL_R<br />
BOARD_MODEL_NEAR_DIFFERENTIAL_R<br />
Type<br />
Specifies, in ohms, the board trace model near differential resistance.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name BOARD_MODEL_NEAR_DIFFERENTIAL_R -to -<br />
entity <br />
set_global_assignment -name BOARD_MODEL_NEAR_DIFFERENTIAL_R -section_id<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 16: Advanced I/O Timing Assignments 16–11<br />
BOARD_MODEL_NEAR_PULLDOWN_R<br />
BOARD_MODEL_NEAR_PULLDOWN_R<br />
Type<br />
Specifies, in ohms, the board trace model near pull-down resistance.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name BOARD_MODEL_NEAR_PULLDOWN_R -to -entity<br />
<br />
set_global_assignment -name BOARD_MODEL_NEAR_PULLDOWN_R -section_id<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
16–12 Chapter 16: Advanced I/O Timing Assignments<br />
BOARD_MODEL_NEAR_PULLUP_R<br />
BOARD_MODEL_NEAR_PULLUP_R<br />
Type<br />
Specifies, in ohms, the board trace model near pull-up resistance.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R -to -entity<br />
<br />
set_global_assignment -name BOARD_MODEL_NEAR_PULLUP_R -section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 16: Advanced I/O Timing Assignments 16–13<br />
BOARD_MODEL_NEAR_SERIES_R<br />
BOARD_MODEL_NEAR_SERIES_R<br />
Type<br />
Specifies, in ohms, the board trace model near series resistance.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R -to -entity<br />
<br />
set_global_assignment -name BOARD_MODEL_NEAR_SERIES_R -section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
16–14 Chapter 16: Advanced I/O Timing Assignments<br />
BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH<br />
BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH<br />
Type<br />
Specifies, in farads or inches, the board trace model near transmission line distributed<br />
capacitance.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH -to <br />
-entity <br />
set_global_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH -<br />
section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 16: Advanced I/O Timing Assignments 16–15<br />
BOARD_MODEL_NEAR_TLINE_LENGTH<br />
BOARD_MODEL_NEAR_TLINE_LENGTH<br />
Type<br />
Specifies, in inches, the board trace model near transmission line length.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH -to -<br />
entity <br />
set_global_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH -section_id<br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
16–16 Chapter 16: Advanced I/O Timing Assignments<br />
BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH<br />
BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH<br />
Type<br />
Specifies, in henrys or inches, the board trace model near transmission line distributed<br />
inductance.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH -to <br />
-entity <br />
set_global_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH -<br />
section_id <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 16: Advanced I/O Timing Assignments 16–17<br />
BOARD_MODEL_TERMINATION_V<br />
BOARD_MODEL_TERMINATION_V<br />
Type<br />
Specifies, in volts, the board trace model termination voltage.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name BOARD_MODEL_TERMINATION_V -to -entity<br />
<br />
set_global_assignment -name BOARD_MODEL_TERMINATION_V -section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
16–18 Chapter 16: Advanced I/O Timing Assignments<br />
BOARD_MODEL_TLINE_C_PER_LENGTH<br />
BOARD_MODEL_TLINE_C_PER_LENGTH<br />
Type<br />
Specifies, in farads or inches, the board trace model far transmission line distributed<br />
capacitance.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH -to -<br />
entity <br />
set_global_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH -section_id<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 16: Advanced I/O Timing Assignments 16–19<br />
BOARD_MODEL_TLINE_LENGTH<br />
BOARD_MODEL_TLINE_LENGTH<br />
Type<br />
Specifies, in inches, the board trace model far transmission line length.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH -to -entity<br />
<br />
set_global_assignment -name BOARD_MODEL_TLINE_LENGTH -section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
16–20 Chapter 16: Advanced I/O Timing Assignments<br />
BOARD_MODEL_TLINE_L_PER_LENGTH<br />
BOARD_MODEL_TLINE_L_PER_LENGTH<br />
Type<br />
Specifies, in henrys or inches, the board trace model far transmission line distributed<br />
inductance.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH -to -<br />
entity <br />
set_global_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH -section_id<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 16: Advanced I/O Timing Assignments 16–21<br />
ENABLE_ADVANCED_IO_TIMING<br />
ENABLE_ADVANCED_IO_TIMING<br />
Type<br />
Allows the TimeQuest timing analyzer to use Advanced I/O Timing to generate I/O<br />
timing results. Timing results are based on the board trace model specified for each<br />
pin, and may differ from the results currently reported.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
Syntax<br />
set_global_assignment -name ENABLE_ADVANCED_IO_TIMING <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
16–22 Chapter 16: Advanced I/O Timing Assignments<br />
OUTPUT_IO_TIMING_ENDPOINT<br />
OUTPUT_IO_TIMING_ENDPOINT<br />
Type<br />
Specifies the node at which output I/O Timing ends.<br />
Enumeration<br />
■ Far End<br />
■ Near End<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name OUTPUT_IO_TIMING_ENDPOINT -to -entity<br />
<br />
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT -entity <br />
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT <br />
Default Value<br />
Near End<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 16: Advanced I/O Timing Assignments 16–23<br />
OUTPUT_IO_TIMING_FAR_END_VMEAS<br />
OUTPUT_IO_TIMING_FAR_END_VMEAS<br />
Type<br />
Specifies, in volts, the measurement voltage at the far-end.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS -to -<br />
entity <br />
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS -section_id<br />
<br />
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
16–24 Chapter 16: Advanced I/O Timing Assignments<br />
OUTPUT_IO_TIMING_NEAR_END_VMEAS<br />
OUTPUT_IO_TIMING_NEAR_END_VMEAS<br />
Type<br />
Specifies, in volts, the measurement voltage at the near-end.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS -to -<br />
entity <br />
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS -section_id<br />
<br />
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 16: Advanced I/O Timing Assignments 16–25<br />
PCB_LAYER<br />
PCB_LAYER<br />
Type<br />
Specifies which PCB layer the signal breaks out on.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name PCB_LAYER -to -entity <br />
<br />
set_global_assignment -name PCB_LAYER -section_id <br />
<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
16–26 Chapter 16: Advanced I/O Timing Assignments<br />
PCB_LAYERS<br />
PCB_LAYERS<br />
Type<br />
Specifies the properties of all PCB layers.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name PCB_LAYERS -to <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 16: Advanced I/O Timing Assignments 16–27<br />
PCB_LAYER_THICKNESS<br />
PCB_LAYER_THICKNESS<br />
Type<br />
Specifies the thickness of the specific PCB layer.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name PCB_LAYER_THICKNESS -to -entity <br />
set_global_assignment -name PCB_LAYER_THICKNESS -section_id <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
16–28 Chapter 16: Advanced I/O Timing Assignments<br />
SYNCHRONOUS_GROUP<br />
SYNCHRONOUS_GROUP<br />
Type<br />
A logic option that assigns a synchronous group number for the specified node. This<br />
option directs the SSN Analyzer to view the specified nodes as a synchronous group<br />
during SSN voltage noise analysis. This option can be set in the Assignment Editor.<br />
Integer<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name SYNCHRONOUS_GROUP -to -entity <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS<br />
Type<br />
© 2012 <strong>Altera</strong> Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos<br />
are trademarks of <strong>Altera</strong> Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as<br />
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. <strong>Altera</strong> warrants performance of its<br />
semiconductor products to current specifications in accordance with <strong>Altera</strong>'s standard warranty, but reserves the right to make changes to any products and<br />
services at any time without notice. <strong>Altera</strong> assumes no responsibility or liability arising out of the application or use of any information, product, or service<br />
described herein except as expressly agreed to in writing by <strong>Altera</strong>. <strong>Altera</strong> customers are advised to obtain the latest version of device specifications before relying<br />
on any published information and before placing orders for products or services.<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong><br />
June 2012<br />
17. TimeQuest Timing Assignments<br />
Directs the <strong>Quartus</strong> <strong>II</strong> TimeQuest timing analyzer to analyze latches as synchronous<br />
elements, rather than as combinational elements. Although latches continue to be<br />
implemented as a LUT feeding back onto itself, turning on this option directs the<br />
TimeQuest analyzer to analyze all latches as synchronous elements. Specifically, the<br />
clock enable is analyzed as an inverted clock. The TimeQuest analyzer reports the<br />
results of setup and hold analysis on these latches.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS<br />
<br />
Default Value<br />
On<br />
ISO<br />
9001:2008<br />
Registered<br />
Subscribe
17–2 Chapter 17: TimeQuest Timing Assignments<br />
DO_COMBINED_ANALYSIS<br />
DO_COMBINED_ANALYSIS<br />
Type<br />
Analyzes both the fast corner (min delays) and the slow corner (max delays) and<br />
reports the results from each analysis.<br />
Directs the TimeQuest analyzer to run and report timing results using both the Fast<br />
timing model (best-case) and slow timing model (worst-case). The results of each<br />
analysis are reported in the Fast Timing and Slow Timing folders of the TimeQuest<br />
analyzer report. When you run a combined fast or slow analysis, the netlist is<br />
annotated only with worst-case timing model results.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
Syntax<br />
set_global_assignment -name DO_COMBINED_ANALYSIS <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 17: TimeQuest Timing Assignments 17–3<br />
DO_COMBINED_ANALYSIS<br />
Default Value<br />
Off<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
17–4 Chapter 17: TimeQuest Timing Assignments<br />
INPUT_TRANSITION_TIME<br />
INPUT_TRANSITION_TIME<br />
Type<br />
Specifies the input transition time to be used for HardCopy designs. This assignment<br />
is used in the <strong>Quartus</strong> <strong>II</strong> software to adjust the timing of the I/O buffers. It is also used<br />
when generating the PrimeTime script that it is used by the HardCopy back end. This<br />
assignment gets converted as a set_input_transition SDC command. If the<br />
assignment does not exist, the <strong>Quartus</strong> <strong>II</strong> software generates a set_input_transition<br />
using 80% of VCCN * 1V/ns where VCCN depends on the I/O standard used.<br />
Time<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment supports wildcards.<br />
This assignment is copied to any duplicated nodes<br />
Syntax<br />
set_instance_assignment -name INPUT_TRANSITION_TIME -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 17: TimeQuest Timing Assignments 17–5<br />
MAX_CORE_JUNCTION_TEMP<br />
MAX_CORE_JUNCTION_TEMP<br />
Type<br />
This is the maximum core junction temperature that will be encountered during<br />
operation. Specified in degrees Celsius.<br />
String<br />
Device Support<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name MAX_CORE_JUNCTION_TEMP <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
17–6 Chapter 17: TimeQuest Timing Assignments<br />
MIN_CORE_JUNCTION_TEMP<br />
MIN_CORE_JUNCTION_TEMP<br />
Type<br />
This is the minimum core junction temperature that will be encountered during<br />
operation. Specified in degrees Celsius.<br />
String<br />
Device Support<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name MIN_CORE_JUNCTION_TEMP <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 17: TimeQuest Timing Assignments 17–7<br />
NOMINAL_CORE_SUPPLY_VOLTAGE<br />
NOMINAL_CORE_SUPPLY_VOLTAGE<br />
Type<br />
Specifies the voltage for the core power supply. For Stratix <strong>II</strong>I devices, the core supply<br />
voltage applies only to the VCCL power rail. For more information, refer to the<br />
respective device family data sheet.<br />
String<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Notes<br />
The value of this assignment is case sensitive.<br />
This assignment is included in the Fitter report.<br />
Syntax<br />
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
17–8 Chapter 17: TimeQuest Timing Assignments<br />
PACKAGE_SKEW_COMPENSATION<br />
PACKAGE_SKEW_COMPENSATION<br />
Type<br />
Indicates that the package skew for the signal is compensated by the board trace<br />
delays.<br />
Boolean<br />
Device Support<br />
You can use this setting in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
This assignment supports wildcards.<br />
Syntax<br />
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION -to -entity<br />
<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 17: TimeQuest Timing Assignments 17–9<br />
PLL_EXTERNAL_FEEDBACK_BOARD_DELAY<br />
PLL_EXTERNAL_FEEDBACK_BOARD_DELAY<br />
Type<br />
Specifies an external board delay between a feedback output pin and a feedback input<br />
pin (fbin) for a PLL in external feedback mode. This option is ignored if it is assigned<br />
to anything other than the fbin pin of a PLL.<br />
Time<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone V<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Syntax<br />
set_instance_assignment -name PLL_EXTERNAL_FEEDBACK_BOARD_DELAY -to -<br />
entity <br />
set_global_assignment -name PLL_EXTERNAL_FEEDBACK_BOARD_DELAY <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
17–10 Chapter 17: TimeQuest Timing Assignments<br />
TIMEQUEST_DO_CCPP_REMOVAL<br />
TIMEQUEST_DO_CCPP_REMOVAL<br />
Type<br />
Directs the TimeQuest analyzer to remove common clock path pessimism (CCPP)<br />
during slack computation.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ EPC1<br />
■ EPC2<br />
■ Enhanced Configuration Devices<br />
■ FLEX10KB<br />
■ FLEX8000<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
■ MAX9000<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 17: TimeQuest Timing Assignments 17–11<br />
TIMEQUEST_DO_CCPP_REMOVAL<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL <br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
17–12 Chapter 17: TimeQuest Timing Assignments<br />
TIMEQUEST_DO_REPORT_TIMING<br />
TIMEQUEST_DO_REPORT_TIMING<br />
Type<br />
Directs the TimeQuest analyzer to report the worst-case path per clock domain and<br />
analysis.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING <br />
Default Value<br />
Off<br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 17: TimeQuest Timing Assignments 17–13<br />
TIMEQUEST_MULTICORNER_ANALYSIS<br />
TIMEQUEST_MULTICORNER_ANALYSIS<br />
Type<br />
Directs the TimeQuest analyzer to perform multicorner timing analysis, which<br />
analyzes the design against best-case and worst-case operating conditions. Turning on<br />
this option does not enable multicorner analysis in the Fitter. To optimize fast-corner<br />
timing, see the Fitter <strong>Settings</strong> page of the <strong>Settings</strong> dialog box.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ EPC1<br />
■ EPC2<br />
■ Enhanced Configuration Devices<br />
■ FLEX10KB<br />
■ FLEX8000<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
17–14 Chapter 17: TimeQuest Timing Assignments<br />
TIMEQUEST_MULTICORNER_ANALYSIS<br />
■ MAX7000S<br />
■ MAX9000<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 17: TimeQuest Timing Assignments 17–15<br />
TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS<br />
TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS<br />
Type<br />
Specifies the maximum number of worst-case timing paths for the TimeQuest<br />
analyzer to report per clock domain and analysis.<br />
Integer<br />
Device Support<br />
The value must be between these two numbers, inclusive: 1, 100000<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS<br />
<br />
Default Value<br />
100<br />
June 2012 <strong>Altera</strong> Corporation <strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong><br />
<strong>Reference</strong> <strong>Manual</strong>
17–16 Chapter 17: TimeQuest Timing Assignments<br />
TIMEQUEST_REPORT_SCRIPT<br />
TIMEQUEST_REPORT_SCRIPT<br />
Type<br />
Specifies the name of the Tcl script that is used to overwrite the default TimeQuest<br />
report panels created during a normal compile.<br />
<strong>File</strong> name<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Notes<br />
The value of this assignment is case sensitive.<br />
Syntax<br />
set_global_assignment -name TIMEQUEST_REPORT_SCRIPT <br />
<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />
<strong>Reference</strong> <strong>Manual</strong>
Chapter 17: TimeQuest Timing Assignments 17–17<br />
TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS<br />
TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS<br />
Type<br />
Directs the TimeQuest Timing Analyzer to perform default timing analysis prior to<br />
running the user-specified report script specified by TIMEQUEST_REPORT_SCRIPT.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting any <strong>Altera</strong> device family.<br />
Syntax<br />
set_global_assignment -name<br />
TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS <br />
Default Value<br />
On<br />
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17–18 Chapter 17: TimeQuest Timing Assignments<br />
TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS<br />
TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS<br />
Type<br />
Directs the TimeQuest analyzer to report worst-case timing paths per clock domain<br />
and analysis.<br />
Boolean<br />
Device Support<br />
This setting can be used in projects targeting the following device families:<br />
■ Arria GX<br />
■ Arria <strong>II</strong> GX<br />
■ Arria <strong>II</strong> GZ<br />
■ Arria V<br />
■ Cyclone<br />
■ Cyclone <strong>II</strong><br />
■ Cyclone <strong>II</strong>I<br />
■ Cyclone <strong>II</strong>I LS<br />
■ Cyclone IV E<br />
■ Cyclone IV GX<br />
■ Cyclone V<br />
■ EPC1<br />
■ EPC2<br />
■ Enhanced Configuration Devices<br />
■ FLEX10KB<br />
■ FLEX8000<br />
■ HardCopy <strong>II</strong><br />
■ HardCopy <strong>II</strong>I<br />
■ HardCopy IV<br />
■ MAX <strong>II</strong><br />
■ MAX V<br />
■ MAX3000A<br />
■ MAX7000A<br />
■ MAX7000AE<br />
■ MAX7000B<br />
■ MAX7000S<br />
■ MAX9000<br />
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Chapter 17: TimeQuest Timing Assignments 17–19<br />
TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS<br />
■ Stratix<br />
■ Stratix GX<br />
■ Stratix <strong>II</strong><br />
■ Stratix <strong>II</strong> GX<br />
■ Stratix <strong>II</strong>I<br />
■ Stratix IV<br />
■ Stratix V<br />
Syntax<br />
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS<br />
<br />
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17–20 Chapter 17: TimeQuest Timing Assignments<br />
TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS<br />
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Revision History<br />
© 2012 <strong>Altera</strong> Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos<br />
are trademarks of <strong>Altera</strong> Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as<br />
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. <strong>Altera</strong> warrants performance of its<br />
semiconductor products to current specifications in accordance with <strong>Altera</strong>'s standard warranty, but reserves the right to make changes to any products and<br />
services at any time without notice. <strong>Altera</strong> assumes no responsibility or liability arising out of the application or use of any information, product, or service<br />
described herein except as expressly agreed to in writing by <strong>Altera</strong>. <strong>Altera</strong> customers are advised to obtain the latest version of device specifications before relying<br />
on any published information and before placing orders for products or services.<br />
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Additional Information<br />
The <strong>Quartus</strong> ® <strong>II</strong> design software settings are made in the <strong>Quartus</strong> <strong>II</strong> <strong>Settings</strong> <strong>File</strong><br />
(.qsf).<br />
The following table shows the revision history for this manual.<br />
Date and<br />
Document Version Changes Made Summary of Changes<br />
June 2012, v12.0 ■ Updated for <strong>Quartus</strong> <strong>II</strong> version 12.0 —<br />
December 2011, v10.0 ■ Updated for <strong>Quartus</strong> <strong>II</strong> version 11.1 —<br />
May 2011, v9.0 ■ Updated for <strong>Quartus</strong> <strong>II</strong> version 11.0 —<br />
December 2010, v8.0 ■ Updated for <strong>Quartus</strong> <strong>II</strong> version 10.1 —<br />
September 2010, v7.0 ■ Updated for <strong>Quartus</strong> <strong>II</strong> version 10.0 —<br />
December 2009, v6.0 ■ Updated for <strong>Quartus</strong> <strong>II</strong> version 9.1 —<br />
November 2008, v5.0 ■ Updated for <strong>Quartus</strong> <strong>II</strong> version 8.1<br />
—<br />
■ Undated new document template<br />
■ Updated “Revision History” section<br />
September 2008, v4.2 ■ Minor editorial updates —<br />
September 2008, v4.1 ■ Minor editorial updates —<br />
July 2008, v4.0 ■ Updated for <strong>Quartus</strong> <strong>II</strong> version 8.0 —<br />
December 2007, v3.0 ■ Updated for <strong>Quartus</strong> <strong>II</strong> version 7.2 —<br />
ISO<br />
9001:2008<br />
Registered
About–2 Appendix :<br />
How to Contact <strong>Altera</strong><br />
How to Contact <strong>Altera</strong><br />
Typographic Conventions<br />
For the most up-to-date information about <strong>Altera</strong> ® products, see the following table.<br />
Contact (1)<br />
Contact<br />
Method Address<br />
Technical support Website www.altera.com/support<br />
Technical training Website www.altera.com/training<br />
Email custrain@altera.com<br />
Product Literature Website www.altera.com/literature<br />
<strong>Altera</strong> literature services Email literature@altera.com<br />
Non-technical support (General) Email nacomp@altera.com<br />
(Software Licensing) Email authorization@altera.com<br />
Note:<br />
(1) You can also contact your local <strong>Altera</strong> sales office or sales representative.<br />
The following table shows the typographic conventions that this document uses.<br />
Visual Cue Meaning<br />
Bold Type with Initial Capital<br />
Letters<br />
Command names, dialog box titles, checkbox options, and dialog box options are<br />
shown in bold, initial capital letters. Example: Save As dialog box.<br />
bold type External timing parameters, directory names, project names, disk drive names, file<br />
names, file name extensions, and software utility names are shown in bold type.<br />
Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.<br />
Italic Type with Initial Capital Letters Document titles are shown in italic type with initial capital letters. Example: AN 75:<br />
High-Speed Board Design.<br />
Italic type Internal timing parameters and variables are shown in italic type.<br />
Examples: tPIA, n + 1.<br />
Variable names are enclosed in angle brackets (< >) and shown in italic type.<br />
Example: , .pof file.<br />
Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples:<br />
Delete key, the Options menu.<br />
“Subheading Title” <strong>Reference</strong>s to sections within a document and titles of on-line help topics are shown<br />
in quotation marks. Example: “Typographic Conventions.”<br />
Courier type Signal and port names are shown in lowercase Courier type. Examples: data1, tdi,<br />
input. Active-low signals are denoted by suffix n, e.g., resetn.<br />
Anything that must be typed exactly as it appears is shown in Courier type. For example:<br />
c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a<br />
Report <strong>File</strong>, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well<br />
as logic function names (e.g., TRI) are shown in Courier.<br />
1., 2., 3., and<br />
a., b., c., etc.<br />
Numbered steps are used in a list of items when the sequence of the items is important,<br />
such as the steps listed in a procedure.<br />
■ ■ Bullets are used in a list of items when the sequence of the items is not important.<br />
v The checkmark indicates a procedure that consists of one step only.<br />
1 The hand points to information that requires special attention.<br />
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Appendix : About–3<br />
Assignment Value Syntax<br />
c<br />
Visual Cue Meaning<br />
Assignment Value Syntax<br />
There are rules for using certain characters in assignment values to ensure the value is<br />
legal. An unquoted value with only alphabetic, numeric, underscore (_), period (.) or<br />
forward slash (/) characters is legal. A value containing any of the following<br />
characters must be enclosed in double quotation marks (" ") to be legal.<br />
{ } ( ) ; : , < >= - # "<br />
In addition, values containing any of the following characters must escape the<br />
character with a backslash:<br />
{ } $ " \<br />
For example, the following values are legal:<br />
■ “EPF10K10LC84-3”<br />
■ MODE1<br />
■ “ModelSim (VHDL output from <strong>Quartus</strong> <strong>II</strong>)”<br />
Although it is not required, you can also enclose assignments containing only legal<br />
characters in double quotation marks.<br />
Assignment Types<br />
Each <strong>Quartus</strong> <strong>II</strong> assignment has a required type that identifies legal values for the<br />
assignment. This section describes the types and lists some examples of legal values.<br />
bool<br />
An assignment with type bool requires a boolean value of ON or OFF. Boolean<br />
arguments are not case sensitive.. For example, ON, On, oN, and on are all legal.<br />
int<br />
A caution calls attention to a condition or possible situation that can damage or<br />
destroy the product or the user’s work.<br />
A warning calls attention to a condition or possible situation that can cause injury to<br />
w<br />
the user.<br />
r The angled arrow indicates you should press the Enter key.<br />
f The feet direct you to more information on a particular topic.<br />
The envelope links to the Email Subscription Management Center page of the <strong>Altera</strong><br />
website, where you can sign up to receive update notifications for <strong>Altera</strong> documents.<br />
The feedback icon allows you to submit feedback to <strong>Altera</strong> about the document.<br />
Methods for collecting feedback vary as appropriate for each document.<br />
The social media icons allow you to inform others about <strong>Altera</strong> documents. Methods<br />
for submitting information vary as appropriate for each medium.<br />
An assignment with type int requires an integer value. The value must be an integer,<br />
such as 1. Some assignment definitions may list a range of legal integers.<br />
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About–4 Appendix :<br />
Assignment Value Syntax<br />
string<br />
An assignment with type string requires an argument that is a string. If the string<br />
contains any illegal characters, you must enclose the entire string argument in double<br />
quotation marks.<br />
filename<br />
An assignment with type filename requires a value that is the name of a file. You can<br />
specify directory separators with the forward slash character (/) or back slash<br />
characters (\). For example, the following values are legal:<br />
■ simulation/output.vho<br />
■ “c:\design\top.edf”<br />
All filename assignment values are case sensitive..<br />
time<br />
An assignment with type time requires a value that is a time. A time value consists of<br />
a numeric value and text representing units of duration. The numeric value can<br />
include a decimal point, and the numeric value and units of duration can be separated<br />
by a single space. For example, the following values are legal:<br />
■ “1 ps”<br />
■ “-2ns”<br />
■ 10.0µs<br />
Table About–1 shows abbreviations for units of time.<br />
Table About–1. Abbreviations for Units of Time<br />
Time Unit Description<br />
s second(s)<br />
ms millisecond(s)<br />
µs microsecond(s)<br />
ns nanosecond(s)<br />
ps picosecond(s)<br />
fs femtosecond(s)<br />
Hz hertz<br />
kHz kilohertz<br />
MHz megahertz<br />
GHz gigahertz<br />
enum<br />
An assignment with type enum requires an value from the enumerated list included<br />
with the assignment definition. Only values in the list are legal.<br />
location<br />
An assignment with type location requires a value that defines a physical resource<br />
location in a device. For example, the following values are legal in certain devices:<br />
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Appendix : About–5<br />
Overview<br />
Overview<br />
■ LC_X1_Y20_N0<br />
■ LAB_X1_Y1<br />
■ M4K_X17_Y12<br />
frequency<br />
An assignment with type frequency requires a value that is a frequency. A frequency<br />
value consists of a numeric value and text representing units of frequency. The<br />
numeric value can include a decimal point, and the numeric value and units of<br />
frequency can be separated by a single space. For example, the following values are<br />
legal:<br />
■ “50.5 MHz”<br />
■ 10kHz<br />
Benefits of Command-Line Operation & Tcl Scripting Support<br />
Each stage of the <strong>Quartus</strong> <strong>II</strong> software design flow corresponds to a command-line<br />
executable file. Many of these executable files also support industry-standard Tcl<br />
scripting for custom functionality or processing beyond the GUI design flow. The<br />
<strong>Quartus</strong> <strong>II</strong> software offers the following scripting support benefits, also known as<br />
CAR:<br />
■ Custom Analysis<br />
■ Automation<br />
■ Reproducibility<br />
Custom analysis allows you to build test procedures into the script and change design<br />
processing based on the test results. Scripts can automate design flows to perform on<br />
multiple computers simultaneously and easily archive and restore projects.<br />
Reproducibility ensures that scripts use the same project setup and assignments for<br />
every compilation, even when you transfer a project from one engineer to another. In<br />
other words, you can use scripts as another level of design quality assurance.<br />
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About–6 Appendix :<br />
Overview<br />
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