Flyer APECS Pilot Line
APECS is the novel pan-European pilot line to establish a groundbreaking infrastructure for heterogeneous integration.
APECS is the novel pan-European pilot line to establish a groundbreaking infrastructure for heterogeneous integration.
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Three dimensions, unprecedented potential
APECS is the novel pan-European pilot line to establish a groundbreaking infrastructure for advanced
packaging and heterogeneous integration.
Combining the know-how of our partners we will offer services, capabilities and training for European
companies and research organizations to integrate and package chiplets and further
advanced electronic components into novel electronic systems.
INNENSEITE
Europe’s leading microelectronics players are developing together in APECS a platform
that features advanced characterization, quality assurance, and reliability
methods. With a System-Technology Co-Optimization (STCO) framework, it ensures
quality, security, green manufacturing, and rapid production ramp-up through close
collaboration with manufacturing partners.
The APECS pilot line will be implemented by the Research Fab Microelectronics
Germany (FMD). As a cooperation between the Fraunhofer Group for Microelectronics and
the Leibniz Institutes FBH and IHP, the FMD is the central point of contact on all matters concerning
applied research and development in the field of micro and nanoelectronics in Germany and Europe.
Technological background
Future microelectronic systems will require higher levels of functionality that cannot be managed by a single
chip, even if advanced System-on-Chip (SoC) concepts are applied. Instead of manufacturing one large
semiconductor chip and then packaging it as single monolithic IC component, the IC is broken down into
various smaller parts, chiplets. The assembly of multiple small chiplets into a complex, and often three-dimensional
package leads to highly integrated system components.
INNENSEITE
With this heterogeneous integration the current System-in-Package (SiP) approaches will be surpassed.
This concept of true heterogeneous integration is highly relevant for next-generation devices based on future
CMOS-nodes, SiGe, SiC, III/Vs like GaAs, GaN or InP, and all different kinds of micro-electromechanical
systems (MEMS). Such modern electronic systems benefit from the versatility
of components and functions.
Heterogeneous integration enables the consolidation of these functions into a
compact form factor while ensuring high reliability, all in alignment with the
guidelines of the European Green Deal.
Figure: Illustration of possibilities and the complexity of advanced heterogeneous
system integration and advanced packaging. © Fraunhofer IZM
Services for the entire microelectronics value chain
Design services aimed at expanding the value chain share of companies, with a focus on nextgeneration
chiplet integration. This encompasses the development of advanced process modules
for microelectronics, MEMS, optoelectronics, and nanoelectronics, driving innovation in these
cutting-edge fields.
Process development and adaptation, including the validation of the materials and tools used.
INNENSEITE
Development of electronic systems that enable new products and business oportunities using the
technologies of the APECS pilot line.
Starting with the development of a proof of concept, progressing through high-TRL demonstrators
and small-scale production, and extending to prototype runs and limited series manufacturing –
particularly for the fabrication and integration of small-volume chiplet prototypes and customized
product integration services.
Access to research facilities for academic institutions and European RTOs with a special focus on
supporting the accelerated translation of research results into suitable applications.
APECS is co-funded by the Chips Joint Undertaking and national funding authorities of Austria, Belgium, Finland, France, Germany,
Greece, Portugal, Spain, through the Chips for Europe Initiative. Overall funding for APECS amounts to € 730 million over 4.5 years.
The APECS Partners:
Picture: Advanced Fan-Out Wafer and Panel Level Packaging
based on Embedding Technology. © Fraunhofer IZM | Volker Mai
Coordinated by
Implemented by
VORLAGE ZUR
GESTALTUNG EINES
FALTBLATTES
(Endformat 210 x 105 mm)
Format Ihres fertigen Druckproduktes
Co-funded by
Co-funded by
the European Union
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