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Engineers’ <strong>Guide</strong> <strong>to</strong><br />
<strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong><br />
<strong>VME</strong>’s Long From Dead;<br />
Destined To Co-Exist With<br />
<strong>VPX</strong> And Serial Fabrics<br />
www.eecatalog.com/vme<br />
Gold Sponsors<br />
<strong>VPX</strong> Backplanes Go Optical<br />
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Annual Industry <strong>Guide</strong><br />
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Welcome <strong>to</strong> <strong>the</strong> Engineers’<br />
<strong>Guide</strong> <strong>to</strong> <strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong> <strong>2013</strong><br />
The trends in <strong>VME</strong> are clear: systems are migrating <strong>to</strong> high-speed fabric interconnects<br />
using PCI Express, Serial RapidIO, and 10 Gigabit E<strong>the</strong>rnet on platforms such as <strong>VPX</strong><br />
(VITA 46) and Open<strong>VPX</strong> (VITA 65). While copper is still <strong>the</strong> preferred data plane material,<br />
lots of work is going in<strong>to</strong> optical interconnects of spaghetti fiber on <strong>the</strong> backplane. As well,<br />
<strong>VME</strong> vendors are offering all manner of pre-packaged rugged boxes—<strong>the</strong> term I coined<br />
is “shoeboxes”—which may or may not contain 6U, 3U <strong>VME</strong> or <strong>VPX</strong>. In fact, <strong>the</strong>y might<br />
contain anything, including one of <strong>the</strong> several Working Group VITA standards: 73, 74, or 75.<br />
The challenge, of course, is dealing with <strong>the</strong> requisite I/O, heat, and environmentals.<br />
I love <strong>VME</strong>, and have been associated with <strong>the</strong> ecosystem for nearly 25 years. That’s why<br />
when colleague Michael Munroe from Elma Bustronic offered up “<strong>VPX</strong> Backplanes Go<br />
Optical” I jumped on <strong>the</strong> chance <strong>to</strong> include it here. Michael’s an expert on all manner of<br />
PHY and signaling on <strong>VME</strong> and <strong>VPX</strong>. Curtiss-Wright describes how <strong>VPX</strong> is “Bringing HPC<br />
Technology <strong>to</strong> Mil-Aero Embedded Deployment”, and since power is what drives everything,<br />
Dawn <strong>VME</strong> gives us an overview of “VITA 62 Power Supplies: Filling a Standards<br />
Gap for 3U <strong>VPX</strong> Systems”.<br />
As mentioned, heat is a killer in all of <strong>the</strong>se systems so Men<strong>to</strong>r Graphics, <strong>the</strong> recent<br />
acquirer of FloTHERM and o<strong>the</strong>r CFD-related <strong>to</strong>ols, presents an excellent overview of<br />
“Tackling <strong>the</strong> Challenge of Building...Avionics with CFD”. This one’s a must-read.<br />
Yet hardware’s not <strong>the</strong> only game in <strong>VME</strong> and <strong>VPX</strong>. I ran in<strong>to</strong> MultiCoreWare at an AMD<br />
conference and twisted a few arms <strong>to</strong> get <strong>the</strong>m <strong>to</strong> talk about programming in OpenCL<br />
in <strong>the</strong>ir article “Performance-Portable Programming”. And we give an “attaboy” (and<br />
“attagirl”) <strong>to</strong> <strong>the</strong> <strong>VME</strong> community for being “Agile” before it was popular, as evidenced<br />
by <strong>the</strong> article “The Softer Side of Agile” penned by ESI International.<br />
Last, but not least: be sure <strong>to</strong> read our insightful Round table Q&A featuring commentary<br />
by friends from Aitech and Curtiss-Wright in my article “<strong>VME</strong>’s Long From Dead;<br />
Destined <strong>to</strong> Co-Exist with <strong>VPX</strong> and Serial Fabrics”.<br />
Of course, that’s not all—this issue is full of product news, datasheets, events and o<strong>the</strong>r<br />
resources <strong>to</strong> keep you up <strong>to</strong> date with <strong>the</strong> latest in programmable logic. As always, we’d<br />
love <strong>to</strong> hear your feedback, thoughts and comments. Send <strong>the</strong>m <strong>to</strong> info@extensionmedia.com.<br />
Thanks for joining us by reading.<br />
Chris A. C iufo, Edi<strong>to</strong>r<br />
cciufo@extensionmedia.com<br />
PS: Watch for InfiniBand on <strong>VPX</strong>; it’s a trend I’m following closely in <strong>the</strong> blog<br />
www.eecatalog.com/caciufo.<br />
Engineers’ <strong>Guide</strong> <strong>to</strong><br />
<strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong> <strong>2013</strong><br />
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2 Engineers’ <strong>Guide</strong> <strong>to</strong> <strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong> <strong>2013</strong>
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CONTENTS<br />
<strong>VME</strong>’s Long From Dead; Destined To Co-Exist With <strong>VPX</strong> And Serial Fabrics<br />
By Chris A. Ciufo, Edi<strong>to</strong>r ..............................................................................................................................................................................................6<br />
OpenATR - SigPro1 Platform Open<strong>VPX</strong>Based Signal Acquisition System<br />
By ELMA .............................................................................................................................................................................................10<br />
3U <strong>VPX</strong> Solutions from Extreme Engineering Solutions (X-ES)<br />
By Embedded Engineering Solutions (X-ES) .........................................................................................................................................12<br />
<strong>VPX</strong> Backplanes Go Optical<br />
By Michael Munroe, Technical Specialist, Elma Bustronic ...................................................................................................................14<br />
VITA 62 Power Supplies: Filling a Standards Gap for 3U <strong>VPX</strong> Systems<br />
By Brian Roberts, Dawn <strong>VME</strong> ..............................................................................................................................................................................................18<br />
Tackling <strong>the</strong> Challenge of Building Smaller, Lighter, and More Efficient<br />
Component-based Avionics with CFD<br />
By Boris Marovic, Product Marketing Manager, Men<strong>to</strong>r Graphics ............................................................................................................................. 21<br />
Bringing HPC Technology <strong>to</strong> Mil-Aero, Embedded Deployment<br />
By Eran Strod, System Architect, Curtiss-Wright Controls Defense Solutions .......................................................................................24<br />
The Softer Side of Agile: Leading Collaborative Teams <strong>to</strong> Success<br />
By Nancy Y. Nee, PMP, CBAP, CSM Executive Direc<strong>to</strong>r, Project Management & Business Analysis Programs ESI International ............28<br />
The Pro<strong>to</strong>col Wedge<br />
By Ray Alderman, Executive Direc<strong>to</strong>r, VITA ..........................................................................................................................................40<br />
Products and Services<br />
Chips and Cores<br />
Test and Analysis<br />
Teledyne LeCroy<br />
Teledyne LeCroy’s PCI Express® Pro<strong>to</strong>col<br />
Analysis and Test Tools ...................................................................31<br />
Hardware<br />
Backplanes<br />
SIE Computing Solutions<br />
<strong>VPX</strong> Backplanes ...............................................................................32<br />
CPU or Single Board Computers<br />
CES - Creative Electronic Systems SA<br />
QorlQ T4240 3U Open<strong>VPX</strong> SBC (RIOV-2440) ...................................33<br />
CSP Inc.<br />
3220Q Open<strong>VPX</strong> Intel Blade ............................................................34<br />
3300GTX Open<strong>VPX</strong> NVIDIA GPGPU Blade .......................................35<br />
Emerson Network Power<br />
M<strong>VME</strong>8100 Freescale P5020 QorlQ processor <strong>VME</strong> Board ............36<br />
M<strong>VME</strong>2500 ......................................................................................36<br />
Data Aquisition<br />
PENTEK<br />
Model 53720 3-Channel 200 MHz A/D and 2-Channel 800 MHz<br />
D/A with Virtex-7 FPGA - 3U <strong>VPX</strong> Board .........................................37<br />
Enclosures<br />
SIE Computing Solutions<br />
717 Series Air-Over Conduction Cooled ATR Enclosures ................38<br />
“Mupac” 760 Small Form Fac<strong>to</strong>r Series ..........................................39<br />
Engineers’ <strong>Guide</strong> <strong>to</strong><br />
<strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong><br />
UAVs Drive Call for<br />
Small Form Fac<strong>to</strong>r<br />
Standard<br />
www.eecatalog.com/vme<br />
Vetronics Architectures Emerge<br />
<strong>to</strong> Facilitate NEOs<br />
Critical Embedded Systems<br />
Design Challenges<br />
Annual Industry <strong>Guide</strong><br />
Solutions for <strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong><br />
system engineers<br />
COVER CREDIT: A U.S. Air Force C-17 Globemaster<br />
III aircraft sits on a runway on Fort<br />
Polk, La., before picking up soldiers for an<br />
airdrop mission during <strong>the</strong> Large formation<br />
exercise, Dec. 15, 2010. The large formation<br />
exercise demonstrated <strong>the</strong> global projection<br />
of U.S. airpower and <strong>the</strong> mission <strong>to</strong> perform<br />
aerial refueling training. The soldiers are assigned<br />
<strong>to</strong> Task Force 1, Operations Group at<br />
<strong>the</strong> Joint Readiness Training Center. U.S. Air<br />
Force pho<strong>to</strong> by Master Sgt. Jeremy Lock.<br />
4 Engineers’ <strong>Guide</strong> <strong>to</strong> <strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong> <strong>2013</strong><br />
Gold Sponsors<br />
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SPECIAL FEATURE<br />
<strong>VME</strong>’s Long From Dead; Destined To Co-<br />
Exist With <strong>VPX</strong> And Serial Fabrics<br />
A discussion with Aitech and Curtiss-Wright about heat, processors, fabrics, and <strong>VME</strong>’s<br />
synergy with <strong>VPX</strong> and all things “U”.<br />
By Chris A. Ciufo, Edi<strong>to</strong>r<br />
“Born” in 1981, <strong>the</strong> parallel <strong>VME</strong>bus lives on as strong as ever, thanks<br />
<strong>to</strong> a robust VITA standards organization, highly active suppliers and<br />
contribu<strong>to</strong>rs, and <strong>the</strong> defense industry. <strong>VME</strong>, <strong>VPX</strong>, Open<strong>VPX</strong> and<br />
all <strong>the</strong> related standards are ideal for long life-cycle, high-reliability<br />
systems that need finely tuned performance along with size, weight<br />
and power.<br />
The newest specs—including VITA 46 (<strong>VPX</strong>), VITA 65 (Open<strong>VPX</strong>),<br />
and several new proposals for small form fac<strong>to</strong>r (SFF) versions—are<br />
all designed with multi-gigabit serial fabrics in mind. So it comes as<br />
a bit of a surprise that <strong>the</strong> much older 32- and 64-bit parallel bus<br />
<strong>VME</strong> versions continue <strong>to</strong> live on stronger than ever. This edi<strong>to</strong>r<br />
first became associated with <strong>VME</strong> in <strong>the</strong> late 1980s, writing his first<br />
article on <strong>VME</strong> around 1990. Yet it surprises me not one bit that<br />
<strong>VME</strong> is as popular <strong>to</strong>day as <strong>the</strong>n, partially because of <strong>the</strong> cus<strong>to</strong>mer<br />
base that relishes consistency with carefully managed upgrades.<br />
And upgrades are happening, all <strong>the</strong> time. Intel processors have<br />
replaced <strong>the</strong> “traditional” Mo<strong>to</strong>rola/Freescale PowerPC CPUs of 10<br />
years ago. Our panelists tell us that lower-power ARM processors<br />
are being designed in over Intel CPUs where power or SFF size is<br />
advantageous. Yet as algorithm-intensive FPGAs replace some singleboard<br />
computer CPUs, ultra-fast data pipes like Serial RapidIO, PCI<br />
Express, InfiniBand, and 10 GigE represent <strong>the</strong> next wave of <strong>VME</strong>based<br />
upgrades.<br />
Still, as we learned from our discussions with rugged suppliers Aitech<br />
and Curtiss-Wright, <strong>the</strong>re are real-time, closed-loop applications<br />
that will deploy traditional <strong>VME</strong> right alongside <strong>the</strong> most leadingedge<br />
new <strong>VME</strong> standard.<br />
Read on <strong>to</strong> see how our panelists responded <strong>to</strong> this set of industry<br />
insider questions.<br />
EECatalog: What is <strong>the</strong> state of <strong>the</strong> <strong>VME</strong>/<strong>VPX</strong> industry <strong>to</strong>day?<br />
Doug Patterson is VP, Military & Aerospace Business Sec<strong>to</strong>r, for<br />
Aitech Defense Systems, Inc.<br />
Patterson, Aitech: The <strong>VPX</strong> market is emerging slowly despite all <strong>the</strong><br />
press that continues <strong>to</strong> predict that it’s replacing “obsolete technologies”<br />
like [<strong>the</strong> predecessors] <strong>VME</strong>bus and CompactPCI. Cus<strong>to</strong>mers<br />
with real-time, hard deadline, tight control-loop applications still<br />
Doug Patterson (L), Mike Slonsky(C), and Steve Edwards(R)<br />
value parallel buses like cPCI or <strong>VME</strong>bus, and don’t yet use <strong>the</strong> new<br />
serial, point-<strong>to</strong>-point fabric <strong>to</strong>pologies.<br />
Parallel buses including <strong>VME</strong> and cPCI are by definition, “commandresponse”,<br />
synchronous data buses with bus message formats<br />
and machine instructions often dedicated <strong>to</strong> this architecture—<br />
including Read-Modify-Write, an instruction that “locks” <strong>the</strong> bus so<br />
critical messages arrive in order and are, by definition, synchronized<br />
in process and in time. Some of <strong>the</strong> newer high speed serial fabrics<br />
represent numerous data pipes that seem like a collection of asynchronous<br />
“snakes” all swirling and spitting out data at random.<br />
Serial fabrics are ideal for C4ISR applications where passing massive<br />
quantities of high speed data serially <strong>to</strong> and from predefined points<br />
around a system vehicle, platform or backplane is needed for postprocessing.<br />
If data is generated and passed throughout a subsystem<br />
platform asynchronously, data packets can, and most likely will, get<br />
out of sync causing all sorts of unintended actions.<br />
Mike Slonosky, is product marketing manager for <strong>the</strong> Power<br />
Architecture single board computers at Curtiss-Wright Controls<br />
Defense Solutions.<br />
Steve Edwards, is chief technology officer for COTS Solutions at<br />
Curtiss-Wright Controls Defense Solutions.<br />
Edwards, Curtiss-Wright: <strong>VPX</strong> (VITA 46) was started in March<br />
2003 and ratified in 2007. Open<strong>VPX</strong> (VITA 65) was started in<br />
January 2009 (outside of VITA) and brought in<strong>to</strong> VITA at <strong>the</strong> end of<br />
2009. The first revision of VITA 65 was released in 2010 and revision<br />
2 (current rev) was released in 2012. We are currently working on rev<br />
3 which should be approved mid-<strong>2013</strong>. The major additions <strong>to</strong> <strong>the</strong> rev<br />
3 specification are faster speed fabrics such as Gen 3 PCIe, 40 GigE<br />
(40GBase-KR) and QDR/FDR InfiniBand.<br />
6 Engineers’ <strong>Guide</strong> <strong>to</strong> <strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong> <strong>2013</strong>
Established platform parallel bus pro<strong>to</strong>cols like <strong>VME</strong>bus and<br />
CompactPCI still have <strong>the</strong>ir place in <strong>to</strong>day's and <strong>to</strong>morrow's<br />
harsh environment, real-time/hard-deadline embedded<br />
sub-system applications...especially when <strong>the</strong>se products<br />
are upgraded and maintained <strong>to</strong> keep pace with <strong>the</strong> newest,<br />
fastest processor and memory technologies.<br />
While <strong>the</strong>re are some applications where high speed serial<br />
fabrics like <strong>VPX</strong> are ideal, <strong>the</strong>re are o<strong>the</strong>rs where <strong>VME</strong>bus<br />
or CompactPCI still rule <strong>the</strong> roost.<br />
One company continues <strong>to</strong> actively invest in maintaining –<br />
and not obsolescing – <strong>the</strong>ir military and space embedded<br />
computing products with a proactive 12-year minimum<br />
COTS Lifecycle+ Program.<br />
And one company continues <strong>to</strong> also invest in delivering<br />
<strong>the</strong> very best of <strong>the</strong> newest embedded COTS computing<br />
platforms with <strong>the</strong> new, serial fabric pro<strong>to</strong>cols.<br />
And one company actively invests in technology insertion<br />
at <strong>the</strong> board level, creating backplane, pin-compatible<br />
products with <strong>the</strong> latest, next generation memory and<br />
processor technologies "on-board".<br />
And that same company still delivers <strong>the</strong>ir legacy bus<br />
products at full speed and full capability and full mil temp<br />
range (-55 <strong>to</strong> +85°C) with those latest technologies.<br />
The one company <strong>to</strong> do all that? Aitech. Check our website<br />
<strong>to</strong> learn more about our technology roadmaps and how<br />
<strong>the</strong>y protect your investments.<br />
Aitech Defense Systems, Inc.<br />
19756 Prairie Street<br />
Chatsworth, CA 91311<br />
email: sales@rugged.com<br />
Toll Free: 888-Aitech8 - (888) 248-3248<br />
Fax: (818) 407-1502<br />
www.rugged.com
SPECIAL FEATURE<br />
We are also in <strong>the</strong> process or creating one or more “dot” specifications<br />
<strong>to</strong> cover <strong>the</strong> use of alternate connec<strong>to</strong>rs (optical, RF, etc). We decided<br />
that <strong>the</strong>se alternate connec<strong>to</strong>rs were best defined in a dot(s) spec<br />
ra<strong>the</strong>r than adding <strong>the</strong>m <strong>to</strong> <strong>the</strong> current VITA 65 spec. New profiles<br />
that use only <strong>the</strong> VITA 46 (<strong>VPX</strong>) connec<strong>to</strong>r will continue <strong>to</strong> be added<br />
<strong>to</strong> VITA 65.<br />
EECatalog: Conventional wisdom says boards are getting hotter.<br />
What are you seeing, and what are <strong>the</strong> trends in <strong>the</strong>rmal management?<br />
Patterson, Aitech: “Conventional wisdom” only applies when one<br />
complies and acquiesces <strong>to</strong> convention, when in fact, only some<br />
boards are getting hotter. Newer processor technologies—like Freescale’s<br />
QorIQ and ARM processors— are challenging convention in<br />
terms of performance and power dissipation. The proof can be seen<br />
in <strong>to</strong>day’s full-featured 3G and 4G Smartphones that provide stellar<br />
performance with milliwatt power dissipations. Reductions in SWaP<br />
remain <strong>the</strong> goal, <strong>the</strong> engineering prize and <strong>the</strong> promise of Nirvana.<br />
Edwards, Curtiss-Wright: Boards are getting hotter … and cooler.<br />
Certainly at <strong>the</strong> high end we are seeing boards getting hotter. This is<br />
driven primarily by <strong>the</strong> latest generation Intel processors, GPGPUs<br />
and large FPGAs. But we are also seeing that a number of products<br />
(especially in 3U) are using lower power devices such as lower-end<br />
Power Architecture and ARM processors. These processors have more<br />
performance with less power than <strong>the</strong> CPUs <strong>the</strong>y are replacing from<br />
5+ years ago.<br />
Slonosky, Curtiss-Wright: For technology insertions or technology<br />
refreshes (and <strong>the</strong>re is a difference), cus<strong>to</strong>mers are requiring next<br />
generation products <strong>to</strong> fit in<strong>to</strong> <strong>the</strong> same or similar <strong>the</strong>rmal footprint.<br />
Hence, <strong>to</strong> meet <strong>the</strong>se needs COTS vendors are designing next generation<br />
boards that provide similar <strong>the</strong>rmal footprints <strong>to</strong> those in older<br />
products but with increased performance. Not all next-generation<br />
products are going <strong>to</strong> be able <strong>to</strong> “fit” <strong>the</strong>rmally—but many can be.<br />
On <strong>the</strong> hot end <strong>the</strong>re are a number of innovative approaches that<br />
companies are taking for <strong>the</strong>rmal management. Air Flow Through or<br />
AFT (VITA 48.5) is becoming more popular for higher power products.<br />
Curtiss-Wright also has a patent pending approach <strong>to</strong> cooling<br />
high power Intel processors.<br />
EECatalog: The march <strong>to</strong>wards SFFs has affected even predominantly<br />
“U” based VITA. Why is <strong>the</strong> market so interested in small<br />
form fac<strong>to</strong>rs?<br />
Patterson, Aitech: Small, rugged, stand-alone form fac<strong>to</strong>rs, coupled<br />
with high performance, power-efficient, deeply embedded processors<br />
bring <strong>the</strong> reality of distributed processing and “computing-at-<strong>the</strong>edge”<br />
<strong>to</strong> <strong>to</strong>day’s mobile computing platforms and vehicles. Bus-based<br />
embedded computing subsystems are ideal and still used <strong>to</strong> create<br />
large, centralized embedded computers.<br />
Compact “smaller than U” embedded computers acting as remote<br />
interface units or data concentra<strong>to</strong>rs can now be distributed at <strong>the</strong><br />
end of high speed networks and communication buses <strong>to</strong> ga<strong>the</strong>r,<br />
analyze and—more importantly— can ga<strong>the</strong>r and compress sensor<br />
data closer <strong>to</strong> <strong>the</strong> sensor, <strong>the</strong>n send that data <strong>to</strong> <strong>the</strong> central mission<br />
computer, which in-turn, lowers <strong>the</strong> overall network bandwidth.<br />
Edwards, Curtiss-Wright: In a word: “SWaP”. SFF boards fit best<br />
in niches where <strong>the</strong> platform is constrained in Size, Weight and/or<br />
Power. Typically smaller UAVs and some ground systems are <strong>the</strong> biggest<br />
areas in defense for SFF. Systems that need more performance<br />
use 3U or 6U since <strong>the</strong>y can be used <strong>to</strong> build <strong>the</strong> larger systems<br />
required by more demanding applications.<br />
EECatalog: Talk a bit about inter- and intra-box interconnects.<br />
What’s <strong>the</strong> state of <strong>the</strong> art <strong>to</strong>day, and where does <strong>the</strong> user base want<br />
us <strong>to</strong> go?<br />
Patterson, Aitech: Currently, inter-box interconnect is tending <strong>to</strong><br />
adopt <strong>the</strong> E<strong>the</strong>rnet TCP/IP and UDP pro<strong>to</strong>cols almost universally.<br />
The advent of multi-Gigahertz, multi-core processors with higher<br />
speed RAM and block-oriented Flash memory allows <strong>the</strong> system<br />
designer <strong>to</strong> easily overwhelm <strong>the</strong> box-<strong>to</strong>-box communications pro<strong>to</strong>col<br />
stacks with plenty of speed and data throughputs left over for<br />
analysis and compression algorithms.<br />
Intra-box data passing is adopting <strong>the</strong> asynchronous high speed PCIe<br />
(PCI Express) and SRIO (Serial Rapid I/O) serial fabrics with synchronous,<br />
even-driven parallel, data buses (like <strong>VME</strong> and cPCI) that<br />
are providing <strong>the</strong> real time, interrupt-based system synchronization.<br />
A parallel bus’ interrupt-driven structure with minimal latencies is<br />
<strong>the</strong> only architecture that can handle <strong>the</strong>se kinds of control-loop<br />
applications in real-time.<br />
Serial fabrics cannot yet replace parallel buses in <strong>the</strong>se closed-loop<br />
feedback systems: none of <strong>the</strong>se fabrics possess <strong>the</strong> needed real-time<br />
synchronization capability. This is why many systems integra<strong>to</strong>rs<br />
for event-driven apps are choosing a hybrid approach <strong>to</strong> systems<br />
designs—mixing <strong>the</strong> power, performance and raw speed of high<br />
speed serial data pipes and parallel buses like <strong>VME</strong> or cPCI for <strong>the</strong><br />
control loops.<br />
Edwards, Curtiss-Wright: Today users are predominantly using<br />
3.125 – 6.25 Gbaud fabrics such as SRIO Gen 1 or 2, 10 GigE or PCIe<br />
Gen 1 or 2 inside a box. Interconnects are generally copper. Connection<br />
between boxes are less standardized. We see cus<strong>to</strong>mers using<br />
sFPDP, Fibre Channel, 10 GigE and proprietary interfaces. Optical<br />
and copper are both used for box-<strong>to</strong>-box.<br />
40 GigE data plane and PCIe Gen 3 expansion plane products will<br />
be available in <strong>the</strong> next year. Optical and RF user I/O modules will<br />
also become more prevalent. The general feeling is that <strong>VPX</strong> can, with<br />
proper layout/routing, support 10Gbaud signaling. Beyond that, <strong>the</strong><br />
general belief is that we need <strong>to</strong> move <strong>to</strong> optical interfaces (or pick a<br />
new connec<strong>to</strong>r that supports 20-25 Gbaud signaling).<br />
EECatalog: Board consolidation continues unabated, and it’s looking<br />
<strong>to</strong>day like that could wind up being all manner of svelte, purposebuilt<br />
boxes that don’t seem <strong>to</strong> follow any standard at all (let alone<br />
<strong>VME</strong> or <strong>VPX</strong>). What’s up with this trend?<br />
8 Engineers’ <strong>Guide</strong> <strong>to</strong> <strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong> <strong>2013</strong>
Patterson, Aitech: Until <strong>the</strong> smaller, purpose-built, small form<br />
fac<strong>to</strong>r boxes can provide all <strong>the</strong> raw processing power and performance<br />
of a multi-slot, large, super high-performance mission<br />
computer, larger C4ISR, sensor-intensive systems will still use a mix<br />
of open system architecture processor and packaging technologies.<br />
Remember how <strong>the</strong> COTS/NDI market got its start, first a <strong>to</strong>e-hold,<br />
<strong>the</strong>n a foot-hold and is now deeply entrenched in <strong>to</strong>day’s embedded<br />
processing subsystems and platforms—it’s <strong>the</strong> limited volumes<br />
associated with <strong>the</strong> economies of scale that will always displace <strong>the</strong><br />
purpose-built systems until <strong>the</strong> volume increases <strong>to</strong> justify <strong>the</strong> development<br />
and deployment expenses.<br />
The o<strong>the</strong>r fac<strong>to</strong>r <strong>to</strong>day is <strong>the</strong> rampaging costs of component obsolescence<br />
and how it’s making subsystems obsolete even before <strong>the</strong>y are<br />
deployed out in<strong>to</strong> <strong>the</strong> field; but that’s a different subject and s<strong>to</strong>ry,<br />
al<strong>to</strong>ge<strong>the</strong>r...<br />
Slonosky, Curtiss-Wright: That is no different than what <strong>the</strong>y do<br />
<strong>to</strong>day, and will probably not change significantly. Standards such as<br />
Open<strong>VPX</strong> provide a means <strong>to</strong> start development with “standard profile<br />
cards” in “standard” backplanes or enclosures that can be bought<br />
off <strong>the</strong> shelf. For example, a system designer is unlikely <strong>to</strong> use a 5 slot<br />
backplane in an application that requires or only has <strong>the</strong> space for 2<br />
slots. Not all applications will be able <strong>to</strong> use standard off-<strong>the</strong>-shelf<br />
implementations.<br />
<strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong> ONLINE<br />
SPECIAL FEATURE<br />
EECatalog: What will <strong>the</strong> future hold regarding SWaP-C and open<br />
standards?<br />
Patterson, Aitech: As implied and eluded <strong>to</strong> in number 5 above, cost<br />
will always drive system solutions. When <strong>the</strong> volumes increase <strong>to</strong><br />
that “magic quantity” (which is different for every company), where<br />
<strong>the</strong> volume does not displace <strong>the</strong> costs <strong>to</strong> design and manufacture a<br />
unit internally, <strong>the</strong> use of COTS products will predominate by economics<br />
alone as long as <strong>the</strong>re are companies who invest <strong>the</strong>ir IP in<strong>to</strong><br />
producing compatible, inter-mateable, open systems architectures.<br />
Edwards, Curtiss-Wright: Open standards are here <strong>to</strong> stay, but<br />
“openness” can be defined at many levels and we may start seeing<br />
open standards at a subsystem or interface level and not so much at<br />
<strong>the</strong> module level.<br />
Chris A. Ciufo is senior edi<strong>to</strong>r for embedded content<br />
at Extension Media, which includes <strong>the</strong> EECatalog<br />
print and digital publications and website, Embedded<br />
Intel® Solutions, and o<strong>the</strong>r related blogs and<br />
embedded channels. He has 29 years of embedded<br />
technology experience, and has degrees in electrical<br />
engineering, and in materials science, emphasizing solid state<br />
physics. He can be reached at cciufo@extensionmedia.com.<br />
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Adver<strong>to</strong>rial<br />
3U <strong>VPX</strong> Solutions from Extreme<br />
Engineering Solutions (X-ES)<br />
Product<br />
Name<br />
X-ES has an extensive <strong>VPX</strong> product line. Highlighted here are some of our newest 3U <strong>VPX</strong> products providing<br />
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DEVELOPMENT PLATFORMS<br />
Product<br />
Name<br />
CARRIER<br />
Dimensions Chassis<br />
Cooling<br />
Mezzanine<br />
Sites<br />
XChange3000 1 PMC/XMC<br />
Module<br />
Cooling<br />
12 Engineers’ <strong>Guide</strong> <strong>to</strong> <strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong> <strong>2013</strong><br />
# of<br />
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Overview<br />
XPand1000 8.3"D x 4.2"W x 8.5"H Air Conduction 2 Small development<br />
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XPand1200 11.5"D x 5.5"W x 16.5"H Air Conduction 10 Development platform<br />
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development enclosure<br />
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XPand1300 11.6"D x 13.5"W x 13.5"H Air Air 15 Development platform<br />
for air-cooled modules.<br />
STORAGE<br />
Product<br />
Name<br />
Capacity <strong>VPX</strong><br />
Interface<br />
XPort6172 512 GB 1 x4 PCI<br />
Express<br />
POWER SUPPLIES<br />
Product<br />
Name<br />
Input power Max<br />
output<br />
power<br />
XPm2020 MIL-STD-704<br />
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XPm2120 MIL-STD-704<br />
28 V DC<br />
300W<br />
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SINGLE BOARD COMPUTERS<br />
Product<br />
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Processor Memory Mezzanines Gb E<strong>the</strong>rnet USB 2.0<br />
XPedite5470 QorIQ P3041, P4040,<br />
p4080, P5010, P5020,<br />
P5040<br />
8 GB DDR3-1333 1 PMC/XMC 2 2<br />
XPedite5570 QorIQ P1011, P1020,<br />
P2010, P2020<br />
XPedite7470 Dual-core and quadcore<br />
3 rd generation<br />
Intel Core i7 processor<br />
SWITCHES<br />
Product<br />
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ENCLOSURES<br />
Product<br />
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XPand3200<br />
Series<br />
XPand4200<br />
Series<br />
XPand5200<br />
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Mezzanines Backplane<br />
E<strong>the</strong>rnet<br />
4 GB DDR3-800 1 PMC/XMC 2 1<br />
8 GB DDR3-1333 1 PMC/XMC 2 2<br />
Dimensions Chassis<br />
Cooling<br />
Backplane<br />
PCI Express<br />
CONTACT INFORMATION<br />
Module<br />
Cooling<br />
8.75"D x 4.88"W x 5.62"H Conduction Conduction 6<br />
13.5"D x 4.88"W x 6.0"H Air Conduction 6<br />
10.30"D x 4.88"W x 5.65"H Convection<br />
or<br />
Conduction<br />
Functionality<br />
XChange3011 - 14 1000BASE-T 10/100/1000BASE-T E<strong>the</strong>rnet<br />
switch<br />
XChange3012 1 XMC 6 1000BASE-X 6 x4 PCIe Integrated 6-port PCI Express<br />
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www.xes-inc.com<br />
www.eecatalog.com/vme 13<br />
# of<br />
Slots
SPECIAL FEATURE<br />
<strong>VPX</strong> Backplanes Go Optical<br />
<strong>VPX</strong> backplanes surpass 40 Gbps in copper E<strong>the</strong>rnet and also gain a backplane optical<br />
interface connec<strong>to</strong>r.<br />
By Michael Munroe, Technical Specialist, Elma Bustronic<br />
Optical backplanes are seen by some as <strong>the</strong> ultimate solution for<br />
higher bandwidth interconnections, and hence long anticipated in<br />
embedded computing. The practicality of backplane-based optical<br />
solutions is closer <strong>to</strong> becoming a reality with <strong>the</strong> release of two ANSI-<br />
VITA standards addressing backplane optical interfaces.<br />
<strong>VPX</strong> has become <strong>the</strong> backplane architecture of choice for new<br />
embedded applications in <strong>the</strong> mil-aero marketplace. Important attributes<br />
of <strong>VPX</strong> include:<br />
<br />
<br />
<br />
a 6U card and even more if <strong>the</strong> 48 volt option were used<br />
<br />
<br />
<br />
tial<br />
pairs and a 6U card with 192 differential pairs in addition <strong>to</strong> all<br />
<strong>the</strong> standard power and utility signals.<br />
The last point is becoming an increasingly<br />
important aspect of <strong>the</strong> <strong>VPX</strong> architecture.<br />
In addition <strong>to</strong> both conventional rear transition<br />
modules and a very capable rear copper<br />
cable interface <strong>the</strong>re are now a series of<br />
ANSI-VITA standards that define backplane<br />
coaxial cables for RF signals and backplane<br />
optical ribbon cables. The <strong>VPX</strong> optical backplane<br />
module accepts a standard optical ribbon assembly terminated<br />
with an MT ferrule. (see Figure 1).<br />
The Need For More Speed<br />
<strong>VPX</strong> backplanes on <strong>the</strong> market <strong>to</strong>day regularly support 5 Gbps and<br />
6.2 Gbps channels and several new <strong>VPX</strong> backplanes are supporting<br />
8, 10 and even 14 Gbps channels. All <strong>the</strong> <strong>VPX</strong> specifications such as<br />
VITA 65 and <strong>the</strong> various VITA 46 dot specifications point <strong>to</strong> VITA<br />
68 for <strong>the</strong>ir electrical channel requirements. This document is still<br />
in draft version and when released will address <strong>the</strong> three currently<br />
defined backplane bandwidths, 3.125, 5.0 and 6.25 Gbaud. It is also<br />
intended <strong>to</strong> address 10GBASE-KR and 40GBASE-KR4. This document<br />
is progressing slowly.<br />
"<strong>VPX</strong> IS POISED TO<br />
OFFER A GRACEFUL<br />
TRANSITION FROM<br />
COPPER TO OPTICAL."<br />
Figure 1: A 12 optical fiber ribbon terminated <strong>to</strong> an MT ferrule.<br />
PCIe Gen3 and InfiniBand FDR are not currently planned <strong>to</strong> be<br />
included because of <strong>the</strong> additional engineering work it will require<br />
<strong>to</strong> define card and backplane electrical margins <strong>to</strong> ensure intermateability.<br />
So although it will take some time for <strong>the</strong> <strong>VPX</strong> interface<br />
channel specification <strong>to</strong> address <strong>the</strong>se new higher speeds, <strong>the</strong>se backplanes<br />
already now exist and card vendors have begun offering <strong>VPX</strong><br />
cards that utilize PCIe Gen3 and 10GBASE-KR E<strong>the</strong>rnet signaling.<br />
10GBASE-KR and 40GBASE-KR4 are both<br />
backplane E<strong>the</strong>rnet standards based upon<br />
bi-directional 10Gbps differential lanes.<br />
These are fully defined within IEEE 802.3-<br />
2008. However, in that document individual<br />
backplane and daughter card losses are not<br />
defined because <strong>the</strong>re is no backplane connec<strong>to</strong>r<br />
addressed in that document. Each<br />
backplane architecture must undertake apportion losses and define<br />
channel requirements individually for <strong>the</strong> backplane and daughter<br />
card. This work has just been completed within PICMG for PICMG<br />
3.1r2. This should make it easier for all subsequent standards <strong>to</strong><br />
address <strong>the</strong> same issue for <strong>the</strong>ir backplane and daughter card designs.<br />
Although <strong>the</strong>re are <strong>VPX</strong> backplanes that can support serial communication<br />
across <strong>the</strong> backplane at 8, 10 and 14 Gbps, maintaining<br />
<strong>the</strong>se speeds over copper I/O cables is no longer practical. Copper<br />
cables supporting PCIe Gen3 are only defined <strong>to</strong> support distances of<br />
two meters or less. For longer distances optical cables must be used.<br />
If I/O is going <strong>to</strong> be able <strong>to</strong> keep parity with <strong>the</strong> backplane, it is going<br />
<strong>to</strong> have <strong>to</strong> be optical. Copper cabling can carry 1000 Base-T Gigabit<br />
14 Engineers’ <strong>Guide</strong> <strong>to</strong> <strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong> <strong>2013</strong>
SPECIAL FEATURE<br />
Figure 2: Top: Hybrid <strong>VME</strong>/<strong>VPX</strong> backplane with VITA 66.1 optical<br />
connec<strong>to</strong>rs and VITA 67.2 coaxial copper connec<strong>to</strong>rs and standard VITA<br />
46 MultiGig connec<strong>to</strong>rs in positions J0-J4. Bot<strong>to</strong>m: Optical ferrules<br />
close up.<br />
signals for 1,000 meters. At <strong>the</strong> InfiniBand FDR 14.1 Gbps data rate,<br />
<strong>the</strong> practical distance for copper I/O cabling is less than seven meters.<br />
VITA’s <strong>VPX</strong> Keeps Pace<br />
Two new standards released in 2011, ANSI-VITA 66.0 (Optical<br />
Interconnect on <strong>VPX</strong> – Base Standard) and ANSI-VITA 66.1 (Optical<br />
Interconnect on <strong>VPX</strong> – MT Variant) are laying <strong>the</strong> groundwork for<br />
migration <strong>to</strong> optical technologies within <strong>the</strong> embedded computing<br />
industry. These two VITA 66 dot standards are <strong>the</strong> first in a family of<br />
documents that will define a variety of backplane optical interfaces<br />
compatible with <strong>the</strong> existing Eurocard form fac<strong>to</strong>r used by <strong>the</strong> <strong>VPX</strong><br />
architecture. Because <strong>the</strong> Eurocard architecture also utilizes CompactPCI,<br />
CompactPCI Express, CompactPCI SO as well as PXI and PXI<br />
Express <strong>the</strong>se new optical connec<strong>to</strong>r interfaces have <strong>the</strong> potential <strong>to</strong><br />
rapidly migrate <strong>to</strong> o<strong>the</strong>r platforms if <strong>the</strong>y first become established<br />
within <strong>the</strong> <strong>VPX</strong> community. In addition, AdvancedTCA utilizes a<br />
connec<strong>to</strong>r system with <strong>the</strong> same mating interface as required for <strong>the</strong><br />
previously mentioned embedded architectures. This means <strong>the</strong> <strong>VPX</strong><br />
optical module could potentially be used for Zone 3 implementations<br />
in that architecture as well.<br />
It’s Not All “Just Optics”<br />
There are three basic system implementations that are now possible<br />
based upon <strong>the</strong> VITA 66.1 interconnect: 1) Fiber optic I/O from <strong>the</strong><br />
chassis <strong>to</strong> external points such as sensor arrays, 2) Direct slot-<strong>to</strong>slot<br />
fiber optic links providing high bandwidth paths between pairs<br />
of cards within a system, and 3) Switched optical data planes with<br />
multiple payload cards connected <strong>to</strong> an optical switch slot (Figure 2).<br />
Figure 1 shows an optical cable assembly with 12 fibers terminated at<br />
each end with an MT ferrule. This assembly would plug in<strong>to</strong> <strong>the</strong> VITA<br />
66.1 backplane module and could connect from slot <strong>to</strong> slot or be used<br />
<strong>to</strong> connect <strong>the</strong> backplane <strong>to</strong> an external sensor array.<br />
Figure 2 shows a 6U backplane with <strong>the</strong> VITA 66.1 optical modules<br />
implemented in <strong>the</strong> J5 position of slots 5, 6 and 7. Although <strong>the</strong> VITA<br />
66.1 optical module is new, it is based upon <strong>the</strong> existing well-established<br />
MT and MPO ferrule technology first introduced as an EIA<br />
standard around 1993. VITA 66.1 defines a <strong>VPX</strong> compatible module<br />
that positions <strong>the</strong> MPO multi-fiber ferrule with sufficient precision<br />
<strong>to</strong> allow it <strong>to</strong> be used as a backplane interface for conventional <strong>VPX</strong><br />
plug in cards. The VITA 66.1 standard provides for up <strong>to</strong> two MT ferrules<br />
in a one-inch long module. Each of <strong>the</strong> two MT ferrules can hold<br />
up <strong>to</strong> 24 optical fibers.<br />
This means that a 6U <strong>VPX</strong> module could support up <strong>to</strong> six VITA 66.1<br />
modules for a <strong>to</strong>tal of 288 optical fibers, such as <strong>the</strong> one shown in<br />
Figure 1. Of course, this represents a <strong>the</strong>oretical maximum and it is<br />
not expected that any card would implement more than one or two<br />
modules for a <strong>to</strong>tal of between 24 and 96 optical fibers. The reason<br />
for <strong>the</strong> wide range is that although an individual MT ferrule <strong>to</strong>day<br />
can hold more than <strong>the</strong> two 12-fiber ribbons defined within VITA<br />
66.1 and slots could potentially be populated with up <strong>to</strong> six modules,<br />
<strong>the</strong>re are no defined <strong>to</strong>pologies at this time for card-<strong>to</strong>-card optical<br />
connections. Therefore <strong>the</strong> most likely implementations within <strong>VPX</strong><br />
will be <strong>to</strong> carry signals between systems or between a system and an<br />
external sensor field and this will be unlikely <strong>to</strong> require more than a<br />
single optical module on any individual <strong>VPX</strong> card.<br />
Figure 3: Proposed alternate optical connec<strong>to</strong>r, with a single MT<br />
ferrule. This connec<strong>to</strong>r will be useful on 3U <strong>VPX</strong> modules.<br />
Ano<strong>the</strong>r important aspect of <strong>the</strong> VITA 66.1 technology is that it only<br />
defines <strong>the</strong> positioning of MT ferrules. The MT ferrule allows <strong>the</strong> use<br />
of one or more optical fiber ribbons of that can each be comprised of<br />
up <strong>to</strong> 12 fibers. These fibers can be ei<strong>the</strong>r single mode or multi-mode.<br />
The data rate at which <strong>the</strong>se fibers can be driven is independent of<br />
<strong>the</strong> MT ferrule. However, <strong>the</strong> optical devices that are available <strong>to</strong>day<br />
<strong>to</strong> drive MT ribbon assemblies are readily available that drive each<br />
fiber at 10 or 14 Gbps and some are already available that drive each<br />
fiber at 28 Gbps. Any such device coupled <strong>to</strong> a fiber ribbon that is<br />
terminated with an MT ferrule will be accepted by <strong>the</strong> new VITA 66.1<br />
optical modules.<br />
Although <strong>the</strong> VITA 66.1 connec<strong>to</strong>r is ideal for 6U <strong>VPX</strong> backplanes, it<br />
is not a good solution for 3U <strong>VPX</strong> backplanes because it occupies an<br />
16 Engineers’ <strong>Guide</strong> <strong>to</strong> <strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong> <strong>2013</strong>
Table 1: Notional VITA 65 Channel Gbaud rate implementation timeline<br />
entire connec<strong>to</strong>r module. This is acceptable for 6U cards as shown in<br />
Figure 2 above. However, pins are precious in 3U. Therefore one connec<strong>to</strong>r<br />
company is preparing a proposed optical module that provides<br />
a single MT ferrule in half <strong>the</strong> space of a full 16 wafer <strong>VPX</strong> module.<br />
Figure 3 shows an example of a single MT ferrule implemented in a<br />
half size connec<strong>to</strong>r. This is much <strong>the</strong> same approach that was taken<br />
by <strong>the</strong> VITA 67.1 committee for <strong>the</strong>ir 4-cavity RF module.<br />
Figure 4: Embedded Server card from CSPI with provisions for VITA<br />
66.1 connectivity. (Courtesy CSPI).<br />
Figure 5: This 6U <strong>VPX</strong> switch card from Annapolis Microsystems is<br />
<strong>the</strong> first <strong>VPX</strong> switch capable of switching ei<strong>the</strong>r 40GBASE-KR4 E<strong>the</strong>rnet<br />
channels or 56Gbps InfiniBand FDR channels. (Courtesy Annapolis<br />
Micro Systems.)<br />
SPECIAL FEATURE<br />
Optical and Copper InfiniBand cross paths in<br />
<strong>the</strong> <strong>VPX</strong> backplane architecture<br />
In mid November 2012, <strong>the</strong> InfiniBand Trade Association<br />
made available <strong>to</strong> <strong>the</strong> public Release 1.3 of its Architectural<br />
Specification. This release includes <strong>the</strong> InfiniBand FDR<br />
electrical interface that supports 14 Gbps lanes as well as<br />
<strong>the</strong> FDR optical interface.<br />
<strong>VPX</strong> is at an interesting intersection of optical and copper<br />
technologies. At <strong>the</strong> present time, companies within <strong>the</strong><br />
VITA community have introduced backplanes and cards<br />
supporting both copper signaling and optical IO at <strong>the</strong><br />
InfiniBand data rate:<br />
<br />
<strong>VPX</strong> slots compliant <strong>to</strong> VITA 66.1 optical modules. Two backplanes<br />
are currently available <strong>to</strong> support <strong>the</strong>se higher data rates - one is a<br />
12-slot dual star and <strong>the</strong> o<strong>the</strong>r is a 4-slot mesh (see Figure 2).<br />
<br />
InfiniBand FDR, 56 Gbit/s Host Channel Adapter with failover<br />
capabilities via a 56 Gbp/s QSFP transceiver on <strong>the</strong> front panel or<br />
<strong>the</strong> VITA 66.1 optical interconnect <strong>to</strong> <strong>the</strong> backplane (see Figure 4).<br />
-<br />
Band FDR at 14 Gbps/lane on <strong>the</strong> data plane and PCIe Gen3 at 8 Gbps/<br />
lane on <strong>the</strong> expansion plane (see Figure 5).<br />
Currently, ANSI-VITA 65 recognizes data rates up <strong>to</strong> 6.25 Gbaud in<br />
three different steps shown for year 2012 in Table 1. As mentioned,<br />
<strong>the</strong>re are products on <strong>the</strong> market already that correspond <strong>to</strong> <strong>the</strong> lines<br />
shown for year <strong>2013</strong>. A big unknown is whe<strong>the</strong>r or not <strong>the</strong> copper<br />
data rates will continue <strong>to</strong> rise. Note, however that <strong>the</strong> optical data<br />
rates will continue <strong>to</strong> grow. This table represents <strong>the</strong> author’s opinion<br />
and is not sanctioned by VITA.<br />
Embedded computer pundits have been predicting <strong>the</strong> demise of<br />
copper interconnects for some time and those of in <strong>the</strong> industry<br />
have wondered when this would happen and what <strong>the</strong> future would<br />
look like. <strong>VPX</strong> is poised <strong>to</strong> offer a graceful transition from copper <strong>to</strong><br />
optical. It is well designed <strong>to</strong> provide all <strong>the</strong> power future cards will<br />
require. <strong>VPX</strong> also has features <strong>to</strong> support system management and<br />
distributed clocks as well as JTAG, and all of <strong>the</strong>se features will be<br />
required regardless of how <strong>the</strong> data plane communicates with o<strong>the</strong>r<br />
cards and <strong>the</strong> outside world. Now it is clear that if I/O goes optical,<br />
<strong>VPX</strong> has <strong>the</strong> necessary features <strong>to</strong> support that transition as well.<br />
Going slot <strong>to</strong> slot can also make use of <strong>the</strong> VITA 66.1 optical ribbon<br />
module.<br />
Michael Munroe is a Backplane Technical Specialist<br />
for Elma Bustronic Corporation. In addition<br />
<strong>to</strong> over 20 years of experience in <strong>the</strong> packaging<br />
and interconnect industry, Michael is an active<br />
member of <strong>the</strong> VITA Standards Organization, a<br />
professional member of <strong>the</strong> IEEE and currently<br />
serves as Secretary-Treasurer of PICMG.<br />
www.eecatalog.com/vme 17
SPECIAL FEATURE<br />
VITA 62 Power Supplies: Filling a<br />
Standards Gap for 3U <strong>VPX</strong> Systems<br />
The recently ratified VITA 62 standard provides clear definitions for power supply<br />
vendors and supports a powerful set of advanced features, making <strong>the</strong> mission-critical<br />
system designer’s job immensely easier.<br />
By Brian Roberts, Dawn <strong>VME</strong><br />
In <strong>to</strong>day’s defense electronics environment, systems designers rely<br />
on open standards <strong>to</strong> help <strong>the</strong>m deal with both compressed development<br />
schedules and <strong>the</strong> expectation of frequent technology upgrades.<br />
This is especially true for systems targeting smaller platforms where<br />
time <strong>to</strong> deployment can be sandwiched in<strong>to</strong> a one year window. The<br />
3U <strong>VPX</strong> board-level standard has evolved <strong>to</strong> fill this need.<br />
However, while <strong>the</strong> embedded systems community has embraced<br />
board-level open standards for processing modules, mezzanine<br />
cards, I/O pro<strong>to</strong>cols and backplane connections, power supplies have<br />
continued <strong>to</strong> be addressed in an ad hoc manner, without <strong>the</strong> guidance<br />
of an accepted standard. The recently ratified VITA 62 standard was<br />
developed <strong>to</strong> address this gap.<br />
As an accepted industry standard, VITA 62 promotes competition,<br />
reduces costs and advances technology with ready <strong>to</strong> deploy COTS<br />
(commercial off <strong>the</strong> shelf) power supply modules, allowing developers<br />
<strong>to</strong> rapidly integrate reliable power in<strong>to</strong> <strong>VPX</strong> system designs.<br />
A comprehensive power supply standard<br />
The VITA 62 power supply standard supports interoperability, configuration<br />
flexibility, advanced levels of reliability and sophisticated<br />
systems management. It ensures that power supply electrical and<br />
mechanical standards are compatible with <strong>the</strong> popular <strong>VPX</strong> system<br />
platform and assures that any standard-compliant power supply can<br />
be interchanged with any o<strong>the</strong>r, will fit mechanically in<strong>to</strong> <strong>the</strong> same<br />
chassis and will meet <strong>the</strong> same electrical standards.<br />
In scope, <strong>the</strong> standard defines a connec<strong>to</strong>r configuration, power<br />
generation requirements, and utility, functionality and form fac<strong>to</strong>r<br />
requirements for power supply modules mating <strong>to</strong> a <strong>VPX</strong> backplane.<br />
At a detailed level, VITA 62 specifies power supply input and output<br />
voltages and currents, pin-outs, slot size, and mechanical configurations<br />
for <strong>VPX</strong> systems, and allocates specific pins for multiple power<br />
supply load sharing capability. The VITA 62 connec<strong>to</strong>r is specified<br />
so as <strong>to</strong> withstand frequent reconnect cycles, while <strong>the</strong> slot and<br />
mechanical sizes and <strong>to</strong>lerances are defined <strong>to</strong> achieve <strong>the</strong> tight fit<br />
required for efficient conduction cooling.<br />
The VITA 62 3U pin out specifies power and signal connections. There<br />
are also User Defined (UD) pins allotted for application-specific tasks<br />
(marked as OPT(x) in Figure 1),<br />
blades and receptacles and pins<br />
provided for power in and out.<br />
This figure shows <strong>the</strong> VITA 62<br />
3U compliant connec<strong>to</strong>r pinout<br />
(card view). UD (User Defined)<br />
pins are available for optional,<br />
application specific purposes.<br />
Power blade and receptacles are<br />
provided for power supply outputs<br />
PO1 +12V, PO2 +3.3V and<br />
PO3 +5V. These voltages are also<br />
provided on pins as auxiliary<br />
outputs. VBAT is provided for<br />
memory back-up battery.<br />
VITA 62 also exploits <strong>the</strong><br />
effectiveness of interlocking<br />
standards, referencing definitions<br />
that already exist and are<br />
widely used. It supports VITA<br />
46.11 IPMB (Intelligent Platform<br />
Management Bus), VITA 48 REDI<br />
(Ruggedized Enhanced Design<br />
Implementation) and provides<br />
guidelines for adherence <strong>to</strong><br />
MIL-STD-461F (electromagnetic<br />
interference), MIL-STD-704F<br />
(electrical standards and holdup<br />
Figure 1: VITA 62 compliant connec<strong>to</strong>r<br />
pin out (card view). Note<br />
<strong>the</strong> voltage options for 12V, 3.3V<br />
and 5V (PO1-PO3) along with <strong>the</strong><br />
User Defined (UD) pins.<br />
time) and MIL-STD-810F (mission critical ruggedization) compliance.<br />
Interlocking With Electrical And Harsh Environment<br />
Standards<br />
VITA 62 supports MIL-STD-704F which sets electrical standards<br />
for military aircraft such as AC voltage power fac<strong>to</strong>r, harmonics,<br />
dis<strong>to</strong>rtion spectrum and load balance currents, DC voltage, currents,<br />
ripple, transients, ground configuration and <strong>the</strong> crucial <strong>to</strong> mission<br />
critical deployment holdup time, which allocates for power on “meltdown.”<br />
Chassis, electrical and power supply return must be separate<br />
<strong>to</strong> one point.<br />
18 Engineers’ <strong>Guide</strong> <strong>to</strong> <strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong> <strong>2013</strong>
Also supported is VITA 48<br />
REDI (Ruggedized Enhanced<br />
Design Implementation). Part<br />
of VITA 48 has a defined pitch<br />
–<strong>the</strong> interval on a backplane<br />
of each module–of 1.0”. This is<br />
an increase over <strong>the</strong> 0.8” pitch<br />
of <strong>the</strong> older <strong>VME</strong> standard, a<br />
change which permits higher<br />
power levels and taller components.<br />
In addition, air, liquid,<br />
and conduction cooling parameters<br />
are defined within VITA 48<br />
<strong>to</strong> provide uniform packaging<br />
alignment.<br />
Although all semiconduc<strong>to</strong>r<br />
devices are subject <strong>to</strong> damage by<br />
ionizing radiation, high density<br />
semiconduc<strong>to</strong>rs are <strong>the</strong> easiest<br />
<strong>to</strong> be damaged by ionizing radia- Figure 2: Typical VITA 62 3U<br />
tion. A NED (Nuclear Event<br />
Detect) input is supported by<br />
electrical configuration<br />
VITA 62 <strong>to</strong> shut down power during such an event.<br />
SENSE pins permit feedback of +12V, +5V and +3.3V <strong>to</strong> <strong>the</strong> power<br />
supply. These voltages compensate for IR (current-resistance) drop<br />
at <strong>the</strong> connection and provide correction <strong>to</strong> some<br />
of <strong>the</strong> transients produced by load surges. SHARE<br />
pins facilitate current balancing between power<br />
supplies operated in parallel. The VBAT pin permits<br />
an on board battery <strong>to</strong> supply power <strong>to</strong> system nonvolatile<br />
memory. This is important <strong>to</strong> save system<br />
CMOS settings and o<strong>the</strong>r low power volatile s<strong>to</strong>rage.<br />
The block diagram in Figure 2 shows VITA 62 3U<br />
power supply electrical connections. VS1, VS2 and<br />
VS3 show DC outputs +12V, +3.3V and +5V respectively.<br />
Current sharing signals represented by <strong>the</strong><br />
SHARE signals are sent between power supplies in a<br />
sharing configuration. SENSE lines feedback signals<br />
<strong>to</strong> regulate power output voltages VS1, VS2 and VS3<br />
<strong>to</strong> <strong>the</strong> remote load. VITA 46.11 Bus is <strong>the</strong> I2C link <strong>to</strong><br />
<strong>the</strong> Chassis Manager. The NED input indicates <strong>the</strong><br />
presence of Nuclear Event. ACL and ACN are AC line<br />
(hot) and neutral.<br />
Intelligent Platform Management Bus<br />
support<br />
VITA 46.11 IPMB (Intelligent Platform Management<br />
Bus) is focused on ensuring reliable systems<br />
operation and is referenced in VITA 62. VITA 46.11 specifies that<br />
an I2C serial bus be used for communication between modules and<br />
<strong>the</strong> Intelligent Chassis Manager. This link facilitates sophisticated<br />
systems management through onboard processor control and<br />
moni<strong>to</strong>ring. Moni<strong>to</strong>ring on board sensors permits an Error Log <strong>to</strong><br />
be created that flags conditions that may have contributed <strong>to</strong> failure.<br />
SPECIAL FEATURE<br />
Conditions in <strong>the</strong> field can never fully be anticipated by any test since<br />
an unusual set of circumstances may act <strong>to</strong>ge<strong>the</strong>r <strong>to</strong> cause system<br />
failure. The Error Log produced by <strong>the</strong> Intelligent Chassis Manager<br />
is thus extremely important because it documents conditions in <strong>the</strong><br />
field that led <strong>to</strong> failure. It is important that <strong>the</strong> cause of failure be<br />
identified for future maintenance and design. The design engineer<br />
must be fully aware of events leading <strong>to</strong> failure. This is where <strong>the</strong><br />
Error Log is important, it keeps a log of critical parameters such as<br />
vibration, humidity, and temperature.<br />
For example, <strong>the</strong> Error Log may indicate that a particular board<br />
has a problem with temperature caused by cooling fans. The System<br />
Manager can <strong>the</strong>n be programmed <strong>to</strong> lower <strong>the</strong> fan speed so that <strong>the</strong><br />
temperature of <strong>the</strong> board is just below its upper specification.<br />
Critical Vita 62 Power Supply Characteristics<br />
VITA 62 power supplies have unique challenges in modern deployment<br />
systems. Smart VITA 62 power supplies have voltage rail<br />
control which enables <strong>the</strong>m <strong>to</strong> be individually sequenced, up and<br />
down. This provides critical sequencing <strong>to</strong> CPU cards, FPGA cards<br />
and o<strong>the</strong>r VITA 65 cards, which are sensitive <strong>to</strong> which voltage comes<br />
up first.<br />
Power sharing between two or more supplies can be advantageous<br />
if <strong>to</strong>tal current requirements exceed that which can be delivered by<br />
a single supply. It can also be advantageous if <strong>the</strong>re is at least one<br />
supply more than that required. Referred <strong>to</strong> as N+1 redundancy, if<br />
Figure 3: Examples of 3U VITA 62-compliant power supplies from Dawn <strong>VME</strong> Products.<br />
The PSC-6236 air-cooled design on <strong>the</strong> left includes a front panel with connections, while<br />
<strong>the</strong> equivalent conduction-cooled LRU on <strong>the</strong> right clearly shows wedgelocks for cold<br />
plate cooling. These compact PSUs can source 400 W over a wide temperature range.<br />
one power supply fails <strong>the</strong> system can still supply <strong>the</strong> required current<br />
using <strong>the</strong> remaining functional supplies. It also means that<br />
power supplies can be hot swapped. In addition, N+1 redundancy<br />
reduces <strong>the</strong> power dissipated by each supply and reduced power<br />
means a lower onboard temperature.<br />
www.eecatalog.com/vme 19
SPECIAL FEATURE<br />
Paralleling power supplies requires that <strong>the</strong> output current of each<br />
power supply’s voltage rail be balanced. This is a task accomplished by<br />
a SHARE reference signal. An analog reference signal for each of <strong>the</strong><br />
voltage rails is connected between each of <strong>the</strong> system power supplies<br />
through <strong>the</strong> appropriate SHARE pin.<br />
VITA 62 compliant solutions<br />
The first implementations of VITA 62 compliant solutions are now<br />
appearing on <strong>the</strong> market. An example is shown in Figure 3, <strong>the</strong><br />
Dawn PSC-6236 Universal AC Input VITA 62 3U Power Supply for<br />
air or conduction cooled systems. Designed for mission critical<br />
applications, it delivers up <strong>to</strong> 400 Watts of output power over a wide<br />
temperature range.<br />
New products like this represent a standardized power supply ready<br />
<strong>to</strong> deliver in harsh mission critical environments.<br />
<strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong> ONLINE<br />
A short summary of <strong>the</strong> benefits includes:<br />
<br />
<br />
<br />
<br />
<br />
and maintainability.<br />
<br />
Brian Roberts has 22 years of design experience<br />
in Silicon Valley developing electronic products for<br />
commercial and defense applications. Over this<br />
period, he has worked with clients in <strong>the</strong> areas of<br />
system engineering, power supply design, and o<strong>the</strong>r<br />
printed circuit board based solutions. Brian has<br />
been with <strong>the</strong> team at Dawn <strong>VME</strong> Products since 2005.<br />
Dawn <strong>VME</strong> Products 510-657-4444 www.dawnvme.com<br />
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Tackling <strong>the</strong> Challenge of Building Smaller,<br />
Lighter, and More Efficient Componentbased<br />
Avionics with CFD<br />
Component <strong>the</strong>rmal issues have <strong>to</strong> be managed in order<br />
<strong>to</strong> maintain high reliability in military aircraft and<br />
avionics environments. The ratio and tradeoff of size,<br />
weight, and power (SWaP) is a crucial system design<br />
consideration in modern defense systems. As aircraft<br />
are fitted with an increasing amount of electronics and<br />
with more components, <strong>the</strong>y become heavier—and<br />
more weight can mean less time in <strong>the</strong> target zone. But<br />
<strong>the</strong>y also become hotter as size density increases. The<br />
<strong>the</strong>rmal behavior can also vary from component vendor<br />
<strong>to</strong> vendor but also over <strong>the</strong> component aging process.<br />
This is due <strong>to</strong> <strong>the</strong> degradation of <strong>the</strong> materials used in<br />
<strong>the</strong> component and <strong>the</strong> influence of <strong>the</strong>rmal management<br />
over <strong>the</strong> lifetime of <strong>the</strong> component.<br />
A good understanding of semiconduc<strong>to</strong>r components’<br />
<strong>the</strong>rmal behavior is important because it is crucial <strong>to</strong><br />
<strong>the</strong> optimum <strong>the</strong>rmal design for a low SWaP ratio. Insufficient<br />
understanding of a component can lead not only<br />
<strong>to</strong> an oversized cooling system but also <strong>to</strong> a bad choice<br />
of <strong>the</strong> selected components intended for <strong>the</strong> lifetime system use.<br />
Thermal Characterization of Semiconduc<strong>to</strong>r Components<br />
A good way <strong>to</strong> begin formal component characterization is <strong>to</strong> create<br />
a “smart” implementation of <strong>the</strong> static test version of <strong>the</strong> Joint Electron<br />
Devices Engineering Council (JEDEC) JESD51-1 electrical test<br />
method [1] that allows for continuous measurement during a heating<br />
or cooling transient.<br />
The characterization method uses <strong>the</strong> temperature sensitivity of<br />
<strong>the</strong> semiconduc<strong>to</strong>r component. This sensitivity has <strong>to</strong> be measured<br />
before <strong>the</strong> actual characterization can begin, and it should be done<br />
according <strong>to</strong> <strong>the</strong> JESD51-14 standard <strong>to</strong> record <strong>the</strong> cooling curve of<br />
<strong>the</strong> component.<br />
Once <strong>the</strong> measured temperature sensitivity parameters (TSP) are<br />
obtained, <strong>the</strong> component can be characterized by powering up <strong>the</strong><br />
device (heating it) with PH [Watt] until a steady state is reached.<br />
Once <strong>the</strong> junction temperature TJ is constant, <strong>the</strong> heating current<br />
is switched off <strong>to</strong> a lower measuring current that creates a low<br />
SPECIAL FEATURE<br />
Computational Fluid Dynamics software helps defense systems designers doubly:<br />
it aids in optimizing component SWaP, and models device <strong>the</strong>rmal behavior across<br />
time and vendors.<br />
By Boris Marovic, Product Marketing Manager,<br />
Men<strong>to</strong>r Graphics<br />
Figure 1: Cooling curve of a sample component.<br />
measuring power PM [Watt]. The measuring current is negligible<br />
compared <strong>to</strong> <strong>the</strong> heating current. This sharp power step introduces<br />
<strong>the</strong> cooling process and is recorded until a steady state is reached.<br />
From <strong>the</strong> temperature sensitivity of <strong>the</strong> component and <strong>the</strong> lower<br />
steady state temperature, ideally realized with a cold plate, <strong>the</strong> transient<br />
cooling curve is created as shown in Figure 1. The temperature<br />
difference ΔT (Kelvin) is derived by <strong>the</strong> temperature sensitivity of<br />
<strong>the</strong> component; and <strong>the</strong> <strong>the</strong>rmal resistance of <strong>the</strong> component can be<br />
calculated as shown in <strong>the</strong> equation: Rth = ΔT/(PH ‒ PM).<br />
From <strong>the</strong> recorded cooling curve, a structure function can be<br />
derived as shown in Figure 2. This structure function shows <strong>the</strong>rmal<br />
resistance and capacitance of <strong>the</strong> single component layers from<br />
junction <strong>to</strong> environment. The vertical sections of <strong>the</strong> curve show<br />
<br />
[K/W] materials such as metallic layers in <strong>the</strong> component structure;<br />
whereas horizontal lines show higher <strong>the</strong>rmal resistance layers such<br />
as die attach, glue, grease, and o<strong>the</strong>r <strong>the</strong>rmal interface materials<br />
(TIM), PCB layers, and so on.<br />
www.eecatalog.com/vme 21
SPECIAL FEATURE<br />
Figure 2: Structure function of a sample component showing <strong>the</strong>rmal capacitance<br />
(vertically) and <strong>the</strong>rmal resistance (horizontally)<br />
Each step of <strong>the</strong> structure function can <strong>the</strong>n be described as a resis<strong>to</strong>r<br />
and capaci<strong>to</strong>r in a Cauer ladder as shown in Figure 3. By specifying <strong>the</strong><br />
final node “case” of <strong>the</strong> component in <strong>the</strong> curve, a compact <strong>the</strong>rmal<br />
model can be derived and used for accurate component representation<br />
in a simulation for <strong>the</strong> <strong>the</strong>rmal resistance from junction <strong>to</strong> case.<br />
Lifetime Testing and Failure Characterization<br />
Component characterization is important <strong>to</strong> be able <strong>to</strong> judge <strong>the</strong><br />
quality of components for two reasons. Firstly, manufacturers should<br />
characterize components production by taking samples <strong>to</strong> determine<br />
if <strong>the</strong> production process is running without errors. Secondly, system<br />
integra<strong>to</strong>rs should also characterize<br />
components used because naturally<br />
component properties can vary from<br />
vendor <strong>to</strong> vendor and such variation can<br />
affect SWaP tradeoffs.<br />
With <strong>the</strong> necessity of high reliability<br />
for safety critical components, it’s<br />
important <strong>to</strong> ensure perfect functioning<br />
of <strong>the</strong> system over its lifetime. A system’s<br />
lifetime can be several thousand<br />
hours under constantly changing<br />
environmental conditions such as temperature<br />
variations and shocks, pressure<br />
variations, humidity, and so on. These<br />
conditions increase <strong>the</strong> aging process<br />
and can result in component or material<br />
failures. Material degrades over time<br />
because of <strong>the</strong>se fluctuations and can<br />
result in TIM degradation, die delamination,<br />
package hermeticity failure, and<br />
o<strong>the</strong>r undesirable behavior.<br />
When characterizing components, <strong>the</strong>y are usually exposed <strong>to</strong> harsh<br />
environments that are even worse than <strong>the</strong> actual environments in<br />
order <strong>to</strong> accelerate <strong>the</strong> aging process and identify degradation. This<br />
Figure 3: Step by step from component <strong>to</strong> Cauer ladder.<br />
is called highly accelerated life testing (HALT) and can<br />
shorten <strong>the</strong> original testing time by several orders of<br />
magnitude.<br />
Thermal characterization is a nondestructive measurement<br />
and can reveal failures caused by this process<br />
inside <strong>the</strong> component. If, for example, <strong>the</strong> die attach is<br />
degrading and <strong>the</strong> die delaminating, it will result in an<br />
increased <strong>the</strong>rmal resistance. Such an increase of <strong>the</strong><br />
<strong>the</strong>rmal resistance increases <strong>the</strong> junction temperature of<br />
<strong>the</strong> component because <strong>the</strong> heat cannot be dissipated as<br />
it is for a healthy component. As a result, <strong>the</strong> component<br />
is likely <strong>to</strong> fail sooner than a healthy component, as long<br />
excessive temperature increases <strong>the</strong> aging process even<br />
more.<br />
As <strong>the</strong> component changes and heat builds up, <strong>the</strong> failure<br />
process has begun. As well, <strong>the</strong> <strong>the</strong>rmal management<br />
system that was designed for <strong>the</strong> system is no longer<br />
efficient and powerful enough <strong>to</strong> cope with basically a “different”<br />
component than <strong>the</strong> originally designed component. If in addition<br />
<strong>the</strong> system has <strong>to</strong> function in a worse-case scenario of a failing cooling<br />
system, <strong>the</strong> situation becomes even worse.<br />
The Men<strong>to</strong>r Graphics T3Ster® <strong>the</strong>rmal transient tester uses a measurement<br />
methodology for <strong>the</strong> junction-<strong>to</strong>-case <strong>the</strong>rmal resistance<br />
of power semiconduc<strong>to</strong>r devices that makes it possible <strong>to</strong> <strong>the</strong>rmally<br />
characterize a component with high accuracy and repeatability. The<br />
result is far richer data that is measured from much earlier in <strong>the</strong><br />
junction temperature transient than possible with o<strong>the</strong>r techniques.<br />
The T3Ster post-processing software fully supports <strong>the</strong> JESD51-14<br />
standard for junction-<strong>to</strong>-case <strong>the</strong>rmal resistance measurement [2],<br />
allowing <strong>the</strong> temperature versus time curve obtained directly from<br />
<strong>the</strong> measurement <strong>to</strong> be re-cast as “structure functions” (described in<br />
JESD51-14 Annex A), and <strong>the</strong>n au<strong>to</strong>matically find <strong>the</strong> value of <strong>the</strong><br />
22 Engineers’ <strong>Guide</strong> <strong>to</strong> <strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong> <strong>2013</strong>
Figure 4: Tecnobit special chassis that allowed avionics <strong>to</strong> be housed<br />
in a very small space, optimized using CFD software dedicated for<br />
electronics cooling applications.<br />
junction-<strong>to</strong>-case <strong>the</strong>rmal resistance. The au<strong>to</strong>matically generated<br />
dynamic compact <strong>the</strong>rmal model of <strong>the</strong> component can <strong>the</strong>n be<br />
applied directly in computational fluid dynamics (CFD) simulation<br />
software embedded in an MCAD system.<br />
CFD Saves Time and Money<br />
Engineers at Tecnobit used CFD software <strong>to</strong> help <strong>the</strong>m understand<br />
and optimize <strong>the</strong> different heat transfer paths and mechanisms<br />
between electronic components and <strong>the</strong> ambient surroundings in<br />
<strong>the</strong> harsh environmental conditions found in aircraft. Designing<br />
appropriate cooling systems is necessary <strong>to</strong> ensure reliability of<br />
avionics equipment as power and heat dissipation issues increase.<br />
Weight minimization and space optimization were Tecnobit’s key<br />
design goals, and <strong>the</strong>y avoid using cooling fans wherever possible<br />
<strong>to</strong> minimize possible causes of failure, so <strong>the</strong>rmal management is a<br />
major challenge from <strong>the</strong> very first design phase.<br />
In <strong>the</strong> example shown in Figure 4, engineers at Tecnobit designed<br />
a special chassis enabling <strong>the</strong> avionics <strong>to</strong> be housed in a reduced<br />
space (maximum dimension close <strong>to</strong> 10 cm). The system was <strong>to</strong>tally<br />
sealed, so <strong>the</strong> task was <strong>to</strong> maximize heat transfer by conduction,<br />
radiation, and natural convection from <strong>the</strong> outside surface. The preliminary<br />
design was not <strong>the</strong>rmally acceptable, and so <strong>the</strong>y modified<br />
<strong>the</strong> internal chassis structure <strong>to</strong> increase heat conduction from <strong>the</strong><br />
components <strong>to</strong> <strong>the</strong> chassis walls.<br />
They also modified <strong>the</strong> outer surfaces of <strong>the</strong> chassis using special<br />
fins, sand blasting treatment, and electrostatic painting <strong>to</strong> enhance<br />
convection and radiation exchange with <strong>the</strong> external ambient. By<br />
using CFD, <strong>the</strong>y were able <strong>to</strong> save time and money because no time<br />
was wasted building unfeasible pro<strong>to</strong>types, and <strong>the</strong> CFD simulations<br />
SPECIAL FEATURE<br />
enabled <strong>the</strong>m <strong>to</strong> optimize <strong>the</strong> <strong>the</strong>rmal design rapidly<br />
and reduce component junction temperatures by 40°C<br />
compared with <strong>the</strong> initial design.<br />
References<br />
1. JEDEC Standard JESD51-1; “Integrated Circuit Thermal Measurement<br />
Method – Electrical Test Method (Single Semiconduc<strong>to</strong>r<br />
Device)”, http://www.jedec.org/standards-documents/docs/jesd-<br />
51-1, JEDEC, Dec. 1995.<br />
2. JEDEC Standard JESD51-14: “Transient Dual Interface Test<br />
Method for <strong>the</strong> Measurement of <strong>the</strong> Thermal Resistance Junction-<br />
To-Case of Semiconduc<strong>to</strong>r Devices with Heat Flow through a<br />
Single Path”, http://www.jedec.org/standards-documents/<br />
results/JESD51-14, JEDEC, Nov. 2010.<br />
Boris Marovic is product marketing<br />
manager for aerospace and defense<br />
in <strong>the</strong> Men<strong>to</strong>r Graphics Mechanical<br />
Analysis Division. He studied aerospace<br />
engineering at <strong>the</strong> University of<br />
Stuttgart, majoring in aircraft design<br />
and aerodynamics, and started with Men<strong>to</strong>r Graphics as an application<br />
engineer where he was responsible for support, training,<br />
consulting, and software demonstration. In his current role, he is<br />
responsible for future product enhancements and requirements, as<br />
well as cus<strong>to</strong>mer relations and marketing activities for <strong>the</strong> aerospace<br />
and defense industries. He is located in Frankfurt, Germany.<br />
www.eecatalog.com/vme 23
SPECIAL FEATURE<br />
Bringing HPC Technology <strong>to</strong> Mil-Aero,<br />
Embedded Deployment<br />
Embedded HPEC systems are following <strong>the</strong> commercial HPC trend <strong>to</strong>wards Intel x86<br />
architectures running Linux, but deployed on VITA’s rugged Open<strong>VPX</strong> form fac<strong>to</strong>r with<br />
RapidIO interconnect fabrics.<br />
By Eran Strod, System Architect, Curtiss-Wright Controls<br />
Defense Solutions<br />
The five hundred of <strong>the</strong> fastest computers<br />
in <strong>the</strong> world, based on <strong>the</strong><br />
Linpack benchmark, are featured on a<br />
website called <strong>to</strong>p500.org. Recently,<br />
91% of <strong>the</strong> commercial high-performance<br />
computing (HPC) systems on<br />
<strong>the</strong> list were running Linux, nearly<br />
half (44%) were using E<strong>the</strong>rnet and<br />
over 80% were using an x86 architecture<br />
CPU. These systems are used in<br />
scientific, complex simulation, and<br />
many o<strong>the</strong>r computationally intensive<br />
applications. It’s a fair bet that<br />
<strong>the</strong>se would be <strong>the</strong> architectures that<br />
sensor systems like high-end radar,<br />
SIGINT and o<strong>the</strong>r sensor integra<strong>to</strong>rs<br />
would be using if <strong>the</strong>ir applications<br />
requirements were not SWaP- and<br />
cost-constrained.<br />
In contrast <strong>to</strong> <strong>the</strong>se “big iron” systems,<br />
for many years embedded vendors and<br />
system integra<strong>to</strong>rs built large, distributed systems around niche-oriented<br />
architectures such as PowerPC, real-time operating systems,<br />
and <strong>the</strong> not-yet-mainstream RapidIO serial fabric. Sensor modes<br />
developed for one platform could not be used on any o<strong>the</strong>r. Software<br />
was platform-specific and was difficult <strong>to</strong> port and maintain. This<br />
constrained innovation. Different platforms could not talk <strong>to</strong> each<br />
o<strong>the</strong>r so data sharing was difficult, resulting in lost opportunities <strong>to</strong><br />
take advantage of actionable information.<br />
But Intel’s investment in AVX changed that. Advanced Vec<strong>to</strong>r Extensions<br />
(AVX) is an extension <strong>to</strong> <strong>the</strong> x86 instruction set architecture<br />
that makes <strong>the</strong> Single Instruction Multiple Data (SIMD) x86 engine<br />
suitable for floating point-intensive calculations in multimedia,<br />
scientific and financial applications. In short: Intel-based CPUs are<br />
more than suitable for high-speed, floating point intensive calculations.<br />
As well, <strong>the</strong> OpenFabrics Alliance has created open source<br />
software that, along with development by Curtiss-Wright, allows<br />
interfacing RDMA-based E<strong>the</strong>rnet layers <strong>to</strong> <strong>the</strong> very common<br />
Figure 1: RapidIO enables a cross-platform ecosystem composed of various CPU/GPU vendors, software,<br />
and sensors.<br />
RapidIO-based embedded boards deployed in many SWaP-constrained<br />
sensor platforms.<br />
HPEC is Embedded HPC<br />
With this new-found performance, <strong>the</strong> large node parallel computing<br />
systems that are specifically oriented <strong>to</strong> sensor computing<br />
are moving away from PowerPC <strong>to</strong> Intel. This gives <strong>the</strong> application<br />
developer access <strong>to</strong> a broad software ecosystem and opens up a whole<br />
new set of possibilities for open architecture development.<br />
The shift <strong>to</strong> Intel CPUs allows sensor computing architectures <strong>to</strong><br />
more easily use Linux. While it’s true that Linux practically runs on<br />
every processor architecture known (and probably some unknown),<br />
<strong>the</strong> marriage of Intel and Linux provides <strong>the</strong> most seamless path <strong>to</strong><br />
adopting software components developed for HPC. The vast majority<br />
of HPC systems run Linux and Intel, and <strong>the</strong> majority of open source<br />
projects also focus on this architecture. With Linux/Intel as <strong>the</strong> basis<br />
of <strong>the</strong> Open<strong>VPX</strong> computing standard, back-end sensor processing<br />
that needs <strong>to</strong> be able <strong>to</strong> scale <strong>to</strong> many nodes can take advantage of<br />
commercial HPC’s software ecosystem (Figure 1).<br />
24 Engineers’ <strong>Guide</strong> <strong>to</strong> <strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong> <strong>2013</strong>
The process of adapting HPC technologies <strong>to</strong> <strong>the</strong> embedded space has<br />
recently been described as high-performance embedded computing<br />
(HPEC). Several vendors in COTS computing, including Curtiss-<br />
Wright, use <strong>the</strong> term HPEC <strong>to</strong> mean embedded HPC. Just as HPC<br />
is synonymous with <strong>the</strong> his<strong>to</strong>rical term “supercomputing,” HPEC<br />
systems are <strong>the</strong> SWaP-constrained variant of supercomputers. In<br />
<strong>the</strong> defense computing market, <strong>the</strong> highest performing Open<strong>VPX</strong><br />
systems, from vendors like Curtiss-Wright, fit 28 Intel CPUs (112<br />
cores) in a 16-slot chassis, interconnected with a 224 GB/sec dualstar<br />
system fabric (Figure 2). But it’s not only about CPUs, buses and<br />
interconnects. HPEC is about being able <strong>to</strong> run <strong>the</strong> same software<br />
that is used in HPC.<br />
Fabric Discontinuity – Software Continuity<br />
HPC is dominated by E<strong>the</strong>rnet and InfiniBand, while HPEC 6U<br />
Open<strong>VPX</strong> computing has been and continues <strong>to</strong> be dominated by<br />
RapidIO. This apparent discontinuity<br />
has been one of <strong>the</strong> major<br />
roadblocks <strong>to</strong> bringing HPC technologies<br />
<strong>to</strong> <strong>the</strong> HPEC world as <strong>the</strong><br />
fabric has traditionally had a major<br />
impact on software architecture.<br />
The first thing <strong>to</strong> consider is why<br />
stick with RapidIO in <strong>the</strong> face of<br />
o<strong>the</strong>r reasonably good options?<br />
The answer is simple: RapidIO<br />
dominates telecommunications<br />
DSP computing which faces many<br />
of <strong>the</strong> same constraints as military<br />
DSP. Even better, RapidIO is<br />
backed by a volume commercial<br />
market. IDT, <strong>the</strong> leading RapidIO<br />
switch vendor, just announced<br />
that <strong>the</strong>y have shipped 2.5 million<br />
RapidIO switches. RapidIO has a<br />
dominant position in <strong>the</strong> DSP processing<br />
that is essential <strong>to</strong> 4G and<br />
3G wireless base stations. RapidIO<br />
has captured virtually 100% of <strong>the</strong><br />
3G market in China, <strong>the</strong> fastest<br />
growing telecom market. To put<br />
it ano<strong>the</strong>r way, when you talk on<br />
your cell phone, <strong>the</strong>re is something<br />
like a 90% chance that <strong>the</strong> bits that represent your voice are at some<br />
point transmitted between two DSP processors over a RapidIO link.<br />
There are a number of reasons why RapidIO makes sense in <strong>the</strong> context<br />
of HPEC Open<strong>VPX</strong> computing:<br />
<br />
saving SWaP and cost.<br />
<br />
performance<br />
<br />
<br />
choice in HPC, it is a point technology in Open<strong>VPX</strong> HPEC. Unlike<br />
Figure 2: Curtiss-Wright showcasing 224GB/s dual-star fabric with<br />
28 Intel CPUs (112 cores) in a mere 16-slot chassis.<br />
SPECIAL FEATURE<br />
alternatives such as E<strong>the</strong>rnet and RapidIO, InfiniBand is not<br />
anticipated (per simulation) <strong>to</strong> run reliably at 10 GHz over existing<br />
Open<strong>VPX</strong> technology. It will require a connec<strong>to</strong>r change which is a<br />
fairly involved and slow-moving process for an organization like VITA.<br />
There were two major challenges in getting RapidIO working in <strong>the</strong><br />
Intel environment. The first was a classic interconnect problem.<br />
PowerPC processors supported RapidIO natively, but Intel did not,<br />
so a bridge was needed. The IDT Tsi721 provided this critical piece<br />
of technology. The Tsi721 converts from PCIe <strong>to</strong> RapidIO and vice<br />
versa and provides full line rate bridging at 20 Gbaud. Using <strong>the</strong><br />
Tsi721 designers can develop heterogeneous systems that leverage<br />
<strong>the</strong> peer <strong>to</strong> peer networking performance of RapidIO while at <strong>the</strong><br />
same time using multiprocessor clusters that may only be PCIe<br />
enabled. Using <strong>the</strong> Tsi721, applications that require large amounts<br />
of data transferred efficiently without processor involvement can be<br />
executed using <strong>the</strong> full line rate<br />
block DMA+Messaging engines of<br />
<strong>the</strong> Tsi721.<br />
The second major challenge related<br />
<strong>to</strong> RapidIO was software. RapidIO<br />
isn’t used in HPC so it doesn’t<br />
run <strong>the</strong> same software as those<br />
large cluster-based systems in <strong>the</strong><br />
<strong>to</strong>p500 that use fabrics like E<strong>the</strong>rnet<br />
and InfiniBand. InfiniBand<br />
vendors encountered <strong>the</strong>se same<br />
market constraints while trying <strong>to</strong><br />
grow beyond <strong>the</strong>ir niche. It’s hard<br />
<strong>to</strong> “fight” E<strong>the</strong>rnet. However, E<strong>the</strong>rnet<br />
wasn’t appropriate for <strong>the</strong><br />
highest performance HPC systems<br />
because of <strong>the</strong> CPU and/or silicon<br />
overhead associated with TCP<br />
offload. The answer came in <strong>the</strong> form<br />
of new pro<strong>to</strong>cols and new software.<br />
Open Fabric Alliance<br />
The OpenFabrics Alliance (OFA)<br />
was formed <strong>to</strong> promote Remote<br />
Direct Memory Acess (RDMA)<br />
functionality that allows E<strong>the</strong>rnet<br />
silicon <strong>to</strong> move packets from <strong>the</strong><br />
memory of one compute node <strong>to</strong> <strong>the</strong> memory of ano<strong>the</strong>r with very<br />
little CPU intervention. There are competing pro<strong>to</strong>cols <strong>to</strong> do this, but<br />
wisely, <strong>the</strong> OFA created a unified software layer called OFED which<br />
is supported by Intel, Chelseo, Mellanox and <strong>the</strong> o<strong>the</strong>r members of<br />
<strong>the</strong> E<strong>the</strong>rnet RDMA ecosystem. OFED is used in business, research<br />
and scientific environments that require highly efficient networks,<br />
s<strong>to</strong>rage connectivity and parallel computing.<br />
The OpenFabrics Enterprise Distribution (OFED) is open-source<br />
software for RDMA and kernel bypass applications. One of <strong>the</strong><br />
things that traditionally slowed E<strong>the</strong>rnet down and wasted <strong>the</strong> CPU<br />
was <strong>the</strong> need <strong>to</strong> copy a packet payload numerous times before it was<br />
shipped out <strong>the</strong> E<strong>the</strong>rnet interface (Figure 3). RDMA has eliminated<br />
www.eecatalog.com/vme 25
SPECIAL FEATURE<br />
Figure 3: OpenFabrics Enterprise Distribution (OFED) is open source<br />
RDMA that efficiently moves data from one application across a fabric<br />
<strong>to</strong> ano<strong>the</strong>r application, with minimal CPU overhead. Contrast this <strong>to</strong><br />
<strong>the</strong> multi-copy process of E<strong>the</strong>rnet, as shown here.<br />
<strong>the</strong> unnecessary copying so a packet can be transferred from one<br />
application <strong>to</strong> ano<strong>the</strong>r across <strong>the</strong> fabric with minimal CPU impact<br />
(single digit CPU utilization). The term that is used <strong>to</strong> describe OFED<br />
is software verbs, but for those readers not deeply in<strong>to</strong> software,<br />
verbs can be thought of like an API, a uniform software interface that<br />
provides application portability.<br />
OFED over RapidIO<br />
Our company has ported OFED <strong>to</strong> <strong>the</strong> IDT Tsi721 bridge which<br />
we believe represents <strong>the</strong> first time that OFED is running on <strong>the</strong><br />
industry de fac<strong>to</strong> standard IDT implementation of RapidIO (ie, not<br />
requiring non-mass market, proprietary FPGA IP controlled by a<br />
single vendor). This makes data movement over <strong>the</strong> RapidIO fabric<br />
indistinguishable from any o<strong>the</strong>r fabric that uses OFED, such as<br />
E<strong>the</strong>rnet, except that RapidIO operates at about twice <strong>the</strong> speed of<br />
10GbE. OFED support on a RapidIO system enables it <strong>to</strong> run a broad<br />
set of open source software components supported by members of<br />
<strong>the</strong> OFA and <strong>the</strong> open source community.<br />
One of <strong>the</strong> most important software components is middleware<br />
called Message Passing Interface (MPI) as supported by <strong>the</strong> open<br />
source project Open MPI. MPI is a message passing library interface<br />
specification and is a key enabling technology for <strong>the</strong> HPEC systems.<br />
MPI is developed by <strong>the</strong> MPI Forum, a large developer community<br />
comprised of both industry and research organizations. It is a<br />
portable, language independent pro<strong>to</strong>col that is used <strong>to</strong> share data<br />
among distributed processors. It has become a de fac<strong>to</strong> standard for<br />
communication among high-performance compute clusters and is<br />
used by many of <strong>the</strong> TOP500 most powerful computers in <strong>the</strong> world.<br />
MPI includes <strong>the</strong> following:<br />
<br />
<br />
<br />
<br />
<br />
<br />
<br />
<br />
guages<br />
Summary<br />
With OFED support, Open<strong>VPX</strong> systems based on <strong>the</strong> RapidIO data<br />
plane are able <strong>to</strong> seamlessly leverage <strong>the</strong> software ecosystem that<br />
has developed for High-Performance Computing as illustrated by<br />
TOP500 systems. This brings a new level of software portability <strong>to</strong><br />
<strong>the</strong> highest performing <strong>VPX</strong> systems as this new generation takes<br />
advantage of <strong>the</strong> wide ecosystem around Linux-based x86 computing.<br />
Eran Strod is a System Architect in <strong>the</strong> Advanced<br />
Multicomputing Group at Curtiss-Wright Controls<br />
Defense Solutions. He leads <strong>the</strong> HPEC<br />
Center of Excellence (HPEC COE) which provides<br />
middleware and <strong>to</strong>ols for high-performance DSP<br />
applications. Prior <strong>to</strong> joining CWCDS, while at<br />
Mercury Computer Systems, Eran served on <strong>the</strong> VITA Board of<br />
Direc<strong>to</strong>rs. Prior <strong>to</strong> that, at Freescale Semiconduc<strong>to</strong>r, Eran led <strong>the</strong><br />
group-wide RapidIO fabric initiative. His career in <strong>the</strong> embedded<br />
and software industries has recently passed <strong>the</strong> 20 year mark.<br />
26 Engineers’ <strong>Guide</strong> <strong>to</strong> <strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong> <strong>2013</strong>
SPECIAL FEATURE<br />
www.eecatalog.com/vme 27
SPECIAL FEATURE<br />
The Softer Side of Agile: Leading<br />
Collaborative Teams <strong>to</strong> Success<br />
By Nancy Y. Nee, PMP, CBAP, CSM Executive Direc<strong>to</strong>r, Project<br />
Management & Business Analysis Programs ESI International<br />
Edi<strong>to</strong>r’s note: The <strong>VME</strong> set of specifications is <strong>the</strong> result of 30 years’ collaboration<br />
between competi<strong>to</strong>rs and cus<strong>to</strong>mers; it is <strong>the</strong> successful progeny<br />
of a team-based standards process through <strong>the</strong> VITA organization. Though<br />
a relatively recent term, “Agile development” was being practiced by all<br />
those <strong>VME</strong> and <strong>VPX</strong> collabora<strong>to</strong>rs years ago. Today VITA remains more<br />
relevant than ever—with oft-attempted emulation by o<strong>the</strong>r standards<br />
bodies. We thought this article on Agile might give credence <strong>to</strong> some of<br />
VITA’s successful processes. Hats off and take a bow.<br />
— Chris A. Ciufo, Edi<strong>to</strong>r<br />
The Agile Manifes<strong>to</strong> places cus<strong>to</strong>mer collaboration over contract<br />
negotiation with a keen focus on a highly skilled, motivated team<br />
in constant interaction with <strong>the</strong> product and <strong>the</strong> cus<strong>to</strong>mer at every<br />
phase of <strong>the</strong> project. As a result of this collaborative, cus<strong>to</strong>mercentric<br />
view, Agile requires more than <strong>the</strong> technical expertise needed<br />
<strong>to</strong> ga<strong>the</strong>r requirements, and develop and test new product lines. It<br />
requires soft skills, leadership competencies and an understanding<br />
of how <strong>to</strong> apply those skills in a more malleable, people-focused setting.<br />
As practitioners know, collaboration brings a set of challenges.<br />
With <strong>the</strong> Agile approach, project managers are called upon <strong>to</strong> team<br />
up with cus<strong>to</strong>mers in a constant stakeholder dialogue.<br />
Constant cus<strong>to</strong>mer collaboration provides great opportunities <strong>to</strong><br />
measure project success by gauging <strong>the</strong> level of cus<strong>to</strong>mer satisfaction<br />
throughout each life cycle of <strong>the</strong> project. It creates <strong>the</strong> framework<br />
for faster time-<strong>to</strong>-market and a more nimble process <strong>to</strong> deliver successful<br />
project outcomes. When it comes <strong>to</strong> successful agile project<br />
delivery, collaboration also is key for <strong>the</strong> integrated project team.<br />
What Makes Good, Effective Collaboration?<br />
To begin <strong>to</strong> understand, we should first take a look at <strong>the</strong> 12 principles<br />
behind <strong>the</strong> Agile Manifes<strong>to</strong>. These principles, which are <strong>the</strong><br />
building blocks of Agile, identify three areas that lend <strong>the</strong>mselves <strong>to</strong><br />
successful collaboration. These principles are as follows:<br />
<br />
throughout <strong>the</strong> project.<br />
<br />
<strong>the</strong> environment and support <strong>the</strong>y need, and trust <strong>the</strong>m <strong>to</strong> get <strong>the</strong><br />
job done.<br />
<br />
and within a development team is face-<strong>to</strong>-face conversation.<br />
Based on <strong>the</strong> above three principles, successful collaboration among<br />
<strong>the</strong> team relies heavily on three key fac<strong>to</strong>rs:<br />
<br />
<br />
<br />
Feedback<br />
How does feedback work in a team environment? What is <strong>the</strong> most<br />
successful way <strong>to</strong> deliver it on an Agile project? Remember that feedback<br />
during <strong>the</strong> iterative development work of an Agile project must<br />
increase awareness and insight as well as foster innovation, yielding<br />
positive alternatives. Having <strong>the</strong> business as part of <strong>the</strong> core Agile<br />
project team creates <strong>the</strong> environment for continuous feedback and an<br />
opportunity <strong>to</strong> take positive risks in doing things differently, which<br />
is <strong>the</strong> very nature of why <strong>the</strong> project is being done in an Agile setting.<br />
Within <strong>the</strong> iteration work, it is essential <strong>to</strong> provide feedback that:<br />
<br />
<br />
<br />
For all members of <strong>the</strong> Agile project team, it is important <strong>to</strong> identify<br />
what <strong>to</strong> start, s<strong>to</strong>p and continue doing when it comes <strong>to</strong> iteration<br />
work. This is where effective feedback is most often used. You can<br />
easily integrate <strong>the</strong>se practices in<strong>to</strong> your daily stand up meetings <strong>to</strong><br />
prepare for <strong>the</strong> day’s work.<br />
Communication<br />
What makes effective communication? When it comes <strong>to</strong> communication,<br />
it is important <strong>to</strong> deliver information in a manner that is<br />
unders<strong>to</strong>od by <strong>the</strong> receiver, which means that we need <strong>to</strong> get past<br />
<strong>the</strong> receiver’s filters and ensure that <strong>the</strong> individual unders<strong>to</strong>od <strong>the</strong><br />
28 Engineers’ <strong>Guide</strong> <strong>to</strong> <strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong> <strong>2013</strong>
intended message. To get past those filters, we, as <strong>the</strong> sender of<br />
this message, have a responsibility <strong>to</strong> understand how our receiver<br />
takes in information. Does he communicate in a direct manner? Is<br />
she considerate in her messaging? Understanding your receiver’s<br />
communication style will help you provide feedback that enables<br />
effective dialogue.<br />
Motivation<br />
When you combine productive feedback with effective communication,<br />
<strong>the</strong> foundation for motivation has been established. Motivation<br />
is built on encouragement, partnership and compromise without<br />
making concessions that damage trust. Working <strong>to</strong>ge<strong>the</strong>r <strong>to</strong> ensure<br />
Designing with<br />
Intel ® Embedded<br />
Processors?<br />
Visit<br />
www.embeddedintel.com<br />
SPECIAL FEATURE<br />
that barriers, impediments and unrealistic expectations do not derail<br />
<strong>the</strong> creative impulses of <strong>the</strong> team brings about team unity. When <strong>the</strong><br />
Agile PM delegates <strong>to</strong> team members <strong>the</strong> authority and responsibility<br />
<strong>to</strong> complete features <strong>to</strong> which <strong>the</strong>y’ve committed, <strong>the</strong> Agile PM has<br />
created an environment of trust, partnership and self-directedness.<br />
By creating this environment, <strong>the</strong> team can discover <strong>the</strong>ir patterns<br />
of working.<br />
The soft side of Agile is just as important as <strong>the</strong> technical side of<br />
Agile. Both sets of skills are required and dependent upon each o<strong>the</strong>r<br />
for success in <strong>the</strong> Agile environment. Given what you just read, ask<br />
yourself, how soft is your Agile team?<br />
Nancy Nee, PMP, CBAP, CSM, Executive Direc<strong>to</strong>r,<br />
Project Management & Business Analysis<br />
Programs, ESI International, guides clients in<br />
<strong>the</strong> development and implementation of learning<br />
programs cus<strong>to</strong>mized <strong>to</strong> <strong>the</strong>ir specific needs. Her<br />
solutions reflect <strong>the</strong> insight of almost two decades<br />
of PM and BA experience in healthcare, information technology,<br />
financial services and energy. www.esi-intl.com<br />
© 2012 Reprinted with permission from ESI International.<br />
Winter <strong>2013</strong><br />
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Test and Analysis<br />
Teledyne LeCroy’s PCI Express ®<br />
Pro<strong>to</strong>col Analysis and Test Tools<br />
Compatible Operating Systems: Windows XP/7/8<br />
Specification Compliance: PCI Express Standards: 1.1, 2.0, and 3.0<br />
Whe<strong>the</strong>r you are a test engineer or firmware developer,<br />
Teledyne LeCroy’s Pro<strong>to</strong>col Analyzers will help you measure<br />
perfor mance and quickly identify, troubleshoot and<br />
solve your pro<strong>to</strong>col problems.<br />
Teledyne LeCroy’s products include a wide range of probe<br />
connec tions <strong>to</strong> support XMC, AMC, <strong>VPX</strong>, ATCA, microTCA,<br />
Express Card, MiniCard, Express Module, CompactPCI<br />
Serial, MidBus connec<strong>to</strong>rs and flexible mult-lead probes<br />
for PCIeR 1.0a, 1.1 (“Gen1” at 2.5GT/s), PCIe 2.0 (“Gen2” at<br />
5 GT/s) and PCIe 3.0 (“Gen3” at 8 GT/s).<br />
The high performance Summit Pro<strong>to</strong>col Ana lyzers feature<br />
<strong>the</strong> new PCIe virtualization extensions for SR-IOV and<br />
MR-IOV and in-band logic analysis. Decoding and test for<br />
SSD drive/devices that use NVM Express, SCSI Express<br />
and SATA Express are also supported.<br />
Teledyne LeCroy offers a complete range of pro<strong>to</strong>col test<br />
solutions, including analyzers, exercisers, pro<strong>to</strong>col test<br />
cards, and physical layer testing <strong>to</strong>ols that are certified<br />
by <strong>the</strong> PCI-SIG for ensuring compliance and compatibility<br />
with PCI Express specifications, including PCIe 2.0.<br />
FEATURES & BENEFITS<br />
◆ One but<strong>to</strong>n pro<strong>to</strong>col error check. Lists all pro<strong>to</strong>col errors<br />
found in a trace. Great starting point for beginning a<br />
debug session.<br />
◆ Flow control screen that quickly shows credit balances<br />
for root complex and endpoint performance bottlenecks.<br />
Easily find out why your add-in card is underperforming<br />
on its benchmarks.<br />
◆ LTSSM state view screen that accurately shows power<br />
state transitions with hyperlinks <strong>to</strong> drill down <strong>to</strong> more<br />
detail. Helps identify issues when endpoints go in<strong>to</strong> and<br />
out of low power states.<br />
◆ Full power management state tracking with Teledyne<br />
LeCroy’s Interposer technology. Prevents loosing <strong>the</strong><br />
trace when <strong>the</strong> system goes in<strong>to</strong> electrical idle.<br />
◆ Teledyne LeCroy’s Data View shows only <strong>the</strong> necessary<br />
pro<strong>to</strong>col handshaking ack/naks so you don’t have <strong>to</strong> be<br />
a pro<strong>to</strong>col expert <strong>to</strong> understand if root complexes and<br />
endpoints are communicating properly.<br />
◆ Real Time Statistics puts <strong>the</strong> analyzer in<strong>to</strong> a moni<strong>to</strong>ring<br />
mode showing rates for any user term chosen. Good for<br />
showing performance and bus utilization of <strong>the</strong> DUT.<br />
◆ Zero Time Search provides a fast way <strong>to</strong> search large<br />
traces for specific pro<strong>to</strong>col terms.<br />
◆ Config space can be displayed in its entirety so that<br />
driver registers can be verified.<br />
TECHNICAL SPECS<br />
◆ Analyzer<br />
Lanes supported: X1,x2,x4,x8,x16<br />
Speeds: 2.5GT/s, 5GT/s and 8GTs<br />
Probes/Interposers: active and passive PCIe slot,<br />
XMC, AMC, <strong>VPX</strong>, Express card, Express Module,<br />
Minicard, Mid-Bus, Multi-lead, External PCIe cable,<br />
CompactPCI Serial and o<strong>the</strong>rs<br />
Form fac<strong>to</strong>r: Card, Chassis<br />
◆ Exerciser<br />
Lanes supported: X1,x2,x4,x8,x16<br />
Speeds: 2.5GT/s, 5GT/s, 8GT/s<br />
Emulation: root complex and endpoint emulation<br />
◆ Pro<strong>to</strong>col Test Card<br />
Speeds: 2.5GT/s and 5GT/s operation<br />
Tests: Add-in-card test<br />
BIOS Platform Test<br />
Single Root IO Virtualization Test<br />
APPLICATION AREAS<br />
Mezzanine Boards, Add-in Cards, Host Carrier Systems,<br />
System Boards, Chips<br />
CONTACT INFORMATION<br />
Teledyne LeCroy<br />
Teledyne LeCroy<br />
3385 Scott Blvd.<br />
Santa Clara, CA, 95054<br />
USA<br />
1 800 909-7211 Toll Free<br />
1 408 727-6622 Fax<br />
psgsales @teledynelecroy.com<br />
www.teledynelecroy.com<br />
<br />
Test and Analysis
Backplanes<br />
SIE Computing Solutions<br />
<strong>VPX</strong> Backplanes<br />
VITA 46/48/65 Backplanes<br />
SIE Computing Solutions <strong>VPX</strong> backplanes are designed<br />
<strong>to</strong> <strong>the</strong> latest VITA 46, 48, 65 and OPEN <strong>VPX</strong> standards.<br />
The 5-slot I/O PLUS(TM) 3U <strong>VPX</strong> Full Mesh Backplane is<br />
designed for a wide array of <strong>VPX</strong> applications. The highly<br />
configurable backplane offers high-bandwidth in a compact<br />
size and provides greater I/O flexibility through I/O<br />
PLUS(TM), an innovative use of configurable I/O daughter<br />
cards <strong>to</strong> accommodate an array of <strong>VPX</strong> applications.<br />
FEATURES & BENEFITS<br />
◆ 5 slot full mesh<br />
◆ 2 dedicated I/O daughter card slots<br />
◆ Over 200 watts per slot<br />
◆ 28 layer board<br />
◆ Supports Gen2 PCIe<br />
TECHNICAL SPECS<br />
◆ J1: 10 fat pipes/high-speed differential channels<br />
◆ J2: 16 fat pipes/high-speed differential channels<br />
◆ J2: 20 single-ended signals<br />
sie-cs.com<br />
rugged & ready when you are<br />
AVAILABILITY<br />
CONTACT INFORMATION<br />
CONTACT INFORMATION<br />
SIE Computing Solutions<br />
10 Mupac Drive<br />
Brock<strong>to</strong>n, MA 02301<br />
USA<br />
800.926.8722 Toll Free<br />
508.588.6110 Telephone<br />
508.588.0498 Fax<br />
www.sie-cs.com<br />
Enclosures<br />
Backplanes<br />
System Integration<br />
& Cus<strong>to</strong>m Solutions<br />
cPCI<br />
<strong>VME</strong><br />
Open <strong>VPX</strong><br />
xTCA<br />
SIE Computing Solutions | 10 Mupac Drive | Brock<strong>to</strong>n, MA 02301 | 508-588-6110<br />
Engineers’ <strong>Guide</strong> <strong>to</strong> <strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong> <strong>2013</strong><br />
Now<br />
APPLICATION AREAS<br />
Military/Aerospace, Industrial, Transportation<br />
Backplanes
CPU or Single Board Computers<br />
QorIQ T4240 3U Open<strong>VPX</strong><br />
SBC (RIOV-2440)<br />
Compatible Operating Systems: Integrity, VxWorks, VxWorks<br />
653, Linux<br />
Compatible Architectures: Open<strong>VPX</strong>, PCIe, SRIO, GbE, 10GbE,<br />
SATA II<br />
The RIOV-2440 features <strong>the</strong> QorIQ T4240, <strong>the</strong> first<br />
Advanced Multiprocessing SoC from Freescale, with 12<br />
dual-threaded cores. The 24 virtual cores of <strong>the</strong> T4240,<br />
along with <strong>the</strong> associated Altivec technology SIMD<br />
engines and hardware accelera<strong>to</strong>rs, provide excellent<br />
performance for calculation-intensive applications. The<br />
integrated I/O peripherals and <strong>the</strong> data-path acceleration<br />
architecture (DPAA) guarantee <strong>the</strong> highest performance<br />
for I/O-intensive applications. The CoreNet fabric<br />
provides very efficient point-<strong>to</strong>-point interconnection<br />
between <strong>the</strong> multiple cores and peripherals, making <strong>the</strong><br />
T4240 <strong>the</strong> ideal choice for applications requiring very<br />
high performance, both in I/O and calculation. The hardware-assisted<br />
virtualization support enables <strong>the</strong> safe and<br />
flexible partitioning of applications on <strong>the</strong> multiple cores.<br />
The RIOV-2440 supports <strong>the</strong> T4240 processor with up <strong>to</strong><br />
12 GB of high-speed DDR3 memory in three separate<br />
banks, 2 GB of onboard Flash, and direct I/O connections<br />
<strong>to</strong> <strong>the</strong> backplane. The overhead of additional switches<br />
and bridges is eliminated, while flexibility is provided<br />
by <strong>the</strong> multiple processor I/O configuration options,<br />
including PCIe, SRIO, GbE, 10GbE and SATA II. It is compatible<br />
with most Open<strong>VPX</strong> payload slot profiles. As<br />
<strong>the</strong> first SBC with <strong>the</strong> T4240 processor, <strong>the</strong> RIOV-2440<br />
is intended for air-cooled applications and labora<strong>to</strong>ry<br />
models. It provides easy access <strong>to</strong> <strong>the</strong> essential I/Os on<br />
<strong>the</strong> front panel, as well as complete connectivity on <strong>the</strong><br />
backplane. Various RTM modules are available <strong>to</strong> access<br />
<strong>the</strong> wide range of I/O and debug signals.<br />
FEATURES & BENEFITS<br />
◆ Very high computing power in a single 3U <strong>VPX</strong> slot, ideal<br />
for SWaP-sensitive HPEC applications<br />
◆ Based on T4240, <strong>the</strong> latest Freescale QorIQ SoC, 24<br />
virtual PPC cores with AMP and Altivec technology<br />
◆ Easy access <strong>to</strong> front-panel I/O and modular RTM<br />
options for full connectivity, including 10GbE, SRIO<br />
and PCIe<br />
◆ Rugged air-cooled variant available, conductioncooled<br />
version on request<br />
◆ Support for <strong>the</strong> latest VSIPL++ libraries as well as<br />
legacy Altivec software<br />
CES - Creative Electronic Systems SA<br />
TECHNICAL SPECS<br />
◆ Open<strong>VPX</strong> Profiles: Slot profile: SLT3-PAY-<br />
1F2F2U-14.2.2, Payload module profile:<br />
MOD3-PAY-1F2F2U-16.2.2-n<br />
◆ Processor: Freescale QorIQ T4240 (twelve dualthreaded<br />
cores) at 1.6 GHz, 2 MBytes internal L2<br />
cache (per cluster) with ECC protection, triple 512<br />
KBytes internal L3 cache with ECC protection<br />
◆ Memory: triple 2/4 GBytes DDR3 SDRAM at 12<br />
GBytes/s peak (per channel) with ECC protection,<br />
2 GBytes Flash EPROM (NAND), 128 MBytes Flash<br />
EPROM (NOR), 256 KBytes NVRAM<br />
◆ Interconnect: four PCIe x4 on <strong>VPX</strong>-P1/P2, two SRIO x4<br />
on <strong>VPX</strong>-P1, twelve GbE on <strong>VPX</strong>-P1/P2 + one on front,<br />
three 10GbE on <strong>VPX</strong>-P1/P2, one SATA II on <strong>VPX</strong>-P2 +<br />
one on front, one USB 2.0 on front, one UART on <strong>VPX</strong>-<br />
P2 + one on front, one Aurora on <strong>VPX</strong>-P2<br />
◆ Advanced Board Management Controller: for VITA<br />
46.11 support, configuration management, event logging<br />
and o<strong>the</strong>r supporting tasks<br />
CONTACT INFORMATION<br />
CES - Creative Electronic Systems SA<br />
38 avenue Eugene Lance<br />
Grand-Lancy<br />
1212 Switzerland<br />
+41.22.884.51.00 Telephone<br />
+41.22.794.74.30 0 Fax<br />
ces@ces.ch<br />
http://www.ces.ch<br />
<br />
CPU or Single Board Computers
CPU or Single Board Computers<br />
CSP Inc.<br />
3220Q Open<strong>VPX</strong> Intel Blade<br />
Compatible Operating Systems: Red Hat Enterprise Linux, Red<br />
Hat Enterprise MRG<br />
Compatible Architectures: Open<strong>VPX</strong>, <strong>VPX</strong><br />
The 3220Q is a rugged high-performance 6U Open<strong>VPX</strong><br />
Blade, with a dual socket Intel® Xeon® processor and<br />
QuickPath Interconnect (QPI) <strong>to</strong> deliver superior performance-per-watt<br />
and low latency. Operating as a general<br />
purpose compute engine, it is one of <strong>the</strong> fundamental<br />
building blocks in <strong>the</strong> CSPI TeraXP family of Embedded<br />
Servers.<br />
The 3220Q supports Red Hat Enterprise MRG delivering<br />
realtime capabilities and high speed messaging in a<br />
commercial off <strong>the</strong> shelf (COTS) Linux based operating<br />
system.<br />
Featuring an Open Software Stack (OpenMPI/OFED,<br />
AMQP) and a Converged Fabric (supporting FDR Infini-<br />
Band, 10/40GbE, Fibre Channel) <strong>the</strong> TeraXP Embedded<br />
Servers provide <strong>the</strong> scalable processing power and I/O<br />
bandwidth needed for embedded military computing<br />
applications such as radar, sonar, digital signal processing,<br />
command and control, intelligence, surveillance<br />
and reconnaissance (ISR).<br />
FEATURES & BENEFITS<br />
◆ Intel® Multi-core general purpose processors for<br />
compute density<br />
◆ Converged Fabric technology for high bandwidth<br />
InfiniBand, E<strong>the</strong>rnet and Fibre Channel connectivity<br />
TECHNICAL SPECS<br />
◆ Dual Socket Intel® Xeon® Processors - 4 Cores/8<br />
Threads per socket - 8 MB On-chip L3 Cache per<br />
socket - 2.13 GHz Core Clock - 4.8 GT/s QPI between<br />
sockets - 16 GB DDR3 ECC protected device-down<br />
Memory<br />
◆ Support for FDR 56 Gb/s InfiniBand, 10/40GbE via a<br />
companion Carrier Card<br />
◆ 32 Lanes of PCIe Gen2 <strong>to</strong> <strong>the</strong> Open<strong>VPX</strong> Data and<br />
Expansion Planes; Two 1000Base-T Interfaces <strong>to</strong> <strong>the</strong><br />
VITA-46.6 E<strong>the</strong>rnet Control Plane<br />
◆ Full IPMC Implementation<br />
◆ Available in Air-Cooled or Conduction-Cooled versions<br />
APPLICATION AREAS<br />
Embedded Military Computing: Radar, sonar,<br />
digital signal processing, command and control,<br />
intelligence,surveillance and reconnaissance (ISR)<br />
AVAILABILITY<br />
CONTACT INFORMATION<br />
Engineers’ <strong>Guide</strong> <strong>to</strong> <strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong> <strong>2013</strong><br />
Now<br />
CSP Inc.<br />
43 Manning Road<br />
Billerica, MA<br />
01821, USA<br />
978-663-7598 Telephone<br />
978-663-0150 Fax<br />
sales@cspi.com<br />
www.cspi.com<br />
CPU or Single Board Computers
CPU or Single Board Computers<br />
3300GTX Open<strong>VPX</strong> NVIDIA<br />
GPGPU Blade<br />
Compatible Operating Systems: Red Hat Enterprise Linux, Red<br />
Hat Enterprise MRG<br />
Compatible Architectures: Open<strong>VPX</strong>, <strong>VPX</strong><br />
The 3300GTX provides CSPI’s TeraXP Embedded<br />
Servers with a high performance co-processor blade featuring<br />
many CUDA cores <strong>to</strong> accelerate parallel streaming<br />
and FFT based applications. Optimizing computational<br />
density in a 6U Open<strong>VPX</strong> slot, <strong>the</strong> 3300GTX is configured<br />
with one NVIDIA MXM Graphics Processing Unit (GPU)<br />
and one FDR InfiniBand 56 Gbit/s Host Channel Adapter<br />
(HCA).<br />
Application development for <strong>the</strong> GPGPU’s is enhanced<br />
by <strong>the</strong> use of <strong>the</strong> industry standard CUDA, OpenCL and<br />
OpenACC <strong>to</strong>olkits.<br />
The 3300GTX board also features failover capabilities via<br />
<strong>the</strong> HCA supporting a 56 Gbp/s QSFP transceiver on <strong>the</strong><br />
front panel and a VITA 66.1 optical interconnect on <strong>the</strong><br />
backplane. The addition of this fiber-optic connectivity<br />
brings benefits in higher bandwidth and lower weight.<br />
FEATURES & BENEFITS<br />
◆ NVIDIA GPGPU coprocessor with GPUDirect Technology<br />
◆ FDR InfiniBand technology with 56 Gbit/s Host<br />
Channel Adapter<br />
◆ <strong>VPX</strong> Backplane with <strong>the</strong> VITA 66.1 Optical Interconnect<br />
TECHNICAL SPECS<br />
◆ 6U Open<strong>VPX</strong> GPGPU Co-processor Blade with one<br />
MXM site supporting a NVIDIA GTX 560M GPGPU<br />
◆ Implemented with <strong>the</strong> Mobile PCI Express Module<br />
(MXM) version 3.0 standard, capable of hosting<br />
newer GPGPU’s as <strong>the</strong>y become available<br />
◆ mDP Interface (one link <strong>to</strong> Front Panel, one link <strong>to</strong><br />
backplane)<br />
◆ Mellanox HCA with ConnectX-3 Virtual Pro<strong>to</strong>col<br />
Interconnect (VPI)<br />
◆ Available in Air-Cooled or Conduction-Cooled versions<br />
APPLICATION AREAS<br />
Embedded Military Computing: Radar, sonar, digital<br />
signal processing, command and control, intelligence,<br />
surveillance, and reconnaissance (ISR)<br />
AVAILABILITY<br />
Now<br />
CONTACT INFORMATION<br />
CSP Inc.<br />
CSP Inc.<br />
43 Manning Road<br />
Billerica, MA<br />
01821, USA<br />
978-663-7598 Telephone<br />
978-663-0150 Fax<br />
sales@cspi.com<br />
www.cspi.com<br />
<br />
CPU or Single Board Computers
CPU or Single Board Computers<br />
Emerson Network Power<br />
M<strong>VME</strong>8100 Freescale P5020<br />
QorIQ processor <strong>VME</strong> Board<br />
Compatible Operating Systems: Linux, Wind River VxWorks,<br />
Green Hills Integrity<br />
Compatible Architectures: Power<br />
The M<strong>VME</strong>8100 is a high performance 6U <strong>VME</strong>/<strong>VXS</strong><br />
SBC featuring <strong>the</strong> new Freescale P5020 QorIQ processor<br />
supporting high speed ECC DDR3-1333MHz. It offers<br />
expanded IO and memory features with PCIe and SRIO<br />
fabric connectivity and multiple USB, Serial and E<strong>the</strong>rnet<br />
ports. Memory includes up <strong>to</strong> 8GB DDR3, 512K FRAM<br />
non-volatile memory, and 8GB eMMC NAND Flash. The<br />
M<strong>VME</strong>8100 is offered in commercial and rugged variants<br />
for extreme environments with extended shock, vibration,<br />
temperatures and conduction cooling. It is designed for<br />
a range of high end industrial control such as SPE and<br />
pho<strong>to</strong> lithography and C4ISR, including radar/sonar. It will<br />
provide technology insertion <strong>to</strong> prolong current programs<br />
while providing more performance and throughput.<br />
Emerson Network Power<br />
M<strong>VME</strong>2500<br />
Compatible Operating Systems: Linux, Wind River VxWorks<br />
Compatible Architectures: Power Architecture<br />
Emerson Network Power’s M<strong>VME</strong>2500 series features<br />
<strong>the</strong> Freescale QorIQ single-core P2010 or dual-core<br />
P2020 processor. It is a cost effective migration path for<br />
older generation M<strong>VME</strong>3100, M<strong>VME</strong>4100, M<strong>VME</strong>5100<br />
and M<strong>VME</strong>5110 boards. The M<strong>VME</strong>2500 series is ideal<br />
for au<strong>to</strong>mation, medical, and military applications such<br />
as railway control, semiconduc<strong>to</strong>r processing, test<br />
and measurement, image processing, and radar/sonar.<br />
Memory includes up <strong>to</strong> 2GB DDR3 and 512KB non-volatile<br />
MRAM. The M<strong>VME</strong>2502 variant has 8GB soldered eMMC<br />
solid state memory for additional rugged, non-volatile<br />
s<strong>to</strong>rage. Connectivity includes Gigabit E<strong>the</strong>rnet, USB2,<br />
serial, SATA and ei<strong>the</strong>r one or two PMC/XMC sites. A hard<br />
drive mounting kit and conformal coating are available.<br />
TECHNICAL SPECS<br />
◆ Freescale QorIQ P5020 1.8/2.0GHz<br />
◆ 2 PMC/XMC sites<br />
◆ Optional hard drive mounting kit<br />
◆ 2x4 PCIe or 2x4 SRIO connectivity <strong>to</strong> <strong>VXS</strong> backplane<br />
P0<br />
◆ Up <strong>to</strong> 3 USB 2.0 ports, 5 E<strong>the</strong>rnet ports, 5 Serial<br />
ports, GPIO<br />
CONTACT INFORMATION<br />
TECHNICAL SPECS<br />
CONTACT INFORMATION<br />
Emerson Network Power<br />
2900 South Diablo Way, Suite 190<br />
Tempe, AZ 85282-3222<br />
USA<br />
+1 800 759 1107 Toll Free<br />
+1 602 438 5720 Telephone<br />
embeddedcomputingsales@<br />
emerson.com<br />
Emerson.com/EmbeddedComputing<br />
◆ 800 MHz or 1.2G Hz Freescale QorIQ P2010 or P2020<br />
processor<br />
◆ Up <strong>to</strong> 8GB soldered memory<br />
◆ Optional rear transition module<br />
Emerson Network Power<br />
2900 South Diablo Way, Suite 190<br />
Tempe, AZ 85282-3222<br />
USA<br />
+1 800 759 1107 Toll Free<br />
+1 602 438 5720 Telephone<br />
embeddedcomputingsales@<br />
emerson.com<br />
Emerson.com/EmbeddedComputing<br />
Engineers’ <strong>Guide</strong> <strong>to</strong> <strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong> <strong>2013</strong><br />
CPU or Single Board Computers
Data Aquisition<br />
Model 53720 3-Channel 200 MHz<br />
A/D and 2-Channel 800 MHz D/A<br />
with Virtex-7 FPGA - 3U <strong>VPX</strong> Board<br />
Compatible Operating Systems: Linux, Windows, and VxWorks<br />
operating systems<br />
Compatible Architectures: COTS and rugged, 3U <strong>VPX</strong>,<br />
3U/6U cPCI, PCIe and XMC<br />
Model 53720 is a member of <strong>the</strong> Onyx family of high<br />
performance 3U <strong>VPX</strong> boards based on <strong>the</strong> Xilinx Virtex-7<br />
FPGA. A multichannel, high-speed data converter, it is<br />
suitable for connection <strong>to</strong> HF or IF ports of a communications<br />
or radar system. Its built-in data capture and<br />
playback features offer an ideal turnkey solution. The<br />
53720 includes three A/Ds, one upconverter, two D/As<br />
and four banks of memory. It features built-in support<br />
for PCI Express over <strong>the</strong> 3U <strong>VPX</strong> backplane.<br />
FPGA Functions<br />
The 53720 fac<strong>to</strong>ry-installed functions include three A/D<br />
acquisition and a D/A waveform playback IP modules for<br />
simplifying data capture and data transfer. IP modules<br />
for DDR3 SDRAM memories, a controller for all data<br />
clocking and synchronization functions, a test signal<br />
genera<strong>to</strong>r, and a PCIe interface complete <strong>the</strong> fac<strong>to</strong>ryinstalled<br />
functions and enable <strong>the</strong> 53720 <strong>to</strong> operate as a<br />
complete turnkey solution without <strong>the</strong> need <strong>to</strong> develop<br />
any FPGA IP.<br />
Extendable IP Design<br />
For applications that require specialized functions, users<br />
can install <strong>the</strong>ir own cus<strong>to</strong>m IP for data processing using<br />
Pentek GateFlow FPGA Design Kits.<br />
GateXpress for FPGA Configuration<br />
The Onyx architecture includes GateXpress, a sophisticated<br />
FPGA-PCIe configuration manager for loading and<br />
reloading <strong>the</strong> FPGA. At power up, GateXpress immediately<br />
presents a PCIe target for <strong>the</strong> host computer <strong>to</strong><br />
discover, effectively giving <strong>the</strong> FPGA time <strong>to</strong> load from<br />
FLASH. This is especially important for larger FPGAs<br />
where <strong>the</strong> loading times can exceed <strong>the</strong> PCIe discovery<br />
window.<br />
FEATURES & BENEFITS<br />
◆ Supports GateXpress FPGA-PCIe Configuration<br />
Manager<br />
◆ Complete radar and software radio interface solution<br />
◆ Supports Xilinx Virtex-7 VXT FPGAs<br />
◆ Three 200 MHz 16-bit A/Ds<br />
TECHNICAL SPECS<br />
◆ Two 800 MHz 16-bit D/As<br />
◆ 4 GB of DDR3 SDRAM<br />
◆ Sample clock synchronization <strong>to</strong> an external system<br />
reference<br />
◆ LVPECL clock/sync bus for multiboard synchronization<br />
◆ Optional user-configurable gigabit serial interface<br />
APPLICATION AREAS<br />
Software radio, radar, communications, UAV, signals<br />
intelligence<br />
AVAILABILITY<br />
Contact Pentek for price and availability<br />
CONTACT INFORMATION<br />
PENTEK<br />
PENTEK<br />
UPPER SADDLE RIVER, NJ<br />
07458, USA<br />
201-818-5900 Telephone<br />
201-818-5904 Fax<br />
sales@pentek.com<br />
http://www.pentek.com<br />
<br />
Data Aquisition
Enclosures<br />
SIE Computing Solutions<br />
717 Series Air-Over Conduction<br />
Cooled ATR Enclosures<br />
Compatible Architecture: <strong>VME</strong>, <strong>VME</strong>64x, <strong>VXS</strong>, <strong>VPX</strong> and CPCI<br />
architectures<br />
The 717 Series is available in standard ARINC sizes<br />
that include 1/2 ATR Short <strong>to</strong> 1-1/2 ATR Long and any<br />
cus<strong>to</strong>m form fac<strong>to</strong>r. From bus standards <strong>to</strong> applicationspecific<br />
cus<strong>to</strong>m designs, <strong>the</strong> 717 Series provides an<br />
expansive offering of ATRs for platforms such as <strong>the</strong><br />
<strong>VME</strong>, <strong>VME</strong>64x, <strong>VXS</strong>, <strong>VPX</strong> and CPCI architectures. The<br />
717 Series is a member of SIE’s conduction-cooled line<br />
of ATRs. Designed specifically for rugged deployment<br />
and <strong>to</strong> direct air over <strong>the</strong> <strong>the</strong>rmal conducting walls, its<br />
cooling can be configured <strong>to</strong> meet application requirements<br />
by ei<strong>the</strong>r drawing air through <strong>the</strong> walls and out a<br />
rear exhaust plenum or forcing air down <strong>the</strong> walls and<br />
directing it away from <strong>the</strong> equipment. When configured<br />
for unpressurized environments, <strong>the</strong> 717 Series can be<br />
configured with a high-altitude cooling scheme <strong>to</strong> permit<br />
ultimate performance at altitudes up <strong>to</strong> 50,000 feet. When<br />
used in conjunction with SIE’s System Performance<br />
Moni<strong>to</strong>ring” technology, <strong>the</strong> 717 Series ATR can be configured<br />
<strong>to</strong> activate internal heaters in cold start-ups or<br />
control <strong>the</strong> performance outputs of <strong>the</strong> optional external<br />
cooling fan <strong>to</strong> maintain an optimal <strong>the</strong>rmal environment<br />
for <strong>the</strong> circuit card assemblies. In addition, <strong>the</strong> 717 Series<br />
is sealed from <strong>the</strong> environment and meets MIL standards<br />
for up <strong>to</strong> 95% RH (humidity), 5% for 48 hours (salt fog),<br />
no fungal growth, 13.5g acceleration, and <strong>the</strong>rmal shock<br />
performance. The 717 Series can be configured with an<br />
optional avionics trays for isolation from shock and vibration<br />
environments common <strong>to</strong> airborne, vehtronics and<br />
shipboard applications. For applications where stringent<br />
weight requirements are an issue, SIE Computing Solutions<br />
offers a lightweight composite solution.<br />
FEATURES & BENEFITS<br />
◆ Dip-brazed construction<br />
◆ Expansive range of ARINC sizes<br />
◆ Modular power supply /AC or DC filtered inputs<br />
◆ Cold start heaters & high altitude fan offering<br />
◆ Configurable I/O panel<br />
TECHNICAL SPECS<br />
◆ S<strong>to</strong>rage Temp (-40°C <strong>to</strong> +85°C MIL-STD-810F)<br />
◆ EMC (MIL-STD-461D)<br />
◆ Input Power (28VDC, 115VAC/ 400Hz. 1Ø, 115VAC/<br />
400Hz. 3Ø- MIL-STD-704A Thru 704E, MIL-STD-<br />
1275A)<br />
◆ Wiring (Low Toxicity -MIL-C-24643)<br />
◆ Vibration (15 <strong>to</strong> 2,000Hz At 0.1g2/ Hz. (RMS~12g)<br />
MIL-STD-810F Method 514.5) & Shock (20g for 11ms<br />
MIL-STD-810F Method 516.5)<br />
AVAILABILITY<br />
CONTACT INFORMATION<br />
SIE Computing Solutions<br />
10 Mupac Drive<br />
Brock<strong>to</strong>n, MA 02301<br />
USA<br />
800-926-8722 Toll Free<br />
508-588-6110 Telephone<br />
508-588-0498 Fax<br />
jtierney@sie-cs.com<br />
www.sie-cs.com<br />
Engineers’ <strong>Guide</strong> <strong>to</strong> <strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong> <strong>2013</strong><br />
Now<br />
Enclosures
Enclosures<br />
“Mupac” 760 Small<br />
Form Fac<strong>to</strong>r Series<br />
Designed <strong>to</strong> deliver mission-critical computing performance<br />
in a fully portable enclosure - ideal for rugged<br />
small spaces.<br />
Building on SIE Computing Solution’s 40-year his<strong>to</strong>ry of<br />
design excellence in rugged electronic and embedded<br />
systems, <strong>the</strong> “Mupac” 760 Small Form Fac<strong>to</strong>r product<br />
line is designed for mission-and performance-critical<br />
communications and intelligence. “Mupac” 760 Small<br />
Form Fac<strong>to</strong>r compute platforms allow data processing<br />
in <strong>the</strong> field in a fully transportable, highly rugged computing<br />
module that improves speed and efficiency by<br />
completing processing in <strong>the</strong> machine, at <strong>the</strong> distributed<br />
level, before delivering data upstream. SIE Computing<br />
Solutions’ Small Form Fac<strong>to</strong>r line provides a complete<br />
distributed computing module – exceptionally powerful<br />
and fully portable in everything from a UAV <strong>to</strong> a backpack.<br />
“Mupac” 760 Small Form Fac<strong>to</strong>r compute modules<br />
enable <strong>the</strong> most modern technology <strong>to</strong> work in harsh conditions<br />
at a level of distributed computing never before<br />
possible. In addition <strong>to</strong> standard offerings, <strong>the</strong> “Mupac”<br />
760 Small Form Fac<strong>to</strong>r line can also be cus<strong>to</strong>mized for<br />
a wide variety of unique specifications, providing highend<br />
compute-class performance for harsh industrial and<br />
military environments where extreme temperatures,<br />
air particulates, liquids and vibration prevent <strong>the</strong> use of<br />
standard commercial computers.<br />
FEATURES & BENEFITS<br />
◆ Extremely rugged<br />
◆ Easily cus<strong>to</strong>mized<br />
◆ Dip-brazed construction<br />
◆ Modular power supply<br />
◆ Rated <strong>to</strong> operate in temperatures ranging from -40 <strong>to</strong><br />
+85 degrees Celsius<br />
TECHNICAL SPECS<br />
◆ Two standard dimensions: 3.25” h x 6.5” w x 8.5” d<br />
or 5.25” h x 6.5” w x 8.5” d<br />
◆ Available in an IP67 NEMA Rated Version and IP50<br />
NEMA Rated Version<br />
◆ Quickly deployable with Intel® Core i3/i5/i7 multicore<br />
processors and up <strong>to</strong> 4 GB RAM<br />
◆ Standard I/O includes dual DVI display: one DVI-I<br />
(DVI-D+VGA) and one DVI-D; GbE E<strong>the</strong>rnet Port, 8 x<br />
USB 2.0, 2 x RS-232, 2 x SATA 3Gb/s with RAID 0,<br />
1 support; 1 x 6-pin header for KB/MS<br />
SIE Computing Solutions<br />
ALC888 HD SUPPORTED AUDIO<br />
◆ Enhanced configurability via a Mini PCIe Expansion<br />
Slot that can be configured by SIE for video capture,<br />
DOM, wireless and many o<strong>the</strong>r functions<br />
AVAILABILITY<br />
Now<br />
APPLICATION AREAS<br />
Harsh industrial and military environments requiring<br />
small form fac<strong>to</strong>rs and where extreme temperatures,<br />
air particulates, liquids and vibration prevent <strong>the</strong> use of<br />
standard commercial computers.<br />
CONTACT INFORMATION<br />
SIE Computing Solutions<br />
10 Mupac Drive<br />
Brock<strong>to</strong>n, MA 02301<br />
USA<br />
800-926-8722 Toll Free<br />
508-588-6110 Telephone<br />
508-588-0498 Fax<br />
jtierney@sie-cs.com<br />
www.sie-cs.com<br />
<br />
Enclosures
VIEWPOINT<br />
The Pro<strong>to</strong>col Wedge<br />
Pro<strong>to</strong>col, while giving us <strong>the</strong> benefits of security and reliability, kills performance<br />
and efficiency.<br />
By Ray Alderman, Executive Direc<strong>to</strong>r, VITA<br />
When you look at all <strong>the</strong> interconnects in <strong>the</strong> market, things can<br />
get confusing and frustrating fast. The best way <strong>to</strong> untangle this<br />
morass, as a rule of thumb, is <strong>to</strong> look at <strong>the</strong> interconnects by <strong>the</strong><br />
distance <strong>the</strong>y are designed <strong>to</strong> run (http://en.wikipedia.org/wiki/<br />
List_of_device_bit_rates .) The closer <strong>to</strong>ge<strong>the</strong>r <strong>the</strong> connected<br />
devices reside, <strong>the</strong> “lighter” <strong>the</strong> pro<strong>to</strong>col stack, and less pro<strong>to</strong>col<br />
latency will be experienced. The fur<strong>the</strong>r away <strong>the</strong> devices are, <strong>the</strong><br />
“heavier” <strong>the</strong> pro<strong>to</strong>col stack, and more pro<strong>to</strong>col latency will be<br />
induced. This observed phenomenon<br />
creates a reverse “wedge”,<br />
with <strong>the</strong> apex starting at chip-<strong>to</strong>chip<br />
connections, and <strong>the</strong> wide end<br />
of <strong>the</strong> wedge at <strong>the</strong> location-<strong>to</strong>location<br />
end, <strong>the</strong> Internet.<br />
Chip-<strong>to</strong>-chip connections don’t<br />
need a lot of pro<strong>to</strong>col <strong>to</strong> control data<br />
flow. PCI and PCIExpress are some<br />
examples. You don’t have <strong>to</strong> worry<br />
about multiple packet recipients,<br />
you don’t need <strong>to</strong> worry <strong>to</strong>o much<br />
about synchronization and error<br />
handling, and you don’t have big<br />
packet headers defining <strong>the</strong> origin<br />
of <strong>the</strong> data and who handled it<br />
before it was received. In a point-<strong>to</strong>point<br />
connection like chip-<strong>to</strong>-chip, it can only come from <strong>the</strong> trusted<br />
device on that link.<br />
Board-<strong>to</strong>-board connections have heavier pro<strong>to</strong>cols. RapidIO and<br />
InfiniBand are examples. You could have multiple data senders, error<br />
handling gets messier, critical data may need time-stamping, and<br />
synchronization becomes necessary. Box-<strong>to</strong>-box connections get<br />
even heavier. E<strong>the</strong>rnet is a perfect example. Not only do you have<br />
<strong>the</strong> overheads of <strong>the</strong> board-<strong>to</strong>-board connections, but now you need<br />
<strong>to</strong> verify <strong>the</strong> sender as a valid data source, you need a his<strong>to</strong>ry of who<br />
handled <strong>the</strong> data before it was received, error handling becomes<br />
more prolific, and packet headers become huge.<br />
Finally, we have location-<strong>to</strong>-location connections. Internet Pro<strong>to</strong>col<br />
(IPv6) is an example here. The pro<strong>to</strong>col stack is a monster; all <strong>the</strong><br />
legacy pro<strong>to</strong>col requirements are <strong>the</strong>re plus many more. Packet<br />
headers are now massive, <strong>the</strong> his<strong>to</strong>ry of <strong>the</strong> packet across all <strong>the</strong> previous<br />
internet systems involved in its transmission is needed, and<br />
byte counts plus packet numbers are needed, <strong>to</strong>o (since most large<br />
packets are broken-up in<strong>to</strong> smaller packets and must be reassembled,<br />
in order, by <strong>the</strong> receiver).<br />
“DATA CENTERS AND<br />
‘CLOUD COMPUTING’<br />
MACHINES ARE BEGINNING<br />
TO TELL US THAT WE<br />
NEED TO REDUCE<br />
THE PROTOCOL STACK<br />
OVERHEADS OF THE<br />
BOARD-TO-BOARD AND<br />
BOX-TO-BOX<br />
INTERCONNECTS.”<br />
Nicholas Negroponte warned us about this increasing pro<strong>to</strong>col-stack<br />
burden in his 1996 book, “Being Digital”. He claims that “<strong>the</strong> bits<br />
about <strong>the</strong> bits” are becoming more important that <strong>the</strong> bits <strong>the</strong>mselves<br />
(<strong>the</strong> real usable data). Pro<strong>to</strong>col, while giving us <strong>the</strong> benefits of security<br />
and reliability, kills performance and efficiency. Data centers and<br />
“cloud computing” machines are beginning <strong>to</strong> tell us that we need <strong>to</strong><br />
reduce <strong>the</strong> pro<strong>to</strong>col stack overheads of <strong>the</strong> board-<strong>to</strong>-board and box<strong>to</strong>-box<br />
(or rack-<strong>to</strong>-rack) interconnects. The way <strong>to</strong> do this is <strong>to</strong> make<br />
those interconnections look more<br />
like chip-<strong>to</strong>-chip connections, with<br />
<strong>the</strong>ir lighter pro<strong>to</strong>col stacks. RDMA<br />
(Remote Direct Memory Access)<br />
used in InfiniBand and E<strong>the</strong>rnet<br />
<strong>to</strong>day are doing just that. But, IPvx<br />
pro<strong>to</strong>cols continue <strong>to</strong> expand and<br />
become heavier. This modifies <strong>the</strong><br />
pro<strong>to</strong>col “wedge” somewhat, and<br />
gives us much better performance<br />
and efficiency once <strong>the</strong> internet<br />
connection pro<strong>to</strong>cols are strippedoff<br />
when <strong>the</strong>y enter <strong>the</strong> data center.<br />
Ray Alderman is<br />
<strong>the</strong> Executive Direc<strong>to</strong>r<br />
of VITA,<br />
an ANSI-certified standards developer for<br />
high-performance computer systems and architectures<br />
used in critical embedded applications.<br />
He is a recognized authority on embedded architectures<br />
and computing.<br />
40 Engineers’ <strong>Guide</strong> <strong>to</strong> <strong>VME</strong>, <strong>VPX</strong> & <strong>VXS</strong> <strong>2013</strong>
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