30.04.2013 Views

BSV by Example - Computation Structures Group

BSV by Example - Computation Structures Group

BSV by Example - Computation Structures Group

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

2.2.2 Components of a <strong>BSV</strong> design<br />

The following file types are generated when building a design with <strong>BSV</strong>. Not all file types will be<br />

generated for all designs; some depend on the target simulation environment (Bluesim or Verilog).<br />

Bluesim is a cycle simulator for <strong>BSV</strong> designs, included in your <strong>BSV</strong> release.<br />

File Types in a <strong>BSV</strong> Design<br />

File Type Description Bluesim Verilog<br />

.bsv <strong>BSV</strong> source File<br />

.bspec Bluespec<br />

project File<br />

Development Workstation<br />

.bi, Intermediate files not directly viewed <strong>by</strong><br />

.bo,<br />

.ba<br />

the user<br />

.v Generated Verilog file<br />

√ √<br />

√ √<br />

√ √<br />

The .h, and .cxx files are intermediate files not directly viewed <strong>by</strong> the user<br />

√<br />

.h C++ header files<br />

√<br />

.cxx Generated C++ source file<br />

√<br />

.o Compiled object files<br />

√<br />

.so Compiled shared object files<br />

Note that the workstation and the compiler have various flags to direct the intermediate files into<br />

various sub-directories to keep your project organized and uncluttered.<br />

2.2.3 Overview of the <strong>BSV</strong> build process<br />

Figure 1 illustrates the following steps in building a <strong>BSV</strong> design:<br />

1. A designer writes a <strong>BSV</strong> program. It may optionally include Verilog, SysteMVerilog, VHDL,<br />

and C components.<br />

2. The <strong>BSV</strong> program is compiled into a Verilog or Bluesim specification. This step has two<br />

distinct stages:<br />

(a) pre-elaboration - parsing and type checking<br />

(b) post-elaboration - code generation<br />

3. The compilation output is either linked into a simulation environment or processed <strong>by</strong> a synthesis<br />

tool.<br />

Once you’ve generated the Verilog or Bluesim implementation, the workstation provides the following<br />

tools to help analyze your design:<br />

• Interface with an external waveform viewer with additional Bluespec-provided annotations,<br />

including structure and type definitions<br />

• Schedule Analysis viewer providing multiple perspectives of a module’s schedule<br />

• Scheduling graphs displaying schedules, conflicts, and dependencies among rules and methods.<br />

18<br />

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!