BSV by Example - Computation Structures Group

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Contents Table of Contents 2 1 Introduction 9 1.1 Design activities where BSV is used . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 Key ideas in BSV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.1 Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2.2 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 Why BSV? Can’t we do all this with existing languages (like C++)? . . . . . . . . . 11 1.4 About this book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Getting started with BSV 15 2.1 A simple example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.1 Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.2 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.3 (* synthesize *) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.4 Module definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.5 Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.6 System tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 Building the design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.1 Bluespec Development Workstation (BDW) . . . . . . . . . . . . . . . . . . . 17 2.2.2 Components of a BSV design . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.3 Overview of the BSV build process . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.4 Create a project file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.5 Compile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3 Multiple modules in a single package . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.1 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4 Multiple packages in a single design . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 Data types 23 3.1 Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2 Uppercase and lowercase in type and value identifiers . . . . . . . . . . . . . . . . . . 24 3.3 Typeclasses and overloading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4 Pre-defined type classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.5 Data type conversion functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.6 Some common scalar types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.6.1 Bit#(n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.6.2 Bool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2
3.6.3 UInt#(n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6.4 Int#(n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.7 Using abstract types instead of Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.8 Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.9 Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4 Variables, assignments, and combinational circuits 31 4.1 Variable declaration and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1.1 Side-effect initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1.2 Value initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1.3 Value initialization from a Value method . . . . . . . . . . . . . . . . . . . . 33 4.1.4 Initializing sub-interface components . . . . . . . . . . . . . . . . . . . . . . . 33 4.1.5 Additional examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2 Combinational circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.2.1 Error - no type declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.2.2 Error - no initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5 Rules, registers, and fifos 38 5.1 Defining and updating a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.2 Updating the register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.2 Rules and their semantics: atomicity and orderings . . . . . . . . . . . . . . . . . . . 40 5.3 Composition of rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.3.1 Attribute descending_urgency . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.4 Multiple registers in a rigid synchronous pipeline . . . . . . . . . . . . . . . . . . . . 43 5.5 Using register syntax shorthands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.6 Using valid bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.7 Multiple FIFOs in an elastic asynchronous pipeline . . . . . . . . . . . . . . . . . . . 47 6 Module hierarchy and interfaces 49 6.1 Module hierarchies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1.1 Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.2 Scope of methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.1.3 Analyzing a design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.2 Implicit conditions of methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3 ActionValue methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3.1 The let statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3.2 The
Page 1: BSV by Example The next-generation
Page 5 and 6: 10 Advanced types and pattern-match
Page 7 and 8: A.6.1 Scheduling error due to paral
Page 9 and 10: 1 Introduction BSV (Bluespec System
Page 11 and 12: • Haskell, for more advanced type
Page 13 and 14: would be unnecessary if sequential
Page 15 and 16: A few examples span multiple sectio
Page 17 and 18: In this simple example, the name of
Page 19 and 20: 2.2.4 Create a project file Figure
Page 21 and 22: This next example looks at a design
Page 23 and 24: • ActionValue Methods: These meth
Page 25 and 26: Another example: the Ord typeclass
Page 27 and 28: cannot automatically convert from a
Page 29 and 30: $display("maxInt16/4 = %x", maxInt1
Page 31 and 32: 3.9 Strings Source directory: data/
Page 33 and 34: 4.1.3 Value initialization from a V
Page 35 and 36: ActionValue #(Coord) g = s.response
Page 37 and 38: if (pack(cycle)[1:0] == 3) a = a +
Page 39 and 40: package Tb; (* synthesize *) module
Page 41 and 42: In BSV, the logical sequence of rul
Page 43 and 44: These are both legal final states o
Page 45 and 46: ule r1; x2
Page 47 and 48: Because of the rule condition if (v
Page 49 and 50: 6 Module hierarchy and interfaces 6
Page 51 and 52: Wherever mkM2 is instantiated, the
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Window Bluespec Development Worksta
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6.3.1 The let statement This statem
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module mkTb (Empty); Dut_ifc dut 0
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interface Put_int; method Action pu
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module mkStimulusGen (Client_int);
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interface Server#(type req_type, ty
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Conflicts are discussed in more det
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(* descending_urgency = "r1, r2, r3
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Figure 6: Execution Order Graph As
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If you compile with the mutually_ex
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(* preempts = "(the_bar.r1, (r2, r3
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However, the rule calls dut.put() a
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After you compile and observe the r
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Sometimes, splitting a rule syntact
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Note that in each cycle, with respe
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interface Counter; method int read(
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noAction is a special null Action (
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In this example, the four lines enu
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Notice that the default value on bo
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ule doit; case (tuple2 (rw_incr.wge
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method Action enq(v) if (enq_ok); r
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In the next few examples we’ll cr
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Common Overloading Provisos Proviso
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module mkPlainReg2( Reg#(Bit#(n)) )
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Since type_b is a different type th
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• The optional deriving Eq clause
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color0 color1 color2 8 bits 8 bits
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A common example of a tagged union
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The simple processor module contain
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defines instruction addresses to be
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typedef struct { Reg#(int) ra; Reg#
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Functions like tuple2 are ordinary
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At every state, it tries to reduce
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Reg#(int) cycle
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• Z a wire that is not driven at
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These function expressions can be u
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Reg#(int) arr3[4]; for (Integer i=0
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to produce a vector of 4 elements (
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We can then use the genWith vector
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The output is: 13.4 Whole register
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Error: "Tb.bsv", line 20, column 35
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We’ll take a simple approach and
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arr[5]
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Reg#(int) counter
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ule stateIdle ( state[idle] == 1 );
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statement times (the number of cloc
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function Action functionOfAction( i
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action $display("Enq 10 at time ",
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Warning: "Tb.bsv", line 36, column
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module SizedFIFO(V_CLK, V_RST_N, V_
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• Every import "BVI" wrapper must
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The Verilog parameters, inputs, and
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A Source Files Complete, compilable
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package DeepThought; interface Ifc_
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rule step3 ( step == 3 ); $display(
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Reg#(int) step
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(* synthesize *) module mkTb (Empty
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method Action send (int a); f1.enq
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endmodule // ----------------------
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Copyright 2010 Bluespec, Inc. All r
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interface Put_int put_response; end
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f_out.enq (y); endrule interface re
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endrule rule enq2 (state > 4); f.en
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(* synthesize *) module mkGadget (S
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cycle
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(* descending_urgency = "r1, r2" *)
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$display ("%0d: Enqueuing %d into f
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A.7 RWires and Wire types Chapter e
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endrule method int read(); return v
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Version 2 of the counter (* synthes
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method Action decrement (int dd); v
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-----------------------------------
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-----------------------------------
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ule decr2 (state > 3); c2.decrement
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ule e; let x = state * 10; f.enq (x
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endfunction function Bool isBlock(
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method Action drive(tx ina, ty inb)
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package Tb; import SimpleProcessor:
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Reg#(InstructionAddress) pc
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$display("=== step 0 ==="); $displa
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endrule endmodule: mkTb endpackage:
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it o = 0; for (Bit#(2) i=0; i
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step
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endfunction Vector#(16,bit) bar2 =
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Reg#( Vector#(10,Status) ) regstatu
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endmodule: mkTb endpackage: Tb A.12
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A top-level module connecting the s
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functionOfAction( 30 ); // Create a
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endseq endpar $display("Par block d
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endmodule schedule first SB (clear,
show all

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