Device reference guide - Altium

Hardware Buyer’s Guide 

Tools for Interactive FPGA Design

Making electronics design easier 

Altium has always been at the forefront of desktop EDA technology. 

Altium defined the future of desktop design with the release of the 

world’s first Windows ® -based PCB design tool. Our latest 2004 product 

line continues this history of innovation by bringing to the engineer’s 

desktop a complete electronics design system that covers board-level, 

system-on-FPGA and complete embedded system design technologies. 

Altium creates design solutions that bring together the best of 

electronic design and contemporary software technology to keep 

pace with the changing nature of today’s and tomorrow’s electronics 

design processes. Altium’s edge lies in making its products affordable 

and easy to use for all designers whilst putting the very best 

technology into all of its products. 

Our philosophy is a simple one – we want every designer in the 

world to have access to the best possible design tools at an affordable 

price and to make the engineer’s desktop the most powerful, 

productive and cost-effective design platform. 

At Altium we truly believe in making electronics design easier. 

So let us make life easier for you... 

“ 

The philosophy behind Altium’s vision is a belief that 

all designers must have easy access to the best available 

electronic design tools, and that these tools must be easy 

to use and truly affordable. This is essential if we are 

to continue to see great innovation.” 

Nick Martin 

Founder and Joint CEO – Altium Limited

LiveDesign Hardware Buyer’s Guide 

Tools for Interactive FPGA Design 

Section 01 Interactive FPGA design with the NanoBoard 4 

02 FPGA device support 8 

03 Device reference guide 14 

Altium’s unique reconfigurable development platform 

– the NanoBoard – allows rapid and interactive 

implementation and debugging of your FPGA design. 

Target programmable devices are housed on plug-in 

daughter boards, allowing you to easily change the 

target project architecture, providing a truly FPGA 

vendor-independent development solution. 

For flexible systems design, multiple NanoBoards can 

be chained together to support the development of 

complex systems comprising of multiple FPGA devices 

spread across multiple PCBs. Connections on the 

NanoBoard for user-developed boards enables easy 

porting of designs to your own dedicated PCB. 

The NanoBoard, in combination with Altium’s extensive 

range of LiveDesign-enabled development solutions, 

will transform your desktop into a complete and 

interactive FPGA-based electronics design laboratory.

SECTION 01 INTERACTIVE FPGA DESIGN NANOBOARD-NB1 2004 

4 

Why should I use 

Altium’s NanoBoard 

over other 

development boards? 

Fully LiveDesign enabled 

for seamless integration 

with Altium’s 2004 family 

of design tools 

Multiple target devices 

are included 

Vendor-independence is 

supported by having the 

reprogrammable device 

(FPGA, CPLD) on a 

daughter board; the 

target is changed by 

replacing one daughter 

board with another 

A complex system of 

NanoBoards running the 

same or different projects 

can be created by 

chaining several 

NanoBoards together 

Working with FPGAbased 

user boards only 

requires a JTAG 

connection since the 

NanoBoard acts to 

control the design 

download to the user 

board plus all interactions 

with processors and 

virtual instruments 

A rich set of peripherals 

and connectors are 

included on the board 

for design flexibility 

Interactive FPGA design with 

the NanoBoard 

The NanoBoard is a unique, sophisticated, device- and vendorindependent 

FPGA-based development board that allows rapid 

and interactive implementation and debugging of FPGA designs. 

Altium’s new NanoBoard (nano-level breadboard) 

is the industry’s first FPGA-based, LiveDesign-enabled 

development board. The NanoBoard allows rapid 

and interactive implementation and debugging 

of FPGA designs and has been specially designed 

to take full advantage of Altium’s 2004 family of 

LiveDesign-enabled design tools. Target programmable 

devices are housed on plug-in daughter boards, 

enabling engineers to easily change the target 

project architecture, providing a truly FPGA 

vendor-independent development board. 

For flexible systems design, multiple NanoBoards can 

be chained together to support the development of 

complex systems comprising of multiple FPGA devices 

spread across multiple PCBs. Connections on the 

NanoBoard for user-developed boards enables easy 

porting of designs to your own dedicated PCB, which 

can be linked into the system via the NanoBoard to 

extend the LiveDesign process to the production PCB. 

As well as providing communications to and from 

the FPGA, the NanoBoard incorporates a wide range 

of peripherals such as an LCD, RAM, serial flash 

memory, keypad and ADC/DAC that can easily 

be used for application development. Ports on the 

NanoBoard include PS2, RS232, CAN, VGA, and I2C, 

as well as a range of general purpose I/O headers. 

The NanoBoard, in combination with Altium’s 

extensive range of LiveDesign-enabled electronics 

development tools, will transform your desktop into 

a complete and interactive FPGA-based electronics 

design laboratory. 

FPGA vendor and target independent 

The NanoBoard features swappable daughter boards 

that house the target programmable device. This 

allows easy reconfiguration of the NanoBoard to 

support multiple device families from different FPGA 

vendors. Altium’s LiveDesign-enabled design systems, 

such as Protel ® 

and Nexar , take full advantage 

of this by offering a device-independent design 

environment that allows a single design to be 

retargeted to a wide range of programmable 

devices, providing true design portability. 

Cyclone 

Plug-in daughter boards with Altera ® 

(EP1C12-Q240C7) and Xilinx ® 

Spartan ® 

(XC2S300E- 

PQ208) FPGAs are supplied as standard with 

the NanoBoard. 

Change the target FPGA easily by swapping daughter boards. 

The system will automatically recognise the installed device. 

NanoBoard-NB1 2004 – LiveDesign-enabled FPGA-based development board www.altium.com/nanoboard

Build a complex system by daisy chaining multiple NanoBoards. 

Chaining of multiple NanoBoards 

The NanoBoard includes both Master and Slave 

NanoTalk connectors that allow multiple NanoBoards 

to be chained together when used with Altium’s 

LiveDesign-enabled design systems. The NanoTalk 

controller manages the routing of signals between 

the boards to maintain continuity of the JTAG 

chains across NanoBoards. The target device on 

each NanoBoard forms a hard JTAG chain that is 

accessible via the system software. Similarly, all 

devices (such as Nexus processor cores and virtual 

instruments contained within the designs) running 

on each of the NanoBoards form a continuous ‘soft’ 

chain that is also accessible via the design software. 

The system software allows you to target different 

FPGA projects to each NanoBoard in the chain, 

allowing you to develop complex systems that 

contain multiple FPGAs that may be implemented 

over several PCBs. 

Connect your production board to the design system via the NanoBoard and 

continue the LiveDesign process on the final PCB. 

Connection of production PCBs 

The NanoBoard includes connectors for the 

integration of a designer’s production PCB into the 

LiveDesign environment. By exposing the hard and 

soft JTAG chains in your design, you can connect 

your production PCB to the NanoBoard via a 10-way 

header. The JTAG devices on your board will appear 

in the LiveDesign-enabled design environment as 

devices on the hard JTAG chain. Soft devices such 

as Nexus process cores and virtual instruments 

running on the FPGAs on your production board 

will appear in the soft chain and are accessible 

through the design environment. This extends the 

LiveDesign process to the design and debugging of 

your production board. Up to two user boards can 

be connected to each NanoBoard in the system. 

Features overview 

The NanoBoard is fully 

compatible with all Altium 

DXP 2004-based systems 

FPGA vendor and device 

independent 

Plug-in daughter board 

system supports a wide 

range of target FPGAs 

Altera ® Cyclone (EP1C12- 

Q240C7) daughter board 

supplied 

Xilinx ® Spartan ® IIE 

(XC2S300E-PQ208) 

daughter board supplied 

Other device daughter boards 

can be purchased separately 

System automatically detects 

installed FPGA device 

Multiple NanoBoards 

can be chained together – 

NanoBoard controller 

manages routing of hard 

and soft JTAG chains 

Up to two user boards can be 

connected to the NanoBoard 

with automatic routing of 

hard and soft JTAG chains 

Includes power pack 

with multiple plugs for 

various electrical outlet 

configurations 

Includes ribbon cable for PC 

connection plus other cables 

and connectors 

Extensive NanoBoard 

technical hardware 

reference manual 

Peripherals include: LCD, 

LED array, switch array, 

keypad, buzzer, ADC/DAC, 

256K x 8 RAM, 8M serial flash 

RAM, on-board serial flash 

RAM for FPGA config, 

programmable clock 

Ports include: PS2 mouse 

and keyboard, RS232, CAN, 

VGA, I2C, general purpose 

I/O headers 

continued overleaf 


5

SECTION 01 INTERACTIVE FPGA DESIGN NANOBOARD NANOBOARD-NB1 NB1 2004 

6 

TDI 

U2 

LAX_1K16 

Running 

Logic 

Analyser 

TDI TDO 

Interactive hardware 

debug 

Debugging circuitry inside 

an FPGA can be a difficult 

task. Internal signals can 

be brought out to the pins 

of the FPGA for monitoring 

and testing, but this adds 

to the complexity of the 

design process. What’s 

needed is a way to 

examine and control 

signals inside the FPGA. 

The DXP 2004 system 

provides a library of virtual 

instruments that can be 

wired into your circuit at 

the schematic level. The 

instruments comprise a 

hardware portion that is 

synthesized and downloaded 

into the target FPGA, and 

a soft instrument panel 

controllable from the PC. 

Instruments communicate 

with the system via a 

secondary ‘soft’ JTAG chain 

that is established inside 

the FPGA and brought 

out to defined pins on the 

NanoBoard. These virtual 

instruments then give 

you a window into the 

operation of the loaded 

FPGA for interactive 

debugging of your design. 

What ‘breadboarding at the nano level’ 

has to offer 

1 RS232 

The DTE RS232 connector provides TXD, RXD, RTS 

and CTS signal lines connected to the target FPGA 

via level translation circuitry. 

2 CAN 

The CAN connector is interfaced to the target 

FPGA via a CAN protocol transceiver with 

configurable speed. 

3 VGA 

NB1 includes a VGA-compatible RGB video monitor 

port. The port is configured with two bits per color, 

a total of six bits per pixel or 64 colors. The port is 

directly connected to I/O pins on the target FPGA. 

4 NanoTalk configuration header 

Uses jumpers to configure the operational mode 

of the NB1 NanoTalk controller and to set the 

default clock rate. 

5 PS2 

Two standard PS2 ports are available on NB1 

and are directly connected to I/O pins on the 

target FPGA. These are nominally intended for 

the connection of a PC keyboard and mouse 

to the FPGA design. 

6 Parallel port connection to PC 

NB1 connects to a PC via a standard parallel port. A 

cable for this purpose is supplied with the NanoBoard. 

7 Power connectors 

Two parallel power connector jacks are provided 

so that power can be supplied to a chain of 

NanoBoards in daisychain configuration. 

8 NanoTalk Slave 

Multiple NanoBoards can be chained together using 

the NanoTalk Master and NanoTalk Slave headers. 

Connectors are provided for this. The NanoBoard 

controllers manage the routing of JTAG chains 

between boards to provide access to all hard and 

soft devices on all chained boards. 

9 NanoBoard controller 

The NB1 controller performs a variety of tasks, 

including managing the routing of the various 

JTAG chains to and from the target devices and 

controlling communications to and from the design 

software running on the PC. The controller is 

implemented inside a reconfigurable FPGA device 

to allow for firmware upgrades in the field. 

10 Serial flash RAM 

NB1 includes two 8Mbit serial flash RAM resources. 

These can be programmed by the design system via 

the NanoBoard controller. One of the devices can be 

set as a source to configure the target FPGA on 

power up. 

11 Daughter board sockets 

Dual high-cycle sockets are used to plug in the 

swappable daughter boards containing target FPGA 

devices. The daughter boards allow the NanoBoard 

to be used with a variety of programmable devices. 

12 Static RAM 

NB1 provides two 128k x 8 static RAM devices, which 

are directly connected to I/O pins on the target FPGA 

device. The SRAM devices have a common Chip Select 

and address lines, but separate 8-bit data bus and 

RD/RW signals for each chip. The memory resource 

can be application-configured as single 128k x 16 or 

256k x 8 address space, or two 128k x 8 spaces. 

13 Programmable system clock 

SPI-based programmable clock generator that 

provides a fixed 20MHz reference clock and userprogrammed 

clock with an output frequency from 

6 to 200MHz. Both clocks are connected to global 

clock pins on the plug-in target FPGA. 

14 DIP switch 

8-way DIP switch, accessible directly from target FPGA. 

15 LED array 

8 x high intensity LED array, accessible directly from 

target FPGA. 

16 Test/reset button 

General purpose momentary-action pushbutton, 

accessed directly from the target FPGA. This has no 

intrinsically set function, but is nominally intended 

to be used as a hard reset button for the FPGAbased 

circuit. 

17 General purpose headers 

A total of 36 target FPGA I/O lines are terminated 

on the two general purpose User Headers on NB1. 

These headers also provide ground and power. 

18 ADC/DAC & I2C 

NB1 is equipped with general purpose analog 

to digital and digital to analog converters, both 

interfaced using the I2C protocol. Four channels 

are provided as well as a filtered 3.3V analog 

supply and ground. The same signals are 

available via a header, which additionally provides 

I2C signals and a 5V supply and power ground. 


23 

22 

21 

The Altium NanoBoard is the first 

LiveDesign-enabled development 

platform for Nexar and Protel 

19 Audio CODEC 

NB1 provides an 8-bit audio CODEC, together with 

relevant analog pre- and post- conditioning circuitry, 

terminated with stereo input and output jacks. 

The CODEC is accessible from the target FPGA. 

20 User board connectors 

NB1 includes two user board JTAG headers. 

These headers are used to include a user-developed 

board in the hard and soft JTAG chains, and can 

be used to extend the LiveDesign process to your 

production PCB. 

21 Keypad 

1 2 3 4 5 6 7 

20 

A 16-way keypad is provided for user input to the 

FPGA circuit. The keypad is arranged in a 4 x 4 array 

and organized so that a row-column scanning 

19 

18 

24 

process can read the status of each key. The keypad 

features replaceable overlays. 

22 LCD 

NB1 includes a standard 16 character by two line 

LCD with LED backlight, accessible directly from 

the target FPGA. 

23 Buzzer 

17 

NB1 includes a magnetic audio transducer 

connected to an I/O line on the target FPGA. 

24 High capacity FPGA daughter boards 

Included as standard with the NanoBoard are 

the two most popular FPGA daughter boards to 

accommodate reconfigurable systems including 

processor-based designs. 

8 

9 

10 

11 

12 

13 

14 

15 

16 

Features overview 

On-board programmable 

clock (frequencies from 

6MHz to 200MHz, software 

controllable) and fixed 

frequency reference clock 

Upgradeable NanoBoard 

controller firmware 

Integrated heavy-duty 

NanoBoard stand 

DXP 2004 software 

support for NanoBoard 

Comprehensive set of FPGAbased 

virtual instruments for 

interactive hardware debug 

Virtual instruments include 

soft front panels that 

communicate with the design 

running on the NanoBoard 

Virtual instruments include 

logic analyzers, frequency 

counters, frequency 

generators, I/O blocks 

Central control of FPGA 

design processing and 

download 

Devices view allows 

interaction with all 

NanoBoards connected 

to the system, all FPGA 

target devices and all soft 

devices contained within 

the downloaded designs 

FPGA vendor tools 

(supplied separately) driven 

transparently through DXP 

interface for place and 

route 

NanoBoard port plug-in 

library allows convenient 

schematic-level connection 

to NanoBoard devices 

Configuration Manager 

allows FPGA project to 

be easily retargeted from 

NanoBoard to final PCB 

implementation 


7

SECTION 02 FPGA DEVICE SUPPORT NANOBOARD-NB1 2004 

8 

Hitting the target 

By providing target devices 

on plug-in daughter 

boards, Altium lowers the 

cost of development for 

companies that work with 

more than one device family. 

It also makes it easy to 

evaluate and compare the 

features and benefits of 

different devices without 

the need to support 

multiple development 

systems. Engineers can 

create their FPGA design 

and then plug-in different 

daughter boards to test the 

design on a wide variety of 

target FPGA architectures. 

The system also allows 

engineers to do design 

work on a device that is 

particularly suitable for 

development, and then 

switch to a different device 

for final production. 

FPGA device support 

Swappable FPGA daughter boards offer true device independence, 

allowing you to easily retarget your design to any device family and 

ensuring you always have access to the latest in FPGA device technology. 

With most development systems you’re limited 

to a single target device, and designing for 

different devices requires you to work on multiple 

development boards. Altium’s NanoBoard eliminates 

this constraint by housing the target device on a 

robust daughter board that plugs into the main 

board via a set of high-reliability connectors. This 

allows you to change the target device at any time, 

making it possible to develop systems for a range 

of device families from multiple FPGA vendors. 

System-wide device support 

The available range of daughter board devices 

is fully supported in the system software. When 

you swap daughter boards, the DXP 2004 system 

automatically recognizes the target device and 

configures the environment appropriately. In the 

Devices view the correct vendor tool set for place- 

&-route and timing analysis is automatically 

selected, and any project configurations valid 

for the target device are available for selection. 

Altium’s DXP 2004 product range comes with 

constraint files for each supported daughter board. 

These constraint files map the FPGA pinout on 

the daughter board to the relevant NanoBoard 

resources. You can add these constraint files to your 

project configuration to easily set up your project 

for download to the NanoBoard. Each project can 

have multiple configurations, allowing you to easily 

retarget your design for the full range of available 

daughter boards. 

Altium’s DXP 2004 product range comes with 

a range of FPGA-based components to allow 

for easy schematic-based system development. 

These components are supplied as a schematic 

symbol with attached FPGA models. All components 

are pre-synthesized and pre-verified to support all 

available target daughter boards. This means that 

your designs can be targeted to any supported 

device without the need to re-engineer the circuit. 

The correct models are automatically selected 

and instantiated based on the target device 

you have fitted. 

Continuously updated device support 

Manufacturers continually release new devices 

and device families. Altium’s development team 

is constantly adding additional device support and 

new daughter boards that can be dropped in to 

your existing system. This protects your design tool 

investment and allows you to expand your system 

as new devices come onto the market. 

With Altium’s NanoBoard and DXP 2004-based 

design systems your development environment 

is future-proof. 

The wide range of available daughter boards makes the NanoBoard 

a truly device and FPGA vendor-independent development platform. 


Available daughter boards 

FPGA Devices 

Actel ProASIC Plus 

Device: APA600-FPQ208 

The ProASIC Plus family of devices, Actel’s second generation Flash FPGAs, offers 

enhanced performance over Actel’s ProASIC family. It combines the advantages of 

ASICs with the benefits of programmable devices through nonvolatile Flash technology. 

This enables engineers to create high-density systems using existing ASIC or FPGA 

design flows and tools. In addition, the ProASIC Plus family offers a unique clock 

conditioning circuit based on two on-board phase-locked loops (PLLs). The family 

offers up to 1 million system gates, supported with up to 198kbits of 2-port SRAM 

and up to 712 user I/Os, all providing 50 MHz PCI performance. 

APA600 features: 

21,504 logic elements (as 3-input function generators), 600,000 system gates 

126 Kbits of embedded RAM (total) 

4 global clock networks 

2 phase-locked loops (PLLs) with flexible phase 

Support for 4 selectable I/O standards 

Altera ® 

Cyclone 

Device: EP1C12Q240C7 

The Cyclone field programmable gate array family is based on a 1.5-V, 0.13-µm, 

all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) 

and up to 288 Kbits of RAM. 

EP1C12 features: 

12,060 logic elements (as 4-input LUTs with programmable register 

and carry chain) 

239 Kbits of RAM (total) 

4 dedicated clocks and 8 dual-purpose clocks (DPCLK) 

2 phase-locked loops (PLLs) 


Altera ® 

Cyclone with SRAM 

Device: EP1C20F400C8 

The Cyclone field programmable gate array family is based on a 1.5-V, 0.13-µm, 

all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) 

and up to 288 Kbits of RAM. 

EP1C20 features: 



294 Kbits of RAM (total) 

4 dedicated clocks, and 8 dual-purpose clocks (DPCLK) 

2 phase-locked loops (PLLs) 


Additional daughter board features: 

Two IDT71V416L static RAM ICs – 4 Meg (256K x 16) 10ns advanced 

high-speed CMOS 


9


10 

Altera ® 

Stratix with SRAM 

Device: EP1S10F780C7 

The Stratix family of FPGAs is based on a 1.5-V, 0.13-µm, all-layer copper 

SRAM process, with densities up to 79,040 logic elements (LEs) and up to 

7.5 Mbits of RAM. 

EP1S10 features: 



920 Kbits RAM (total) 

6 digital signal processing (DSP) blocks 

24 embedded multipliers (18 x 18-bit) 

16 dedicated global clocks 

4 fast, and 2 enhanced phase-locked loops (PLLs) 





One MAX1617 SMBus temperature sensor which measures FPGA chip 

temperature and internal sensor temperature 

Xilinx ® 

Spartan ® 

-II 

Device: XC2S200-6PQ208C 

The Spartan ® 

-II 2.5V Field-Programmable Gate Array family gives users 

high performance, abundant logic resources, and a rich feature set, all at an 

exceptionally low price. The six-member family offers densities ranging from 

15,000 to 200,000 system gates. System performance is supported up to 

200 MHz. 

XC2S200 features: 

5,292 logic cells arranged in 2,352 CLB slices (200,000 system gates) 

Up to 4,704 4-input LUTs and 4,704 flip-flops 

Block RAM (to 56K bits) and distributed RAM (to 73.5K bits) 

4 digital clock managers (DLLs) 

4 primary low-skew global clock distribution nets 


Xilinx ® 

Spartan ® 

-IIE 

Device: XC2S300E-6PQ208C 


-IIE 1.8V Field-Programmable Gate Array family gives users 


exceptionally low price. The seven-member family offers densities ranging from 

50,000 to 600,000 system gates. System performance is supported beyond 

200 MHz. 

XC2S300E features: 



Block RAM (to 64K bits) and distributed RAM (to 96K bits) 



Support for 19 selectable I/O standards with fast or slow slew rates 

and multiple drive strengths 


Xilinx ® 

Spartan ® 

-IIE with SRAM 

Device: XC2S600E-6FG456C 


-IIE 1.8V Field-Programmable Gate Array family gives users 


exceptionally low price. The seven-member family offers densities ranging from 

50,000 to 600,000 system gates. System performance is supported beyond 

200 MHz. 

XC2S600E features: 









Two IDT71V416L static RAM ICs – 4 Meg (256K x 16) 10ns advanced high-speed CMOS 

Xilinx ® 

Spartan ® 

-3 with SRAM 

Device: XC3S1000-4FG456C 

The 1.2V Spartan ® 

-3 family of Field-Programmable Gate Arrays is specifically 

designed to meet the needs of high volume, cost-sensitive consumer electronic 

applications. The eight-member family offers densities ranging from 50,000 

to five million system gates. 

XC3S1000 features: 

17,280 logic cells arranged in 7,680 CLB slices (1000K system gates) 




8 global clock lines with abundant routing 





Xilinx ® 

Virtex ® 

-II with SRAM 

Device: XC2V1000-4FG456C 

The Virtex ® 

-II family is a platform FPGA developed for high performance from 

low-density to high-density designs that are based on IP cores and customized 

modules. The family delivers complete solutions for telecommunication, wireless, 

networking, video, and DSP applications. 

XC2V1000 features: 

11,520 logic cells arranged in 5,120 CLB slices (1000K system gates) 




16 global clock multiplexer buffers 







Optional key memory battery backup for bitstream encryption 


11


12 

CPLD Devices 

Xilinx ® 

Virtex-II Pro with SRAM 

Device: XC2VP7-5FG456C 

The Virtex ® 

-II Pro family contains platform FPGAs for designs that are based on 

IP cores and customized modules. The family incorporates multi-gigabit transceivers 

and PowerPC CPU blocks. It empowers complete solutions for telecommunication, 

wireless, networking, video, and DSP applications. 

XC2VP7 features: 

11,088 logic cells arranged in 4,928 CLB slices 




16 global clock multiplexer buffers 



The device contains a ‘hard’ PowerPC 405 processor core, which is supported 

in Nexar by a complete tool-chain (TASKING Viper compiler, source level 

debugger, etc) that allows use of this device in FPGA-based system designs 

Additional daughter features: 





Interface to two of the high speed (3.125GHz) transceivers in the Virtex-II Pro – 

each transceiver channel has 4 gold plated SMA coax connectors mounted along 

the top of the daughter board (transceivers are used with the programmable 

on-board Nanoboard clock that limits their speed to between 1 and 2GHz) 

The board comes with 8 coax connector cables and an example project that 

demonstrates the use of the transceivers 

Altera ® 

MAX ® 

3000/7000 with PLCC sockets 

Device: EPM7032AELC44-10 

The MAX ® 

family of devices are high-density, high performance devices based on 

Altera’s second-generation MAX architecture. The EEPROM-based devices operate 

with a 3.3-V supply voltage and provide 600 to 10,000 usable gates and counter 

speeds of up to 303.0 MHz, dependant on specific device. 

EPM7032AE features: 

32 macrocells 


3.3V supply voltage with 2.5 to 5V I/Os 



The daughter board includes one 44 pin and one 84 pin PLCC socket providing 

support for any of the following devices: EPM3032A, EPM3064A, EPM7032S, 

EPM7064S, EPM7128S, EPM7160S, EPM7032AE, EPM7064AE, EPM7128AE, 

EPM7032B, EPM7064B, EPM7032S, EPM7064S, EPM7128S, EPM7160S. 


Xilinx ® 

CoolRunner ® 

-II 

Device: XC2C256-6PQ208C 

The Xilinx ® 

CoolRunner ® 

-II CPLDs deliver the high speed and ease of use associated 

with the XC9500/XL/XV CPLD family with the extremely low power versatility 

of the XPLA3 family in a single CPLD. Low power consumption and high-speed 

operation are combined into a single family that is easy to use and cost effective. 

XC2C256 features: 

256 macrocells 

2 separate I/O banks 


1.8V supply voltage with 1.5 to 3.3V I/Os 

Fast Zero Power (FZP) architecture 


Xilinx ® 

CoolRunner ® 

XPLA3 

Device: XCR3256XL-12PQ208C 

The CoolRunner ® 

XPLA3 (eXtended Programmable Logic Array) family of CPLDs 

is targeted for low power systems that include portable, handheld, and power 

sensitive applications. Each member of the XPLA3 family includes Fast Zero 

Power (FZP) design technology that combines low power and high speed. 

XCR3256XL features: 



3.3V supply voltage with 3.3 and 5V I/Os 

Fast Zero Power (FZP) architecture 


Xilinx ® 

XC9500XL 

Device: XC95288XL-6PQ208C 

The FastFLASH XC9500XL family is a 3.3V CPLD family targeted for highperformance, 

low-voltage applications in leading edge communications and 

computing systems, where high device reliability and low power dissipation 

is important. 

XC95288XL features: 



3.3V supply voltage with 2.5 to 5V I/Os 


Xilinx ® 

XC9500XV 

Device: XC95288XV-6PQ208C 

The XC9500XV family is a 2.5V CPLD family targeted for high-performance, 

low-voltage applications in leading edge communications and computing systems, 

where high device reliability and low power dissipation is important. 

XC95288XV features: 


4 separate I/O banks 


2.5V supply voltage with 1.8 to 3.3V I/Os 

Split-rail I/O structure with multiple output drive level capability 


13

SECTION 03 DEVICE REFERENCE GUIDE NANOBOARD-NB1 2004 

14 

Device reference guide: FPGA 

Vendor 

Family 

General Logic Capabilities 

Communications Clocks 

Device 

Operating Voltage 

Configuration Memory (Bits) 

Daughter Board Available 

Logic Elements* 

Actel ProASICPlus APA075 3.3 - - 3,072 27 - - 3,072 2 - 2 180 Y 




Actel ProASICPlus APA600 3.3 - 21,504 126 - - 21,504 2 - 2 180 Y 



Altera Cyclone EP1C3 1.5 0.63M - 2,910 59 - - 2,910 34 - 1 320 Y 



Altera Cyclone EP1C12 1.5 2.32M 12,060 239 - - 12,060 103 - 2 320 Y 

Altera Cyclone EP1C20 1.5 3.56M 20,060 294 - - 20,060 129 - 2 320 Y 

Altera Stratix EP1S10 1.5 3.53M 10,570 920 24 - 10,570 88 - 6 420 Y 

Altera Stratix EP1S20 1.5 5.90M - 18,460 1,669 40 - 18,460 132 - 6 420 Y 






Altera Stratix GX EP1SGX10C 1.5 3.58M - 10,570 920 24 - 10,570 42 4, 8 4 420 Y 

Altera Stratix GX EP1SGX10D 1.5 3.58M - 10,570 920 24 - 10,570 42 4, 8 4 420 Y 

Altera Stratix GX EP1SGX25C 1.5 7.95M - 25,660 1,944 40 - 25,660 76 4, 8, 16 4 420 Y 

Altera Stratix GX EP1SGX25D 1.5 7.95M - 25,660 1,944 40 - 25,660 76 4, 8, 16 4 420 Y 

Altera Stratix GX EP1SGX25F 1.5 7.95M - 25,660 1,944 40 - 25,660 76 4, 8, 16 4 420 Y 

Altera Stratix GX EP1SGX40D 1.5 12.53M - 41,250 3,423 56 - 41,250 88 8, 20 8 420 Y 

Altera Stratix GX EP1SGX40G 1.5 12.53M - 41,250 3,423 56 - 41,250 88 8, 20 8 420 Y 

Xilinx Spartan2 XC2S15 2.5 0.2M - 432 16 - 6 384 - - 4 200 Y 

Xilinx Spartan2 XC2S30 2.5 0.4M - 972 24 - 14 864 - - 4 200 Y 

Xilinx Spartan2 XC2S50 2.5 0.6M - 1,728 32 - 24 1,536 - - 4 200 Y 



Xilinx Spartan2 XC2S200 2.5 1.4M 5,292 56 - 74 4,704 - - 4 200 Y 

Xilinx Spartan2E XC2S50E 1.8 0.6M - 1,728 32 - 24 1,536 83 - 4 320 Y 




Xilinx Spartan2E XC2S300E 1.8 1.9M 6,912 64 - 96 6,144 120 - 4 320 Y 


Xilinx Spartan2E XC2S600E 1.8 4.0M 15,552 288 - 216 13,824 205 - 4 320 Y 

Xilinx Spartan3 XC3S50 1.2 0.4M - 1,728 72 4 12 1,536 56 - 2 330 Y 



Xilinx Spartan3 XC3S1000 1.2 3.2M 17,280 432 24 120 15,360 175 - 4 330 Y 


*For Actel ProASICPlus, a logic element is the equivalent of a logic module/tile 

For Altera Cyclone/Stratix/Stratix GX, a logic element is defined as a 4-input LUT + register + carry chain with carry select 

For Xilinx Spartan-3, a logic element/cell is defined as a 4-input LUT + flip-flop 

For Xilinx Spartan-II/IIE, a logic element/cell is defined as a 4-input LUT + a register 

For Xilinx Virtex/E/II/II PRO, a logic element/cell is defined as a 4-input LUT + flip flop + carry logic 

Important: Verify all data in this document with the device data sheets found at the vendor website 

Total Block RAM Bits (K) 

Dedicated Multipliers 

(18 x 18) 

Total Distributed RAM Bits (K) 

Registers 

Maximum Differential 

I/O Pairs 

NanoBoard-NB1 2004 – LiveDesign-enabled FPGA-based development board www.altium.com/nanoboard 

Transceivers Channels 

Digital Clock Manager (DCM) 

DLL/PLL 

Max Clock Frequency (MHz) 

Phase-Shifting 

Frequency Synthesis 

Clocks 

Global Clock Lines 

No. of Supported I/O 

Standards 

Maximum Available User I/O 

I/O Voltage Levels 

Programmable Drive Strength 

Programmable Slew-Rate 

Y 4 4 158 2.5, 3.3 N Y N TQFP100, TQFP144, PQFP208, FBGA144 

Y 4 4 242 2.5, 3.3 N Y N TQFP100, PQFP208, PBGA456, FBGA144, FBGA256 

Y 4 4 290 2.5, 3.3 N Y N PQFP208, PBGA456, FBGA144, FBGA256 

Y 4 4 344 2.5, 3.3 N Y N PQFP208, PBGA456, FBGA144, FBGA256, FBGA484 

Y 4 4 454 2.5, 3.3 N Y N PQFP208, PBGA456, FBGA256, FBGA484, FBGA676 



Y 8 10 104 1.5, 1.8, 2.5, 3.3 Y Y N 100-Pin TQFP, 144-Pin TQFP 

Y 8 10 301 1.5, 1.8 2.5, 3.3 Y Y N 324-Pin BGA, 400-Pin BGA 

Y 8 10 185 1.5, 1.8, 2.5, 3.3 Y Y N 144-Pin TQFP, 240-Pin PQFP, 256-Pin BGA 

Y 8 10 249 1.5, 1.8, 2.5, 3.3 Y Y N 240-Pin PQFP, 256-Pin BGA, 324-Pin BGA 

Y 8 10 301 1.5, 1.8, 2.5, 3.3 Y Y N 324-Pin BGA, 400-Pin BGA 

Y 16 26 426 1.5, 1.8, 2.5, 3.3 Y Y Y 484-Pin BGA, 672-Pin BGA, 672-Pin,BGA, 780-Pin BGA 

Y 16 26 586 1.5, 1.8, 2.5, 3.3 Y Y Y 484-Pin BGA, 672-Pin BGA, 672-Pin,BGA, 780-Pin BGA 

Y 16 26 706 1.5, 1.8, 2.5, 3.3 Y Y Y 672-Pin BGA, 672-Pin BGA, 780-Pin BGA, 1,020-Pin BGA 

Y 16 26 726 1.5, 1.8, 2.5, 3.3 Y Y Y 780-Pin BGA, 956-Pin BGA, 1,020-Pin BGA 

Y 16 26 822 1.5, 1.8, 2.5, 3.3 Y Y Y 780-Pin BGA, 956-Pin BGA, 1,020-Pin BGA, 1,508-Pin BGA 

Y 16 26 1,022 1.5, 1.8, 2.5, 3.3 Y Y Y 956-Pin BGA, 1,020-Pin BGA, 1,508-Pin BGA 

Y 16 26 1,203 1.5, 1.8, 2.5, 3.3 Y Y Y 956-Pin BGA, 1,020-Pin BGA, 1,508-Pin BGA 

Y 16 27 330 1.5, 1.8, 2.5, 3.3 Y Y Y 672-Pin BGA 

Y 16 27 330 1.5, 1.8, 2.5, 3.3 Y Y Y 672-Pin BGA 

Y 16 27 426 1.5, 1.8, 2.5, 3.3 Y Y Y 672-Pin BGA 

Y 16 27 542 1.5, 1.8, 2.5, 3.3 Y Y Y 672-Pin BGA, 1,020-Pin BGA 

Y 16 27 542 1.5, 1.8, 2.5, 3.3 Y Y Y 1,020-Pin BGA 

Y 16 27 548 1.5, 1.8, 2.5, 3.3 Y Y Y 1,020-Pin BGA 

Y 16 27 548 1.5, 1.8, 2.5, 3.3 Y Y Y 1,020-Pin BGA 

Y 4 16 86 1.5, 2.5, 3.3 Y Y N VQ100, TQ144, CS144 

Y 4 16 132 1.5, 2.5, 3.3 Y Y N VQ100, TQ144, CS144, PQ208 

Y 4 16 176 1.5, 2.5, 3.3 Y Y N TQ144, PQ208, FG256 

Y 4 16 196 1.5, 2.5, 3.3 Y Y N TQ144, PQ208, FG256, FG456 

Y 4 16 260 1.5, 2.5, 3.3 Y Y N PQ208, FG256, FG456 

Y 4 16 284 1.5, 2.5, 3.3 Y Y N PQ208, FG256, FG456 

Y 4 19 182 1.5, 1.8, 2.5, 3.3 Y Y N TQ144, PQ208, FT256 

Y 4 19 202 1.5, 1.8, 2.5, 3.3 Y Y N TQ144, PQ208, FT256, FG456 

Y 4 19 265 1.5, 1.8, 2.5, 3.3 Y Y N PQ208, FT256, FG456 

Y 4 19 289 1.5, 1.8, 2.5, 3.3 Y Y N PQ208, FT256, FG456 

Y 4 19 329 1.5, 1.8, 2.5, 3.3 Y Y N PQ208, FT256, FG456 

Y 4 19 410 1.5, 1.8, 2.5, 3.3 Y Y N FT256, FG456, FG676 

Y 4 19 514 1.5, 1.8, 2.5, 3.3 Y Y N FG456, FG676 

Y 8 26 124 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 Y Y N VQ100, TQ144, PQ208 

Y 8 26 173 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 Y Y N VQ100, TQ144, PQ208, FT256 

Y 8 26 264 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 Y Y N TQ144, PQ208, FT256, FG320, FG456 

Y 8 26 391 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 Y Y N FT256, FG320, FG456, FG676 

Y 8 26 487 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 Y Y N FG320, FG456, FG676 

continued overleaf 

I/O Packages 

Programmable Pin Termination 

Packages Available 


15


16 

Device reference guide: FPGA (continued) 

Vendor 

Family 

General Logic Capabilities 

Communications Clocks 



Configuration Memory (Bits) 


Logic Elements* 


Xilinx Spartan3 XC3S4000 1.2 11.3M - 62,208 1,728 96 432 55,296 312 - 4 330 Y 

Xilinx Spartan3 XC3S5000 1.2 13.3M - 74,880 1,872 104 520 66,560 344 - 4 330 Y 

Xilinx Virtex XCV50 2.5 0.5M - 1,728 32 - 24 1,728 - - 4 180 - 









Xilinx Virtex2 XC2V40 1.5 0.4M - 576 72 4 8 512 44 - 4 420 Y 

Xilinx Virtex2 XC2V80 1.5 0.6M - 1,152 144 8 16 1,024 60 - 4 420 Y 



Xilinx Virtex2 XC2V1000 1.5 4.1M 11,520 720 40 160 10,240 216 - 8 420 Y 


Xilinx Virtex2 XC2V2000 1.5 7.5M - 24,192 1,008 56 336 21,504 312 - 8 420 Y 



Xilinx Virtex2 XC2V6000 1.5 21.9M - 76,032 2,592 144 1,056 67,584 552 - 12 420 Y 

Xilinx Virtex2 XC2V8000 1.5 29.1M - 104,882 3,024 168 1,456 93,184 554 - 12 420 Y 

Xilinx Virtex2Pro XC2VP2 1.5 1.3M - 3,168 216 12 44 2,816 100 4 4 420 Y 

Xilinx Virtex2Pro XC2VP4 1.5 3.0M - 6,768 504 28 94 6,016 172 4 4 420 Y 

Xilinx Virtex2Pro XC2VP7 1.5 4.4M 11,088 792 44 154 9,856 196 8 4 420 Y 

Xilinx Virtex2Pro XC2VP20 1.5 8.2M - 20,880 1,584 88 290 18,560 276 8 8 420 Y 

Xilinx Virtex2Pro XC2VP30 1.5 11.3M - 30,816 2,448 136 428 27,392 372 8 8 420 Y 

Xilinx Virtex2Pro XC2VP40 1.5 15.5M - 43,632 3,456 192 606 38,784 396 0, 12 8 420 Y 

Xilinx Virtex2Pro XC2VP50 1.5 19.0M - 53,136 4,176 232 738 47,232 420 0, 16 8 420 Y 

Xilinx Virtex2Pro XC2VP70 1.5 25.6M - 74,448 5,904 328 1,034 66,176 492 16, 20 8 420 Y 

Xilinx Virtex2Pro XC2VP100 1.5 33.5M - 99,216 7,992 444 1,378 88,192 572 0, 20 12 420 Y 

Xilinx VirtexE XCV50E 1.8 0.6M - 1,728 64 - 24 1,728 83 - 8 320 - 










Xilinx VirtexE XCV3200E 1.8 15.5M - 73,008 832 - 1,014 73,008 344 - 8 320 - 

*For Actel ProASICPlus, a logic element is the equivalent of a logic module/tile 

For Altera Cyclone/Stratix/Stratix GX, a logic element is defined as a 4-input LUT + register + carry chain with carry select 

For Xilinx Spartan-3, a logic element/cell is defined as a 4-input LUT + flip-flop 

For Xilinx Spartan-II/IIE, a logic element/cell is defined as a 4-input LUT + a register 

For Xilinx Virtex/E/II/II PRO, a logic element/cell is defined as a 4-input LUT + flip flop + carry logic 


Total Block RAM Bits (K) 

Dedicated Multipliers 

(18 x 18) 

Total Distributed RAM Bits (K) 

Registers 

Maximum Differential 

I/O Pairs 


Transceivers Channels 

Digital Clock Manager (DCM) 

DLL/PLL 

Max Clock Frequency (MHz) 

Phase-Shifting 

Frequency Synthesis 

Clocks 

Global Clock Lines 

No. of Supported I/O 

Standards 



I/O Packages 

Programmable Drive Strength 

Y 8 26 565 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 Y Y N FG676, FG900 

Y 8 26 712 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 Y Y N FG900, FG1156 

Y 8 26 784 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 Y Y N FG900, FG1156 

- 4 15 180 1.5, 2.5, 3.3 Y Y N CS144, TQ144, PQ240, BG256, FG256 

- 4 15 180 1.5, 2.5, 3.3 Y Y N CS144, TQ144, PQ240, BG256, FG256 

- 4 15 260 1.5, 2.5, 3.3 Y Y N PQ240, BG256, BG352, FG256, FG456 

- 4 15 284 1.5, 2.5, 3.3 Y Y N PQ240, BG256, BG352, FG256, FG456 

- 4 15 316 1.5, 2.5, 3.3 Y Y N PQ240, BG352, BG432, FG456 

- 4 15 404 1.5, 2.5, 3.3 Y Y N HQ240, BG432, BG560, FG676 

- 4 15 512 1.5, 2.5, 3.3 Y Y N HQ240, BG432, BG560, FG676, FG680 

- 4 15 512 1.5, 2.5, 3.3 Y Y N HQ240, BG432, BG560, FG676, FG680 

- 4 15 512 1.5, 2.5, 3.3 Y Y N BG560, FG680 

Y 16 34 88 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 Y Y Y CS144, FG256 

Y 16 34 120 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 Y Y Y CS144, FG256 

Y 16 34 200 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 Y Y Y CS144, FG256, FG456 

Y 16 34 264 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 Y Y Y FG256, FG456 

Y 16 34 432 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 Y Y Y FG256, FG456, FF896, BG575 

Y 16 34 528 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 Y Y Y FG676, FF896, BG575 

Y 16 34 624 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 Y Y Y FG676, FF896, BG575, BF957 

Y 16 34 720 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 Y Y Y FG676, FF1152, BG728, BF957 

Y 16 34 912 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 Y Y Y FF1152, FF1517, BF957 

Y 16 34 1,104 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 Y Y Y FF1152, FF1517, BF957 

Y 16 34 1,108 1.2, 1.5, 1.8, 2.5, 3.0, 3.3 Y Y Y FF1152, FF1517 

Y 16 32 204 1.5, 1.8, 2.5, 3.3 Y Y Y FG256, FG456, FF672 

Y 16 32 348 1.5, 1.8, 2.5, 3.3 Y Y Y FG256, FG456, FF672 

Y 16 32 396 1.5, 1.8, 2.5, 3.3 Y Y Y FG456, FF672, FF896 

Y 16 32 564 1.5, 1.8, 2.5, 3.3 Y Y Y FG676, FF896, FF1152 

Y 16 32 644 1.5, 1.8, 2.5, 3.3 Y Y Y FG676, FF896, FF1152 

Y 16 32 804 1.5, 1.8, 2.5, 3.3 Y Y Y FG676, FF1152, FF1148 

Y 16 32 852 1.5, 1.8, 2.5, 3.3 Y Y Y FF1152, FF1148. FF1517 

Y 16 32 996 1.5, 1.8, 2.5, 3.3 Y Y Y FF1517, FF1704 

Y 16 32 1,164 1.5, 1.8, 2.5, 3.3 Y Y Y FF1704, FF1696 

- 4 19 176 1.5, 1.8, 2.5, 3.3 Y Y N CS144, PQ240, FG256 

- 4 19 196 1.5, 1.8, 2.5, 3.3 Y Y N CS144, PQ240, BG352, FG256 

- 4 19 284 1.5, 1.8, 2.5, 3.3 Y Y N CS144, PQ240, BG352, FG256, FG456 

- 4 19 316 1.5, 1.8, 2.5, 3.3 Y Y N PQ240, BG352, BG432, FG256, FG456 

- 4 19 404 1.5, 1.8, 2.5, 3.3 Y Y N PQ240, BG432, BG560, FG676 

- 4 19 512 1.5, 1.8, 2.5, 3.3 Y Y N HQ240, BG432, BG560, FG676, FG680, FG900 

- 4 19 660 1.5, 1.8, 2.5, 3.3 Y Y N HQ240, BG560, FG680, FG860, FG900, FG1156 

- 4 19 724 1.5, 1.8, 2.5, 3.3 Y Y N BG560, FG680, FG860, FG900, FG1156 

- 4 19 804 1.5, 1.8, 2.5, 3.3 Y Y N BG560, FG680, FG860, FG1156 

- 4 19 804 1.5, 1.8, 2.5, 3.3 Y Y N FG1156 

- 4 19 804 1.5, 1.8, 2.5, 3.3 Y Y N FG1156 

Programmable Slew-Rate 

Programmable Pin Termination 



17


18 

Device reference guide: CPLD 

Vendor 

Family 

General Logic Capabilities I/O 

Packages 




Macrocells 

Registers 

Altera MAX 3000A EPM3032A 3.3 32 32 32 34 4.5, 7.5, 10 2.5, 3.3, 5.0 2 Y 

Altera MAX 3000A EPM3064A 3.3 64 64 32 66 4.5, 7.5, 10 2.5, 3.3, 5.0 2 Y 

Altera MAX 3000A EPM3128A 3.3 - 128 128 32 98 5.0, 7.5, 10 2.5, 3.3, 5.0 2 Y 

Altera MAX 3000A EPM3256A 3.3 - 256 256 32 161 7.5, 10 2.5, 3.3, 5.0 2 Y 

Altera MAX 3000A EPM3512A 3.3 - 512 512 32 208 7.5, 10 2.5, 3.3, 5.0 2 Y 

Altera MAX 7000AE EPM7032AE 3.3 * 32 32 32 36 4.5, 7.5, 10 2.5, 3.3, 5.0 2 Y 

Altera MAX 7000AE EPM7064AE 3.3 64 64 32 68 4.5, 7.5, 10 2.5, 3.3, 5.0 2 Y 

Altera MAX 7000AE EPM7128AE 3.3 128 128 32 100 5.0, 7.5, 10 2.5, 3.3, 5.0 2 Y 

Altera MAX 7000AE EPM7256AE 3.3 - 256 256 32 164 5.5, 7.5, 10 2.5, 3.3, 5.0 2 Y 

Altera MAX 7000AE EPM7512AE 3.3 - 512 512 32 212 7.5, 10, 12 2.5, 3.3, 5.0 2 Y 

Altera MAX 7000B EPM7032B 2.5 32 32 32 36 3.5, 5.0, 7.5 1.8, 2.5, 3.3 2 Y 

Altera MAX 7000B EPM7064B 2.5 64 64 32 68 3.5, 5.0, 7.5 1.8, 2.5, 3.3 2 Y 

Altera MAX 7000B EPM7128B 2.5 - 128 128 32 100 4.0, 7.5, 10 1.8, 2.5, 3.3 2 Y 



Altera MAX 7000S EPM7032S 5.0 32 32 32 36 5.0, 6.0, 7.5, 10 3.3, 5.0 2 Y 

Altera MAX 7000S EPM7064S 5.0 64 64 32 68 5.0, 6.0, 7.5, 10 3.3, 5.0 2 Y 

Altera MAX 7000S EPM7128S 5.0 128 128 32 100 6.0, 7.5, 10, 15 3.3, 5.0 2 Y 

Altera MAX 7000S EPM7160S 5.0 160 160 32 104 6.0, 7.5, 10 3.3, 5.0 2 Y 

Altera MAX 7000S EPM7192S 5.0 - 192 192 32 124 7.5, 10, 15 3.3, 5.0 2 Y 

Altera MAX 7000S EPM7256S 5.0 - 256 256 32 164 7.5, 10, 15 3.3, 5.0 2 Y 

Xilinx CoolRunner2 XC2C32 1.8 - 32 32 40 33 3, 4, 6 1.5, 1.8, 2.5, 3.3 3 Y 

Xilinx CoolRunner2 XC2C32A 1.8 - 32 32 40 33 3, 4, 6 1.5, 1.8, 2.5, 3.3 3 Y 


Xilinx CoolRunner2 XC2C64A 1.8 - 64 64 40 64 4, 5, 7 1.5, 1.8, 2.5, 3.3 3 Y 

Xilinx CoolRunner2 XC2C128 1.8 - 128 128 40 100 4.5, 6, 7 1.5, 1.8, 2.5, 3.3 3 Y 

Xilinx CoolRunner2 XC2C256 1.8 256 256 40 184 5, 6, 7 1.5, 1.8, 2.5, 3.3 3 Y 



Xilinx CoolRunnerXPLA3 XCR3032XL 3.3 - 32 32 48 36 5, 7.5, 10 3.3, 5.0 4 Y 



Xilinx CoolRunnerXPLA3 XCR3256XL 3.3 256 256 48 164 7.5, 10, 12 3.3, 5.0 4 Y 

Xilinx CoolRunnerXPLA3 XCR3384XL 3.3 - 384 384 48 220 7.5, 10, 12 3.3, 5.0 4 Y 

Xilinx CoolRunnerXPLA3 XCR3512XL 3.3 - 512 512 48 260 7.5, 10, 12 3.3, 5.0 4 Y 

Xilinx XC9500 XC9536 5.0 - 36 36 90 34 5, 6, 7.5, 10, 15 5.0 3 Y 

Xilinx XC9500 XC95108 5.0 - 108 108 90 108 7.5, 10, 15, 20 5.0 3 Y 

Xilinx XC9500 XC95144 5.0 - 144 144 90 133 7.5, 10, 15 5.0 3 Y 

Xilinx XC9500 XC95216 5.0 - 216 216 90 166 10, 15, 20 5.0 3 Y 

Xilinx XC9500 XC95288 5.0 - 288 288 90 192 10, 15, 20 5.0 3 Y 

Xilinx XC9500XL XC9536XL 3.3 - 36 36 90 36 5, 7.5, 10 2.5, 3.3, 5.0 3 Y 



Xilinx XC9500XL XC95288XL 3.3 288 288 90 192 6, 7.5, 10 2.5, 3.3, 5.0 3 Y 

Xilinx XC9500XV XC9536XV 2.5 - 36 36 90 36 5, 7.5 1.8, 2.5, 3.3 3 Y 



Xilinx XC9500XV XC95288XV 2.5 288 288 90 192 6, 7.5, 10 1.8, 2.5, 3.3 3 Y 

*Installed 


Product Terms per Macrocell 


Pin-to-Pin Delay (Speed ns) 



No. Global Clocks 

Programmable Slew Rate 


44-Pin PLCC/TQFP 

44-Pin PLCC/TQFP, 100-Pin TQFP 

100-Pin TQFP, 144-Pin TQFP, 256-Pin BGA 

144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA 

208-Pin PQFP, 256-Pin BGA 


44-Pin PLCC/TQFP, 100-Pin TQFP, 100-Pin BGA 

84-Pin PLCC, 100-Pin TQFP, 100-Pin BGA, 144-Pin TQFP, 256-Pin BGA 

100-Pin TQFP, 100-Pin BGA, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA 

144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA, 256-Pin BGA 

44-Pin PLCC/TQFP, 49-Pin BGA 

44-Pin TQFP, 49-Pin BGA, 100-Pin TQFP, 100-Pin BGA 

100-Pin TQFP, 100-Pin BGA, 144-Pin TQFP, 256-Pin BGA 

100-Pin TQFP, 144-Pin TQFP, 169-Pin BGA, 208-Pin PQFP, 256-Pin BGA 

144-Pin TQFP, 169-Pin BGA, 208-Pin PQFP, 256-Pin BGA, 256-Pin BGA 


44-Pin PLCC/TQFP, 84-Pin PLCC, 100-Pin TQFP 

84-Pin PLCC, 100-Pin PQFP/TQFP, 160-Pin PQFP 

84-Pin PLCC, 100-Pin TQFP, 160-Pin PQFP 

160-Pin PQFP 

208-Pin PQFP/RQFP 

PC44, VQ44, CP56 

PC44, VQ44, CP56 

PC44, VQ44, CP56, VQ100 

PC44, VQ44, CP56, VQ100 

VQ100, CP132, TQ144 

VQ100, CP132, TQ144, PQ208, FT256 

TQ144, PQ208, FT256, FG324 

PQ208, FT256, FG324 

PC44, VQ44, CS48 

PC44, VQ44, CS48, CP56, VQ100 

VQ100, CS144, TQ144 

TQ144, PQ208, FG256, CS280 

TQ144, PQ208, FT256, FG324 

PQ208, FT256, FG324 

VQ44, PC44, CS48 

PC84, TQ100, PQ100, PQ160 

TQ100, PQ100, PQ160 

PQ160, HQ208, BG352 

HQ208, BG352 

PC44, VQ44, CS48, VQ64 

PC44, VQ44, CS48, VQ64, TQ100 

TQ100, CS144, TQ144 

TQ144, PQ208, BG256, FG256, CS280 

PC44, VQ44, CS48 

PC44, VQ44, CS48, TQ100 

TQ100, CS144, TQ144 

TQ144, PQ208, FG256, CS280 


19


20 

Device reference guide: Configuration 

Vendor 

Family 


Xilinx XC18V00 XC18V04 4M VQ44, PC44 

Xilinx XC18V00 XC18V02 2M VQ44, PC44 

Xilinx XC18V00 XC18V01 1M VQ44, PC20, SO20 

Xilinx XC18V00 XC18V512 512K VQ44, PC20, SO20 

Xilinx XCF XCF01S 1M VO20 



Xilinx XCF XCF08P 8M VO48, FS48 




Size (bits) 



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Altium Japan K.K. 

Resona Gotanda building 7F 

1-23-9, Nishi-Gotanda, 

Shinagawa-ku Tokyo 141-0031 

Ph: +81 3 5436 2501 

Fax: +81 3 5436 2505 

Email: info.jp@altium.com 

Switzerland 

Protel AG 

(A subsidiary of Altium Limited) 

Unterdorfstrasse 1 

CH-4334 Sisseln 

Ph: +41 (0) 62 866 41 11 

Fax: +41 (0) 62 866 41 10 

Email: info.ch@altium.com 

China 

Altium Shanghai Representative Office 

Unit 13B, Hua Du Mansion 

No 838 Zhang Yang Road 

Pudong, Shanghai 200122 

Ph: +86 21 6876 4016 

Fax: +86 21 6876 4015 

Email: info.cn@altium.com 

For a full list of Altium resellers 

visit www.altium.com 

For more information about Altium’s complete range of electronics hardware and software 

design products visit: www.altium.com 

Copyright © 2004 Altium Limited. 

Altium, CAMtastic, CircuitStudio, Design Explorer, DXP, LiveDesign, NanoBoard, NanoTalk, Nexar, nVisage, P-CAD, Protel, Situs, 

TASKING, and Topological Autorouting and their respective logos are trademarks or registered trademarks of Altium Limited or its 

subsidiaries. AutoCAD is a registered trademark of Autodesk, Inc., Board Station and PADS are registered trademarks of Mentor 

Graphics Corp., CoolRunner, Spartan and Virtex are registered trademarks of Xilinx, Inc., Cyclone, MAX and Stratix are trademarks 

of Altera Corporation, OrCAD, OrCAD Capture, OrCAD Layout and SPECCTRA are registered trademarks of Cadence Design 

Systems, Inc., and Windows and Visual SourceSafe are registered trademarks of Microsoft Corporation. All other registered or 

unregistered trademarks referenced herein are the property of their respective owners, and no trademark rights to the same are claimed.

Device reference guide - Altium

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