A Top-Down Verilog-A Design on the Analog-and-Digital
A Top-Down Verilog-A Design on the Analog-and-Digital
A Top-Down Verilog-A Design on the Analog-and-Digital
You also want an ePaper? Increase the reach of your titles
YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.
Chapter 4. Test Bench Study …..……………………………….…….… 32<br />
4-1. R<strong>and</strong>om-Bit Noise Generator…….………………………….…. 32<br />
4-1-1. Uniform-Distributed R<strong>and</strong>om-Bit Generator…….….. 33<br />
4-1-2. Normal-Distributed R<strong>and</strong>om-Bit Generator…………. 34<br />
4-1-3. Pseudo-R<strong>and</strong>om R<strong>and</strong>om-Bit Generator……………… 35<br />
4-2. R<strong>and</strong>om-Bit Included DAC ……….………….………………… 37<br />
Chapter 5. Entire DPLL <str<strong>on</strong>g>Design</str<strong>on</strong>g> <strong>and</strong> Simulati<strong>on</strong>………….…….…… 39<br />
5-1. Schematic of <strong>the</strong> Entire DPLL <str<strong>on</strong>g>Design</str<strong>on</strong>g>…...…..….………….… 39<br />
5-2. Simulati<strong>on</strong> Waveform of <strong>the</strong> Entire DPLL <str<strong>on</strong>g>Design</str<strong>on</strong>g>….…….… 40<br />
Chapter 6. C<strong>on</strong>clusi<strong>on</strong>……………………………………………….…… 41<br />
References……………………………………………………….……….…… 43<br />
3