A Top-Down Verilog-A Design on the Analog-and-Digital

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Index Abstract …………………………………………………….………………. 6 Preview ……………………………………………………….……………... 7 Chapter Chapter 1. Introduction ………………….………………………..……. 10 1-1. <strong>Design</strong> Objectives…………..…………………………………..… 10 1-2. Conventional Phase locked Loop………………………………. 12 1-2-1. Voltage-Controlled-Oscillator (VCO)…………………. 13 1-2-2. Charge-Pump Loop Filter………………………………..14 1-2-3. Phase Detector (PD)…………………………..………….. 15 Chapter 2. Matlab System-Level <strong>Design</strong> and Simulation…….…….. 17 2-1. M-File Block <strong>Design</strong> and Simulation………………….………. 17 2-1-1. Voltage-Controlled-Oscillator…………………….……. 18 2-2. SimuLink Block Diagram and Simulation……………………. 19 2-2-1. Phase-Frequency Detector………………………………. 20 Chapter 3. <strong>Verilog</strong>-A System-Level <strong>Design</strong> and Simulation….……. 21 3-1. VCO <strong>Design</strong> in <strong>Verilog</strong>-A………………………………………... 21 3-2. Practical <strong>Design</strong> of PFD in Digital Block………….…………. 24 2
Chapter 4. Test Bench Study …..……………………………….…….… 32 4-1. Random-Bit Noise Generator…….………………………….…. 32 4-1-1. Uniform-Distributed Random-Bit Generator…….….. 33 4-1-2. Normal-Distributed Random-Bit Generator…………. 34 4-1-3. Pseudo-Random Random-Bit Generator……………… 35 4-2. Random-Bit Included DAC ……….………….………………… 37 Chapter 5. Entire DPLL <strong>Design</strong> and Simulation………….…….…… 39 5-1. Schematic of the Entire DPLL <strong>Design</strong>…...…..….………….… 39 5-2. Simulation Waveform of the Entire DPLL <strong>Design</strong>….…….… 40 Chapter 6. Conclusion……………………………………………….…… 41 References……………………………………………………….……….…… 43 3
Page 1: A Top-Down
Page 5 and 6: Appendix D. Netlist Lists (D-1).Net
Page 7 and 8: Preview While many types of signal
Page 9 and 10: Fig.1 Magnetic hard-disk read chann
Page 11 and 12: cosine equalizer, phase (and level)
Page 13 and 14: Fig.4 Block diagram and transfer fu
Page 15 and 16: 1-2-3. Phase Detector Traditionally
Page 17 and 18: Chapter 2 Matlab System-Level <stro
Page 19 and 20: function y = vco(x,range,Fs) %VCO V
Page 21 and 22: Chapter 3 Verilog-
Page 23 and 24: Fig.15 Waveform of the VCO output a
Page 25 and 26: eceives a discharge command. Fig.18
Page 27 and 28: end else begin end if ((osc_value =
Page 29 and 30: end else begin end if ((vin_up ==0)
Page 31 and 32: Fig.21 A practical phase-frequency
Page 33 and 34: generators are discussed. 4-1-1. Un
Page 35 and 36: Fig.25 Waveform of the Normal-Distr
Page 37 and 38: 4-2. Random-Bit-Generator-Included
Page 39 and 40: Chapter 5 Entire DPLL Desig
Page 41 and 42: Chapter 6 Conclusion According to t
Page 43 and 44: Refere nce A [1] Razavi, De
Page 45 and 46: 1-9. 1-10. . 31 st Processing In Th
Page 47 and 48: Appendix A: Verilog</strong
Page 49 and 50: `include "constants.h" `include "di
Page 51 and 52: end generate i (5, 0) begin end vdo
Page 53 and 54:
code = 0.0; generate j (6,0) begin
Page 55 and 56:
end generate k(5,0) begin end vdout
Page 57 and 58:
(A-9) LevelShifter // Veril
Page 59 and 60:
Appendix C: (C-1) 3-Tap FIR simulat
Page 61 and 62:
(C-5) Simulation results of a low-p
Page 63 and 64:
Appendix D: (D-1) Netlist of the Ra
Page 65 and 66:
(D-2) Netlist of the Entire DPLL <s
Page 67 and 68:
delay=0 rise=1n fall=1n width=2.906
Page 69:
ahdl_include "/rcc4/student/wangc/c
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A Top-Down Verilog-A Design on the Analog-and-Digital

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