Xilinx DS813 LogiCORE IP 10-Gigabit Ethernet MAC v11.1, Data ...

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Applications LogiCORE IP 10-Gigabit Ethernet MAC v11.1 Figure 1 shows a typical Ethernet system architecture and the 10-Gigabit Ethernet MAC core within it. The MAC and all the blocks to the right are defined in Ethernet IEEE specifications. X-Ref Target - Figure 1 Figure 2 shows the 10-Gigabit Ethernet MAC core connected to a physical layer (PHY) device, for example, an optical module using the XGMII interface. X-Ref Target - Figure 2 TCP IP FIFO I/F User Logic (FIFO Example Design) MAC PCS WIS PMA PMD Figure 1: Typical Ethernet System Architecture 10-Gigabit Ethernet MAC Core DDR Regs MDIO Optical Module with XGMII I/F Figure 2: 10-Gigabit Ethernet MAC Core Connected to PHY with XGMII Interface DS813 March 1, 2011 www.xilinx.com 2 Product Specification
LogiCORE IP 10-Gigabit Ethernet MAC v11.1 The 10-Gigabit Ethernet MAC core is designed to be easily attached to the Xilinx IP XAUI core, the Xilinx IP RXAUI core, and the Xilinx IP 10G Ethernet PCS/PMA. Figure 3 illustrates the 10-Gigabit Ethernet MAC and XAUI cores in a system using an XPAK optical module. X-Ref Target - Figure 3 User Logic (FIFO Example Design) 10-Gigabit Ethernet MAC Core Figure 3: 10-Gigabit Ethernet MAC Core Used with Xilinx XAUI Core Functional Description XAUI Core XPAK Optical Module low speed management signals Figure 4 illustrates a block diagram of the 10-Gigabit Ethernet MAC core implementation. The major functional blocks of the core include the following: AXI4-Stream client-side interface: Designed for simple attachment of user logic Transmitter Receiver Flow Control block: Implements both Receive Flow Control and Transmit Flow Control Reconciliation Sublayer (RS): Processes XGMII Local Fault and Remote Fault messages and handles DDR conversion AXI4-Lite management interface and MDIO (optional) Statistics counters (optional) XGMII interface: Connection to the physical layer device or logic DS813 March 1, 2011 www.xilinx.com 3 Product Specification
Page 1: Introduction The LogiCORE IP 10-Gig
Page 5 and 6: Core Interfaces AXI4-Stream Interfa
Page 7 and 8: Management Interface LogiCORE IP 10
Page 9 and 10: Configuration Registers LogiCORE IP
Page 11 and 12: Table 12: Receiver Configuration Si
Page 13 and 14: Clocks and Resets LogiCORE IP 10-Gi
Page 15 and 16: Spartan-6 FPGAs LogiCORE IP 10-Giga
Page 17: Revision History Date Version Revis

Xilinx DS813 LogiCORE IP 10-Gigabit Ethernet MAC v11.1, Data ...

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