Intel 45nm Process Overview - UCSB CAD & Test

More documents

Recommendations

Info

Multiple Microprocessors Single Core Dual Core Quad Core 33
Defect Reduction Trend • Mature yield demonstrated 2 years after 65 nm Defect Density (log scale) 130 nm 90 nm 65 nm 45 nm 2000 2001 2002 2003 2004 2005 2006 2007 2008
Page 1 and 2: A 45nm Logic Technology with High-k
Page 3 and 4: Introduction • SiON scaling runni
Page 5 and 6: High-k + Metal Gate Challenges •
Page 7 and 8: Process Features • 45 nm Groundru
Page 9 and 10: 45nm Design Rules Layer Pitch (nm)
Page 11 and 12: SRAM Cells • 0.346 μm 2 and 0.38
Page 13 and 14: Outline • Introduction • Proces
Page 15 and 16: Transistor Process Flow Dummy Polys
Page 17 and 18: Transistor Process Flow N+ N+ STI S
Page 25 and 26: Transistor Features • 35 nm min.
Page 27 and 28: Threshold Voltage (V) 0.50 0.45 0.4
Page 29 and 30: IOFF (nA/μm) NMOS I DSAT vs. I OFF
Page 31 and 32: Transistor Performance vs. Gate Pit
Page 33 and 34: Transistor Reliability Challenges
Page 35 and 36: Transistor Reliability: Bias Temper
Page 37 and 38: Interconnects • Metal 1-3 pitches
Page 39 and 40: 100% Lead Free Packaging • Enviro
Page 41: 153Mb SRAM Test Vehicle • Process
Page 45 and 46: Conclusions • A 45 nm technology
Page 47: For further information on Intel's

Intel 45nm Process Overview - UCSB CAD & Test

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?