Slides

A Configurable
Asynchronous
Pseudorandom Bit
Sequence Generator
Alex Chow, Bill Coates, David Hopkins
VLSI Research Group
Sun Microsystems Laboratories
1

Outline
• Pseudorandom bit sequences (PRBSs)
• Traditional PRBS generators
• An asynchronous implementation
> Design
> Properties
• Extension to other types of circuits
A. Chow - Mar 14 2007
ASYNC 2007 2

Properties & Applications of PRBSs
• A statistically “random” bit sequence
> Behaves like noise
> Carries an equal number of 1's and 0's
> Has near zero correlation with other PRBSs
• Useful for
> Testing I/O channels
> Cryptography
> Spread-spectrum communication systems
A. Chow - Mar 14 2007
ASYNC 2007 3

Generating a PRBS
Using a Linear Feedback Shift Register (LFSR)
• Next input bit is a linear function of the current state
CLK
A. Chow - Mar 14 2007
Feedback Logic
t 1 t 2 t 3 t N
OUT
ASYNC 2007 4

Generating a PRBS
Using a Linear Feedback Shift Register (LFSR)
• Next input bit is a linear function of the current state
• Feedback logic is a sum (XOR) of a subset of bits in
the register
CLK
A. Chow - Mar 14 2007
t 1 t 2 t 3 t N
OUT
ASYNC 2007 5

Feedback Tap Sequence
• Not every tap sequence generates a PRBS
• A PRBS must be a maximal-length sequence
> An N-stage LFSR produces a PRBS of length 2 N – 1
> The PRBS contains every N-bit pattern (except all 0's)
• Maximal tap sequence found using finite-field math
A. Chow - Mar 14 2007
ASYNC 2007 6

Feedback Tap Sequence
Notation
• We list the positions of all tapped bits
• Example: 5-stage LFSR with taps at positions 3,5
> Notation: N = 5, Taps = [5,3]
> Produces a PRBS with length 2 5 – 1 = 31
CLK
A. Chow - Mar 14 2007
1 2 3 4 5
OUT
ASYNC 2007 7

LFSR Logical Constraints
• Properties of the PRBS strictly defined by LFSR
topology, i.e.
> Number of LFSR stages
> Tap sequence (location and number of taps)
• Each LFSR circuit can produce only one PRBS
A. Chow - Mar 14 2007
ASYNC 2007 8

An Asynchronous PRBS Generator
• Started as a “Friday project”
• Replace shift register with asynchronous FIFO stages
• We present a GasP implementation
A. Chow - Mar 14 2007
ASYNC 2007 9

Two-Tap PRBS Generator
The Circuit
A. Chow - Mar 14 2007
L
Tap 1 Tap 2
L L
L L L
L
Feedback
Logic
DATA OUT
CTL OUT
Data path
Control path
ASYNC 2007 10

Two-Tap PRBS Generator
GasP Control Elements
A. Chow - Mar 14 2007
L
Control
merge
Tap 1 Tap 2
L L
L L L
L
Control
branch
Feedback
Logic
DATA OUT
CTL OUT
Data path
Control path
ASYNC 2007 11

Enforcing Proper Bit Sequence
• LFSR uses global clock
> Every stage contains valid data
> Data moves in lock-step
> Bit sequencing and synchronization implicitly enforced
• Async implementation requires explicit control
> Not every stage contains valid data
> Data bits may propagate autonomously
> Must explicitly synchronize pairs of control tokens to
guarantee correct data sequencing
A. Chow - Mar 14 2007
ASYNC 2007 12

Two-Tap PRBS Generator
Example
• Emulate 5-stage LFSR with taps = [5,3]
A. Chow - Mar 14 2007
X
L
I
X
X X X
L L L L L L L
STOP
DATA
OUT
CTL
OUT
ASYNC 2007 13
L
Data bit
Control token

Two-Tap PRBS Generator
Example
• Emulate 5-stage LFSR with taps = [5,3]
A. Chow - Mar 14 2007
X
L
I
X
X X DATA
L L L L L L L L
OUT
Data bit
Control token
CTL
OUT
ASYNC 2007 14

Two-Tap PRBS Generator
Example
• Emulate 5-stage LFSR with taps = [5,3]
A. Chow - Mar 14 2007
L
I
X
X X
X X DATA
L L L L L L L L
OUT
Data bit
Control token
CTL
OUT
ASYNC 2007 15

Two-Tap PRBS Generator
Example
• Emulate 5-stage LFSR with taps = [5,3]
A. Chow - Mar 14 2007
X
L
I
X
X X X
1L 2L 3L 4L 5L 6L 7L 8L
STOP
Physical taps
[8,4]
Data bit
Control token
DATA
OUT
CTL
OUT
ASYNC 2007 16

Two-Tap PRBS Generator
Example
• Emulate 5-stage LFSR with taps = [5,3]
A. Chow - Mar 14 2007
X
L
I
X
X X X
L
1
L
2
L
3
L L L L
4
L
5
STOP
Logical taps
[5,3]
Data bit
Control token
DATA
OUT
CTL
OUT
ASYNC 2007 17

Physical & Logical Independence
• LFSR:
> Physical tap sequence = logical tap sequence
• Asynchronous implementation:
> Logical tap sequence depends only on token distribution
> Physical circuit structure need only enable logical tap
sequence, not match it
A. Chow - Mar 14 2007
ASYNC 2007 18

Configurability
• Async control decouples logical bit distribution from
physical circuit structure
• One circuit can produce many different PRBSs
A. Chow - Mar 14 2007
ASYNC 2007 19

Generating Different PRBSs
Example
• Construct a circuit to generate all two-tap maximallength
patterns of order N ≤ 7
A. Chow - Mar 14 2007
Order N
Logical Taps # Tokens Seg 1 # Tokens Seg 2
3 [3,2] 2 1
4 [4,3] 3 1
5 [5,3] 3 2
6 [6,5] 5 1
7 [7,4] 4 3
7 [7,6] 6 1
ASYNC 2007 20

Generating All Patterns for N ≤ 7
• N = 3
• Taps = [3,2]
A. Chow - Mar 14 2007
X
L
I
X
X X X
X X X
L L L L L L L L L
STOP
DATA
OUT
CTL
OUT
ASYNC 2007 21

Generating All Patterns for N ≤ 7
• N = 4
• Taps = [4,3]
A. Chow - Mar 14 2007
X
L
I
X
X X
X X X
L L L L L L L L L
STOP
DATA
OUT
CTL
OUT
ASYNC 2007 22

Generating All Patterns for N ≤ 7
• N = 5
• Taps = [5,3]
A. Chow - Mar 14 2007
X
L L
X
X
L
I
X
X X
L L L L L L L
STOP
DATA
OUT
CTL
OUT
ASYNC 2007 23

Generating All Patterns for N ≤ 7
• N = 6
• Taps = [6,5]
A. Chow - Mar 14 2007
L L
X
L
I
X
X X X
L L L L L L L
STOP
DATA
OUT
CTL
OUT
ASYNC 2007 24

Generating All Patterns for N ≤ 7
• N = 7A
• Taps = [7,4]
A. Chow - Mar 14 2007
X
L L
X
L
I
X
X
L L L L L L L
STOP
DATA
OUT
CTL
OUT
ASYNC 2007 25

Generating All Patterns for N ≤ 7
• N = 7B
• Taps = [7,6]
A. Chow - Mar 14 2007
L L
X
L
I
X
X X X
L L L L L L L
STOP
DATA
OUT
CTL
OUT
ASYNC 2007 26

Throughput and I/O
• Throughput varies for different patterns
> Because token occupancy is different for each pattern
• May use the generator in synchronous systems
> Take the output through async-to-clocked interfaces
> Clock rate must be lower than minimum async throughput
A. Chow - Mar 14 2007
ASYNC 2007 27

Summary
• Async design decouples number and distribution of
logical bits from physical shift register structure
• Exploit this orthogonality to let one FIFO circuit
adopt multiple logical configurations
• PRBS generator serves as an illustrative example
> Can apply this idea to other circuits
> Other examples: CRC generators, encoders, filters
A. Chow - Mar 14 2007
ASYNC 2007 28

Extension
• Example: Cyclic Redundancy Checksum (CRC)
generator
IN
CLK
A. Chow - Mar 14 2007
1 2 3 4 5
OUT
ASYNC 2007 29

Questions
Alex Chow
alex.chow@sun.com
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