Accurate and Accurate and Efficient SSN Modeling

Accurate and
Efficient SSN
Modeling
Chris Herrick

� What is SSN?
� Model Types
Agenda
� MModeling d li ttechniques h i
� Simulation Tips and Tricks
� Incorporating the latest Ansoft features
� Conclusions

What is SSN?
� Simultaneous Switching Noise is the
deleterious effect of simultaneous
switching outputs (SSO).
�� Also referred to as Ground Bounce or
Power Bounce
� Exacerbated by poor return path and high
loop inductance
� Measured by fixing victim High or Low
and monitoring output

Why is SSN important?
� SSN Analysis gives more complete picture
of both Signal Integrity and Power Integrity
�� Ignoring the effects of SSO can result in a
failed system design
� IIncreased d challenges h ll as speeds d iincrease,
voltages decrease and current increases
� Helps uncover problematic crosstalk
� Helps p evaluate true PDN pperformance

Ground/Power
Bounce
Ref: BGA Crosstalk by Howard Johnson, March 1, 2005
Typical Setup
Crosstalk
Probe location
�Setupp
�Victim is held “high” or
“low”
�Many I/O’s driven at the
same time
�Worst case Data
Patterns transmitted
�Noise monitored on
victim from PCB location

Ref: BGA Crosstalk by Howard Johnson, March 1, 2005
SSN From Ground Bounce
�BGA between PCB power
and d ground d planes l
�At time zero switches C
closed and F transitions
Low -> huge I/O current
transient
�V glitch = L gnd di/dt
�Victim D is held low will
transmit voltage V glitch

Model Types
� Need to include all relevant effects of
system; Both SI and PI
�� Need models for: ICs, ICs Packages, Packages PCBs
and VRMs
� MModels d l may bbe extracted t t d or gathered th d ffrom
vendors
� Each model should be independently
verified for accuracy

SIwave Extraction
PCB
Voltage
SSource
VRM
Designer Environment
Terminations
N
N
SIwave Extraction SIwave Extraction
N
N
Data
Interposer Package N Drivers
SIwave Extraction SIwave Extraction
NNexxim i EEngine i
N
Interposer Package N Receivers
N

Driver Models
� Need to accurately model Signals
and dPPower
� Obtain transistor level models if at
all possible
� IBIS tends to be pessimistic
because current scales linearly
with ihiincreased ddi drivers
� Verify waveforms for single
driver AND during SSO
˃
Spice IBIS
Rail Collapse
During SSO
Lab

Package Model
� Obtain layout and extract if possible
� Add Solderballs, Solderbumps,
Bondwires to model
� Group Power/Ground pins on die side
�� Extract Bank of signals

PCB Model
� Extract individual Signal
Power/Ground Pins at
Package if feasible
� Place port at VRM
� Pl Place port t on victim i ti ffar
BGA
Ports
VRM
Port
end Vic.
PPortt Terminations
� Terminate far end of line
with resistors

VRM Model
� Almost always modeled as an ideal
voltage source
�� Could also use non non-ideal ideal circuit model
� Important for DC-DC switching power
supplies
li

Modeling Techniques
� Kitchen Sink - Simulate Everything!
� Generally not practical
�� Nearest Neighbors
� Only simulate what’s relevant
� Signal grouping
� Combine many pins into one and scale driver
� Current Mirror
� Mirror a single g driver multiple p
times

Nearest Neighbors
1. Identify Victim and nearest
neighbors i hb bbased d on proximity i it
2. Extract largest segment you can
afford with available hardware
3. Attached Driver models to each
signal pin
Well placed
PWR/GND balls limit
return path loop area
High g Speed p
Packages
generally have
banks-easy to
segment
O15 Load Load GND Load Load SPY SPY O15 Load Load Load GND Load Load O25 Load Load GND clko clko Load Load O25 GND
Load GND Load Load O15 Load Load Load GND Load O25 Load Load Load GND Load Load O25 Load Load Load GND Load Load Load Load GND
GND Load Load Load O15 Load Load Load GND Load Load Load Load GND Load Load O25 Load Load Load GND clko clko
Load Load O25 Load Load Load Load
Load Load O15 Load Load GND Load Load Load O15 Load Load Load GND Load O25 SPY Load GND Load Load Load O25
Load Load Load
Load Load Load Load O15 Load Load Load Load Load Load Load O25 SPY Load Load Load O25 Load Load Load GND Load GND Load GND Load
Load Load Load Load AUX Load Load GND Load Load O25 clki AUX Load Load Load Load O25 Load Load Load GND Load Load
GND O15 Load Load Load GND Load
Load Load Load O15 Load Load GND Load Load Load Load O25 Load Load clki GND INT INT O25 Load AUX Load Load Load Load Load O25
Load Load GND
O15 Load Load Load GND Load Load Load O15 Load Load Load SPY GND Load Load Load Load Load Load GND Load Load VDO Load Load Load
Load O25 AUX Load
GND Load Load Load Load O15 AUX INT GND Load SPY INT O25 Load Load INT GND Load Load INT O25 clko Load Load GND clko
Load Load O15 Load INT Load GND GND INT Load O25 Load
Load
GND INT GND INT Load O25 Load Load Load Load GDO Load Load SPY
Load Load INT Load Load
O15 Load Load Load GND Load INT GND INT GND Load Load GND Load Load INT GND INT GND AUX Load Load GND Load Load Load O25 SPY
Load Load
Load Load Load Load SPY Load Load AUX GND INT GND INT Load Load O25 Load INT GND INT GND Load Load Load O25 Load Load Load GND
GND O15 clki Load
GND Load O15 SPY AUX Load Load GND Load INT clki O25 Load Load Load Load GND Load Load INT Load O25 INT Load Load GND
Load Load GND Load Load Load
Load
INT GND INT GND INT Load O25 Load AUX Load Load GND
Load
O15
Load INT GND GND INT GND AUX GND O25 Load Load GND
GND O15 INT Load Load
AUX Load Load GND INT GND INT GND O25 GND INT GND INT GND GND
GND O25 GND AUX GND VDI GDI INT
GND
INT GND INT GND VDA GND
GND
GND O25 GND
GND INT GND O25 GND INT GND AUX GND GND INT INT GND Load Load
Load O33 Load AUX GND INT GND INT GND INT Load O25
GND
GND Load Load GND
AUX Load O33 Load INT GND INT GND INT O25 Load Load Load Load
GND Load Load Load GND Load
INT Load Load INT Load Load Load Load clki O25 GND Load Load GND Load Load AUX O25 GND Load Load O33 GND INT Load GND
Load O33 Load Load Load GND GND INT Load O25 Load INT clki INT GND INT GND AUX O25 Load Load Load Load
GND Load Load INT Load GND Load Load
SPY Load O33 Load Load Load Load AUX GND INT GND INT Load Load GND Load Load GND INT GND Load GND Load Load Load Load O25
Load GND INT
SPY Load Load Load GND Load Load Load O33 Load INT GND INT GND Load Load Load O25 Load INT GND INT GND Load INT Load O25 Load clko Load clko
Load GND Load Load Load O33 INT Load GND INT Load Load SPY O25 Load Load Load GND INT Load AUX O25 Load Load GND Load
Load Load Load GND
INT
Load AUX Load O25 Load SPY Load Load GND SPY Load Load Load O25 Load Load Load Load Load O25
O33 Load Load Load GND Load Load
Load Load Load AUX O33 Load INT Load INT GND clki Load Load SPY O25 Load Load GND Load Load Load Load O25 Load Load Load
O33 Load GND
Load Load Load Load Load O33 Load Load GND Load Load AUX clki O25 Load Load Load Load AUX Load O25 Load Load Load GND
GND Load Load GND Load
Load Load Load O33 Load Load Load GND Load Load Load O25 Load Load Load GND Load Load Load O25 Load Load Load Load GND Load
O33 Load Load Load GND Load Load O33 Load Load Load Load GND Load Load O25 Load Load Load Load Load Load Load Load
Load Load Load Load Load GND Load O25
Load Load GND Load Load O33 Load Load Load GND Load Load Load O25 Load Load Load Load GND Load Load Load Load Load Load Load GND
Load O25
GND Load Load Load Load Load GND Load O25 GND GND GND Load Load Load Load O25 Load Load Load Load GND GND
O33 Load Load Load Load
O33 Load Load Load GND Load Load O33 Load GND clko clko O25 SPY SPY Load Load GND Load Load O25
GND Load Load Load Load

Nearest Neighbor Tradeoffs
� Most accurate and flexible method
� Simulates Skew/Delay between lines
� All Allows diff different t ddata t patterns tt
� Long transient simulation
� Potential for convergence trouble

1. Apply pin grouping to signals
at Die side
2. Attach single port for
Aggressor group
3. Extract PCB ports as before
4. Create subcircuit for driver
model
5. Multiply subcircuit M times and
connect to aggressor port
Signal Grouping
x25
X1 CK1 CK2 Input Output Power driver M=25

Signal Grouping Tradeoffs
� Much quicker q analysis y
� Greatly reduces port count
� Eliminates convergence issues with multiple drivers
� Not simulating XTLK induced skew
� Same data pattern used on all aggressors
� Assumes all lines are similar in impedance and delay
� Lose information on individual lines
�� One bad signal line will affect net results

1. Use same extracted model
as “Nearest Neighbors”
2. Place driver on one
aggressor
3. Monitor current at signal and
die connections using series
Current Mirroring
0V source Aggressors
0v Voltage sources CCCS
4. Attach CCCS to all other
signal lines mirroring same
current as driver
5. Attach CCCS to die scaling
current x M-1 drivers
Ref: Digital Signal Integrity, Young
Die Current
Scaled xM-1

Current Mirroring Tradeoffs
� Much quicker analysis
� Eliminates convergence issues with
multiple drivers
� Still can inspect individual s-parameters
� Not simulating XTLK induced skew
� Same data pattern p used on all aggressors gg
� Assumes all lines are similar in impedance
and delay

Simulation Tips and Tricks
� Convolution versus state-space
state space
� Frequency sweep setup
� Mi Mixed d port t iimpedances d
� Achieving Convergence

S-parameter S parameter Handling
State State-Space Space (Default)
Convolution
� Much faster for long transients
� Passivity enforcement
� Causality enforcement
� Up front cost building model
� Does not extrapolate
� May not achieve fit on noisy
data
�� Cannot model long delays, delays ~22
λ
� More options for convergence
� Can handle long delays
� Data filtering options
� Extrapolates well
� Sim time increases
quadratically with tran time
� Requires linearly spaced data

DC point i t required i d
Coarser Coa se ssweep eep
used at Higher
frequencies
Sweep Setup
Log g sweep p helps p
capture low
frequencies
important to PDN
Set max even
higher than knee
Discrete Sweep
frequency: State
ensures causality
space doesn’t
and passivity
extrapolate! t l t !
enforcement

Choose port
impedances p that
are relatively
close to structure
impedance
Use 1 or .1 ohms
for power, 50
ohms for signal
lines
This helps model
accuracy and
avoids 0dB values
in touchstone file
Port Impedances
Designer dynamic link to SIwave will preserve port impedances

Achieving Convergence
� Inspect individual models (Divide and Conquer)
� RRealistic li ti ddata, t passive, i causal l
� Sufficient bandwidth, resolution
� Frequency dependent materials
� Bypass/Deactivate components to find root cause
� Check state-space fit; tighten s_element.reltol
� Increase ss_element.max_states element.max states
� Slow risetimes/Soften Edges
� Try generic sources, i.e. Gaussian PRBS
� RReduce d .tran t step t
� Decrease reltol and abstol
� Try convolutions 1-3
� Reduce s-parameter port count

Schematic Setup
� Schematic setup can be tedious and error prone
when working with large number of components
� Modular/hierarchical blocks can aid with design g
management and debugging
� Four methods for automatic setup: p
� Dynamic Linking
� APDS
� Designer I/O Wizard
� SIwave SIwizard

Dynamic Links
Add additional model
choices by dragging
models onto symbol y
Add symbols for each
block in the channel

Stand Stand-alone alone GUI to
setup transient analysis
Specifically tailored to
SSN of DDR interfaces
APDS

Designer I/O Wizard
� Launch GUI from Designer 4.1
� Rapid setup of drivers for high pin
counts
� Easily link generic model types for
y g yp
all blocks in the channel

SIwizard in v4.0 SIwave
11. Select signal nets to
simulate
2. Assign IBIS TX/RX models
to pins p on nets
3. Identify component
power/ground nets
4. (Optional) Set VRM
parameters
5. Set Transient Simulation
parameters
Pin info preserved from layout

Conclusions
� SSN is a powerful simulation offering
insight to both Signal and Power behavior
�� Accurate device models are critical
� Set realistic goals and choose the best
method th d tto obtain bt i th them
� Ansoft has the capabilities and the
automation to perform accurate and
efficient SSN simulations

Current Mirroring
� Place drivers for a single aggressor and the
victim. Mirror the current to all other
aggressors using CCCS. CCCS
Original
Ref: Digital Signal Integrity, Young
Original g
w/ Detectors
Mirrored