Presentation - Modeling and Analysis of Interconnects for RFIC
Presentation - Modeling and Analysis of Interconnects for RFIC
Presentation - Modeling and Analysis of Interconnects for RFIC
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1<br />
2002 Empowering Pr<strong>of</strong>itability<br />
<strong>RFIC</strong> interconnect<br />
10Gb/s Channel <strong>Modeling</strong><br />
<strong>Modeling</strong> <strong>and</strong> <strong>Analysis</strong> <strong>of</strong> <strong>Interconnects</strong> <strong>for</strong> <strong>RFIC</strong><br />
<strong>Presentation</strong> #2
◗ Introduction<br />
Outline<br />
◗ Electrical <strong>Modeling</strong> Solution<br />
◗ EMPOWERING Design Flow<br />
◗ Differential VCO Design<br />
◗ Spiral Inductor Design<br />
◗ On-chip <strong>Interconnects</strong><br />
◗ QFN Package<br />
◗ Conclusion<br />
◗ References
◗ Industry challenge<br />
<strong>RFIC</strong> Design<br />
◗ Great dem<strong>and</strong> on high per<strong>for</strong>mance<br />
◗ Increasing operating frequency while decreasing<br />
size<br />
◗ Reducing development costs <strong>and</strong> time-to-market<br />
◗ Electrical modeling has become one <strong>of</strong> the<br />
most important factors<br />
◗ An accurate electrical model <strong>of</strong><br />
interconnect is an essential part <strong>of</strong> doing<br />
design
What Is An Interconnect <strong>for</strong><br />
<strong>RFIC</strong>?<br />
◗ Path used to carry a signal from one point to another<br />
◗ On-chip interconnects<br />
◗ Spiral inductor<br />
◗ MIM capacitor<br />
◗ Routing traces<br />
◗ Package<br />
◗ C4 Bump<br />
◗ Bondwire<br />
◗ Solderball<br />
◗ Traces<br />
BYP<br />
Tune<br />
GND<br />
SHDN<br />
GND<br />
GND<br />
OUTIP<br />
IND<br />
GND<br />
VCC<br />
OUTIN<br />
GND<br />
GND<br />
OUTQN<br />
GND<br />
OUTQP
Why are <strong>Interconnects</strong><br />
Important to Model?<br />
◗ At lower frequencies, the main loss occurs in the conductor, which is<br />
negligible. Most designers will assume an ideal short in between<br />
connection points<br />
Active<br />
Component<br />
Active<br />
Component<br />
◗ At higher frequencies, there are now 2 loss mechanisms - conductor<br />
<strong>and</strong> substrate loss. The conductor loss is now an important due to<br />
skin effect. Substrate loss will be dominant in the lossy dielectric<br />
medium <strong>of</strong> silicon<br />
Active<br />
Component<br />
L R<br />
Active<br />
Component<br />
◗ Neglecting these 2 modeling parameters will mean the electrical<br />
per<strong>for</strong>mance will be <strong>of</strong>f from expected results, which will cause a<br />
loss in pr<strong>of</strong>itability<br />
C<br />
L R<br />
C
Electrical <strong>Modeling</strong><br />
IC-1 wire<br />
Driver<br />
Physical Geometry<br />
lead frame<br />
signal line<br />
PKG-1 PKG-2<br />
PCB<br />
wire<br />
Electrical Model<br />
L R<br />
C<br />
C<br />
L R<br />
IC-2<br />
Electrical <strong>Modeling</strong><br />
- EM Simulation Based<br />
- Measurement Based<br />
Receiver<br />
IC-1 PKG-1 PCB PKG-2 IC-2
Electrical <strong>Modeling</strong> Procedure<br />
Initial Design<br />
Simulation Based<br />
<strong>Modeling</strong><br />
OK?<br />
Yes<br />
Sample Fabrication<br />
Measurement Based<br />
<strong>Modeling</strong><br />
No<br />
Modification<br />
OK?<br />
No<br />
Yes<br />
Electrical Model
Full-Wave<br />
Quasi-Static<br />
Ans<strong>of</strong>t Electrical <strong>Modeling</strong><br />
SPICE<br />
Fields<br />
Ans<strong>of</strong>t SIWave<br />
Ans<strong>of</strong>t TPA<br />
SPICE/DML/IBIS<br />
RLC<br />
Solution<br />
Design Automation Ans<strong>of</strong>t Optimetrics<br />
Cadence<br />
Zuken Avanti<br />
Mentor<br />
Ans<strong>of</strong>tLinks<br />
IGES STEP<br />
Fields/Radiation<br />
Full-Wave SPICE<br />
S-Parameters<br />
Ans<strong>of</strong>t HFSS<br />
Ans<strong>of</strong>t SpiceLink<br />
SPICE/DML/IBIS<br />
RLC(G)<br />
Fields<br />
Current/Radiation<br />
Full-Wave SPICE<br />
S-Parameters<br />
Ans<strong>of</strong>t Designer<br />
Planar EM<br />
GDSII<br />
DXF<br />
ACIS
Ans<strong>of</strong>t Electrical <strong>Modeling</strong><br />
Advantage<br />
◗ Ans<strong>of</strong>t has a strategic advantage over all <strong>of</strong><br />
EDA s<strong>of</strong>tware companies because <strong>of</strong>:<br />
◗ Advanced Technology<br />
◗ Adaptive meshing<br />
◗ PEEC<br />
◗ Solve-on-dem<strong>and</strong><br />
◗ Integrated translation to 3 rd party layout programs<br />
◗ Diversity <strong>of</strong> Solving techniques
Geometry<br />
(no mesh data)<br />
Create Initial Mesh<br />
Create Initial Mesh<br />
Calculate Field<br />
Calculate Field<br />
Calculate<br />
Field Accuracy<br />
DE Acceptable?<br />
DE Acceptable?<br />
Yes<br />
Display<br />
Simulation Results<br />
Adaptive Mesh<br />
No<br />
Refine Mesh<br />
Refine Mesh<br />
Initial<br />
23981 tets<br />
Final<br />
320620tets
Integration<br />
Cadence<br />
Zuken Avanti<br />
Mentor<br />
Ans<strong>of</strong>tLinks<br />
IGES STEP<br />
◗ By having this tight integration to layout tools, it<br />
saves the engineer time in redrawing structure<br />
◗ Allows engineer to solve the problems as close to<br />
the actual product as possible.<br />
◗ Surface Roughness<br />
◗ Etched traces<br />
◗ Process variability<br />
◗ Allows the engineer to pull data from many<br />
different sources. Not “pigeon-holed”
Diversity <strong>of</strong> Solving Techniques<br />
Solving Method<br />
Desired Output<br />
FWS<br />
RLCG<br />
Eye Diagrams<br />
Parametrics<br />
Sensitivity<br />
FEM<br />
BEM<br />
Harmonic<br />
Balance<br />
PEEC<br />
Transient<br />
<strong>Analysis</strong><br />
S,Y,Z Parameters<br />
Fields<br />
Spice Sub-<br />
Circuits<br />
Radiation<br />
2D FEM<br />
DML<br />
IBIS<br />
Optimization<br />
MOM<br />
BER<br />
Q-Factor<br />
N-Port<br />
Devices
EMPOWERING Design Flow<br />
Ans<strong>of</strong>t Designer<br />
Circuit/System/Planar EM<br />
Cadence<br />
Zuken Avanti<br />
Mentor<br />
Power, Ground / BGA<br />
S-, Y-, Z-<br />
R, L, C<br />
Matrix / Parameters<br />
S-, Y-, Z-<br />
R, L, C<br />
Ans<strong>of</strong>tLinks<br />
GDSII<br />
DXF<br />
TPA / SIwave<br />
HFSS / SpiceLink<br />
with Optimetrics
Differential VCO<br />
Differential VCO [1]<br />
Differential VCO Layout VCO_Core<br />
LC Tank<br />
Resonator<br />
Feedback<br />
Gain block
Ans<strong>of</strong>tLinks <strong>for</strong> Virtuoso
3D Solid<br />
Model<br />
GDSII Translator<br />
2D Pr<strong>of</strong>iles
Center-tapped Multi-layer<br />
Differential Spiral Inductor [2]<br />
◗ Parasitic coupling between two inductors is canceled by differential mode<br />
◗ Differential Q is higher than Single-ended<br />
◗ Self-resonance frequency is higher than single-ended<br />
Port1<br />
Center-tap<br />
Port2<br />
Port3
Stack-up <strong>for</strong> Spiral Inductor<br />
Metal 8 Metal 7 Metal 6<br />
e r = 3.6<br />
e r = 4<br />
e r = 4<br />
e r = 4<br />
e r = 11.9<br />
Conductivity = 13.3333 S/m<br />
Passivation=0.875um<br />
TM8=0.9um<br />
SiO 2 =0.65um<br />
TM7=0.35um<br />
SiO 2 =0.45um<br />
Silicon=300um<br />
Copper<br />
Copper<br />
TM6=0.35um Copper<br />
SiO 2 =4.4um
Spiral Inductor Design<br />
Model Solved In HFSS<br />
Solutions exported <strong>for</strong><br />
use in Designer<br />
simulation<br />
3D model generated<br />
<strong>and</strong> parameterized as a<br />
function <strong>of</strong> (R i , W, S, N)<br />
Optimetrics<br />
Designer circuit specified<br />
<strong>and</strong> parameterized (R s , L s ,<br />
C s , R sub , C sub , C ox )<br />
(R s , L s , C s , R sub ,<br />
C sub , C ox )<br />
Resulting schematic saved <strong>and</strong><br />
parsed to provide Optimetrics<br />
with circuit values.<br />
R<strong>and</strong>om/Gradient optimization<br />
per<strong>for</strong>med to match circuit<br />
response to HFSS results.
S-Parameter<br />
S 11<br />
S 23 , S 32<br />
S 22 , S 33<br />
S 12 , S 13 , S 21 , S 31
Differential Q-factor<br />
Single-ended Q<br />
Differential Q
Phase Noise Comparison<br />
Spiral Inductor<br />
Ideal Inductor
On-chip <strong>Interconnects</strong>
Which <strong>Interconnects</strong> are Important to<br />
Model?<br />
◗ LC tank circuits are used <strong>for</strong> the oscillation frequencies. <strong>Interconnects</strong> can add capacitance <strong>and</strong><br />
inductance to these values which can throw <strong>of</strong>f the expected oscillation point.
Which <strong>Interconnects</strong> are Important to<br />
Model?<br />
◗ Reversed biased diodes are used as capacitors at a known value. The interconnects<br />
between these connections will invariably add to these capacitor's value.
Which <strong>Interconnects</strong> are Important to<br />
Model?<br />
• The interconnects between the VCO core cell will generate negative resistance which is<br />
the source <strong>of</strong> oscillation. It is important to know the parasitics that are present which will<br />
determine the oscillation point<br />
Figure 1: Interconnect in between Varactor Diodes
Out to<br />
Spiral<br />
4 Transistors<br />
Simplifying the Model<br />
Varactors<br />
4 Transistors<br />
Interconnect structures<br />
<strong>of</strong> importance
Source<br />
Spiral to Varactor Interconnect<br />
Sink<br />
0.04 ohms<br />
0.04 ohms<br />
Trace Parasitics<br />
0.006 nH<br />
0.006 nH<br />
6.4 fF<br />
0.05 nH 0.05 nH<br />
15.3 fF<br />
Ground Parasitics<br />
0.04 ohms<br />
0.04 ohms
Varactor to Varactor Interconnect<br />
Source<br />
Sink<br />
0.06 ohms<br />
0.04 ohms<br />
Trace Parasitics<br />
0.01 nH<br />
0.01 nH<br />
6.6 fF<br />
0.05 nH 0.05 nH<br />
17 fF<br />
Ground Parasitics<br />
0.06 ohms<br />
0.04 ohms
Transistor to Varactor Interconnect<br />
Sink<br />
Source<br />
0.13 ohms<br />
0.04 ohms<br />
Trace Parasitics<br />
0.02 nH<br />
0.02 nH<br />
5.4 fF<br />
0.05 nH 0.05 nH<br />
16.1 fF<br />
Ground Parasitics<br />
0.13 ohms<br />
0.04 ohms
0.5 mm<br />
Cu Leadframe<br />
Die Attach Material<br />
BYP<br />
Tune<br />
GND<br />
SHDN<br />
Down<br />
Bond<br />
GND<br />
GND<br />
QFN Package [3][4]<br />
Mold Compound<br />
Exposed Die<br />
Paddle<br />
OUTIP<br />
IND<br />
3.0 mm<br />
GND<br />
VCC<br />
0.3 mm 0.5 mm<br />
OUTIN<br />
GND<br />
Gold Wire<br />
Ground Bond<br />
GND<br />
OUTQN<br />
GND<br />
OUTQP<br />
3.0 mm<br />
� Package Descriptions:<br />
Package height 0.9 mm<br />
Body size 3 x 3 mm<br />
Exposed pad 1.25 x 1.25<br />
mm<br />
Die size 1.0 x 1.0<br />
mm<br />
Die thickness 0.30 mm
Exposed Die<br />
Paddle<br />
Package Model in HFSS<br />
Vias<br />
Die<br />
Port2<br />
Port4<br />
Ports<br />
Port1<br />
Port3<br />
Gold Wire<br />
Cu Leadframe
Package <strong>Analysis</strong> in HFSS<br />
◗ Final mesh size : 320620<br />
tets<br />
◗ Lumped gap source used<br />
◗ Solve surface option<br />
◗ ZERO_ORDER=1
S-parameter
S-parameter
LC VCO with <strong>Interconnects</strong>
Spectral Plot
Output Frequency & Power<br />
<strong>Interconnects</strong><br />
Ideal
Conclusion<br />
◗ Electrically modeling interconnects <strong>for</strong> <strong>RFIC</strong>s is very important to<br />
the first time success <strong>of</strong> the design.<br />
◗ Ans<strong>of</strong>t’s suite <strong>of</strong> s<strong>of</strong>tware provides all <strong>of</strong> the necessary electrical<br />
simulation engines to per<strong>for</strong>m accurate simulations <strong>of</strong> the <strong>RFIC</strong>.<br />
◗ Spiral Inductor – HFSS, Designer<br />
◗ <strong>Interconnects</strong> - Spicelink<br />
◗ QFN Package – HFSS, Spicelink<br />
◗ Circuit/System <strong>Analysis</strong> - Designer<br />
◗ An electrical model was made <strong>for</strong> every part <strong>of</strong> the differential<br />
VCO core including the interconnects.<br />
◗ Using the extracted models, in depth analysis <strong>of</strong> the <strong>RFIC</strong><br />
system within Designer provides results that are used to obtain<br />
phase noise plots.<br />
◗ Optimizing the phase noise provides the engineer a way to<br />
improve the design <strong>and</strong> improve pr<strong>of</strong>itability.
References<br />
1. P. Andreani, H. Sjol<strong>and</strong>, “Tail Current Noise<br />
Suppression in RF CMOS VCOs,” IEEE Jour. Solid-<br />
State Circuits, Vol. 37, No. 3, March 2002<br />
2. A. M. Niknejad, J. L. Tham, <strong>and</strong> R. G. Meyer, "Fully-<br />
Integrated Low Phase Noise Bipolar Differential VCOs<br />
at 2.9 <strong>and</strong> 4.4 GHz," Proceedings <strong>of</strong> the 25th European<br />
Solid-State Circuits Conference, 1999. p. 198-201.<br />
3. http://www.amkor.com/products/notes_papers/MLF_Ap<br />
pNote_0301.pdf<br />
4. http://www.jedec.org/ , JEDEC st<strong>and</strong>ard, “MO-220d”
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