CSCE 212: Example quiz answers 1. Assemble the following ...

CSCE 212: Example quiz answers
1. Assemble the following instruction into hexadecimal representation:
ADDI $2, $3, -8762
op rs rt imm
001000 00011 00010 1101110111000110
convert to hex => 2062DDC6
2. Translate the following high-level code to MIPS assembly. vals is an array of
half-words:
i=0;
sum=0;
while (vals[i]!=0) {
sum=sum+vals[i];
i++;
}
li $t0,0 # i=0
li $t1,0 # sum=0
loop sll $1,$t0,1 # adjust i to become for half word index
lh $t2, vals($1) # load vals[i]
beqz $t2,exit # check to see if we got a 0
add $t1, $t1, $t2 # if not, accumulate into sum
addi $t0, $t0, 1 # i=i+1
j loop # go back to condition check
3. Assume there is a MIPS pseudoinstruction named MERG16 rd, rs, rt that
merges two register values by:
1. moving the low-order 16 bits of rs into the low-order 16 bits of rd, and
2. moving the low-order 16 bits of rt into the high-order 16 bits of rd.
Translate the following instruction into MIPS machine instructions:
MERG16 $2, $3, $4
Do not change the values of any registers except $1 (use for intermediate
values) and $2 (the destination).
sll $2, $4, 16 # shift register $4 into position, keep in destination register
sll $1, $3, 16 # shift register $3 left…
srl $1, $1, 16 # ..then right to zero-out its 16 high-order bits
or $2, $2, $1 # merge the two values

4. Complete the following table by filling in the empty cells to connect MIPS
instruction types with their corresponding encoding format.
Instruction type Encoding format
Load and store instructions I-type
Branch instructions I-type
Arithmetic instructions having 2
R-type
register input operands
Shift instructions R-type
Jump (J, JAL) instructions J-type
5. Describe three different functions of the immediate field in the MIPS instruction
set.
constant operand for arithmetic, PC-relative branch offset for branches,
offset for base-offset addressing for loads and stores
6. When executing the ADDI instruction, the MIPS architecture sign-extends its 16bit
immediate field before adding it to the contents of register rs. Assume for this
question that the hardware designers saved costs by always zero-extending the
immediate value instead. As a result, any ADDI instruction with a negative
immediate value is treated as a pseudoinstruction by the assembler. When the
pseudoinstruction is assembled, it is converted into a series of instructions that
perform a software-based sign extension of the immediate. Assuming there have
been no other architectural changes, how is the following pseudoinstruction
translated:
ADDI $s0, $s1, -12
Hint: the first instruction in the translation moves the 16-bit immediate into
temporary register $1, which (in this case) results in register $1 having value
0000 FFF4. Three more instructions are needed:
1. ADDI $1, $0, -12
2. sll $1, $1, 16
3. sra $1, $1, 16
4. add $s0, $s1, $1

7. Describe what computation the following segment of assembly code is
performing. List what registers need to be initialized before the code begins and
how these registers are used.
li $s0, 0
lw $s2, 0($a1)
loop: lw $s1, 0($a0)
mult $s3, $s1, $s2
add $s0, $s0, $s3
addi $a0, $a0, 4
addi $a2, $a2, -1
bnez $a2, loop
multiplies each element of a word array, starting at address specified in $a0, by a
word value stored in memory at address in $a1, and accumulates a running sum of
the products into $s0. the array size is specified in $a2.
8. Translate the following high-level code to MIPS assembly:
for (i=0;i

9. Many CISC instruction set architectures, such as Intel IA-32 (x86) and IBM 360,
include a set of instructions that do computation using a datatype called binarycoded
decimal (BCD). BCD stores integer values by assigning binary-encoded
decimal values (0-9) into 4-bit fields. Eight of these 4-bit fields can be packed
into a 32-bit word, representing a value between 0 and 99,999,999. For
example, the (16-bit) value 0011 1001 0001 0101 represents 3,915 (instead of
14,613 as it would as a regular base-2 integer).
Assume we have a pseudoinstruction called CBCD rd, rs that converts the
binary value in register rs to an 8-digit packed BCD value written to register rd.
Show (for full credit) or describe (for partial credit) how CBCD $2, $3 could be
translated into MIPS instructions. Hint: how would you perform this base
conversion yourself?
Note that the following answer changes the value of $4 (used by this code as a
counter) and register $3 (the original rs register). This is not typical for
pseudoinstructions, but given the complexity we will allow it.
li $2, 0 # $2 = 0
li $4, 4 # $4 = 0
loop: li $1,10 # $1=10
mult $2,$2,$1 # multiply $2 by 10
sll $3,$3,4 # shift $3 4 bits to the left
srl $1,$3,28 # copy the left-most 4 bits of $3 into $1
add $2,$2,$1 # add $1 into $2
addi $4,$4,-1 # decrement counter
bgtz $4, loop
10. Write a sequence of MIPS assembly instructions that will swap the values of
registers $s0 and $s1 without using any additional registers or any loads
and stores.
Hint: this requires that you use the XOR instruction.
xor $s0,$s0,$s1
xor $s1,$s0,$s1
xor $s0,$s0,$s1