From Simple PALs to High- Speed, High-Density Leading Edge ...

From Simple PALs to High-
Speed, High-Density Leading
Edge FPGAs, Their Technologies
and Applications
John Birkner
birkner@quicklogic.com
http://www.quicklogic.com

PLDs - past, present and future
• From where we have come
• To where we are
• and where are we going

Vision of Programmable Logic
• To Empower Designers with silicon and
tools for fast time-to-design, low cost,
multiple design-spin, prototype and
production of electronic systems.
• To Envision products not otherwise possible
through Design Exploration and
increased Cycles of Learning

Origins
• PLA - Programmable Logic Array
– sum of products, AND/OR arrays
– instruction decoder applications
• 1972 - NSC introduces PLA
– 96 product, 14 in, 8 out, 24 pin .6 DIP
– targets EBCDIC to ASCII conversion

Origins (continued)
• PLA sparks interest, but . . .
is masked programmed like a ROM . . .
designers want programmability like PROM
• 1974 Electronic Arrays, Signetics, TI,
introduce FPLA, field programmable like
PROM

70’s Design Methods
• 54/74 TTL logic building blocks
– gates, muxes, registers, counters, ALUs
– average 30 equivalent gates per chip
– glue logic uses most PCB space with
16 pin DIPs
• Designers mix-and-match puzzle piece
TTL SSI/MSI to minimize DIP count
to complete processor/controller/memory
functions on one PCB

• PLD challenge:
Market Opportunity
– automate glue logic process with
programmable interconnect
– lift PCB traces to silicon substrate
• Problem: discover common denominator
macrocell library to replace TTL functions

Solution
• 1978 - MMI introduces
Programmable Array Logic - PAL
• Single programmable array achieves 35 ns Tpd
• 20 pin Skinny DIP space efficient package
• Effective at replacing 54/74 TTL glue logic
• PALASM synthesis, place route, software
allows designers to “design your own chip”
on a PROM programmer.

Early Applications of
Programmable Logic
• “The Soul of a New Machine”
Data General launches new computer in
record time-to-market by
overlapping PCB and PLD chip design
• Macintosh Computer designed in record
time using PLD for memory and IO control
• Ms PACMAN game achieves security and
time to market using PLDs

100,000,000
10,000,000
1,000,000
100,000
Logic Gate Growth
486
Pentium
386
10,000
8086
1,000
8080
100
1975 1980 1985 1990 1995 2000 2005

100,000,000
10,000,000
1,000,000
Logic Gate Growth 256M
100,000
64K
486
386
10,000
4K 8086
1,000
8080
100
1975 1980 1985 1990 1995 2000 2005
1M
16M
Pentium

100,000,000
10,000,000
1,000,000
Logic Gate Growth
256M
100,000
64K
486
386
10,000
QL24X32
4K 8086
EPM7256
1,000
XC2064
8080
PAL22R10
100
PAL16R8
1975 1980 1985 1990 1995 2000 2005
1M
16M
Pentium

• 2-input NAND
• four transistors
• 1/2 static RAM bit?
What is a gate?

PAL Architecture - one cell
• PAL16R8
• 8 cells per chip
• 12 gates per cell
• 20 pin DIP

PAL Architecture - two cells
• By doubling cells,
interconnect links
quadruple

FPGA Architecture - one cell
• QL3060
• 1584 cells per chip
• 12 gates per cell
• 456 pin BGA

FPGA Architecture - two cells
• By doubling cells, interconnect links double

Technology Migration
• Bipolar transistor, metal fuse, very high power
• CMOS UV erasable, med. power
• CMOS SRAM , re-configurable, med. power
• CMOS antifuse, OTP, low power
• CMOS EE, re-programmable, high power

40
35
30
25
20
15
10
5
Tpd - propagation delay
0
1975 1980 1985 1990 1995 2000 2005

500
450
400
350
300
250
200
150
100
50
LCC
DIP
Packages
QFP
TQFP
BGA
0
1975 1980 1985 1990 1995 2000 2005

• Design Process
Design Tools
– Design Entry, Synthesis, Place Route,
Simulation, Path Analysis, Programming
• Boolean Languages
– PALASM, ABLE, CUPL
• Schematic
• HDL
– VHDL, Verilog

Dini Design Methodology
• Enter design in HDL
– Use Synchronous Design where possible
• Synthesize, Place, Route
• Simulate for basic functionality
• Path Analyze for Fmax, setup and clock to out
• Hand craft critical paths using schematic as
last resort

Design Methodology
• State Machine Design
– Binary Encoded
(CPLD)
– One Hot State
(FPGA)
• Microcoded
– use embedded RAM
– up to 200 MHz
CLK
Status Inputs
Synchronous
Dual PROM Port RAM
Control Outputs
State

Embedded RAM in FPGA

Control Store

Arithmetic Logic Unit -
Schematic Block

Arithmetic Logic Unit -
Verilog Code

Embedded FIFO in FPGA

Waddr
WCLK
Data In
Dual Port RAM
Architecture
Write-Side
E
Read-Side
Raddr
RCLK
WE Bit n
of
Word m
RE RE
D Q
Data Out

PUSH
FULL
Write-Side
State Machine
Synchronous FIFO
0
1
UP
UP
WE
Waddr+2
Waddr
=
CLK
Raddr+1
Dual Port RAM
Data In Data Out
=
Read-Side
State Machine
0
1
UP
RE
POP
EMPTY

PUSH
FULL
WCLK
Write-Side
State Machine
Asynchronous FIFO
0
1
UP
E
E
WE
Waddr+2
Waddr+1
Waddr
Async
Boundary
=
=
Raddr+1
Dual Port RAM
Data In Data Out
=
Read-Side
State Machine
0
1
UP
RE
POP
EMPTY
RCLK

• Limits I/O clock
rates
• System MTBF
can be specified
• New designers
must be informed
Metastability
CLK
DIN
DOUT
DIN
CLK
FF
DOUT

Async FIFO Verilog Code - reset

Async FIFO Verilog Code - full flag
PUSH
FULL
0
1
UP
Waddr+2
=

Async FIFO Verilog Code - waddr
UP
E
E
Waddr+2
Waddr+1
Waddr

FPGA Embedded RAM
Place Route

IP Cores Trends
• 70’s - 1st IP core library: TI TTL databook
• 80’s - PLD application notes
• 90’s - IP vendors
– HDL soft cores
– Schematic crafted firm cores
– Embedded hard cores (PCI)
• 00’s - System on Chip

• Support
– Ready-to-Use
– Source code edits
– Who do you call
• Legal Issues
– Royalty
– License
– Reselling
IP Core Issues

IP Core Module Wizard
• Parameterized Cores implement
RAM, FIFO, ROM

• 80s
PLD Trends of the 80s
– multiple sourcing
– industry standard pinouts
– PLD applications conference
– PREP benchmarks
– honest gates

• 90s
PLD Trends of the 90s
– proprietary architecture
– sole source
– path to gate array
– IP Cores
– gate inflation

PLD Forecast of the 00s
• ESP - Embedded Standard Products
– Combine flexibility of PLD
with proven standard IP cores
• System on Chip
• Millions of Gates

PLD Prime Directive
• To explore new designs . . .
. . . where no one has gone before.