Fully Integrated Differential Distributed VCO using Ansoft IC Solution
Fully Integrated Differential Distributed VCO using Ansoft IC Solution
Fully Integrated Differential Distributed VCO using Ansoft IC Solution
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<strong>Fully</strong> <strong>Integrated</strong> <strong>Differential</strong><br />
<strong>Distributed</strong> <strong>VCO</strong> <strong>using</strong> <strong>Ansoft</strong> <strong>IC</strong><br />
<strong>Solution</strong><br />
George P. Bilionis<br />
<strong>IC</strong> Design Engineer<br />
Analogies S.A.<br />
Patras Science Park<br />
GR-26504 Platani Rio Patras,<br />
Greece<br />
Tel: +30 2610 911575<br />
Fax: +30 2610 911576<br />
Web: www.analogies.eu<br />
© 2008 <strong>Ansoft</strong>, LLC All rights reserved. <strong>Ansoft</strong>, LLC Proprietary
Outline<br />
• Company Introduction<br />
• <strong>Distributed</strong> Circuit Concept p<br />
• <strong>Fully</strong> <strong>Integrated</strong> <strong>Differential</strong> <strong>Distributed</strong> <strong>VCO</strong><br />
– Principle of Operation<br />
– Tuning g Cell for <strong>VCO</strong><br />
• Design Considerations<br />
• Case study of DD<strong>VCO</strong> <strong>using</strong> <strong>Ansoft</strong> HFSS<br />
• Cosimulation<br />
• Measurement Results<br />
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Company Introduction<br />
– A New Semiconductor Intellectual Property Design Company<br />
• Specializes in the development and provision of analog/mixed<br />
signal RF Intellectual Property (IP) cores or components and analog/mixed<br />
signal/RF design services<br />
– Intellectual Property (IP) block development and provision of<br />
• High speed front end PHYs with emphasis in wireline & wireless<br />
communications (SerDes, <strong>VCO</strong>s, PLL, Equalizers, RF functions), high speed<br />
interfaces (memory/bus PHY IFs) and connectivity<br />
• AAnalog/digital l /di it l iimplementations l t ti of f signal i l processing i algorithms l ith ffor<br />
error<br />
correcting codes (emphasis to TURBO-like correcting schemes)<br />
• Low noise/low power design and characterization for read-out circuitry (device<br />
modeling modeling, phase noise reduction, reduction transmission lines)<br />
– Design Services<br />
• Emphasis on physical layer and specialized analog/mixed signal circuits<br />
– CConsulting lti SServices i<br />
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IP Products & Services<br />
• Patent pending distributed differential architecture for very<br />
high speed front end circuit design<br />
Currently as <strong>VCO</strong>, 14GHz DD<strong>VCO</strong> prototype available<br />
Technology applicable as a <strong>VCO</strong>/PLL IP core for 60GHz UWB/WirelessHD RF<br />
applications, as well as 77/79 GHz Automotive Radar and Ultra High Speed<br />
IInterfaces t f (100Gbit/s (100Gbit/ Eth Ethernet) t)<br />
• Direct implementation of computational intensive signal<br />
processing functions for advanced iterative turbo-like error<br />
correction<br />
Currently as Analog SISO decoder prototype (ASISOD)<br />
Work in progress for high throughput TURBO/LDPC codec, suitable for Mobile<br />
WiMAX, P1901 BPL, DVB-S2/RCS applications<br />
• High Speed DDR2 SDRAM PHY with DFI compliant interface<br />
to memor memory controller controller, capable of up p to 800MH 800MHz operating<br />
frequency<br />
Currently as A0 prototype, B0 prototype, including Memory Controller in<br />
development, includes soft and hard IP blocks, in progress<br />
• MMulti-rate lti t 11-10GHz 10GH SSerDes D IP for f next t Generation G ti 10Gb/s 10Gb/<br />
GPON/EPON optical access applications<br />
Currently in specification phase for A0 prototype development, to include soft and<br />
hard IP blocks<br />
DD<strong>VCO</strong><br />
ASISOD<br />
DDR2PHY_A0<br />
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<strong>Distributed</strong> Circuit Concept<br />
• Promising technique<br />
– Increases the gain-bandwidth product in<br />
amplifiers p<br />
– Suitable for high frequency applications<br />
– Demonstrated for silicon-based silicon based <strong>VCO</strong>s in [1] [1]-[4] [4]<br />
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<strong>Fully</strong> <strong>Integrated</strong> <strong>Differential</strong> <strong>Distributed</strong><br />
<strong>VCO</strong><br />
• <strong>Differential</strong> <strong>Distributed</strong> Amplifier as a start and<br />
AC short-circuit its input with its output<br />
Two fundamental issues:<br />
a) Parasitic impedance absorption<br />
from transmission lines (increases<br />
the bandwidth)<br />
b) Superposition (increases the<br />
gain). Requires line<br />
synchronization<br />
© 2008 <strong>Ansoft</strong>, LLC All rights reserved. <strong>Ansoft</strong>, LLC Proprietary
<strong>Fully</strong> <strong>Integrated</strong> <strong>Differential</strong> <strong>Distributed</strong><br />
<strong>VCO</strong><br />
• Parasitic impedance absorption for SiGe HBTs<br />
Diff <strong>Differential</strong>-mode ti l d equivalent i l t hhalf lf circuit i it of f one amplification lifi ti stage t<br />
Absorption of f parasitics by the differential ff base line<br />
Absorption of parasitics by the differential collector line<br />
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<strong>Fully</strong> <strong>Integrated</strong> <strong>Differential</strong> <strong>Distributed</strong><br />
<strong>VCO</strong><br />
• Superposition and line synchronization<br />
•Superposition: p p The signal g at<br />
the output is the sum of the<br />
signals “generated” generated from<br />
every amplification stage at<br />
the differential collector line<br />
• Line Synchronization:<br />
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<strong>Fully</strong> <strong>Integrated</strong> <strong>Differential</strong> <strong>Distributed</strong><br />
<strong>VCO</strong><br />
• Oscillation Frequency: q y Can be determined<br />
by the round-trip delay<br />
• If the AC coupling capacitor is integrated<br />
then it must be included in the calculation<br />
of the oscillation frequency<br />
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<strong>Fully</strong> <strong>Integrated</strong> <strong>Differential</strong> <strong>Distributed</strong><br />
<strong>VCO</strong><br />
• Tuning: Delay variation by positive feedback<br />
• Oscillation frequency curve has a linear region<br />
• Constant output power<br />
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DD<strong>VCO</strong> Design Considerations<br />
– Circuit-EM co-simulation<br />
• Take into account the design rules<br />
– Min Min. spacing, spacing min min. width of the TLs<br />
• Take into account the tuning cell dimensions to the TL design (X-dimension)<br />
• Take into account MIM capacitors' dimensions<br />
– RRequirements i t ffrom th the ddesigner’s i ’ point i t of f view: i<br />
• Parameterized differential TL models<br />
– Accurate broadband modeling (DC to the 3rd harmonic)<br />
– Capture p all the effects<br />
» Conductor skin effect<br />
» Substrate skin effect<br />
» Coupling capacitance<br />
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DD<strong>VCO</strong> Design Considerations<br />
• Cadence is the standard as <strong>IC</strong> Design Flow<br />
• HFSS is the standard as Fullwave 3D Electromagnetic Simulator<br />
• Nexxim provides Integration in Cadence Flow and allows Co-<br />
Simulation with HFSS providing both powerful time and frequency<br />
domain simulations<br />
Cadence<br />
Schematic,<br />
Layout<br />
Nexxim HFSS<br />
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Port Setup:<br />
•Ports name and position<br />
from pins<br />
•Port dimension and<br />
reference can be setup<br />
Boundary setup<br />
Simulation Setup<br />
Advanced Options<br />
DD<strong>VCO</strong> Design Considerations:<br />
HFSS export p from Virtuoso<br />
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DD<strong>VCO</strong> Design Considerations:<br />
HFSS export p from Virtuoso<br />
• Advantages:<br />
– Automatic export of the 3D layout from the 2D<br />
structure<br />
– Automatic creation of the ports starting from<br />
the PINS<br />
– Automatic setup of boundaries<br />
• VVery complex l structures t t can be b exported t d<br />
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DD<strong>VCO</strong> Design Considerations:<br />
HFSS export from Virtuoso<br />
• DD<strong>VCO</strong> simulation requires high accuracy passive modelling.<br />
• Passives have been characterized <strong>using</strong> HFSS<br />
• Transmission lines and interconnections have bee characterized <strong>using</strong> HFSS<br />
• All the simulation must be performed from DC up to 3°-4° harmonics for accurate<br />
transient analysis<br />
Inductors<br />
<strong>Differential</strong> Microstrip lines<br />
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Cosimulation<br />
from ADE <strong>using</strong><br />
Nexxim-HFSS<br />
DD<strong>VCO</strong> Design Considerations:<br />
Nexxim-HFSS Nexxim HFSS Cosimulation<br />
Automatic Link to HFSS<br />
parametric designs<br />
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DD<strong>VCO</strong> Design Considerations:<br />
Nexxim-HFSS Nexxim HFSS Cosimulation<br />
• Advantages:<br />
– User can build his parametric block in HFSS<br />
– Automatic creation of the Cadence cellview<br />
starting from the hfss file<br />
– User can add the cellview to normal<br />
schematic flow and parametrize hfss variables<br />
– Cosimulation automatically load already<br />
simulated solutions and solves where it is<br />
needed<br />
• Cosimulation Speedup design Process<br />
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• HFSS have been used to<br />
characterize all critical parts<br />
• HFSS Models have been<br />
loaded into Cadence<br />
Environment for a full<br />
component analysis<br />
• Nexxim have been used for<br />
both HB and Transient<br />
Analysis<br />
Simuation Setup<br />
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HFSS Simulations<br />
•All critical Passives parts have been<br />
simulated with HFSS from DC up to 50GHz<br />
•Parametric analysis have been performed<br />
in order to optimize the <strong>VCO</strong> behaviour<br />
•Parametric Models have been used into<br />
Cadence <strong>IC</strong><br />
<strong>Ansoft</strong> Corporation XY Plot 1<br />
Collector_Line<br />
Y1<br />
10.00<br />
0.00<br />
-10.00<br />
-20.00<br />
-30.00<br />
-40.00<br />
-50.00<br />
-60.00<br />
-70.00<br />
-80.00<br />
500 5.00 10 10.00 00 15 15.00 00<br />
Freq [GHz]<br />
Curve Info<br />
dB(St(METT_1_T1,METT_1_T1))<br />
Setup1 : Sweep1<br />
$col_spacing='6um'<br />
dB(St(METT_1_T1,METT_1_T1))<br />
Setup1 : Sweep1<br />
$col $ _spacing='8um' p g<br />
dB(St(METT_1_T1,METT_1_T1))<br />
Setup1 : Sweep1<br />
$col_spacing='10um'<br />
dB(St(METT_1_T1,METT_1_T1))<br />
Setup1 : Sweep1<br />
$col_spacing='12um'<br />
dB(St(METT_1_T1,METT_1_T1))<br />
Setup1 : Sweep1<br />
$col_spacing='14um'<br />
dB(St(METT_1_T1,METT_1_T1))<br />
Setup1 : Sweep1<br />
$col_spacing='16um'<br />
dB(St(METT_1_T1,METT_1_T1))<br />
Setup1 : Sweep1<br />
$col_spacing='18um'<br />
dB(St(METT_1_T1,METT_1_T1))<br />
Setup1 : Sweep1<br />
$col_spacing='20um'<br />
dB(St(METT_1_T1,METT_2_T1))<br />
Setup1 : Sweep1<br />
$col_spacing='6um'<br />
dB(St(METT_1_T1,METT_2_T1))<br />
Setup1 : Sweep1<br />
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DD<strong>VCO</strong> Implementation<br />
• Technology: AMS 0.35 μm SiGe BiCMOS<br />
• fft=60 60 GH GHz<br />
• 4 Metal process: TOP METAL TH<strong>IC</strong>K<br />
• DD<strong>VCO</strong> dimensions: 00.9mm 9mm x 00.9mm 9mm<br />
• Chip Die Size: 2.0mm x 2.0mm (For test reasons)<br />
• <strong>Integrated</strong> g 50 Ohm Output p Buffer ( (Lumped p circuit) )<br />
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DD<strong>VCO</strong> Measurements<br />
• Output power -17 -17.5 5 dB<br />
• PN PN: -98 98 dB dBc/Hz /H @ 1 MH MHz<br />
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DD<strong>VCO</strong> Measurements<br />
Tuning range: 420 MHz<br />
Constant Output Power across<br />
frequency of operation<br />
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Measurements vs. Simulation<br />
(Consistency Issues)<br />
• Simulated frequency 14.3 GHz- OK<br />
• Simulated Tuning g range: g 400 MHz – OK<br />
• Simulated Phase Noise: -108 dBc/Hz @ 1 MHz<br />
– Given the fact that external noise is present at Control<br />
Voltage we assumed that we are close enough with<br />
simulations<br />
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DD<strong>VCO</strong> Current Status - Next Steps<br />
Current Status<br />
– Experimental results have demonstrated the feasibility of building fully<br />
integrated distributed oscillators with high oscillation frequencies and<br />
nice characteristics without having to turn into a pricy fabrication<br />
technology<br />
– Patent has been filed for both the architecture and design<br />
Future plans<br />
– Migration of the DD<strong>VCO</strong> architecture to a CMOS technology<br />
» Aiming to hit much higher oscillation frequencies through the use of<br />
advanced commercial CMOS technology<br />
» Feasible to design a 60GHz+ DD<strong>VCO</strong> in 90 nm RF CMOS<br />
technology<br />
» WiMedia (60GHz), Next generation Ethernet (100 Gbit/s),<br />
77/79 GH GHz automotive t ti radar d applications li ti a very good d fit<br />
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References<br />
[1] HH. WWu and d AA. HHajimiri, ji i i “Sili “Silicon-based b d di distributed ib d voltage- l controlled ll d<br />
oscillators,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 493–502, Mar.<br />
2001.<br />
[2] B. Kleveland, et al.“Monolithic CMOS distributed amplifier and<br />
oscillator,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 1999,<br />
pp pp. 70–71 70 71.<br />
[3] D. Guckenberger and K. T. Kornegay, “Design of a differential<br />
distributed amplifier and oscillator <strong>using</strong> close-packed interleaved<br />
transmission lines,” IEEE J. Solid-State Circuits, vol. 40, no. 10, pp.<br />
1997–2007, Oct. 2005.<br />
[4] Bilionis et al al. “ <strong>Fully</strong> integrated differential distributed <strong>VCO</strong> in 00.35 35 μm<br />
SiGe BiCMOS technology” IEEE Trans. MTT, vol. 55, no. 1, pp. 13-22,<br />
Jan. 2007.<br />
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Thank you!!! y<br />
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