Design of LTCC RF Modules for Communication Systems

Presentation #7 

Design of LTCC RF Modules for 

Communication Systems

Agenda 

◗ LTCC Overview & Solution 

◗ Embedded Passives Modeling & Library 

◗ Example1: PAM Module design 

◗ Example2: Coupler Module design 

◗ Example3: Switch Module design 

◗ Summary

LTCC Overview & Solution

LTCC Background 

◗ What is LTCC ? 

- LTCC is a Process Technology which allows RF engineers to 

create Passive components in the LTCC substrate 

◗ LTCC(Low Temperature Ceramic Cofired) 

-Silver and Gold metal alloys are printed onto selected layers of the 

substrate 

-Each layer is a ceramic composite with very stable dielectric 

properties 

-Compliments silicon integration with embedded passives 

-Ceramic technology circuit elements such as capacitors resistors & 

inductors 

-Low-Temperature process allows for the use of highly conductive 

metals(AG,AU)

Buried Capacitor 

LTCC Module structure 

Bare Chip 

Chip Capacitor 

Internal Electrode 

LTCC 

Transistor 

Monolitic IC 

Surface Electrode 

Buried Inductor 

Buried Inductor 

Resist 

or

LTCC Manufacturing process

◗ Castellated 

◗ -Most recent development 

◗ -Best RF performance 

◗ -Lowest cost 

◗ Clip lead 

◗ -Backward Clip lead 

◗ -Backward compatible 

◗ -Good mechanical strength 

◗ -Medium cost 

◗ BGA 

◗ -Standard footprint 

◗ -Good mechanical strength 

◗ -Medium cost 

Package Styles

Company 

Dupont 

Ferro 

Heraeus 

Kyocera 

Samsung 

Dielectric 

constant 

7.8 

7.5 

5.9 

5.9 

7.68 

9.15 

5.6~5.7 

9.4~9.5 

6.3 

6.8 

LTCC Materials 

Substrate & Package 

Tangent d 

0.0063 

0.002 

- 

0.0012 

0.0039 

0.0027 

- 

- 

Model 

951 

943 

A6M 

A6S 

CT800 

CT2000 

GL550 

GL660 

TCL-6A 

TCL-7A 

Description 

standard tape 

low loss tape 

Microwave tape 

Low loss microwave tape 

zero shirink tape 

- 

-

LTCC Considerations 

-Vias- 

◗ Via sizes 

◗ -Via sizes are 150µm, 200µm and 250µm, as punched to the unfired tape. 

◗ -Via diameter is recommended to be close to the tape thickness. 

◗ -One via diameter on any tape layer recommended. 

◗ Catch pads 

◗ -A line connection to a via less than 250µm in diameter shall have a round 

catch pad 50 µm larger than the via diameter 

◗ Via spacing 

◗ -Minimum via to via pitch(center to center) within the same tape layer shall 

be 2.5 x via diameter. 

◗ -Minimum via stagger between tape layers shall be 2 x via diameter. 

◗ -Minimum via center to part edge distance shall be 3 x via diameter.

◗ Stacked vias 

◗ -Stacking of vias is acceptable through any number of layers. 

◗ -A stacked via connection results in a bump on the part surface. Staggering 

of vias is recommended ro avoid this. 

◗ -A minimum of one layer of via stagger is recommended for hermeticity. 

◗ Thermal vias 


-Vias- 

◗ -Recommended thermal via diameter is 200µm for tape materials 951-A2 

and 951-AX and 150µm for 951-AT 

◗ -The minimum via pitch (center to center) in a thermal via shall be 3 x via 

diameter 

◗ -The maximum thermal via array size is 6.5mm length and width 

◗ -The minimum thermal via array to part edge clearance shall be 4mm


◗ Line width and spacing 

-Conductors- 

◗ -The minimum conductor line width shall be 200µm(A) 

◗ -Maximum line width is 1.5mm with unlimited length. 

◗ -The use of 90 o lines is recommended for the optimum line width control. But 

45 o lines are allowed 

◗ -The minimum conductors spacing shall be 200µm(B) 

◗ -The minimum conductor line spacing to a via catch pad shall be 175 µm(C) 

◗ -The minimum conductor line clearance to the substrate edge shall be 380 

µm(D). Lead frame pad clearance to the substrate edge shall be 125 µm 

◗ -The minimum SMD pad spacing to a via catch pad shall be 200 µm(F) 

◗ -The minimum SMD pad spacing to a conductor line shall be 200 µm 

◗ -The minimum SMD pad spacing to substrate edge shall be 500 µm(G)


-Ground and power planes- 

◗ -Ground and power planes shall be a grid pattern of less than 50% conductor 

coverage. 

◗ -The preferred plane uses 250 µm lines and 550 µm spaces. 

◗ -The grid pattern of planes on adjacent layers should be offset to provide a 

uniform substrate thickness. 

◗ -Solid conductor areas on the gridded plane can be used locally to improve 

RF performance 

◗ -The grid plane connection to a via can be improved by using a square catch 

pad that shares the current flow to several grid lines(A) 

◗ -A minimum of 300 µm spacing shall separate the plane pattern and ant feed 

through via. 250µm 300µm 550µm 

A

◗ Cavities 


-Cavities- 

◗ -Cavities or holes are produced in the unfired state by punching the cavity 

windows to the tape sheets before lamination. 

◗ -The cavity walls shall be a minimum of 3.0 mm wide(B) 

◗ -Via edge to cavity wall clearance shall be a minimum of 2.5 x via 

diameter(C) 

◗ -The cavity bottom conductor to cavity wall clearance shall be 200 µm (D) 

◗ -Buried or exposed conductor to cavity wall clearance shall be a minimum of 

250 µm(E) 

◗ -Bond shelf minimum width shall be 0.8 mm(F) 

F B E 

D 

C 

A

Challenges in LTCC RF Module design 

◗RF characterization data is not readily available 

◗ For large embedded components(spiral inductor and parallel plate 

capacitors), considerable electrical modeling required. 

◗ - coupling with ground and between components 

◗ Integrated simulation between Circuit modeling and passive 

components realization required 

◗ - L : length of unconventional line and via , C : area of arbitrary shape 

of plates 

◗ - May use coupling amongst components to realize circuit components 

("intentional" parasitic)

Multi Layer 

Technology 

Embedded L,C,R libraries 

Hybrid IC Multi-layer Substrate 

Chip Monolithic Delay Line 

Chip RC network 

Microwave/mmwave Package 

Ansoft LTCC Solution 

-Empowering profitability- 

Material 

Technology 

Ceramic Material 

Thick Film material 

Via-hole Forming 

3D RF Circuit Design 

Microwave measurement 

Circuit + EM simulation 

Empowering 

3D Integrated Circuit Module 

RF/MW Circuits 

Technology 

Passive Components: 

Coupler, Balun, Combiner, Hybrids etc. 

VCO/PLL module, PA module 

Antenna Switch Module 

Multilayer BPF/Duplexer

3D Planar 

Solver : 

Pattern layout analysis 

Ansoft Designer TM 

Ansoft LTCC Solution 

-Solver on Demand- 

Ansoft HFSS 

System Solver : 

Design spec./ architecture 

Circuit & Layout : 

Circuit design, 

Required component 

parameters fitting 

3D Field Solver: 

Full Module Field analysis 

before manufacturing 

Equivalent Circuit 

Extraction : 

Component extraction and 

library construction

Embedded Passives Modeling 

& Library

Embedded passives 

•Embedded passives: 

- Part of a printed circuit board or a substrate using a type of 

material to make resistors, capacitors or inductors. 

-The surface area can be reduced by using embedded passives. 

-The Cost can be reduced by replacing SMT components. 

-Embedded passives reduce the inherent parasitic.

Embedded Passives 

HFSS simulation model includes embedded passives in 

typical multilayer LTCC substrate 

HFSS 

Embedded Passives : L C R

Typical Properties for Embedded 

Component 

Resistor 

Capacitor 

Inductor 

RF Components 

Range 

1ohm~1Mohm 

1pF~100pF 

(DC to 3µF/cm 2 ) 

1nH~40nH 

Tolerance 

30% embedded 

1% trimmed 

5% typical 

5% typical 

Properties 

TCR

Embedded Passives Modeling & Library 

Physical Model Analysis 

3D solver: Ansoft HFSS 

Planar EM solver: Ansoft Designer simulation 

Auto Parameter extraction: SpiceLink (Q3D) 

Equivalent Circuit with nominal 

parameters 

Ansoft Designer Circuit simulation 

Optimization by S-parameter fitting 

Ansoft Designer Optimetrics 

Circuit Parameter 

R , L, C, Q, Fr 

Add Passives Libraries 

Ansoft Designer User Library

Ansoft Designer for LTCC Modeling 

-Circuit Circuit + Planar EM Field Simulation- Simulation 

Eq. Circuit 

Optimization 

Auto generation 



Circuit Library 

Planar EM

Extracted Capacitor Parameters 

Parallel-plate structure: 

Cp = e 0 e r s 

d 

Multiple parallel-plate 

=> To obtain sufficient capacitance 

Area(mm 2 ) 

: S 

0.5 

1 

2 

3 

4 

5 

Fr(GHz) 

11.79 

9.85 

7.93 

6.98 

6.44 

6.11 

t : 0.007mm 

er =7.8 

Rp(O) 

0.11 

0.14 

0.12 

0.08 

0.08 

0.08 

0.1mm 

Lp(nH) 

1.21 

1.35 

1.45 

1.51 

1.53 

1.57 

2GHz 

Cp(pF) 

2.27 

4.17 

7.81 

12.24 

15.95 

19.58 

Qmax 

331.62 

332.19 

318.03 

315.39 

275.81 

305.59 

d : 0.022mm

L : nH 

C : pF 

R : O 

Extracted Capacitor Parameters 

20 

18 

16 

14 

12 

10 

8 

6 

4 

2 

0 

0.5 1 2 3 4 5 

S : Area of Capacitors (mm 2 ) 

Cp 

Lp 

Rp

Embedded Inductors 

For manufacturing, the important design consideration is the catch pad 

◗ The inner end of the catch pad must clear the adjacent conductor by the 

design rule spacing 

◗ Preferably, the catch pad should occur at the center point of the spiral to 

give the best possible yield.

Extracted Inductor Parameters 

0.4mm 

t : 0.007mm 

er : 7.8 

N of Turns 

0.5 

1 

1.5 

2 

2.5 

3 

0.4mm 

0.1mm 

Fr(GHz) 

11.65 

8.49 

5.76 

4.19 

3.03 

2.38 

0.1mm 

Rs(O) 

0.17 

0.11 

0.30 

0.31 

0.47 

0.54 

Ls(nH) 

1.59 

2.20 

3.25 

4.70 

6.82 

9.56 

2GHz 

Cs(pF) 

0.08 

0.13 

0.20 

0.28 

0.40 

0.47 

Qf 

130.87 

106.72 

90.89 

73.40 

57.60 

30.25

L : nH 

C : pF 

R : O 

Extracted Inductor Parameters 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

0.5 1 1.5 2 2.5 3 

Number of Turns 

Cs 

Ls 

Rs

Advantages: 

Embedded Resistor 

-Size competitive with the chip resistor. 

-The range of values should be one ohm to one mega ohm. 

-Not limited to surface layer mounting. 

Challenges: 

-Resistor tolerance and sheet resistivity: Both resistivity and thickness tolerances 

are goals which have not been met by resistor materials suitable for resistivity 

required for widespread applications. 

-Yields: Yield loss per device must be extremely small (~0.00001) because integral 

resistors cannot be repaired.

Ink 

A 

B 

C 

D 

Ohms/Square 

28 

311 

3,481 

31,174 

Co-Fired Resistors 

Miminimum 

Dimension 

0.030” 

0.030” 

0.030” 

0.030” 

Surface Resistors. DuPont 2000 

-+/- 30% untrimmed : low cost 

-+/- 1% active laser trimed : higher cost 

Overlap: minimum 0.005” 

Maximum 

Dimension 

0.200” 

0.200” 

0.200” 

0.200” 

Maximum 

Ratio 

3:1 

3:1 

3:1 

3:1 

W: minimum 0.03” 

L : minimum 0.03” 

Minimum 

Ratio 

1:3 

1:3 

1:3 

1:3 

R= Rs L 

W 

Aspect Ratio

0.15mm 

0.15mm 

Extracted Resistor Parameters 

W Rs 

Reduced equivalent circuit 

for the embedded resistor 

L 

0.15mm 

0.1mm 

W(mm) 

2.4 

1.6 

0.8 

0.8 

0.8 

2.4 

1.6 

0.8 

0.8 

0.8 

L(mm) 

0.8 

0.8 

0.8 

1.6 

2.4 

0.8 

0.8 

0.8 

1.6 

2.4 

Rs 

(O/square) 

28 

28 

28 

28 

28 

311 

311 

311 

311 

311 

Li(nH) 

1.53 

1.46 

1.45 

0.90 

- 

- 

- 

- 

- 

- 

Ri(O) 

11 

16 

30 

61 

88 

98 

144 

291 

517 

822 

Ci(pF) 

- 

- 

- 

- 

- 

0.41 

0.34 

0.27 

0.30 

0.33

LTCC RF Module Design Example: 

Power Amplifier

Power Amplifier Module Application 

◗ Introduce 

◗ Power Amplifier Module is used to transmitter 

for handset or repeater. 

◗ Design rule was used power gain matching and 

loadpull analysis.

Power Amplifier Specification 

◗ Bluetooth PAM :100mW (level C) 

◗ SiGe HBT : Gummel Poon 

◗ Device: WLE-Q1X8L (Tachyonics) 

Unit cell 60 array 

◗ Frequency: 2400Mhz ~ 2483MHz 

◗ Gain: ~10dB 

◗ Output power: 20 dBm 

◗ Vcc=3.5V Ic=140mA 

◗ Substrate: Si substrate ε r = 9.8

Power Amp Design Procedure 

◗ Unit cell parameter 

◗ Optimize bias network 

◗ Power gain circle matching(linear small signal ) 

◗ Design matching network using Smith Tool 

◗ Harmonic balance simulation and Load Pull 

Analysis method matching 

◗ Nyquist stability analysis 

◗ Multi-tone HB intermodulation analysis 

◗ Conversion lumped component to embedded 

passive component

Unit Cell Parameter 

◗ Vcc=3.5V, at 50Ohm loadline : Vmax =7V Imax=140mA 

◗ -> Ic=70mA, therefore Ic of unit cell =70/64 = 1.09mA (Class A) 

for the increase of linearity, Ic was changed 2.2 mA. 

◗ Collecter feedback bias circuit : Rb= 300KOhm, Rc is omited. 

Unit cell bias


◗ Using Smith tool is normalized 50 Ohm make a power gain 

matching circuit. 

◗ 27 dB Power gain matching circuit added. 

S-parameter :gain 27 dB 

Smith chart


◗ From Dynamic loadline :Vmax-Vmin =3.4V , Imax-Imin=5.1mA 

◗ Pload (forcast)= Vrms*Irms = (Vmax-Vmin*Imax-Imin)/8 =3.4*5.1/8 

Dynamic loadline 

= 2.16mW = (3.3dBm) 

IV-character curve


◗ Forecast P1 dB :2.16mW (3.3dBm) -> result :2.36 dBm 

◗ Forecast 64 cell array : 2.16mW * 64 =138mW (21.3 dBm) 

Tranducer gain @2.4GHz 

G1 dB :input –23.5 dBm 

Power sweep @2.4GHz 

Pout :input –23.5dBm ->2.36 dBm

Optimize Bias Network Using Current Mirror 

◗ Collector feedback circuit is sensitive to changes of BF(forward 

current gain), current mirror circuit should be used to 

supplement for it.


◗ Power Amp module using Current mirror 

◗ Vcc=3.5V , Ic=120mA , Vctrl = 3.5 V Rc= 1Kohm 

Next page


◗ Power Amp module inside DW_1X8L_64 

◗ 64 unit cell block arrayed


◗ BF variation of unit cell into power Amp module.(BF 200~500) 

◗ Collector current variation is about 3mA. 

only 3mA.


◗ Collector current(Ic) with variation of Vctrl voltage and Rc is 

as followed. 

Rc (0.5kohm ~ 2kohm) V ctrl (2.5V ~ 4V)

Power Gain Circle Matching 

◗ Small signal Analysis for PAM (freq. 0.3GHz~5GHz ,100MHz 

step) 

S21:14.5dB@2.4GHz 

Gp :28 dB@2.4GHz 

K:0.94 B1:1.5 @2.4GHz 

Zin:1.61ohm Zout:14.3 @2.4GHz


◗ Power sweep Analysis for PAM 

◗ Power range : -20dbm ~10dbm 1dbm(step) @2.4Ghz 

Transduce gain @2.4GHz 

G1 dB 13.7dB : input -5 dBm 

Power sweep @2.4GHz 

Pout :input 5dBm ->18.77 dBm


◗ Gain matching circuit generation using Smith tool. 

◗ Stability K factor is not >1 ,so negative feedback serial inductor 

(Le: 0.1nH) attached at Emitter. 

Gp :17 dB@2.4GHz 

S21:13.4dB@2.4GHz 

K = 1 

K with variation of Le 

K, B1@2.4GHz

Design Matching Network Using Smith Tool 

◗ Input and Output matching circuit was generated by smith tool. 

Input matching circuit 

Output matching circuit


◗ S-parameter and Input, Output Impedance With matching 

circuit 

50 Ohm 

GP circuit & S11, S22 

S-parameter S21:16.98dB, S11 –41dB, 

S22: 14.25dB @2.4 GHz 

Input Output Impedance


◗ G1 dB and P1dB variation unmatched and matched. 

G1 dB changed 13dB -> 16.98dB 

-> input -4dBm 

Pout is incrased 18.03dBm 

-> 19.03dBm

Harmonic Balance Simulation and Loadpull 

◗ Loadpull method get the better output about 1~2dB than 

power gain matching. 

Loadpull turner added 

For the Loadpull analysis 

harmonic analysis setup is added. 

Input power is 5.5 dBm at 2.4GHz


◗ Using the loadpull turner get the optimum load matching point 

and source matching point get the Gamma S plane power gain 

circle.(26.5dB)


◗ Linearity improved for the loadpull matching method. 

G1 dB is same input -4dBm Output P1 dB is increased 19.03dBm 

-> 20.15dBm

Nyquist Stability Analysis 

◗ For the stability verification perform the Nyquist criterion: 

The circuit will be unstable if the Nyquist plot encircles the origin 

in a clockwise direction.

Multi-tone HB Intermodulation Analysis 

◗ Tone1 this is 2.4GHz and tone 2 is 2.41GHz. 

◗ Input power is –30 dBm. 

◗ OIP3 ~= Pout +IMD2/2 

2-tone sinusodal source added 

IMD2= -44.5 dBc 

IP3= 30.37dBm

Conversion of Lumped Components to 

Embedded Passive Components 

◗ Current mirror bias circuit was included into bare chip. 

◗ Matching and bias network was implemented on to LTCC 

substrate. 

HBT 

Bare chip 

Input 

bias 

Bare chip 

Pam module 

output


Directional Coupler

Coupler Module Application 

• Introduction 

• Derivation of lumped equivalent circuit for 

backward directional coupler 

• Several lumped coupler circuits 

• Simulation and measurement 

• Conclusion

Backward conventional coupler 

θ 

Input Through 

Coupling 

θ 

Self 

Mutual 

Inductance 

Self 

Introduction 

Isolation 

Elimination 

of 

Mutual 

Inductance 

Ce 

Co/2 

A Novel Equivalent Circuit 

Pi-type Structure 

Le 

Coupling 

Lo 

Le 

Le Le 

Ce 

Ce Ce 

Co/2

Derivation of lumped equivalent circuit for 

backward directional coupler 

Symmetrical plane 

(E/M Wall) 

θ 

θ 

Ce 

Symmetrical 

Co 

plane 

(E/M Wall) 

Co 

Ce 

Symmetrical plane 

(E/M Wall) 

Le 

Lo 

Lo 

Lo Lo 

Le 

Le Le 

Ce 

Co 

Co 

Ce

Case 1. Transversal symmetrical plane magnetic wall 

Magnetic/Electric Wall 

(Open, Short) 

θ 

θ 

Magnetic 

Wall 

(open) 

Ce 

Co 

Le 

Lo 

Magnetic Wall (open) 

M/W 

or 

E/W

Case 1. Transversal symmetrical plane magnetic wall 

Longitudinal symmetrical plane 

magnetic wall (even-mode) 

Z 

Z 

Z 

in 

L 

in 

= Z 

= 

∞ 

= − 

θ/2 

0e 

Zoe 

jZ 

Z 

Z 

L 

0e 

0e 

+ 

+ 

jZ 

jZ 

θ 

cot 

2 

0e 

L 

open 

θ 

tan 

2 

θ 

tan 

2 

C = 

e 

Z 

Y 

ω 

in 

0e 

Ce 

= 

1 

jω 

C 

θ 

tan 

2 

e 

Z 

Z 

Y 

in 

L 

in 


electric wall (odd-mode) 

= Z 

= 

0 

= − 

0e 

Zoe 

θ/2 

jY 

Z 

Z 

0e 

L 

0e 

+ 

+ 

jZ 

θ 

cot 

2 

jZ 

0e 

L 

short 

θ 

tan 

2 

θ 

tan 

2 

L = 

e 

Ce 

ω sin 

Z0e 

2 

e 

θ 

Le 

1 

Yin = + jωC 

jω 

L 

e

Case 2. Transversal symmetrical plane electric wall 

Magnetic/Electric Wall 

(Open, Short) 

θ 

θ 

Electric 

Wall 

(short) 

Ce 

Co 

Le 

Lo 

Electric Wall (short) 

M/W 

or 

E/W

Y 

Y 

Y 

in 

L 


magnetic wall (even-mode) 

in 

Case 2. Transversal symmetrical plane electric wall 

= Y 

= 

= 

0 

0o 

jY 

θ/2 

Y 

Y 

0o 

Zoo 

L 

0o 

+ 

+ 

jY 

θ 

tan 

2 

jY 

0o 

L 

θ 

tan 

2 

θ 

tan 

2 

open 

Le 

Ce+Co Lo 

Y in = jω( 

Ce 

+ Co 

) 

1 

+ 

j ω ( L + L ) 

1 

Lo = 

− L 

2 

θ 

ω ( Ce 

+ Co 

) −ωY0 

o tan 

2 

e 

o 

e 

Y 

Y 

Y 

in 

L 

in 


electric wall (odd-mode) 

= Y 

= 

∞ 

= − 

0o 

Zoo 

θ/2 

Y 

Y 

jY 

L 

0o 

0o 

+ 

+ 

jY 

jY 

0o 

θ 

cot 

2 

L 

θ 

tan 

2 

θ 

tan 

2 

Y 

short 

θ 

cot 

Ce+Co 

Le 

Y in = jω( 

Ce 

+ Co 

) 

+ 

1 

2 

jω 

0o 

Co = − + − 2 

ω 2 ω Le 

1 

Le 

C 

e

Summary 

Ce 

Co/2 

Le 

Lo 

Le 

Co/2 

Ce 

Le Le 

Ce Ce 

Equivalent Circuit of 

Proposed Coupler 

e 

o 

o 

e 

o 

e 

e 

o 

e 

e 

e 

e 

o 

e 

dB 

L 

Y 

C 

C 

L 

C 

L 

Y 

C 

Z 

L 

Y 

C 

C 

C 

Z 

Z 

C 

C 

Z 

Z 

dB 

C 

C 

− 

− 

+ 

= 

⎟ 

⎟ 

⎠ 

⎞ 

⎜ 

⎜ 

⎝ 

⎛ 

− 

+ 

= 

= 

= 

+ 

− 

= 

− 

+ 

= 

− 

= 

2 

tan 

) 

( 

1 

1 

2 

cot 

2 

1 

2 

sin 

2 

1 

2 

tan 

1 

1 

1 

1 

1 

log 

10 

0 

2 

2 

0 

0 

0 

0 

0 

0 

0 

0 

2 

10 

θ 

ω 

ω 

ω 

θ 

ω 

θ 

ω 

θ 

ω 

Coupling 

Coefficient

Ce 

Co/2 

LTCC Application 

Le 

Lo 

Le 

Le Le 

Ce 

Ce Ce 

Equivalent Circuit of 

Proposed Coupler 

Co/2 

Center frequency : 2Ghz 

C dB (Coupling Coefficent) : 10 dB 

Dielectric constant : 7.8 

Simulator : Ansoft Designer 

Spicelink V5.0 

HFSS V8.5 

Size : 3mm×2.4mm×0.5mm 

Element values : 

Ce : 2.21pF, Le : 1.43nH 

Co/2 : 0.53pF, Lo :1.55nH

Circuit Simulation Result using Ansoft Designer

Chip-type LC design process using Spicelink 

Element 

Ce(pF) 

Le(nH) 

Co/2(pF) 

Lo (nH) 

Suggested Values 

(Calculated) 

2.21 

1.43 

0.53 

1.55 

Applied Values 

(Spicelink V5.0) 

1.54 

1.3723 

0.5682 

1.6355

Designed chip-type 10dB lumped-element directional 

coupler with a multi-layer configuration.

Simulation Result (Ansoft Designer & HFSS) 

10dB Coupler 

Comparisons of the circuit simulation and EM simulation on the 

designed lumped-element directional couplers.


Switch Module Application

Switch Module Application 

Triple-Band Front End Block Diagram

Dual-band Antenna Switch Module 

• RF Antenna/Switchplexer module 

• Separating the Band of Multi-System 

• Key Technology 

• LTCC technology 

• MLC(Multi-layer Ceramic) Technology 

• Microwave passive component 

• design technology 

• Microwave integration technology 

• Constitution of Switchplexer 

• Chip, Antenna Transmitting 

and receiving 

• Hybrid : Improvement of radiation 

and matching 

• Diplexer : Separating the Dual band 

• RF-Switch : Separating Tx, Rx 

• BPF : Harmonic rejection filter 

GSM_Tx 

GSM_Rx 

DCS_Tx 

DCS_Rx 

Frequency 

880~915MHz 

925~960MHz 

1710~1785MHz 

1805~1880MHz 

Insertion 

Loss 

1.0 dB 

0.5 dB 

1.0 dB 

0.75 dB 

Return 

Loss 

27 dB 

25 dB 

25 dB 

25 dB

Diplexer Design Theory 

◗ Low Pass + High Pass Filter 

LPF 

LPF cutoff freq. 

GSM_Tx 

GSM_Rx 

~ 960MHz 

880~ 915MHz 

925~ 960MHz 

HPF cutoff freq. 

DCS_Tx 

DCS_Rx 

HPF 

1710MHz~ 

1710~1785MHz 

1805~1880MHz

Low Pass Filter Design by Insertion Loss Method 

• Prototype lowpass filter design from spec. 

Cutoff Frequency � 960 MHz 

Insertion Loss � 1 dB max 

Return Loss � 25 dB min 

Termination � In/Out Port Impedance (50 Ohm) 

• Impedance scaling 

• Frequency transformation 

• Circuit simulation 

• Chip-type Low Pass Filter Design from Lumped LPF

Prototype Low Pass Filter Design from Spec. 

Attenuation characteristic equation of 

Chebyshev type filter 

1 

10 

where 

cosh 

cosh 

1 

log 

10 

) 

( 

and 

cos 

cos 

1 

log 

10 

) 

( 

10 

' 

1 

' 

1 

2 

10 

' 

' 

1 

' 

1 

2 

10 

' 

' 

1 

' 

' 

1 

' 

− 

= 

⎪⎭ 

⎪ 

⎬ 

⎫ 

⎪⎩ 

⎪ 

⎨ 

⎧ 

⎥ 

⎦ 

⎤ 

⎢ 

⎣ 

⎡ 

⎟ 

⎟ 

⎠ 

⎞ 

⎜ 

⎜ 

⎝ 

⎛ 

+ 

= 

⎪⎭ 

⎪ 

⎬ 

⎫ 

⎪⎩ 

⎪ 

⎨ 

⎧ 

⎥ 

⎦ 

⎤ 

⎢ 

⎣ 

⎡ 

⎟ 

⎟ 

⎠ 

⎞ 

⎜ 

⎜ 

⎝ 

⎛ 

+ 

= 

≥ 

− 

≤ 

− 

Ar 

L 

A 

A 

n 

L 

n 

L 

ε 

ω 

ω 

ε 

ω 

ω 

ω 

ε 

ω 

ω 

ω 

ω 

ω 

⎪ 

⎭ 

⎪ 

⎬ 

⎫ 

⎪ 

⎩ 

⎪ 

⎨ 

⎧ 

= 

⋅ 

⋅ 

⋅ 

= 

= 

= 

= 

+ 

− 

− 

− 

even 

odd 

g 

n 

k 

g 

b 

a 

a 

g 

a 

g 

g 

n 

k 

k 

k 

k 

k 

, 

) 

4 

( 

coth 

, 

1 

, 

, 

3 

, 

2 

4 

2 

1 

2 

1 

1 

1 

1 

1 

0 

1 

β 

γ 

⎟ 

⎠ 

⎞ 

⎜ 

⎝ 

⎛ 

+ 

= 

⎟ 

⎠ 

⎞ 

⎜ 

⎝ 

⎛ − 

= 

⎟ 

⎠ 

⎞ 

⎜ 

⎝ 

⎛ 

= 

⎥ 

⎦ 

⎤ 

⎢ 

⎣ 

⎡ 

⎟ 

⎠ 

⎞ 

⎜ 

⎝ 

⎛ 

= 

= 

n 

k 

b 

n 

k 

a 

n 

L 

where 

k 

k 

Ar 

c 

π 

γ 

π 

β 

γ 

β 

ω 

2 

2 

sin 

2 

) 

1 

2 

( 

sin 

2 

sinh 

37 

. 

17 

coth 

ln 

1 

Prototype low pass filter with 

Chebyshev polynomial

Response Characteristics of Chebyshev Type Filter 

N=3 

N=5 

N=7 

Attenuation 

Comparison of the frequency characteristic 

according to the number of ladder network N 

1dB 

0. 1dB 

0.01dB 

VSWR 

0.01dB 

0. 1dB 

1dB 

Attenuation 

Comparison of the frequency characteristic 

according to the passband ripple

Impedance Scaling & Frequency Transformation 

VS 

= 2. 

0 

[ V] 

0 

V L 

1 

1 

= V 

1+ 

1 

= 1 

[ V] 

S 

ω 

+ 

VL 

' 

− 

1 

Imp. 

Imp. 

Scaling 

Scaling 

To obtain the same load 

ω1' 

ω 

= 

ω 

' 

1 

c 

ω 

ω' 

voltage, 

Freq. 

Freq. 

Mapping 

Mapping 

Function 

Function 

' ' 

ω : ω = ω : ω 

: 

1 c 

VS 

= 2. 

0[ 

V] 

R 

Z + R 

[ V] 

= VS 

1 

0 

Frequency transformation 

0 

Z o 

ωc 

+ 

VL 

− 

function 

R 

R = 

ω 

Z0

Port impedance leveling ratio : 

Cutoff frequency : 

1.Resistor 

2.Conductance 

Low Pass Filter Summary 

ω c 

R ( n ) × Z 

= g0 

or g + 1 

= g0 

or g + 1 

G ( n ) ÷ Z 

0 

0 

Z 0 

3.Inductance 

g 

0 

∴L 

0 

: ω 

k 

' 

1 

= 

' 

1 

g 

k 

g 

4.Capacitance 

g 

∴C 

: ω 

k 

= 

g 

k 

g 

k 

= Z 

0 

⎛ ω 

⎜ 

⎝ω 

= Z 

k 

0 

⎛ ω 

⎜ 

⎝ω 

' 

1 

c 

' 

1 

c 

: ω 

c 

L 

⎞ 

⎟ 

⎟× 

Z 

⎠ 

: ω 

c 

C 

⎞ 

⎟ ÷ Z 

⎠ 

k 

k 

0 

0

1 1 

−ω1 

': 

ω' 

= : 

ω ω 

1 

ω 

ω' = − 1' 

ω 

ω 

1 

High Pass Filter Design 

(LPF to HPF Frequency transformation function) 

ω' ω1' 

= − 

ω ω 

1 

⎛ ⎞ 

⎜ ω' 

⎟ 1 1 

jω' 

gi 

= jgi 

⎜− 

= − j 

ω ⎟ 

⎜ 

1 

ω ⎟ 

⎝ 

ω 

1 ⎠ ω g 

1 

i 

LPF 

HPF 

Low Pass 

gi (C) 

gi (L) 

High Pass 

1 

( L) 

g i 

1 

( C) 

g i

Port impedance leveling ratio : 

Cutoff frequency : 

where 

ω 

' 

1 = 

1 

1.Resistor 

2.Conductance 

High Pass Filter Summary 

ω c 

R ( n ) × Z 

= g0 

or g + 1 

= g0 

or g + 1 

G ( n ) ÷ Z 

0 

0 

Z 0 

3.Inductance 

L 

4.Capacitance 

C 

k 

k 

= 

= 

1 

g 

k 

1 

g 

k 

⎛ ω 

⎜ 

⎝ω 

⎛ ω 

⎜ 

⎝ω 

' 

1 

c 

' 

1 

c 

⎞ 

⎟ 

⎟× 

Z 

⎠ 

⎞ 

⎟ ÷ Z 

⎠ 

0 

0

Prototype Diplexer Design 

GSM/DCS band Diplexer Design using introduced Conventional design theory 

Tx : GSM Band (~ 960MHz) 

Rx : DCS Band (1710MHz ~)

Designed dual-band Diplexer with a multi-layer 

configuration. 

Dielectric constant : 7.1 

Simulator : Ansoft Designer 

Spicelink V5.0 

HFSS V8.5 

Size : 5.4mm×4.0mm×1.8mm 

Tx : GSM Band (~ 960MHz) 

Rx : DCS Band (1710MHz ~)

Circuit Simulation Result using Ansoft Designer

Simulation Result (Ansoft Designer & HFSS) 

• GSM/DCS Diplexer 

Comparisons of the circuit simulation and EM simulation on the 

designed lumped-element directional couplers.

Conclusion 

LTCC background and design consideration have been reviewed. 

Design examples were shown of 

LTCC PAM module application 

LTCC coupler design application 

LTCC switch module design application 

The validity of proposed applications was verified by applying to 

circuit simulator (Ansoft Designer) 

Small-size chip type circuit model can be realized by using 

proposed circuits, and Ansoft HF/SI product family.

References 

Paolo Antognetti and Giuseppe Massobrio, “Semiconductor Device 

Modeling with Spice,” McGraw-Hill Book Company, 1988 

Steve C. Cripps, “RF Power Amplifier for Wireless Communications,” 

Aertech House, 1999 

Lawrence E. Larson, “RF and Microwave Circuit Design for Wireless 

Communications,” Artech House, Inc. 1997 

George L. Matthaei, Leo Young “Microwave Filters, impedance-matching 

networks, and Coupling structures.” Artech House, Inc. 1980 

David M. Pozar “Microwave Engineering” Addison-Wesley Publishing 

Company. 1993

Design of LTCC RF Modules for Communication Systems

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