01 - BLOCK DIAGRAM

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5 5 4 C89, C90, C91, C92 only populated for boards that do not use external differential microphones. 4 3 C C DGND B B VAUX1_3V0 2,10 uP_I2C3_SCL 2,10 uP_I2C3_SDA U1G TWL4030 1007622 Audio VIO_1V8 VAUX1_3V0 8 7 6 1 2 3 4 5 VIO_1V8 U16 PCA9306DCTR 1004678 2 VREF1 VREF2 7 EN 8 3 SCL1 SCL2 6 4 SDA1 SDA2 5 GND R35 4.7K 1002759 1 R25 100K 5% 1001372 DGND DGND C41 1uF 1003982 TLV_I2C3_SCL_3V0 TLV_I2C3_SDA_3V0 TLV_I2C3_SCL_3V0 5 TLV_I2C3_SDA_3V0 5 A A 3 2 2 08 - AUDIO, TOUCH MICBIAS1 2 IO_1P8 MICBIAS1.OUT MICBIAS1.OUT/VMIC1.OUT MIC.MAIN.P MIC.MAIN.M D1 E2 F2 MIC_MAIN_P 2 MIC_MAIN_M 2 MICBIAS2 2 MIC_SUB_P 2 MIC_SUB_M 2 2,7,10 BT_PCM_CLK 2,10 PCM_DR 2,10 PCM_DX 2,7,10 BT_PCM_VFS R1 T2 T15 R16 PCM.VCK PCM.VDR PCM.VDX PCM.VFS MICBIAS2.OUT MICBIAS2.OUT/VMIC2.OUT MIC.SUB.P/DIG.MIC.0 MIC.SUB.M/DIG.MIC.1 D2 G2 H2 C92 0.1uF 1002396 C91 0.1uF 1002396 C29 C90 0.1uF 1002396 C89 0.1uF 1002396 D 2,10 MCBSP2_CLKX 2,10 MCBSP2_FSX 2,10 MCBSP2_DX 2,10 MCBSP2_DR L3 K6 K4 K3 I2S.CLK/TDM.CLK I2S.SYNC/TDM.SYNC I2S.DIN/TDM.DIN I2S.DOUT/TDM.DOUT VINTANA2.OUT Head Set Mic. VHSMI.OUT HSOL PreDriv.Left/VMID HSOR PreDriv.RIGHT/ADCIN7 E4 B4 B7 B5 B8 C34 0.1uF 1002396 22uF C30 1003902 22uF R22 1003902 33 R23 33 DGND 1003845 5% 1003845 5% C32 47pF CODEC_OUTL 2 CODEC_OUTR 2 C33 47pF D NEED TO CLEAR AIF_TRI_EN BIT IN TWL4030 WHEN OTHER CODECS ARE PRESENT ON BASEBOARD Head SetHSMIC.P HSMIC.M Ear Piece EAR.P EAR.M AUX Input AUXR AUXL VBAT Level Hands-Free IHF.LEFT.P IHF.LEFT.M IHF.RIGHT.P IHF.RIGHT.M VBAT.LEFT VBAT.LEFT GND.LEFT GND.LEFT E3 C31 0.1uF F3 1002396 A6 A7 DGND G1 F1 C37 0.1uF 1002396 C38 0.1uF 1002396 MAIN_BATTERY B9 IHF_LEFT_P 2 B10 IHF_LEFT_M 2 B11 IHF_RIGHT_P 2 B12 IHF_RIGHT_M 2 D10 D9 C10 C9 R24 C36 2.7K 100pF 5% 1002393 1003040 DGND MIC_IN 2 CODEC_INR 2 CODEC_INL 2 C39 C40 47pF 47pF 1003713 1003713 DGND DGND 1003713 1003713 DGND DGND 2,5,6,7,10 SYS_nRESWARM 10 TOUCH_nIRQ 2,10 uP_I2C3_SDA 2,10 uP_I2C3_SCL U14 TSC2004IRTJ 1008224 IOVDD SNSVDD 5 RESET VREF 4 PINTDAV X+ 1 SDA X- 2 SCL Y+ Y- AUX 20 AD0 3 AD1 TPAD SNSGND SUBGND 19 NC DGND 8 NC AGND VIO_1V8 VAUX1_3V0 7 12 11 13 TOUCH_BOTTOM 2 16 TOUCH_TOP 2 14 TOUCH_LEFT 2 17 TOUCH_RIGHT 2 9 A/D1 2 21 18 15 6 10 VBAT.RIGHT VBAT.RIGHT GND.RIGHT GND.RIGHT D12 D11 C12 C11 DGND DGND AVSS4 AVSS3 AVSS2 AVSS1 AVSS1 AVSS1 AVSS1 AVSS1 C7 M15 R10 E5 J8 J7 J6 J4 MICBIAS.GND D3 VREF AGND N16 N15 Title OMAP3430 SOM Number 1007969 Rev 4 1 LOGIC PRODUCT DEVELOPMENT 1 411 WASHINGTON AVE. N MINNEAPOLIS, MN 55401 PHONE: (612) 672-9495 FAX: (612) 672-9489 Project OMAP3430-10 Sheet 8 Of 12
5 5 4 4 3 3 2 2 1 1 D D C C B B A A 09 - POWER NOTE: AC CHARGE PATH NOT POPULATED FOR LABRADOR SOM. USB CHARGE PATH NOT POPULATED FOR MHR SOM. R74 NOT POPULATED BY DEFAULT 4 OMAP3430 SOM 9 OMAP3430-10 12 1007969 411 WASHINGTON AVE. N Title Number Project Sheet Of PHONE: (612) 672-9495 MINNEAPOLIS, MN 55401 FAX: (612) 672-9489 LOGIC PRODUCT DEVELOPMENT Rev T2_VCCS VDDS_DPLL_PER UC2 UC1 PCHGUSB VDDS_DPLL_PER T2_VCCS UC1 V_INTER_USB_CHG PCHGUSB UC2 USB1_VBUS 2,10 SYS_nRESWARM 2,5,6,7,8 uP_DREQ1 4 VSIM VAUX1_3V0 VDAC VPLL1 VMMC1 VPLL2 MAIN_BATTERY DGND DGND VSIM VPLL2 DGND VDD1_CORE DGND VIO_1V8 VIO_1V8 VMMC1 DGND VDAC VIO_1V8 VDD2_CORE DGND DGND VAUX4 DGND VIO_1V8 DGND MAIN_BATTERY MAIN_BATTERY DGND DGND VAUX1_3V0 DGND VAUX4 DGND DGND DGND DGND DGND VPLL1 VPLL2 TWL_RTC TWL_RTC DGND VINTDIG_OUT VINTDIG_OUT DGND VAUX4 VDAC DGND 5V 5V DGND DGND MAIN_BATTERY DGND DGND VDD1_CORE VDD2_CORE VIO_1V8 MAIN_BATTERY MAIN_BATTERY MAIN_BATTERY VIO_1V8 BACKUP_BATT VPLL2 VPLL1 VPLL1 DGND DGND DGND DGND DGND DGND VIO_1V8 VIO_1V8 DGND VDD1_CORE DGND VDD2_CORE DGND C139 1002396 0.1uF R28 1002687 732K 1% TP5 ICT_TESTOUT Regulators VBAT Level Inputs Outputs U1E TWL4030 1007622 M2 M3 K16 H14 J15 G16 B3 C2 A4 K2 P8 P10 L2 L16 H15 R9 J2 B6 H3 P9 L1 C1 B2 A3 K1 K15 VAUX1.OUT VAUX2.OUT VRTC.OUT VPLL1.OUT VPLL2.OUT VAUX3.OUT VAUX4.OUT VMMC1.OUT VMMC2.OUT VSIM.OUT VINTUSB1P5.OUT VINTUSB1P8.OUT VDAC.OUT VINTDIG.OUT VPLLA3R.IN VBAT.USB VINTANA2.OUT VINTANA2.OUT VINTANA1.OUT VUSB.3P1 VAUX12S.IN VMMC1.IN VAUX4.IN VMMC2.IN VDAC.IN VINT.IN U24A 1008074 FDJ1027P 1 5 6 7 S1 S1 G1 D1 C127 1002396 0.1uF U19B 3 2 4 8 G2 S2 S2 D2 TP4 ICT_Programming_OMAP_VPP C134 1002396 0.1uF C80 1003982 1uF R29 1008782 .22 1/4W C60 1003982 1uF Charger U1D TWL4030 1007622 N6 N4 P2 N7 P1 P6 N5 P4 R5 P5 N2 N1 PCHGUSB PCHGAC ICTLAC2 ICTLAC1 ICTLUSB2 ICTLUSB1 VAC VBATS VBAT VCCS VPRECH BCIAUTO C64 1003982 1uF C128 1002396 0.1uF U24B 3 2 4 8 G2 S2 S2 D2 C61 1003982 1uF C65 1003982 1uF C63 1003982 1uF C59 1003982 1uF R68 1003854 51 5% C138 1002396 0.1uF C75 1002396 0.1uF U4C OMAP3430 1008324 Y9 W9 T9 R9 M9 L9 J9 Y10 U10 T10 R10 N10 M10 L10 J10 Y11 W11 K11 J11 W12 K13 Y14 K14 J14 Y15 W15 J15 AC4 J4 H4 D8 AE9 D9 D15 Y16 AE18 Y18 W18 K18 J18 AE19 Y19 U19 T19 N19 M19 J19 Y20 W20 V20 U20 P20 N20 K20 J20 D22 D23 AE24 M25 L25 U1 J1 F1 J2 F2 R4 B5 A5 AH6 B8 A8 B12 A12 D16 C16 B18 A18 B22 A22 A15 J28 M1 AE28 AF28 N1 AA1 AF1 AH10 AH15 AH13 G1 AD3 AD4 W4 AF8 AE8 AF16 AF23 AE23 F25 F26 AG27 W16 AE16 AH20 K25 P25 E25 K15 AG20 H28 AG21 AH21 AE27 V25 AG2 U2 B2 AG3 W3 P3 J3 E3 A3 P4 E4 AG6 D7 C7 V9 U9 P9 N9 K9 W10 V10 P10 K10 D10 C10 AF12 J27 AE12 Y12 K12 J12 Y13 W13 J13 M2 D13 N2 C13 W14 K16 Y17 W17 K17 J17 W19 V19 R19 P19 L19 K19 D19 C19 AF20 AE20 T20 R20 M20 L20 D21 C22 AC25 Y25 W25 AA2 AC26 R26 AF2 L26 A26 G27 B27 AF27 J16 AG11 AG10 AG16 M28 AA26 Y26 A2 A27 A28 AG1 B28 AG28 AH1 AH2 AH27 AH28 G28 U4 V4 L21 B15 M26 AH11 AG13 AH16 C28 AG15 AA15 AA16 AA14 VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_MPU_IVA VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDDS_MEM VDDS_MEM VDDS_MEM VDDS_MEM VDDS_MEM VDDS_MEM VDDS_MEM VDDS_MEM VDDS_MEM VDDS_MEM VDDS_MEM VDDS_MEM VDDS_MEM VDDS_MEM VDDS_MEM VDDS_MEM VDDS_MEM VDDS_MEM VDDS_MEM POP_DDR_VDD POP_DDR_VDD POP_DDR_VDD POP_DDR_VDD POP_DDR_VDD POP_FLASH_VDD POP_FLASH_VDD POP_FLASH_VDD POP_FLASH_VDD POP_FLASH_VDD POP_FLASH_VPP VPP VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS_SRAM VDDS CAP_VDD_DSI VDDS_MMC1 VDDS_SIM VDD_CORE VDDS_DPLL_DLL VDDS_CSI2 VDDS_CSIb VDDS_DSI VSS_DSI VDDS_SDI VDDA_DAC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS POP_VSS_FT VSS VSS VSS VSS VSS VSS VSS POP_VSS_FT VSS POP_VSS_FT VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS POP_VSS_FT VSS VSS POP_VSS_FT VSS VSS VSS VSS POP_VSS_FT VSS POP_INT0_FT POP_VSS_FT VSS_CSI2 VSS_CSIb VSS_SDI VSSA_DAC POP_NC_A2 POP_NC_A22 POP_NC_A23 POP_NC_AB1 POP_NC_B23 POP_NC_AB23 POP_NC_AC1 POP_NC_AC2 POP_NC_AC22 POP_NC_AC23 VDDS_MEM BG_TESTOUT CAP_VDD_SRAM_MPU_IVA CAP_VDD_SRAM_CORE POP_VSS_FT POP_VSS_FT POP_INT1_FT POP_RESET_RP_FT POP_TQ_TEMP_S VDDS_MEM POP_VSS_FT CAP_VDD_WKUP VDDS_DPLL_PER VDDS_WKUP_BG C45 1005620 10uF C130 1002396 0.1uF C57 1003982 1uF C84 1002396 0.1uF R74 1001368np 0 C133 1002396 0.1uF C67 1003982 1uF C78 1003982 1uF C52 1003982 1uF C124 1002396 0.1uF C69 1002396 0.1uF C46 1003982 1uF C58 1003982 1uF C66 1003982 1uF R51 1001372 100K 5% C50 1005620 10uF C129 1002396 0.1uF C48 1005620 10uF TP3 ICT_Programming_POP_VPP R60 1001339 10.0 1% C74 1006399 0.22uF C68 1003982 1uF C77 1003982 1uF C53 1003982 1uF C88 1002396 0.1uF C49 1005620 10uF L2 1008231 1.0uH LPS3314-102ML R59 1001339 10.0 1% C73 1006399 0.22uF C47 1003982 1uF R69 1003754 470K 5% C62 1003982 1uF C82 1003982 1uF C44 1005620 10uF C79 1003982 1uF C54 1003982 1uF C125 1002396 0.1uF C56 1003982 1uF C132 1002396 0.1uF L3 1008231 1.0uH LPS3314-102ML R50 1003854 51 5% C76 1006399 0.22uF C55 1003982 1uF C83 1002396 0.1uF C72 1003982 1uF Switching Regulators VBAT Level Input U1F TWL4030 1007622 D14 E14 E15 C14 D15 D16 E13 B15 C15 C16 R13 P14 N13 R14 T13 T14 R15 T4 R3 N3 R4 P3 T3 R2 H11 H10 H9 H13 C8 M14 VDD1.IN VDD1.IN VDD1.IN VDD1.SW VDD1.SW VDD1.SW VDD1.FB VDD1.GND VDD1.GND VDD1.GND VDD2.IN VDD2.IN VDD2.FB VDD2.SW VDD2.SW VDD2.GND VDD2.GND VIO.SW VIO.SW VIO.FB VIO.IN VIO.IN VIO.GND VIO.GND DGND DGND DGND DGND IO.1P8 BKBAT C126 1002396 0.1uF U19A 1008074 FDJ1027P 1 5 6 7 S1 S1 G1 D1 C51 1005620 10uF C131 1002396 0.1uF C81 1003982 1uF L1 1008231 1.0uH LPS3314-102ML C70 1003982 1uF C71 1002396 0.1uF
Page 1 and 2: PROJECT: OMAP3430-10 PART NUMBER: 1
Page 3 and 4: 5 5 4 4 3 VAUX1_3V0 VIO_1V8 VAUX1_3
Page 5 and 6: 5 5 4 4 3 D D DEFAULT IS C121, C122
Page 7: 5 NOTE: Components on this page are
Page 11 and 12: 5 5 4 4 3 D D DGND B B A A 3 DGND 2

01 - BLOCK DIAGRAM

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