# Design and Analysis of a High-Speed Power Delivery System

Design and Analysis of a High-Speed Power Delivery System

Design and Analysis

of a High-Speed

Power Delivery System (PDS)

Ansoft Design Forum

June 2002

High-Speed

Digital Device

Mag. of Z

Z target

The Impedance of a PDS

V

|Z|

I

f

Z =

V

I

Power

Delivery System

The Impedance seen into the PDS at the device should

keep low from DC to several harmonics of clock frequency!

4A

Target Impedance Calculation

Z

Target

=

Hardware Example

3.3v

VRM

( Power Supply Voltage)

× ( Allowed Ripple)

3.3v�1.8v

Converter

2A

2A

Current

1.8v small plane

( 1.

8v)

× ( 5%

)

ZTarget(1.8v) = = 45mΩ

2A

3.3v plane

( 3.

3v)

× ( 5%

)

ZTarget(3.3v) = = 82.

5mΩ

2A

PDS Components

Voltage Regulator Module (VRM)

Linear model for VRM.

R0: the value of the resistor between the VRM sense point and

the actual load and is usually only a few mOhms

L_out: the output inductance of the VRM

R_flat: the ESR of the capacitor associated with the VRM

Ideal voltage source has the value of the power supply voltage

L_slew is chosen so that current will be ramped up in the

linear model in about the same time that it is ramped up in a

real VRM.

Voltage Regulator Module (VRM)

� V = L*di/dt

Linear model for VRM.

� For a VRM to ramp this 20 A transient current

either up or down in 15 us

R0 = 1mohm

L_out = 4nH

R_flat = 30mohm

L_slew = 67.5nH

L _ slew = V = 0.05⋅1.8V

15μsec

= 67.

5

di

20A

dt

nH

Simulation for VRM

Simulation for VRM (cont’d)

• I = C*dv/dt

Bulk Capacitor

• Suppose there is a 20 A current transient, the

VRM responds in 15us, and the PDS must

remain within 5% of a 1.8V power supply

C

=

I

dV

dt

= 20 A⋅

15μ

sec

= 3333uF

1.

8V

⋅0.

05

Simulation for VRM + Bulk Cap

Simulation for VRM + Bulk Cap (cont’d)

ESR of the Bulk Cap = 1

ESR of the Bulk Cap = 0.1

ESR of the Bulk Cap = 0.01

ESR of the Bulk Cap = 0.001

ESR of the Bulk Cap = 1

ESR of the Bulk Cap = 0.1

ESR of the Bulk Cap = 0.01

ESR of the Bulk Cap = 0.001

Simulation Impedance using Serenade Tune Mode

High Frequency Ceramic Capacitor

• NPO capacitors have the lowest ESR and best

temperature and voltage properties, but are only

available up to a few nF.

• X7R capacitors have reasonable voltage and

temperature coefficients and are available from

several nF to several uF.

• X5R is similar to X7R, but with reduced reliability

and are being extended to 100uF.

• Y5V dielectric is used to achieve high capacitance

values, but has very poor voltage and temperature

characteristics.

Cap 1

10 nF

100 mohm

5 nH

High Frequency Capacitor

Cap 2

1 nF

100 mohm

5 nH

Cap 3

1 nF

100 mohm

0. 5 nH

Cap

Ind

Cap1

10nF

100m Ohm

5nH

High Frequency Capacitor

Cap2

10nF

100m Ohm

2nH

Cap3

10nF

100m Ohm

0.5nH

Decreasing

Inductance

Reducing the Parasitic Inductance

for HF Capacitors

1. Reduce the length of via for decoupling capacitors

(i.e.reduce the loop inductance)

2. Change the layout of decoupling capacitors

3. The thickness of high frequency capacitors

4. Parallel the decoupling capacitors with same value

or multiple skew values

(3)

(1) (2)

Simulation of Impedance of Parallel Capacitors

Both ESR and Inductance improved

performance, but part count increased

Simulation for Impedance of Parallel

Capacitors with Skewed Capacitance

Simulation for VRM+Bulk_cap+HF_cap

VRM

Bulk capacitor

HF capacitor

Simulation for VRM+Bulk_cap+HF_cap

(cont’d)

Z = 82.

5mΩ

Target(3.3v)

Z = 45mΩ

Target(1.8 v)

frequency

DC

l/10

3D Distributed

PEEC

Plane Modeling

TPA(PEEC)

l/4

HFSS & SIwave (Full-Wave)

FULL WAVE

HFSS+Full Wave Spice

SI_wave

Problem

Scale

Physical Design

Using

Full Wave Spice

Model from HFSS

S1

AGND

S2

S3

AVCC_3.3v

S4

S5

DVCC_3.3v

S6

S7

DGND

S8

(1,5)

100uF 2.7uF

V

(1,1)

0.1uF

10nF

1nF

12 Layers PCB

21*10nF

21*0.1uF

21*1nF

(4,3)

2A

Current

Sink

V

22mA

Current

Sink

(5,4) (6,4)

2*1nF

V V

V

V V

11*0.1uF

33mA

Current

Sink

V

(7,5)

(7,1)

Plane Impedance w/ & w/o De-cap

Voltage Transient w/ & w/o De-cap

0.2ns 0.2ns

Simulation for Extra AGND Plane Inserted

S1

AGND

S2

S3

AGND

AVCC_3.3v

S4

S5

DVCC_3.3v

S6

S7

DGND

S8

(1,5)

100uF 2.7uF

V

(1,1)

0.1uF

10nF

1nF

21*10nF

21*0.1uF

21*1nF

(4,3)

2A

Current

Sink

V

22mA

Current

Sink

(5,4) (6,4)

2*1nF

V V

V

V V

11*0.1uF

33mA

Current

Sink

V

(7,5)

(7,1)

Plane Impedance with Extra AGND

Plane Inserted

After extra plane inserted

Voltage w/ & w/o Extra AGND

Plane Inserted

After extra plane inserted

Enhanced de-cap:

100nF*2, 50nF*2

25nF*2, 10nF*2

2.5nF*2, 1nF*10

100pF*2 are in

parallel!!

De-cap Enhancement for HF Range

Plane Impedance w/ & w/o Enhanced De-cap

With Enhanced De-cap

Voltage Transient w/ & w/o Enhanced De-cap

0.2ns 0.2ns

With Enhanced De-cap

Now Meets 5% Voltage Spec.

Impedance Simulation using PEEC

Summary

� Impedance control from DC to GHz:

� Voltage Regulator Module (VRM)

� Bulk Capacitor

High Frequency Ceramic Capacitor

� PCB Planes

� Tools used for simulation:

� Schematic Capture (Maxwell SPICE)

� HFSS

� (SI Wave)

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