Why Silicon Photonics? - Institute of Microelectronics - A*Star

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A publication of the Institute of Microelectronics
Issue 3 October 2009
B u l l e t i n
EISSN 0218-7477 MICA (P) 193/04/2009
Why Silicon
Photonics?
Monolithic 10 Gbs -1
Silicon Optical
Modulators
Diffraction
Grating Effect
on Waveguided
Germanium MSM
Photodetector
Response
Germanium
Photodetector
Technology for
Next Generation
Optical Interconnects
Applications
Light Extraction
Improvement from
Si-based Multilayers
with Photonic
Crystal Patterns
Exclusive Interviews:
Dr. Young-Kai Chen
Bell Laboratories, Alcatel-Lucent
Professor Fujio Masuoka
Unisantis Electronics (Japan) Ltd.

Executive Director’s
Foreword
Kwong Dim-Lee
Executive Director
Dear Readers,
As we live through the Information Age, we witnessed the progression of smoke signals to Morse code,
analog voice transmission to digital voice/video/data content and now massive bandwidth demand for
data communication. The image communications with the World Wide Web created further bandwidth
demand and the advent of interactive computation and imaging activities drive even higher bandwidth
requirements. Optical interconnect technology has been utilized in long haul communications for the past
two to three decades but its applications in short reach communication is not widespread primarily due
to its cost. Silicon Photonics has emerged as a viable alternative for high volume manufacture of photonic
integrated circuits.
In analogy to what Silicon has done for Silicon Electronics and how it influenced our daily life and business
operation, Silicon Photonics is set to revolutionize the traditional multi-billion-dollar optoelectronics
industry. In the near future, applications that can benefit from Silicon Photonics include high data-rate
communications (tera-bit, i.e., 10 12 bit) and high-performance computing. Possible applications of silicon
photonics include optical communications, environmental monitoring, chemical and biochemical analysis, medical, healthcare and
diagnostic areas.
To promote Singapore’s competitive edge at the forefront of this emerging technology, the Institute of Microelectronics (IME) has
made significant contributions to the establishment of a cost effective Silicon Photonics technology platform since late 2006. The
central goal of the Nano-Photonics programme is focused on the development of process technologies and designs needed to
develop application-specific electronic-photonic integrated circuit (AS-EPIC). By leveraging on the well established Si-CMOS
fabrication technology, IME Photonics Team has successfully built up a comprehensive passive and active photonic device library
with versatile building blocks required to support the design and demonstration of EPIC. In this issue of MicroE, we will be providing
readers an overview of IME’s research and development in this technology.
Editorial Team
Kwong Dim-Lee
Teo Yong Chua
Tan Su-Lynn
Contributors
Kwong Dim-Lee
Teo Yong Chua
Tan Su-Lynn
Patrick Lo G.Q.
Ang Kah-Wee
Liow Tsung-Yang
Yu Mingbin
Ren Fang-Fang
Guest Interviewees
Dr. Young-Kai Chen of Bell Laboratories,
Alcatel-Lucent
Professor Fujio Masuoka of Unisantis
Electronics (Japan) Ltd
For enquiries and comments, please write to:
IME Editorial Team
Institute Of Microelectronics
11 Science Park Road
Singapore Science Park II
Singapore 117685
Tel: +65 6779 7522
Fax: +65 6778 0136
Email: editorial@ime.a-star.edu.sg
www.ime.a-star.edu.sg
For research collaboration and business opportunities,
please email: ID@ime.a-star.edu.sg
microE Bulletin is a bi-yearly publication of IME.
All Rights Reserved. No part of this publication may be reproduced or used
in any form without the written permission of IME.
THIS MONTH: OCTOBER 2009
COVER STORY
3 Germanium Photodetector Technology for Next
Generation Optical Interconnects Applications
R&D NEWS
8 Why Silicon Photonics
10 Monolithic 10 Gbs -1 Silicon Optical Modulators
11 Diffraction Grating Effect on Waveguided Germanium
MSM Photodetector Response
13 Light Extraction Improvement from
Si-based Multilayers with Photonic Crystal Patterns
INDUSTRY COLLABORATIONS
Exclusive Interviews:
16 Dr. Young-Kai Chen of Bell Laboratories,
Alcatel-Lucent
17 Professor Fujio Masuoka of Unisantis Electronics
(Japan) Ltd.
PEOPLE
18 Zhao Hui, a former PhD student attached to IME
19 Jiang Yu, PhD graduate from NUS
A Research Institute of the Agency for Science, Technology and Research (A*STAR)

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Story
Germanium Photodetector Technology
for Next Generation Optical Interconnects
Applications
Dr. Ang Kah-Wee
Senior Research Engineer, Nano-
Electronics and Photonics Programme
Dr. Patrick Lo G. Q.
Program Director, Nano-Electronics
and Photonics Programme
Executive Summary
Research into the limits of
electrical interconnects indicates
that the requirements for data
communication in future generations of
CMOS integrated circuits can hardly be
met with metal wires. While the demand
for on-chip functionality continues to
grow as predicted by Moore’s Law, it
is now widely recognized that copper
interconnect will increasingly suffer from
severe propagation delays for clock
signals, overheating, information latency
and electromagnetic interference. Optical
interconnects which readily offer greater
bandwidth, lower power, and resistance
to electromagnetic interference and
signal crosstalk has emerged as one
promising alternative that has attracted
growing interests. This article presents
a brief perspective on the exploration
of silicon photonics to provide high
performance optical interconnects
solutions to support the growing needs
of data communication. In particular,
the progress and development of optical
detections technology using Group-IV
based heterostructure materials are
reviewed. A successful implementation
of such state-of-the-art Ge-based
photodetector technologies is poised to
become an enabling technology to realize
on-chip optical interconnects for nextgeneration
high bandwidth computing
applications. The overall goal is to
develop a scalable approach that extends
the reach and impact of Moore’s Law for
many more generations to come.
Introduction
Continuous scaling of complementary
metal-oxide-semiconductor (CMOS)
transistor technology as driven by
Moore’s Law leads to significant
enhancement in the speed performance
of microprocessor. Over the past
few decades, this was achieved by
aggressively shrinking the physical
dimension of the transistor from one
technology generation to another for
improved drivability and integrated circuits
density. Recent advancement in CMOS
extension via innovative ‘More Moore’
approaches such as the application of
strained channel engineering, metal gate/
high- , and multiple gate structure have
pushed the device performance closer to
its fundamental limits. This has led to a
new generation of microprocessors that
are capable of handling data computation
at a rate that outpaces their abilities
to transmit or receive it from external
circuits.
However, the evolution of Moore’s Law
will soon encounter red-brick walls.
Though the CMOS transistors switching
speed has been significantly enhanced,
the performance gain at the system
level does not seem to match up with
the improvement. This is because a
higher transistor packing density leads
to an increased demand for longer
interconnects, which resulted in a
higher parasitic resistance. Moreover,
the additional capacitive coupling also
causes longer signal delay and power
consumption. While there is a tendency
in high performance computing system to
shifts towards increasing the parallelism
in data processing by partitioning the
microprocessor into multi-cores, such
approach is perceived to be unable to
offer the ultimate solution. The complexity
introduced in this approach is enormous,
and will eventually strained in meeting the
requirements of low power consumption
and high bandwidth data communication
beyond 10Gb/s. Thus, there is an
obvious need to create a radically new
communication technology landscape
to meet the stringent requirements of
data communication in future technology
generations.
Optical interconnect technology is an
increasingly attractive alternative and
has become essential for computing
and communication industries. This
is because optical interconnects offer
advantages such as greater bandwidth,
lower power, reduced interconnects
delay, and immunity to electro-magnetic
interference and signal crosstalk. Over
the last few decades, traditional optical
components are typically made of
exotic III-V compound materials such
as gallium-arsenide (GaAs) and indiumphosphide
(InP) due to their excellent
light emission and absorption properties.
However, compound-semiconductor
devices are generally too complicated
to process and costly to implement
in optical interconnects. To be widely
adopted, this technology must be made
cost effective over the traditional copper
interconnects approach. In search
for such cost-competitive solution,
Si photonics emerges to hold great
promise for its inexpensive material and
its compatibility with current CMOS
fabrication technology. In addition, the
ability to integrate different types of optical
components such as photodetector,
modulator, light source, and waveguide
to form a photonics integrated circuit on
a single silicon chip platform makes it an
extremely favourable approach.
Figure 1 shows a schematic illustration
of the essential optical components
to construct a photonics integrated
circuit for data communication. In a way
analogous to powering the electronic
www.ime.a-star.edu.sg
microE Bulletin | Issue 3 October 2009 3

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regime (1.3~1.55μm), germanium (Ge)
could be exploited as alternative for
the realization of high performance
photodetector due to its favourable
absorption coefficient. However, Ge can
be a challenging material to integrate in
a CMOS environment for its low thermal
budget constraint and its large lattice
mismatch of ~4.2% with Si [1]. High defect
densities seen in the Ge-on-Siliconon-
Insulator (Ge-on-SOI) epitaxial film could
induce unfavourable carrier recombination
process that would degrade the detector’s
quantum efficiency.
Development of Hetero-Epitaxy of
Germanium on Silicon
Figure 1: Schematic illustration of on-chip optical interconnects realized using a photonics integrated
circuit platform.
circuit using an electrical power supply,
a high quantum efficiency laser source
is employed to provide the required
optical power in a photonics integrated
circuit. By leveraging on the high index
contrast between the Si core and the
silicon-dioxide cladding, routing of
optical signals using photonic waveguide
with low propagation loss can be
made possible. To harness increased
data capacity, a wavelength division
multiplexing (WDM) based on arrayedwaveguide
grating (AWG) composed
of rib SOI waveguides or ring resonator
in photonic domain can be exploited to
provide multiple channels transmission
for parallel data processing. Using an
optical filter, a particular wavelength
(λ n
) can be selected into the photonic
waveguide data bus. While Si-based
modulator exhibits weaker electrooptical
coefficients due to its central symmetry in
the lattice structure, a free carrier plasma
dispersion effect can be exploited to
enable effective optical modulation. The
modulated optical signals are channelled
through the photonic waveguide data bus
where multiple wavelengths signals can
be delivered on the same channel without
suffering interference from one another.
At the receiving end, signal of a specific
wavelength channel is filtered and fed
into a photodetector for enabling opticalto-electrical
encoding. The encoded
electrical signal will then pass through the
CMOS circuitry for data processing.
Although it appears promising that an
electronic-photonic integration could
enable the convergence of computing
and communication capabilities on
single ship platform, its wide spread
implementation has been hindered by
the grand challenge in demonstrating an
important active photonic component
needed to perform opto-electric (OE)
signal conversion. The search for a new
material that is compatible with the
mainstream CMOS process technology is
of particular interest. While silicon (Si) has
been shown to be unsuitable for optical
detection in the near-infrared wavelength
The key challenge to high quality
germanium (Ge) epitaxy growth on silicon
(Si) rests with the huge lattice mismatch
between the two heterostructure
materials. The existence of ~4.2% lattice
mismatch strain has been shown to
give rise to two major issues: (1) high
densities of threading dislocations and
(2) rough surface morphology due to 3D
Stranski-Krastanov (SK) growth. Both of
these defects present much concerns
for the generation of high leakage
current which would compromise the
efficiency of a photodetector. Strategies
proposed in the literature to overcome
these challenges vary to a large extent.
Colace et al. proposed a direct heteroepitaxy
growth of Ge on Si through the
use of a low temperature thin SiGe buffer
layer (a few 10nm) [2]. The insertion of
such thin buffer avoids the occurrence
of 3D SK growth and allows the misfit
dislocations to be concentrated at
the hetero-interfaces. However such
approach requires a cyclic annealing
process to be carried out at both high
and low temperature (900°C/780°C) to
reduce the threading dislocation density
within the Ge active film. Using a similar
cyclic thermal annealing approach, Luan
et al. had also demonstrated a significant
improvement in both the surface
roughness and the dislocation density
[1]. Unfortunately, the needs for a high
temperature post-epitaxy Ge anneal with
long cycle time present a major concern
for CMOS implementation.
4 Institute of Microelectronics

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In our approach, selective epitaxial
growth of Ge on silicon-on-insulator
(SOI) was performed using an ultra-high
vacuum chemical vapor deposition
reactor [3]-[13]. Unlike the conventional
approaches, a thin pseudo-graded
SiGe buffer with a thickness of ~20nm
is proposed in this study to relieve the
large lattice mismatch stress between
the two heterostructure materials (Figure
2). The Ge mole fraction within the SiGe
buffer is compositionally graded from
10% to ~50%. The precursor gases used
for the SiGe growth comprise of diluted
germane (GeH 4
) and pure disilane (Si 2
H 6
).
A relatively thin Ge seed layer of ~30nm
is subsequently grown on the SiGe buffer
at a process temperature of 370°C.
The use of a low temperature growth is
intended to suppress adatoms migration
on Si and thus prevents the formation
of 3D SK growth, which allows a flat
Ge surface morphology to be achieved.
Upon obtaining a smooth Ge seed layer,
the epitaxy process temperature is then
increased to ~550°C to facilitate faster
epitaxy growth to obtain the desired Ge
thickness. Using this approach, high
quality Ge epilayer with a thickness of
up to ~2μm has been demonstrated,
along with the achievement of threading
dislocation density as low as ~107 cm -2
without undergoing any high temperature
cyclical thermal annealing step. In
addition, selective area growth of Ge on Si
has also been developed using a cyclical
deposition and etch back approach. In
each deposition cycle, the Ge growth
time is carefully optimized to avoid
exceeding the incubation time needed
for Ge seeds to nucleate on the dielectric
film. After every Ge deposition cycle, a
short etch back process using chlorine
(Cl 2
) precursor gas is then introduced
to remove possible Ge nucleation sites
on the dielectric. This allows a highly
selective Ge epitaxy process to be
developed, along with the achievement of
excellent surface roughness of ~0.28nm.
Waveguided Ge Photodetector
Platform Technology
For future realization of ultra-compact
photonics integrated circuit, the
integration of Ge photodetector with
optical waveguide and the demonstration
of high sensitivity with thin Ge epilayer
(

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the optical mode within the core of the Si
waveguide so as to prevent leakage into
the underneath Si substrate.
Performance Metrics of Waveguided
Ge Photodetector
Figure 4(a) examines the current-voltage
characteristics of the VPD and LPD
detectors under dark and illumination
conditions. Excellent rectifying
characteristics were demonstrated in
both the detectors, showing a forwardto-reverse
current ratio of ~4 orders of
magnitude. For a given applied bias of
−1.0V, the dark current (I dark
) in a VPD
was measured to be ~0.57μA (or ~0.7nA/
μm 2 ), which is below the typical 1.0μA
generally considered to be the upper limit
for high speed receiver design. On the
other hand, the dark current performance
in a LPD showed a much higher I dark
value
of ~3.8μA (or ~1.9nA/μm 2 ).
the VPD and LPD detectors achieved a
comparable photocurrent level at high
applied biases beyond -1.0V. Figure
4(b) compares the responsivity of the
detectors as a function of the applied
voltages. It is interesting to note that
the vertical PIN detector demonstrated
a lower responsivity as compared to the
lateral PIN detector for biases below−0.5
V. This could possibly be due to an
enhanced carrier recombination process
at the high density of defect centres near
the Ge-Si heterojunction. This is set to
compromise the absolute photocurrent
value of a vertical PIN detector under low
field influence. For an applied bias larger
than −1.0 V, a comparable responsivity
was measured for both the vertical and
lateral PIN detectors. Despite that the
metallurgical junction is separated by
merely 0.8μm, a lateral PIN detector also
showed a high absolute responsivity of
~0.9 A/W.
compared to that of LPD detector with
a slightly larger FWHM of ~28.9ps.
This could be attributed to the smaller
depletion layer width design in a VPD
detector which reduces the carrier transit
time. The FWHM pulse width is related
to the bandwidth and can be used as a
metric to gauge the speed performance of
the detectors. The theoretical modelling
results of the RC-time constant and the
transit-time bandwidth are also plotted
in Figure 5(b). Reducing the depletion
spacing could be exploited to enhance
the transit-time bandwidth performance
significantly, but it could impose concern
for a degraded RC-time bandwidth. To
overcome such trade-off, one could scale
the detector’s optical absorption length
to achieve lower device capacitance for
enabling bandwidth improvement.
Industry Collaborations and MPW
Services
In order to compare the sensitivity
performance between the VPD and LPD,
optical measurements were performed
by injecting an incident photon with
a wavelength of 1550nm into the SOI
micro-waveguide. The typical optical
propagation loss in our SOI microwaveguide
under TE polarization mode
is ~2dB/cm. No coupler was integrated
with the Si waveguide and the incidence
light was coupled through a single mode
lensed fiber directly into the Si nano-taper.
For an incident light power of ~300μW,
optical measurements showed that both
To investigate the factors affecting the
speed performance of the VPD and LPD
detectors used in this study, impulse
response measurements were performed
at a photon wavelength of 1550nm. A
pulsed laser source having a 80fs pulse
width was used in the measurements.
Both the detectors were characterized
using microwave probes and the impulse
responses were captured with a high
speed sampling oscilloscope. Figure
5(a) shows that a VPD detector achieved
a smaller full-width-at-half-maximum
(FWHM) pulse width of ~24.4ps as
Figure 4: (a) The current-voltage characteristics of the VPD and LPD detectors measured under dark
and illumination conditions. (b) Responsivity as a function of applied voltages for both the VPD and LPD
detectors measured at a wavelength of 1550nm.
Since the inception of silicon photonics
program in 2006, the Institute of
Microelectronics (IME) has been
actively engaged with industry partners
in developing and prototyping high
performance optical components and
photonics integrated circuits. Such
prototyping services can be divided into
two categories - Multi-Project-Wafer
(MPW) prototyping and customized
prototyping, both of which offer high-end
fabrication services at a cost affordable
to research groups and companies.
MPW prototyping works on the principle
of combining designs from various
users on shared masks, sharing a large
fraction of the process cost among the
users. On the other hand, many of IME’s
existing partners welcome the flexibility
that customized prototyping offers. To
shorten the development life-cycle, IME
also provides a host of both active and
passive baseline photonic devices in its
design libraries. Fabrication is performed
using standard CMOS processes in its
200 mm R&D foundry, which facilitates
quick technology transfers to commercial
foundries for mass production. The
service has proven to be a boost for users
- fabless companies and research groups.
An excellent example of a company
which has benefited from this service
6 Institute of Microelectronics

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Figure 5: (a) Impulse responses of the VPD and LPD detectors measured at a wavelength of 1550nm.
A smaller FWHM pulse width of ~24.4 ps was achieved in a VPD as compared to a LPD with a pulse
width of ~28.9ps. (b) Downscaling of detector length results in bandwidth enhancement due to a
reduced device capacitance.
is Lightwire, a US-based interconnect
company.
The Future Evolution of Silicon
Photonics
The future evolution of Silicon Photonics
will become increasingly promising
with the development of cutting edge
nanophotonic technologies. As the
electronics devices continue to scale in
advanced CMOS technology nodes, the
foot-print of existing photonics devices
which are typically in the micrometer
scale seems to impose much constraint
to enable the realization of ultra-compact
electronic-photonic integrated circuit
(EPIC). In order to address the needs
for small form factor, low power and
high speed integration while achieving
costeffectiveness, the introduction of
Si nano-photonics solutions become
imperative. However, aggressive
downsizing of physical dimensions could
compromise the device performance.
Innovative approaches to enhance the
efficiency of these nano-scale photonics
devices are therefore highly desirable.
For instance, the application of surface
plasmon antenna technology to boost
the quantum efficiency of nano-photodetector
emerges as a practical solution.
The discovery of surface plasmons can
be exploited to generate resonance at the
metal-dielectric interface with the same
frequency as the impinging electromagnetic
waves, but with a much shorter
wavelength. By exploiting this effect,
it becomes possible to guide optical
signals in nanoscale structures, resulting
in the miniaturization of the photonic
circuits. It is believed that nanophotonic
technologies can potentially change the
landscape for Silicon Photonics, allowing
for greater miniaturization and taking the
performance to new heights.
References
[1]
[2]
[3]
[4]
[5]
[6]
[7]
H.-C. Luan, D. R. Lim, K. K. Lee, K. M. Chen, J. G. Sandland, K.
Wada, and L. C. Kimerling, “High-quality Ge epilayers on Si with low
threading-dislocation densities”, Applied Physics Letters, Vol. 75, No.
19, pp. 2909–2911, 1999.
L. Colace, G. Masini, and G. Assanto, “Ge-on-Si approaches to the
detection of nearinfrared light”, IEEE Journal of Quantum Electronics,
Vol. 35, No. 12, pp. 1843–1852, 1999.
K.-W. Ang, T.-Y. Liow, M.-B. Yu, Q. Fang, J. Song, G.-Q. Lo, and D.-L
Kwong, “Low thermal budget monolithic integration of evanescent
coupled Ge-on-SOI photodetector on Si-CMOS platform”, IEEE
Journal of Selected Topics in Quantum Electronics, Vol. 14, In Press.
T.-Y. Liow, K.-W. Ang, Q. Fang, J. Song, Y. Xiong, M.-B. Yu, G.-Q. Lo,
and D.-L. Kwong, “Silicon Modulators and Germanium Photodetectors
on SOI: Monolithic Integration, Compatibility and Performance
Optimization”, IEEE Journal of Selected Topics in Quantum
Electronics, Vol. 14, In Press.
K.-W. Ang, T.-Y. Liow, Q. Fang, M. B. Yu, F. F. Ren, S. Y. Zhu, J.
Zhang, J. W. Ng, J. F. Song, Y. Z. Xiong, G. Q. Lo, and D.-L. Kwong,
“Silicon Photonics Technologies for Monolithic Electronic-Photonic
Integrated Circuit (EPIC) Applications: Current Progress and Future
Outlook”, IEEE International Electron Device Meeting 2009, Baltimore,
Dec. 7-9, 2009.
K.-W. Ang, J. W. Ng, G.-Q. Lo, and D.-L. Kwong, “Impact of fieldenhanced
band-trapsband tunneling on the dark current generation
in germanium (Ge) p-i-n photodetector”, Applied Physics Letters, vol.
94(22), 223515, Jun. 2009.
J. Wang, W. Y. Loh, K. T. Chua, H. Zang, Y. Z. Xiong, S. M. F.
Tan, M. B. Yu, S. J. Lee, G. Q. Lo, and D. L. Kwong, “Low-Voltage
High-Speed (18 GHz/1 V) Evanescent-Coupled Thin-Film-Ge Lateral
PIN Photodetectors Integrated on Si Waveguide”, IEEE Photonics
Technology Letters, vol. 20(17-20), pp. 1485–1487, Sep. 2008.
[8]
[9]
K.-W. Ang, S. Y. Zhu, J. Wang, K. T. Chua, M. B. Yu, G. Q. Lo,
and D. L. Kwong, “Novel Silicon-Carbon (Si:C) Schottky Barrier
Enhancement Layer for Dark Current Suppression in Ge-on-SOI
MSM Photodetectors”, IEEE Electron Device Letters, vol. 29(7), pp.
708–710, Jul. 2008.
K.-W. Ang, M.-B. Yu, S.-Y. Zhu, K.-T. Chua, G.-Q. Lo, and D.-L.
Kwong, “Novel NiGe MSM Photodetector Featuring Asymmetrical
Schottky Barriers using Sulfur Co-Implantation and Segregation”, IEEE
Electron Device Letters, vol. 29(7), pp. 704–707, Jul. 2008.
[10] K.-W. Ang, S. Zhu, M. Yu, G.-Q. Lo, and D.-L. Kwong, “High
Performance Waveguided Ge-on-SOI Metal-Semiconductor-Metal
Photodetectors with Novel Silicon-Carbon (Si:C) Schottky Barrier
Enhancement Layer”, IEEE Photonics Technology Letters,vol. 20(9),
pp. 754–756, May 2008. Germanium Photodetector Technologies for
Next Generation Optical Interconnects Applications 9
[11] S. Y. Zhu, M. B. Yu, G. Q. Lo, and D.-L. Kwong, “Near-infrared
waveguide-based nickel silicide Schottky-barrier photodetector for
optical communications”, Applied Physics Letters, Vol. 92, No. 8, p.
081103, Feb. 2008.
[12] W. Y. Loh, J. Wang, J. D. Ye, R. Yang, H. S. Nguyen, K. T. Chua, J.
F. Song, T. H. Loh, Y. Z. Xiong, S. J. Lee, M. B. Yu, G. Q. Lo, and D.
L. Kwong, “Impact of local strain from selective epitaxial germanium
with thin Si/SiGe buffer on high-performance p-i-n photodetectors with
a low thermal budget”, IEEE Electron Device Letters, vol. 28(11), pp.
984–986, Nov. 2007.
[13] T. H. Loh, H. S. Nguyen, R. Murthy, M. B. Yu, W. Y. Loh, G. Q. Lo, N.
Balasubramanian, D. L. Kwong, J. Wang, and S. J. Lee, “Selective
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www.ime.a-star.edu.sg
microE Bulletin | Issue 3 October 2009 7

R&D News
Why Silicon Photonics?
Dr. Liow Tsung-Yang
Senior Research Engineer, Nano-
Electronics and Photonics Programme
Dr. Patrick Lo G. Q.
Program Director, Nano-Electronics
and Photonics Programme
The convergence of electronic and
photonic technologies holds great
promise for keeping up with the
performance roadmap known as Moore’s
Law. Today, it is generally known that high
data rate communication beyond 10 Gb/s
requires the replacement of conventional
copper interconnect technology with
optical interconnect technology, due
to its advantages in bandwidth, power
consumption and reach. Optical
interconnect technology has been utilized
in long haul communications for the
past two to three decades. However, its
presence in shorter reach applications is
not widespread and has primarily been
limited by cost. Due to rising bandwidth
demands for short reach applications,
there is potentially a huge market for
optical technology. These include
consumer applications such as Fiber-tothe-home
(FTTH), which will enable the
delivery of high bandwidth content such
as high definition video and interactive
entertainment to individual homes. There
are also a variety of applications for
much shorter reach optical interconnect
technologies in the next-generation high
performance computers.
Silicon photonics is expected to play a
vital role in the market growth of short
to mid-range communications, since
it combines both low-cost and massproductivity.
Silicon is a compelling
platform for integrated optics, with
largely available infrastructure, toolsets,
knowledge, and capacity that have been
developed for Silicon-microelectronics.
With the adoption of Silicon MEMS
technique to create Silicon-trenches,
grooves and other micro-structures, the
cost of laser and fiber precision assembly
can be significantly reduced. Perhaps the
greatest benefit of Silicon photonics is
the cost effectiveness, in addition to the
performance gain via integrating different
types of optical devices (e.g., signal
routers, modulators, photodetectors) onto
a single silicon platform together with the
existing integrated electronics. Besides
lowering production costs, Silicon
photonics also provides the facilities for
product designers to add more integrated
functions.
On top of optical communications, Silicon
photonics may also be applied to new
applications in environmental monitoring,
chemical and biochemical analysis,
medical, healthcare and diagnostic areas.
All of these again have the common
requirement of low cost, small form factor,
and high-volume manufacturability, which
will only be possible if one can deliver
these technologies on an integrated
silicon platform cost-effectively. In brief,
the emerging demand for low-cost
high-volume production of components
with integrated functionality is the
pull factor for Silicon photonics. Upon
successful introduction of this technology,
the impact it has on applications and the
quality of human life will be of the same
magnitude as what we have experienced
from the introduction of electronic IC.
IME’s Silicon Photonics Program
IME’s Silicon Photonics Program was
launched in late 2006. Since then, the
fundamental process technologies and
device building blocks were aggressively
developed. This included the development
of dedicated processes such as the
selective epitaxial growth of germanium
on silicon (for forming Ge photodetectors),
high selectivity silicon deep reactive ion
etching (DRIE) process (for fiber coupling)
and the different process modules. Most
importantly, process integration schemes
and techniques were developed to
enable the monolithic integration of the
various types of photonic devices. In
parallel, device development involving
both electrical and optical design
and simulation work was also carried
out with experimental fabrication and
characterization. As a result of these
intensive effort, IME was able to develop
a Silicon photonic device library which
includes both active and passive
functional blocks such as photodetectors,
modulators, mode-converters, optical
filters, etc. Some examples are shown in
Figure 1.
The Silicon Photonics Program has
well-balanced efforts in core-research
development as evidenced by active
patent portfolio establishment, academic
collaborations and industry partnerships
in a near complete spectrum of research
activities revolving around the optical
transceiver. IME’s Silicon photonic
device library greatly expedites the joint
development projects with its industry
partners, while the Silicon photonics
platform is flexible enough to cater to
the differing needs of each industry
partner. As the Silicon photonics platform
is developed on existing standard 200
mm CMOS processes, rapid technology
transfers to customer-identified
commercial foundries is facilitated (e.g.
Chartered Semiconductor has received
IME’s technology for its modulator
process for SiOptical/Lightwire for massproduction).
The industrial collaborations
are gradually seeing active participation
from multinational corporations (e.g.
Alcatel-Lucent) in the tele-communications
industry. Not only does this indicate strong
industrial interest in Silicon photonics,
it also strongly validates the program’s
industrial applicability.
The future of Silicon photonics is
expected to become even more exciting
with the development of cutting edge
nano-photonic technologies such as
8 Institute of Microelectronics

R&D News
Figure 1: Examples of devices in IME’s Silicon photonics library
plasmonics and photonic crystals. The
sizes of Silicon photonic waveguides or
devices are constrained by the diffraction
limit, which is related to the wavelength
of light propagating inside the material
(i.e. silicon). Researchers have found
a way of exceeding this constraint by
using plasmonics. They discovered that
surface plasmons can be generated
at a metal-dielectric interface with the
resonant frequency as the impinging
electromagnetic waves, but with a much
shorter wavelength. By exploiting this
effect, it becomes possible to guide
optical signals in nanoscale structures,
resulting in the miniaturization of the
photonic circuits. Recently, IME has
demonstrated the use of plasmonics
to enhance the photo-response of Ge
photodetectors. The technology is
expected to yield smaller and faster
photodetectors. In parallel, a photonic
crystal is the optical analogue of the
semiconductor crystal. Photonic crystals
comprise periodic patterns of nanoscale
dielectric or metal and dielectric
structures. The propagation behavior of
electromagnetic waves through a photonic
crystal depends on its wavelength. A
photonic crystal can be designed such
that certain wavelengths are disallowed
or allowed. Control and manipulation of
light can also be engineered. Interesting
applications of photonic crystals include
lossless 90˚ waveguide bends, compact
modulators and even nanocavity lasers.
IME researchers have also shown the
enhanced photoluminescence of light
emitting devices with the use of photonic
crystals. We believed that nanophotonic
technologies can potentially change the
landscape for Silicon photonics, allowing
for greater miniaturization and it is the
goal of the Silicon Photonics team to take
its performance to a new height.
microE Bulletin | Issue 3 October 2009 9

R&D News
Monolithic 10 Gbs -1 Silicon
Optical Modulators
Dr. Liow Tsung-Yang
Senior Research Engineer, Nano-
Electronics and Photonics Programme
Silicon Photonics is set to revolutionize
the Optical Communications
industry due to its low cost,
volume manufacturability and intrinsic
compatibility for monolithic integration with
CMOS circuits. An optical modulator is a
vital component of an optical transceiver.
Current commercial optical modulators
are fabricated using expensive materials
such as III-V compound semiconductors
or Lithium Niobate (LiNbO 3
). In addition,
such modulators necessitate the use
of hybrid integration techniques during
manufacturing. This involves higher cost
and complexity compared to monolithic
integration.
IME researchers have developed
monolithic silicon optical modulators
capable of wavelength independent
operation at data transmission rates of
up to 10 Gbs -1 . Excellent phase-shifting
efficiency and jitter performance were
also demonstrated.
IME’s silicon modulators are based on
a Mach-Zehnder interferometer (MZI)
design and exploit the free carrier
plasma dispersion effect to achieve
optical modulation. In MZI modulators,
light from a continuous laser source
enters the modulator and is split into two
beams. The two beams are re-combined
at the output after each of them passes
through a phase-shifter waveguide. By
electrically controlling the carrier density
in each phase-shifter, the refractive index
of silicon can be controlled and in turn
induces a phase difference in the two
beams of light, resulting in constructive
or destructive interference at the point
of re-combination. Hence, the intensity
of light at the output can be modulated
by controlling the carrier density in the
phase-shifters.
The modulators utilize p-n junction phaseshifters
which are embedded in siliconon-insulator
(SOI) rib waveguides. These
are operated in the carrier depletion
regime (much faster carrier transport
compared to operating in the carrier
injection regime), resulting in excellent
speed characteristics Fig. 1 shows the eye
pattern measurements for a modulator
tested at 10 Gbs -1 . An extinction ratio of 6
dB was achieved with an electrical driving
signal of 5 V peak-to-peak. Excellent jitter
performance of ~4 ps was also measured.
The speed measurement is limited by the
measurement equipment. Nevertheless,
the short rise and fall-times indicate that
the modulator can be operated at even
higher speeds.
The phase-shifting efficiency (V π
.L π
~2.6
V.cm) is comparable to or exceeds those
of the best reported carrier depletion
type modulators. Detailed results are
published in the Journal of Selected
Topics in Quantum Electronics: Issue on
Silicon Photonics, “Silicon Modulators
and Germanium Photodetectors on SOI:
Monolithic Integration, Compatibility and
Performance Optimization”.
The monolithic carrier depletion-type
silicon optical modulator will be an
attractive component for future silicon
photonic transceivers due to its high
performance and simplicity in fabrication.
Such monolithically integrated silicon
optical modulators will become the
enabling components for low-cost optical
transceivers. It is likely that this can extend
high performance optical communications
capabilities even to mainstream consumer
applications in the near future.
Fig. 1 Eye pattern measurements showing an extinction ratio of ~6 dB and jitter (RMS) of ~4 ps for
operation at 10 Gbs -1 .
10 Institute of Microelectronics

R&D News
Diffraction Grating Effect on Waveguided
Germanium MSM Photodetector Response
Dr. Ren Fang-Fang
Senior Research Engineer, Nano-
Electronics and Photonics Programme
Dr. Ang Kah-Wee
Senior Research Engineer, Nano-
Electronics and Photonics Programme
Dr. Patrick Lo G. Q.
Program Director, Nano-Electronics
and Photonics Programme
Germanium-on-silicon-on-insulator
(Ge-on-SOI) photodetectors
have been actively pursued for
optical interconnection/communication
applications because of its large
absorption coefficient [1] and its
integration compatibility with silicon
(Si) complementary metal-oxidesemiconductor
(CMOS) process
technology. In particular, the metalsemiconductor-metal
(MSM) configured
photodiodes have been widely used due
to its relative ease of fabrication and high
speed performance [2,3]. Although the
MSM configured detector may exhibit
low quantum efficiency and large dark
current as compared to the p-i-n detector,
the latter can be successfully overcome
by incorporating a Si:C Schottky-barrier
enhancement layer [4] or by using sulfursegregation
at the NiGe/Ge interface
to de-pin the Fermi level away from
the valence band edge [5]. However,
the illumination incident into the MSM
photodetectors may be sensitive to
the dimension of interdigitated metallic
electrodes that acts as a one-dimension
diffraction grating.
The interdigitated structure acted as the
metallic electrodes and a one-dimensional
(1D) metallic rectangular grating above the
Ge active region. The measurements were
operated at near-infrared wavelength of
1.55 µm under transverse magnetic (TM)
mode, because TM mode is more sensitive
to diffraction grating than transverse
electric (TE) mode [6]. A relatively low
dark current was observed due to an
effective hole barrier modulation by the
Si:C Schottky barrier layer. Based on the
optical near-field simulation, we analyzed
the relationship between photocurrent
and optical energy confined inside the
Ge region, demonstrating the diffraction
effect induced by the metallic grating.
Figure 1 shows a schematic structure
of the Ge-on-SOI MSM photodetector
proposed in this work. The device was
fabricated on an 8-inch SOI wafer with
a 2 µm thick buried oxide. Dry etching
was used to form a Si waveguide 220
nm in thickness and 500 nm in width.
After active window definition, a pure
Ge film with ~500 nm thickness was
allowed to grow in an ultra-high vacuum
chemical vapor deposition (UHVCVD)
reactor. A thin silicon-germanium buffer
was adopted to reduce the formation
of misfit dislocations by minimizing
the lattice mismatch between the two
heterostructure materials [4]. A crystalline
Si:C interfacial layer of ~20 nm was then
deposited on the Ge region to act as a
Schottky barrier enhancement layer
for effective dark current reduction.
Subsequently, the SiO 2
passivation layer
of 400nm was deposited and selectively
dry etched to form contact hole. The
metallization comprising of aluminum (Al)
was deposited and patterned to complete
the device fabrication.
Figure 1(a) depicts the top-view scheme
of the interdigitated electrodes that
formed a 1D metallic rectangular grating
as shown from the cross-sectional
viewpoint [Figure 1(b)]. The groove depth
was having the same thickness of Al
layer, which was fixed at 400 nm in this
experiment. The finger width, spacing and
periodicity were indicated by w, s, and Λ=
w + s, respectively. Figure 2 shows the
Figure 2: Top-view SEM image of the Ge-on-
SOI MSM photodetector featuring interdigitated
electrodes with an effective device width W of 25
µm and length L of 50 µm.
To date, there are only few studies focusing
on this issue and our aim is to study the
effect of the electrode diffraction grating
in Ge Schottky MSM photodetectors on
SOI substrate by varying the electrode
periods from 1.7, 1.8, to 1.9 µm. Higher
responsivity in MSM photodetectors
indicate higher noise margin, wider
allowance for smaller device design and
also the elimination of amplifier.
Figure 1: Schematic illustration of the Ge-on-
SOI MSM photodetector with interdigitated
metal electrodes. (a) Top view of the
interdigitated fingers. (b) Cross-sectional view
of the device structure.
top-view scanning electron microscopy
(SEM) image of our fabricated Ge-on-SOI
MSM detector structure with an effective
device width W of 25 μm and a length L
of 50 μm, respectively. Due to a difference
in the refractive index between Si and Ge,
the incidence photon traveling in the Si
waveguide would be up-coupled into the
Ge region for absorption.
The photoresponse characteristics of the
Ge-on-SOI MSM photodetectors were
www.ime.a-star.edu.sg
microE Bulletin | Issue 3 October 2009 11

R&D News
By comparing Figure 5(a) with 5(b), the
measured photocurrent showed good
consistency with the simulated optical
energy. The extent of confinement
and resonant quality factor due to the
diffraction effect was shown to exhibit
strong dependence on the finger width
geometry, which in turn resulted in a
difference in the photon absorption. During
the process of simulation, we assumed
there were no optical absorption by the
Ge layer so that we could estimate the
optical energy inside the active region.
Figure 3: Photoresponse characteristics of a Ge-on-SOI interdigitated MSM photodetector with finger
width w of 1.2 μm and spacing s of 0.6 μm. The optical measurement was performed by injecting a
TM-mode incident electromagnetic (EM) wave with a wavelength λ of 1.55 μm into the Si waveguide
and coupled into the Ge active region for absorption. The responsivity of the detector was calculated by
subtracting the waveguide transmission loss of ~3.5 dB/cm and a coupling loss of ~4.5 dB.
plotted in Figure 3. The devices were
featuring w of 1.2 μm and s of 0.6 μm. At
an applied bias of 1.0 V, a low dark current
of 0.5 μA (0.4 nA/μm²) was measured.
This measurement was below the typical
1.0 µA generally considered to be the
upper limit for high speed receiver design
and consistent with the previous reported
value on MSM devices [3]. The optical
measurement was performed by injecting
a TM mode incident electromagnetic
(EM) wave with a wavelength λ of 1.55
µm into the Si waveguide and coupled
into Ge active region for absorption. The
incidence light power was estimated
to be ~1 mW. At an applied bias of 1 V,
the photocurrent was measured to be
~1.51 mA. The responsivities were well
demonstrated to be over 1 A/W.
Figure 4: The normalized distribution of magnetic
field under TM mode in a photodetector with finger
width w of 1.2 µm and spacing s of 0.6 µm.
12 Institute of Microelectronics
In order to evaluate the effect of the
electrode diffraction grating on the
response performance, the spatial
distribution of the magnetic field in the
structure based on the Finite-Difference
Time-Domain method was calculated as
shown in Figure 4, for a detector with a
w of 1.2 μm and s of 0.6 μm. It was noted
that the optical field appeared to be locally
concentrated beneath the electrodes
attributed to the diffraction grating effect
of metallic electrodes.
To further confirm the impact of the
metallic grating, we compared the
measurement and simulation results
for samples with varied electrode width
w of 1.2, 1.3, and 1.4 µm (period Λ
corresponding to 1.7, 1.8, and 1.9 µm)
under TM modes, as shown in Figure 5(a)
and 5(b). The spacing width s was fixed
at 0.5 μm to maintain the same lateral
spacing between the two adjacent fingers.
The other structural parameters such as l
and g (refer to Figure 1) were designed
to ensure the same order dark current
density. Photocurrent measurements
were performed at an applied bias of
1 V. In Figure 5(b), we integrated the
optical energy localized in the whole Ge
active layer for these three dimensions.
Figure 5: Effects of the electrode diffraction
grating on the detector’s photoresponse. (a) is the
photocurrent measurement results at an applied
bias of 1 V. (b) shows the calculated optical energy
confinement within the Ge region.
In summary, Schottky interdigitated
Ge-on-SOI MSM photodetectors with
various finger width were fabricated
with low dark current leakage. The
photoresponse exhibited strong
dependence on the finger width geometry,
and showed good consistency with
the numerical simulation. The results
imply that the occurrence of optical
energy localization beneath the metallic
electrodes is beneficial to achieve
higher photoresponse, which allows
simultaneous achievement of high-speed
response and sufficient responsivity in a
small semiconductor element.
References
[1]
[2]
[3]
[4]
[5]
[6]
R. A. Soref, Proc. IEEE, 81(12), 1687
(1993).
J. Oh, S. Csutak, and J. C. Campbell, IEEE
Photon. Technol. Lett., 14, 369 (2002).
K. W. Ang, S. Zhu, M. Yu, G. Q. Lo, and
D. L. Kwong, IEEE Photon. Technol. Lett.,
20(9), 754 (2008).
K. W. Ang, S. Y. Zhu, J. Wang, K. T. Chua,
M. B. Yu, G. Q. Lo, and D. L. Kwong, IEEE
Elect. Dev. Lett., 29(7), 704 (2008).
K. W. Ang, M. B. Yu, S.Y. Zhu, K. T. Chua,
G. Q. Lo, and D. L. Kwong, IEEE Elect.
Dev. Lett., 29(7), 708 (2008).
A. S. Vengurlekar, Optics Lett., 33, 1669
(2008).

Efficient silicon-based light
source could enable full
monolithically integrated photonic
circuits leveraging on Si-CMOS
technology [1-7]. However, the brightness
of light emission from silicon-based
materials is insufficient due to the low
radiative recombination efficiency in the
indirect-gap system. As an alternative
approach, the Photonics team in IME
designed and fabricated triangularlattice
airhole photonic crystal patterns
in the silicon rich oxide (SRO)/SiO 2
multilayer stacks to improve the light
extraction by providing a convenient
way of redistribution the light energy
in desired form and orientation
[8-13]. As a result, the intensity and
profile of spontaneous emission
were found to be efficiently modulated
by controlling the optical modes via
varying the structural dimensions
of photonic crystals. With lattice
constant/radius of 700 nm/280 nm, the
roomtemperature photoluminescence
intensity was enhanced up to ~9 times in
the vertical direction. The mechanisms for
different enhancement features have also
been theoretically analyzed based on
coherent scattering and quantum
electrodynamic effects, well consistent
with the experiment observation.
R&D News
Light Extraction Improvement from
Si-based Multilayers with Photonic
Crystal Patterns
Dr. Yu Mingbin
Member of Technical Staff, Nano-
Electronics and Photonics Programme
Dr. Ren Fang-Fang
Senior Research Engineer, Nano-
Electronics and Photonics Programme
Figure 1: (a) Schematic diagram of the
3D-confined structure. (b) X-TEM image of
the active region composed of ten periods
of SRO/SiO 2
multiple quantum well. (c) SEM
top view of a 2D triangular-lattice air-hole
photonic crystal (PC) geometry.
(100) by plasmaenhanced chemical vapor
deposition (PECVD) system using SiH 4
and N 2
O as the source gases. Figure 1(b)
shows the cross-sectional transmission
electron microscopy (X-TEM) of the
SRO (~12.9nm)/SiO 2
(~13.1nm) MQW
layers. As shown in Figure 1(c), the
top-view image of scanning electron
microscope (SEM) exhibited the exact
regular 2D triangular-lattice air-hole PC
geometry, which was fabricated by dry
etching of the upper cladding down
through the entire active region with the
etching depth of h = 300 nm. The lattice
constant and the radius were labeled as a
and r, and thus the duty cycle of air holes
was described as 2πρ 2 √¯3 , here ρ = r / a .
Two groups of PC patterns (A-B and
C-E) were fabricated and tested with
various lattice constants and duty cycles,
as listed in Table I. All fabricated samples
were annealed at 900 o C for 30 minutes
in N 2
-ambient to enhance the internal
light emission efficiency.
The photoluminescence (PL) spectra
were collected at room temperature using
a Renishaw Micro-PL system with the
excitation source of He-Cd laser (325 nm)
and the incident power of ~1 mW. The light
emissions were recorded for wavelength
of 400-900 nm by the liquid-N 2
cooled
CCD system in the vertical direction
through the microscope. Figure 2 shows
the PL emissions from the patterned
regions A-E, and from an unpatterned
region as reference. To illustrate the
enhancement features, the PL intensities
have been normalized to the effective
area of the active material (1 – 2πρ 2 √¯3) for
each pattern. The light emission around
620 nm dominated the spectrum of the
unpatterned region and appeared in the
patterned areas without discernable shift,
which was originated from the vertical
quantum confinement effect in the MQW
layers. The significant enhancements of
light emissions were observed around
720 nm from all the patterned regions,
but the enhancement magnitudes and
peak positions were strongly dependent
on the lattice constants and duty cycles.
Figure 1(a) shows the schematic of the
patterned structure. The upper and lower
claddings were Si 3
N 4
and SiO 2
with
thickness of 50 and 150 nm, respectively.
A 10-period thin SRO/SiO 2
multilayer
stack acted as the light emitting source
with vertical quantum confinement in
SRO well layers. These multilayers were
deposited sequentially on silicon substrate
Table 1: Structural parameters of patterns A-E
microE Bulletin | Issue 3 October 2009 13

R&D News
Especially, for the pattern E with a=700
nm and ρ=0.40, the spectral integrated
PL intensity in the vertical direction was
boosted up to 9 folds, indicating that such
2D PC arrays had a large impact on the
output of the spontaneous emission. The
exact origin of such enhancement features
Figure 2: PL spectra recorded in the vertical
direction at room temperature for patterns A-E
and an unpatterned region.
could be well explained theoretically
based on the band structure modulation
of 2D PC slabs.
In this study, a non-linear equation
method based on plane-wave expansion
was employed to calculate the band
structures of PC patterns [14-16]. Here,
only the results for pattern E (a=700 nm,
ρ=0.40) is shown in Figure 3.
Figure 3: The photonic band diagrams for phonic
crystal slabs with pattern E (a=700 nm, ρ=0.40).
Results
As shown in Figure 2, the PL intensities
from patterns with a=700 nm (C, D and
E) were much stronger than those from
patterns with a=400 nm (A and B), which
indicated that the enhancement factor
of emission was primarily influenced by
the variation of lattice constant rather
than duty cycle in the tested range. In the
case of pattern E (a=700 nm, ρ=0.40), the
PL peak around 694 nm corresponded to
the normalized frequency a / λ = 1.0, near
the ρ point of the TE-like leaky conduction
band (indicated by arrow) in Figure 3. The
light generated thus strongly coupled with
the high-Q (quality factor) leaky modes [8]
and eventually escaped into free space
from the slab in the vertical direction
[13, 15]. Based on the same mechanism,
PL intensities of the regions with patterns
C (a=700 nm, ρ=0.25) and D (a=700 nm,
ρ=0.35) were also greatly improved. As
for patterns A (a=400 nm, ρ=0.35) and
B (a=400 nm, ρ=0.40), the PL intensities
exhibited about 2 -3× enhancement over
the reference, mainly within the range
of 550-800 nm. The corresponding
optical modes of PC slab move to the
lower normalized frequencies from about
0.5 to 0.73 due to the smaller constant
lattice compared with C, D and E, which
overlapped with the photonic band gap
(PBG) region and the TM-like resonant
radiation band (not shown).
We therefore speculated that the
enhancement in this case was mainly due
to two possible mechanisms. First of all,
since the lateral propagation of guided
modes in PBG region was prohibited
in the slab, light generated could only
radiate in the vertical direction, which
was described as the redistribution of
saved energy by PBG effect [17]. Secondly,
the light emission corresponding to
TM-like guided modes was folded to
high-Q resonant radiation modes at
the Brillouin zone boundaries by phase
compensation from a reciprocal lattice
vector, thus leading to higher external
quantum efficiencies [10]. The relatively
small enhancement factor observed was
partially due to the inhibition of
recombination of excited carriers in the
in-plane direction by PBG effect [13].
With the radius of air hole being increased
from C, D to E, the significant PL peak
exhibited blue-shift from 750 to 694
nm. Similar phenomena also occur in
the cases of patterns A and B. That was
because the effective refractive index of
PC slab decreased with the increasing
of duty cycle while maintaining the
lattice constant and slab depth, which
consequently resulted in the blue-shift
of photonic band structures [15]. When
the value of ρ was reduced down to 0.25
in pattern C, the states around K point
lying in the conduction band would fall
outside the light cone and become guided
modes, which might be responsible for
the smaller enhancement compared with
D and E.
Although the active material was partially
removed by the dry etching process,
spontaneous emission could also be
compensated through two beneficial ways
dominated by quantum electrodynamic
effects. The first was the so-called Purcell
spontaneous emission rate enhancement
occurring in the wavelength-size cavities
of PC, due to the high quality factor
and small mode volume [16]. The second
was the redistribution of pump energy in
the active region. As an example, we
calculated the electromagnetic (EM) field
distribution of pump light (325 nm) in the
plane of h/2 for the sample with pattern
E, based on the Rigorous Coupled
Wave Analysis (RCWA) method [18]. The
image had been chosen as the cover
image for Applied Physics Letters (Vol. 93,
Issue 9) (Figure 4). From the electric and
magnetic fields distribution, we could
clearly notice that most of the energy was
concentrated in the dielectric material
region outside the air holes, thus provide
Figure 4: The normalized electric and magnetic field
intensity distribution of excitation incidence (325
nm) in the plane of h/2 for the sample with pattern
E. This was published on the cover page of Applied
Physics Letters (Vol. 93, Issue 9).
14 Institute of Microelectronics

R&D News
magnified pump power intensities for
spontaneous emission.
Starting from 2006, the Photonics team
made significant progress in Si-based
light emission (as shown in Figure 5).
Good PL and EL (Electroluminescence)
performance from amorphous Si and
PL from erbium (Er) doped materials
were demonstrated over the visible or
infrared communication wavelength
range, which provide a potential platform
for the integrated solution application.
Figure 5: IME Roadmap for Si and Er based Emission
References
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
L. T. Canham, Appl. Phys. Lett. 57, 1046 (1990).
A. Polman, Nat. Mater. 1, 10 (2002).
R. J. Walters, G. I. Bourianoff, and H. A. Atwater, Nat. Mater. 4, 143
(2005).
I. Bineva, D. Nesheva, Z. Aneva, and Z. Levi, J. Lumin. 126, 497
(2007).
W. K. Tan, M. B. Yu, Q. Chen, J. D. Ye, G. Q. Lo, and D. L. Kwong,
Appl. Phys. Lett. 90, 221103 (2007).
A. Morales-Sánchez, J. Barreto, C. Domínguez-Horna, M. Aceves-
Mijares, and J. A. Luna-López, Sens. Actuat. A 142, 12 (2008).
M. H. Wang, D. R. Yang, D. S. Li, Z. Z. Yuan, and D. L. Que, J. Appl.
Phys. 101, 103504 (2007).
M. Boroditsky, T. F. Krauss, R. Coccioli, R. Vrijen, R. Bhat, and E.
Yablonovitch, Appl. Phys. Lett. 75, 1036 (1999).
S. Fan, P. R. Villeneuve, J. D. Joannopoulos, and E. F. Schubert,
Phys. Rev. Lett. 78, 3294 (1997).
[10] A. A. Erchak, D. J. Ripin, S. Fan, P. Rakich, J. D. Joannopoulos, E. P.
Ippen, G. S. Petrich, and L. A. Kolodziejski, Appl. Phys. Lett. 78, 563
(2001).
[11] J. Y. Kim, M. K. Kwon, K. S. Lee, S. J. Park, S. H. Kim, and K. D. Lee,
Appl. Phys. Lett. 91, 181109 (2007).
[12] S. H. Kim, K. D. Lee, J. Y. Kim, M. K. Kwon, and S. J. Park,
Nanotechnology 18, 055306 (2007).
[13] H. Y. Ryu, Y. H. Lee, R. L. Sellin, and D. Bimberg, Appl. Phys. Lett. 79,
3573 (2001).
[14] D. S. Gao and Z. P. Zhou, Appl. Phys. Lett. 88, 163105 (2006).
[15] S. G. Johnson, S. Fan, P. R. Villeneuve, J. D. Joannopoulos, and L. A.
Kolodziejski, Phys. Rev. B 60, 5751 (1999).
[16] M. Boroditsky, R. Vrijen, T. F. Krauss, R. Coccioli, R. Bhat, and E.
Yablonovitch, J. Lightwave Technol. 17, 2096 (1999).
[17] S. Noda, M. Fujita, and T. Asano, Nat. Photonics 1, 449 (2007).
[18] E. Noponen and J. Turunen, J. Opt. Soc. Am. A 11, 2494 (1994).
www.ime.a-star.edu.sg
microE Bulletin | Issue 3 October 2009 15

Industry
Collaboration
Bell Laboratories, Alcatel-Lucent
Bell Laboratories began to work with IME in September 2008 to
realize a siliconbased coherent optical receiver on a single chip.
Dr. Young-Kai Chen
Director of High
Speed Electronics and
Optoelectronics Research,
Bell Laboratories
On 15 th June 2009, the Institute of Microelectronics and
Bell Labs, the central research and development division
of Alcatel-Lucent, signed a research collaboration
agreement to jointly develop advanced photonics technology
for next generation cost-effective high data-rate communication
networks. The Editorial Team took this opportunity to interview
Dr. Young-Kai Chen, Director of High Speed Electronics and
Optoelectronics Research at the Bell Laboratories on his vision
for the project and the partnership.
“The joint research project with IME is to investigate advanced
silicon photonic circuits. Silicon photonic circuit is a low cost and
high functionality solution for future optic fiber communication
systems to transport high capacity data and multi-media
contents. The CMOS fabrication technology today is able to
delineate features with dimensions below the commonly used
wavelengths in optical communications. It will be promising to
integrate the optical elements on the CMOS electronics platform
for added intelligence and functionalities at a lower cost.” said
Dr. Chen.
He continued, “Bell Laboratories is exploring several areas to
provide our customers with cost effective infrastructure products
for optic fiber data links and fiber at their homes. Our initial
objective was to explore the speed limit of the silicon photonics
technology and we achieved the next generation optic fiber
communications at 100 Gb/s. This result is very promising as
it enables many new applications in delivering high speed data
and multimedia contents to our customers in a “green” and cost
effective manner.”
“The result is amazing.” Dr Chen disclosed, “The team achieved a
world-record data rate of 112 Gb/s which is ten-times faster than
the current optical receivers being used in today’s back-bone
optic fiber networks. The device integrates many functions
such as polarization beam splitter, precision optical mixers
and balanced photodetector array on a single chip to receive
and decode received optical signals with complex modulated
signaling format.” The record is reported in the post-deadline
session of the Optical Fiber Communication Conference in April
2009 and Bell Laboratories is continuing to work with IME to
investigate new silicon photonic devices and circuits as well as
to explore the manufacturing capability of the technology in the
next phase of the collaboration.
On the working relationship with IME, Dr. Chen revealed, “We are
aware of IME’s offerings in silicon photonics foundry. IME has
excellent semiconductor researchers and fabrication facilities
which have successfully powered Singapore’s semiconductor
industry over the past few decades. Their close collaborations
with the local foundries are definitely a very good path for future
ramp up in manufacturing for our joint project.” Dr. Chen went
on, “Researchers at IME provide excellent knowledge and
timely feedback on our proposed advanced components and
processes such that we have fully functional devices and circuits
from the first pass of the fabrication. We are very impressed by
the “can-do” attitude of IME’s researchers. Despite the 12-hours
difference between our time zones, we were able to carry our
conference calls in late evenings and even weekends on both
sides and got the problem resolved within 24 hours.”
“This successful research collaboration with IME has
demonstrated and realized many advantages of our open
research initiative at Alcatel-Lucent. By leveraging on the global
expertise of the joint Bell Labs-IME team, we are able to carry
out state-of-the-art research in a timely and effective manner.
Bell Laboratories is very pleased to participate in developing the
next generation silicon photonics technology in Singapore.”
16 Institute of Microelectronics

Industry
Collaboration
Unisantis Electronics (Japan) Ltd.
We at Unisantis are now engaged in the prototyping of
Surrounding Gate Transistor (SGT) with IME. The collaboration
with IME aims to develop the basic process technology of SGT
and to overcome the limitations of existing planar technology
(as defined by Moore’s Law) by shrinking the chip size. This will
be realized by shrinking the occupied area of the transistor and
creation of an integrated circuit using such three dimensional
transistors. With IME’s technical expertise in integrated circuits
and their excellent integrated process capabilities, I am confident
of achieving our mission.
Q: What are the results of the collaboration and how
will this invention change or impact end users?
Professor Fujio Masuoka
Chief Technology Officer,
Unisantis Electronics (Japan) Ltd.
Unisantis Electronics (Japan) Ltd., is part of Newscope
Group Holdings AG. The NewScope Group is a science
and innovation driven conglomerate with widely diversified
individual technology businesses and activities including
design, research, development, manufacturing, marketing, and
supplying innovative products. Unisantis Electronics (Japan) Ltd
was established in 2004 and, under the leadership of its CTO
Professor Fujio Masuoka, is engaged in the development of a
new three dimensional (3-D) transistor called the Surrounding
Gate Transistor (SGT).
In Dec 2007, Unisantis Electronics and IME inked a research
collaboration agreement to jointly develop the SGT in Singapore,
marking the beginning of the 24 months journey aimed at
transforming the technological world. In this month’s exclusive
interview, MicroE editorial team takes you behind the scene of
the development of the world’s first 3-D transistor with the man
behind this astonishing invention, Professor Fujio Masuoka.
Q: What are the motivating factors for the project
collaboration?
Prof. Masuoka: The Semiconductor industry has grown with
“micronization” over the past 50 years and it is well known and
acknowledged that “micronization” will soon reach its physical
limits. I believe that a structural change of the transistor from
planar to three dimensional will provide a solution to this
challenging issue.
Prof. Masuoka: I am pleased and proud that the collaboration
team is progressing much ahead of their schedule and will be
embarking on the new phase of the collaboration with IME
for further development of SGT technology. I believe that our
collaborative efforts with IME will take successful shape and will
bring plenty of chances to generate inventive patents related
to SGT. We are also calling out to all capable and ambitious
researchers to join us and be part of the team responsible in
changing the world with SGT.
The industry is poised to experience a major milestone upon
successful completion of the project. The SGT will create a
global impact and will change the way many technologies work.
First and foremost, SGT will enable higher processing speeds
and higher image resolution on computers. Researchers will be
able to carry out most of their work on their own workstations in
real time instead of depending on advanced computing facilities.
With increased speeds, SGT can be used to screen new drugs
for life threatening diseases in Biomedical research, to achieve
faster and accurate mapping of DNA in Genome Research,
for faster generation of weather forecasting models in Climate
research, and to attain complex designs in the Aircraft and
Automobile industries. The potential applications of SGT are vast
and boundless.
Q: How was your experience in the collaboration
with IME?
Prof. Masuoka: The IME research team has lived up to the
challenges of this unique development and had consistently
contributed at a superior level throughout the course of the joint
project. From the planning to the development stage, the IME
team has demonstrated their high enthusiasm and passion in the
development of the SGT. I am very pleased and satisfied with
their work, attitude, excellent skill levels and cooperation.
www.ime.a-star.edu.sg
microE Bulletin | Issue 3 October 2009 17

People
IME is indeed an excellent training
place for researchers and engineers
specializing in semiconductor
research.
Zhao Hui
a former PhD student attached to IME.
Graduated recently from the National University of
Singapore (NUS), Zhao Hui is one of the pool of students
who have pursued their PhD project in a research
institute through A*STAR research attachment programme. She
was attached to IME’s Nano-Electronics & Photonics (NanoEP)
Programme for three years under the Joint Microelectronics
Laboratory (JML) scheme from the Department of Electrical and
Computer Engineering.
When the editorial team caught up with the young post graduate,
she was all perky and excited about the interview. The bubbly
graduate was fast to get down to the interview and quipped, “The
attachment opportunity in IME was arranged by my university’s
supervisor but the main motivation factors for me were its first
class facilities and expertise in the field of nanofabrication.”
Zhao Hui recently joined one of the largestelectronic design
automation (EDA) company for IC industry, Synopsys, as a
Corporate Application Engineer. Looking back on her attachment
in IME, she said, “I had gained and picked up important technical
knowledge from my attachment in IME. I was given opportunities
to propose and test out my ideas through experiments with the
comprehensive facilities in the institute. These had given me
invaluable hands-on experience of the equipment and processes
in nano device fabrication.”
Zhao Hui was working on the design, fabrication and characterization
of Nanowire devices during her attachment. “I
had simulated, designed, and fabricated the test keys for
femto-farad nanowire capacitance measurement. The fabricated
devices were used for measurement of current and capacitance.
Series resistance and carrier mobility were then extracted for
further device study”, she disclosed. Under the guidance of Dr.
Subhash, Zhao Hui’s research work on “CBCM Measurement of
Femto-Farad Nanowire Capacitance” was published in IEDM
2008. This is the first demonstration of a single channel silicon
nanowire capacitance and mobility extraction. “It provides a very
simple and innovative approach to measuring extremely small
capacitances accurately. I am very proud and pleased of the
result and I want to thank the team for their contribution”, Zhao
Hui continued.
”My supervisor at IME was Dr. Subhash Chander and I could
not wish for any better or friendlier supervisor than him. Apart
from his expertise in modeling and characterization, he is
also a very patient and bighearted mentor. His generosity in
sharing his knowledge and patience helped me most during
my attachment. As a very hands-on person, he would sit down
with us to brainstorm, whenever we experience any difficulties
in the research work. Through his guidance, I learnt that to be
an outstanding researcher, apart from overcoming the technical
challenges, it also involving prioritizing, working in a team and
managing stress. I am extremely fortunate to work with IME and
Dr. Subhash over the past 3 years. It is an experience I would
cherish forever.”
18 Institute of Microelectronics

People
Similarly, Jiang Yu, a former PhD student from the Electrical
and Computer Engineering department, National University
of Singapore, was attached to IME for her research work,
through the A*STAR Joint Microelectronics Laboratory scheme.
She was attached to IME’s Nano-Electronics & Photonics
(NanoEP) Programme, under the mentorship of Prof. Kwong
Dim-Lee.
Known as a pleasant and outstanding student, Jiang Yu’s
research focus was on exploring solutions for advanced high
performance nanowire transistors. On her view about IME,
Jiang Yu commented, “IME possesses advance research and
semiconductor device fabrication facilities. It is full of experts and
senior engineers in many diverse research fields. The research
atmosphere in IME is very active. The environment promotes
constructive discussions between fellow attached students and
its research staffs. The research topics offered by IME are both
attractive and interesting and the focus on staying relevant to
the industry brings significant worth to researchers’ work and
publications. IME has a conducive environment for students to
learn and the opportunity to work as part of the team.”
During her attachment, Jiang Yu had presented 4 papers in
prestigious international conferences. Of these, 2 papers were
published in VLSI 2008 and IEDM 2008, the top conferences in
her research field. One of her papers was awarded the Maruban
Foundation Award in SSDM 2007, while another was selected as
one of the technical highlights in SSDM 2008. Jiang Yu has filed
a patent for high speed SiGe nanowire transistors.
On her mentor, she said, “Prof. Kwong was a really nice supervisor
to work with. I remember the first time I met Prof. Kwong. He
was very friendly and provided many valuable suggestions and
options on the selection of my research topic. He wanted me to
know and understand my options before making a choice. I am
very grateful to him as I was able to work on a research topic that
I had keen interest in. This approach enticed my commitment to
the research. On top of that, Prof. Kwong encouraged me to read
at least one journal paper each day, which he practices despite
his busy work schedule. He trained my analytical skills and my
ability to work independently.”
“IME had prepared me well for a career in R&D. The institute has
many experts in the different research fields and I was always
able to find experts like Dr. Patrick Lo, Dr. Navab Singh and
many other module engineers to discuss my work at the different
stages of my research. Besides technical, I learned to work in a
team. I would not have gained such valuable experiences from
the university environment. IME has indeed helped in preparing
me for the R&D workforce.”
Jiang Yu is currently a researcher with Unisantis Electronics
(Japan) Ltd., one of IME’s most valuable R&D partners. IME and
Unisantis are in a partnership to jointly develop the Surrounding
Gate Transistor (SGT) in Singapore and Jiang Yu is part of the
team working on the project.
Jiang Yu shared further, “My goal is to become a world-class
researcher and I hope to be able to contribute significantly in the
field of semiconductor devices.”
The research atmosphere in
IME is really active and promotes
constructive discussions between
fellow attached students and its
research staffs.
Jiang Yu
PhD graduate from NUS
Successful Master/PhD applicants with NTU or NUS as well as AGS scholars who are
interested to conduct their graduate research work in our young and vibrant research
atmosphere, please write to uni-collaboration@ime.astar.edu.sg.
microE Bulletin | Issue 3 October 2009 19

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