The System Manual of SOL-20 - History of Computers
The System Manual of SOL-20 - History of Computers
The System Manual of SOL-20 - History of Computers
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PROCESSOR TECHNOLOGY CORPORATION<br />
Sol THEORY OF OPERATION<br />
SECTION VIII<br />
an eight-line parallel output port, an eight-line sense switch logic<br />
input port, and a unidirectional eight-line internal data bus.<br />
<strong>The</strong> use <strong>of</strong> a unidirectional (input) data bus accommodates<br />
Sol's internal low-drive memory and I/O devices that do not meet the<br />
heavy drive requirement <strong>of</strong> the bidirectional data bus. <strong>The</strong> low-drive<br />
requirement <strong>of</strong> the internal bus also allows using the tri-state capabilities<br />
<strong>of</strong> the UART's (Universal Asynchronous Receiver/Transmitter)<br />
in the serial and audio cassette I/O circuits without additional<br />
drivers.<br />
All CPU data and address lines are buffered through tri-state<br />
drivers to support a larger array <strong>of</strong> memory and I/O devices than<br />
would otherwise be possible with the 8080 output drive capability.<br />
Data input to the CPU is selected by a four-input multiplexer from<br />
the Keyboard Port, Parallel Port, Bidirectional Data Bus and Internal<br />
Data Bus. <strong>The</strong> Internal Data Bus is the source <strong>of</strong> all data input to<br />
the CPU from Sol's internal memory, the serial interface and the<br />
cassette interface. <strong>The</strong> Bidirectional Data Bus is the source <strong>of</strong> all<br />
data fed to memory and I/O, both internal and external. It is also<br />
the source <strong>of</strong> data input to the CPU from eight internal sense switches<br />
as well as from external memory and I/O.<br />
8.3 BLOCK DIAGRAM ANALYSIS, Sol-PC<br />
8.3.1 Functional Elements And <strong>The</strong>ir Relationships<br />
As can be seen in the Sol block diagram on Page X-24 in Section<br />
X, timing signals for Sol are derived from a crystal controlled<br />
oscillator that produces a "dot clock" frequency <strong>of</strong> 14.31818 MHz.<br />
(This frequency, four times that <strong>of</strong> the NTSC color burst, provides<br />
compatibility with color graphics devices.) <strong>The</strong> dot clock is applied<br />
directly to the Video Display Generator circuit and divided in the<br />
Clock Generator to provide φ1, φ2 and CLOCK. CLOCK synchronizes all<br />
control inputs to the 8O8O; φ1 and φ2 are the nonoverlapping, two<br />
phase clocks required by the 8O8O.<br />
Memory internal to the Sol is divided between 2K <strong>of</strong> ROM (Read<br />
Only Memory), 1K <strong>of</strong> <strong>System</strong> RAM (Random Access Read/Write Memory) and<br />
1K <strong>of</strong> Display RAM. <strong>The</strong> ROM permanently stores the instructions that<br />
direct the CPU's activities. (To enhance Sol's versatility, this<br />
particular memory is on a plug-in "personality module". Thus, Sol<br />
can be easily optimized for a particular application by plugging in a<br />
personality module that contains a s<strong>of</strong>tware control program designed<br />
for the task. <strong>The</strong> CON<strong>SOL</strong> and <strong>SOL</strong>OS programs, which are described in<br />
Section IX, are examples <strong>of</strong> such personality modules.) Display RAM<br />
stores data for display on a video monitor, and the <strong>System</strong> RAM provides<br />
temporary storage for programs and data. All memories are addressed<br />
on the Address Bus (ADR0-15) and, except for the Display RAM,<br />
input data to the CPU on the Internal Data Bus (INT0-7). Data entry<br />
into both RAM's is done on the Bidirectional Data Bus (DIO0-7).<br />
VIII-3