The System Manual of SOL-20 - History of Computers

PROCESSOR TECHNOLOGY CORPORATION
Sol THEORY OF OPERATION
SECTION VIII
Assume VDISP is active (low), which it is during the vertical
display portion of the displayable area on the screen. (Refer to
Figure 8-4.) U62 is then preset to a count of 0 and will count from
0 through 15 (16 character rows). The resulting carry output on
count 15 of the Text Counter causes the U43 VDISP flip-flop to toggle.
It also appears as a low on the load input of the Text Counter. The
Text Counter is also enabled to reset by virtue of the OVERFLOW_LINE
going low after the reset of the Scan Counter. Since VDISP is now
high, the Text Counter is reset to a count of 12 and will count 12
through 15 (four character rows). The carry output from the Text
Counter then causes the U43 VDISP flip-flop to toggle, and the Text
Counter is reset to a count of 0. We can now see that the Text Counter
counts 16 character rows when the display is active (VDISP is low)
and four character rows when the display is blanked (VDISP is high).
The total of 20 character rows represents a full display of 260 scan
lines for 60 Hz operation (13 scan lines/row x 20 rows = 260 scan
lines per page).
Horizontal and vertical synchronization signals are generated
by two one-shot multivibrators consisting of three two-input NOR gates
in U102. Horizontal sync is triggered by SCAN_ADVANCE and vertical
sync by !VDISP. Both circuits generate fixed-length sync pulses with
adjustable starting times. C52 determines the length of the horizontal
sync pulse and C53 the length of the vertical sync pulse. The
starting times, with respect to triggering, are variable with variable
resistors VR1 (HORIZ) and VR2 (VERT) to provide continuous
adjustment of the display position on the screen. An exclusive OR
gate in U74 combines the two sync pulses into a composite sync (COMP_
SYNC) signal. Note that the use of the exclusive OR inverts the horizontal
sync pulses when the vertical sync pulse appears. Since
vertical sync information is extracted in a monitor by an integrating,
or averaging, process, this technique maintains horizontal synchronization
during the vertical sync period.
Two types of blanking are available: control character blanking
and video blanking. The first blanks control characters and
causes cursor information to be displayed in their place. Video blanking
forces portions of the video display to a white or black level,
depending on whether normal or reverse video is selected with S1-4.
Control character blanking, switch selectable with S1-3, is
accomplished with one NAND gate in U60 and one NAND gate in U61.
When a control character is present in the Data Latch (U26 and U27),
pins 3 and 15 of U26 are high. Assuming the blanking option is selected
(S1-3 closed), the output of U60 (!LOAD_CLOCK) is gated with
the control character bits by U61 to clear the video parallel-toserial
converter, U41. U41 then loads all zeros instead of the
character.
Video blanking is initiated by the PRE_BLANK or COMP_BLANK
(pin 14 of Blank Latch U42) inputs to U59, a three-input NOR gate.
The third input, the video output on pin 6 of exclusive OR gate U74,
is blanked when any of the two blanking inputs is active.
VIII-26