The System Manual of SOL-20 - History of Computers

PROCESSOR TECHNOLOGY CORPORATION
Sol THEORY OF OPERATION
SECTION VIII
respectively, prevent damage to the logic circuitry in the Input/
Output section due to inductive kickback. R155 and 156 are current
limiters that keep the relay contacts from "welding" together.
When the CDI is in the write mode, data is input to the UART
(U69) under control of !PORT_OUT_FB. Upon completion of this strobe,
the transmit sequence is initiated within the UART, with the transmission
rate being governed by BYTE_WRITE_CLOCK.
The transmission sequence begins with a start bit, a low
(data zero) on the UART's TO output. It is followed by eight data
bits and two stop bits (high on the UART's TO output), with the number
of bits being fixed by the connections to pins 34 through 39 of
U69.
The data from U69 is applied to the D input of D flip-flop
U100 which is clocked at 1200 Hz. Consequently, the output on pin 1
of U100 follows the input data on pin 5 after the rising edge of the
1200 Hz clock. This output is connected to the reset (pin 4) of
U101, so when the data out of the UART is high, the first section in
U101 is forced to a reset condition. In this condition the J and K
inputs to the second stage of U101 are held high which allows the
flip-flop to change state on the rising edge of the clock.
The clock for U101 (OUTPUT_CLOCK) is 2400 Hz in the high
speed mode or 4800 Hz in the low speed mode. This clock is derived
from 2400 Hz in conjunction with the low speed select signal in NAND
gate U98 and exclusive-OR gate U99.
In the high speed mode, pins 12 and 13 of U98 are held low,
thus holding pin 10 of U98 high. As a result the 2400 Hz signal is
inverted in U99 to become the clock for U101.
Pins 12 and 13 of U98 are held high, however, in the low
speed mode to enable U98. In this case R117 and C47 provide a delay
in the U98 gate. When the 2400 Hz signal on pin 2 of U99 changes
state, so does pin 3 of U99. Also, C47 charges through R117 for
several usec, at which point pin 10 of U98 is brought to the opposite
polarity. The output from U99 then goes high. A series of positive
pulses, with a pulse width approximately equal to the R117, C47 time
constant (10 usec) and occuring at every transition of the 2400 Hz
signal, appears on pin 3 of U99. This circuit thus operates as a
frequency doubler in the low speed mode to provide a 4800 Hz clock
for U101.
The 2400 Hz signal from which the U101 clocks are derived also
produces the 1200 Hz clock signal for U100. As a result the 1200
Hz signal changes state following a propagation delay after the 2400
Hz signal falls.
VIII-35