May 2013 - I-Micronews
May 2013 - I-Micronews
May 2013 - I-Micronews
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M A Y 2 0 1 3 I S S U E N ° 2 7<br />
E D I T O R I A L<br />
An established platform rescues most<br />
advanced silicon technologies<br />
Dear 3D Packaging readers,<br />
It’s my pleasure to share with you our outlook for the fantastic, long-lasting<br />
potential of a proven Advanced Packaging technology: flip chip.<br />
No doubt you’re wondering why the spotlight is now being shone on this<br />
long-established technology. There are several reasons, two of which are<br />
value and technology. Technology equates to the customer’s perception<br />
of a product’s advantages, be they features, performance or reliability.<br />
Of the three, performance has always been the key decision-making<br />
parameter for consumers, because each new device generation brings<br />
significant speed improvements like calculation, graphical display or data<br />
transfer time. Performance improvement is the outcome of mainstream<br />
semiconductor technology’s node change, and it always carries large<br />
...the opening of<br />
interconnection between<br />
heterogeneous<br />
chips in the same package,<br />
flip chip is the ideal path...<br />
investments. Of course, return on investment is the driving force for<br />
most IC manufacturers -- but going from a 90nm technology node to 32<br />
and beyond requires an increased interconnect need that wire-bonding<br />
simply cannot match. So what could be the way out?<br />
Enter flip chip, which has resurfaced to rescue designers and solve the<br />
technological challenge of linking the sub-20 nanometer gate length to<br />
the millimeter world. With copper pillar pitch reduction allowing for wider<br />
I/O connectivity, and the opening of interconnection between heterogeneous<br />
chips in the same package, flip chip is the ideal path. Moreover,<br />
any Advanced Packaging scheme ends with bumping opening the<br />
door to very large adoption.<br />
Regarding value, flip chip offers the outstanding benefit of being realized<br />
at wafer level, thus significantly reducing manufacturing cost compared<br />
e v e n t s<br />
• Electronic Components and Technology<br />
Conference (ECTC)<br />
<strong>May</strong> 28 to 31, <strong>2013</strong> - Las Vegas, NV<br />
• SEMICON Russia<br />
June 5 to 6, <strong>2013</strong> - Moscow, Russia<br />
• SEMI Networking Day: Packaging - Key<br />
Driver for System Integration<br />
June 27, <strong>2013</strong> - Porto, Portugal<br />
to single chip wire bonding.<br />
I’m confident that by the end of this 3D Packaging issue, you’ll have a<br />
much better understanding of Flip chip’s technology, market and potential.<br />
Christophe Fitamant<br />
Sales & Marketing Director<br />
Yole Développement<br />
fitamant@yole.fr<br />
• SEMICON West<br />
July 9 to 11, <strong>2013</strong> - San Francisco, CA<br />
platinum partners:<br />
3 D P a c k a g i n g 3<br />
For more information, please contact S. Leroy (leroy@yole.fr)