Lock-in Amplifiers

INTEGRATED LOCK-IN
AMPLIFIER
by
MEILI LO, B.S.E.
A THESIS
IN
ELECTRICAL ENGINEERING
Submitted to the Graduate Faculty
of Texas Tech University in
Partial Fulfillment of
the Requirements for
the Degree of
MASTER OF SCIENCE
IN
ELECTRICAL ENGINEERING
Approved
May, 1996

T
I '^'A\^
Kio.M-l
CONTENTS
b./r
r ^
LIST OF FIGURES
CHAPTER
iv
1. INTRODUCTION 1
2. BASIC THEORY OF LOCK-IN AMPLIFIERS 3
2.1 Basic concepts of lock-in recovery 3
2.2 Basic lock-in amplifiers 4
2.2.1 The signal channel 4
2.2.2 The multiplier detector 5
2.2.3 The reference channel 7
2.3 Noise rejection 9
2.4 The implementation of a lock-in amplifier 11
3. THE DETAILED CIRCUIT BEHAVIOR OF LOCK-IN AMPLIFIER 14
3.1 OP amplifier 14
3.1.1 The differential input amplifier stage 16
3.1.2 Output stage 18
3.2 Active resistor 18
3.3 Instrumentation amplifier 19
3.4 Switched capacitor filter 20
3.5 Phase shifl;er 26
3.6 Multiplier 27
4. SIMULATIONS AND ANALYSIS 31
4.1 The result analysis of OP amphfier 31
4.2 The simulation result of instrumentation amplifier 35
4.3 The switched capacitor filters 35
4.4 The multiplier 36
4.5 The simulation results of the whole system 36
5. SUMMARY 59
REFERENCES 63
11

APPENDIX
A. THE OPERATION OF THE OP AMPS 64
B. THE BASIC CONCEPT OF THE ACTIVE RESISTORS 69
C. THE FORMULA REDUCTION OF THE INSTRUMENTATION
AMPLIFIER 72
D. THE SUBCIRCUITS OF THE LOCK-IN AMPLIFIER 74
E. OUTPUT PLOTS 83
111

LIST OF FIGURES
2.1 A general experiment system of lock-in amplifier 4
2.2 A basic lock-in amplifier 5
2.3 Synchronous detector 6
2.4 The implementation of lock-in amplifier 12
3.1 The block diagram of an op-amp 14
3.2 The schematic of the lock-in amplifier 17
3.3 The simple transistor astive resistor 21
3.4 The active resistor 21
3.5 The implementation of Figure 3.4 22
3.6 The instrumentation amplifier implementation by three op-amp 23
3.7 Parallel switched capacitor realization of a continuous resistor 24
3.8 The equivalent circuit of the continuous resistor 24
3.9 Clock waveforms for the switched capacitor 24
3.10 A basic Wien bridge phase shifl:er 29
3.11 The basic circuit of four-quadrant Gilbert multiplier cell 30
4.1 The parameter of MOSIS CMOS 2-|.im N-wdl process 32
4.2 Open-loop mode with offset compensation 33
4.3 A method of measuring open-loop characteristics with dc bias stability 33
4.4 The measurement result of open-loop gain margin by using the circuit
of Figure 4.3 38
IV

4.5 The measurement result of the open-loop gain and phase 39
4.6 Op-amp with only common-mode input voltage 40
4.7 Op-amp with differential-mode input 40
4.8 The simulation result of CMRR 41
4.9 CMRR of instrumentation amplifier 42
4.10 The result analysis of instrumentation amplifier 43
4.11 The frequency and noise response of bandpass filter 44
4.12 The output response of input signal frequency at lOK Hz 45
4.13 The bandpass filter output response of input signal frequency at
lOOKHzand IKHz 46
4.14 The fi"equencyand noise response of lowpass filter 47
4.15 The lowpass filter output response of input signal frequency at IK Hz 48
4.16 The lowpass filter output response of input signal frequency at lOK Hz 49
4.17 The output response of multiplier 50
4.18 The DC transfer characteristics of multiplier 51
4.19 Ac characteristics of multiplier 52
4.20 An input signal and its amplitude modulation 53
4.21 The wideband noise 54
4.22 The recovery signal of Figure 4.21 by the lock-in amplifier 55
4.23 A input signal with high noise (SNR =1:10) 56
4.24 The recovery signal of Figure 4.23 57
4.25 A recovery signal of a wide band noise but high SNR (SNR =1:1) 58

5.1 Block diagram of an extended lock-in amplifier 61
5.2 The two-phase lock-in amplifier 62
A.l Equivalent circuit of Ro 65
A.2 Equivalent circuit of Figure A.1 66
A. 3 The small signal model of folded cascode amplifier 67
A.4 The equivalent output resistance circuit of folded cascode amplifier 67
B. 1 The different linear ranges of active resistance under different Vc 70
B.2 The simulation result of Figure D.6 71
D. 1 Instrumentation amplifier 75
D.2 Bandpass filter 76
D.3 Phase shifter 77
D.4 Multiplier 78
D.5 Lowpass filter 79
D.6 Active resistance 80
D.7 OP amplifier with push-pull as output buffer 81
D.8 OP amplifier with source follower as output buffer 82
E. 1 The measure result of the dc feedback 84
E.2 The open-loop transfer curve and output swing limits 85
E.3 The simulation method of slew rate and setting time 86
E.4 Simulation result of slew rate and setting rate 87
VI

CHAPTER 1
INTRODUCTION
When a signal is obscured by high levels of noise, signal recovery techniques are
necessary to obtain a high quality signal, thus signal recovery instruments play an
important role in modem technology. Of all the techniques that have been developed for
signal recovery, methods based on a phase-sensitive detector and its modern counterpart,
the lock-in amplifier, are by far the most widely applied in all fields of scientific research.
A phase-sensitive detector is responsive to the amplitude of a signal, but is also
sensitive to the phase difference between a signal and the derived reference. Phasesensitive
detector-based systems can, therefore, be devised to measure variations in both
the amplitude and phase of periodic signals in the presence of noise and interference.
Systems using phase-sensitive detectors are called lock-in systems, and the usual way of
introducing a phase-sensitive detector into an experiment is to use a lock-in amplifier. A
lock-in amplifier has come to mean an instrument that incorporates a phase-sensitive
detector, which is supported by preamplifiers, post-detection amplifiers, and a
comprehensive reference processing section[l].
The sensitivity of a lock-in amplifier makes it an exceptionally useful instrument for
extracting signals from noise, even when the noise and signal frequencies are close
together. Lock-in amplifiers are widely used in situations involving low signal-to-noise
ratios. These situations frequently arise when making accurate measurements, such as
displacement, temperature, stress-strain and many others.

Lock-in amplifiers are widely and usefully applied in all fields of scientific research
to obtain of signals from noise. However, most lock-in amplifiers are build as an
instrument or a board instead of single chip. The price of either an instrument or a circuit
board is expensive. For a wide-band lock-in amplifier instrument, the price is around
$4,000 or up. Furthermore, for the purposes of reducing the size of products and the
extra noise caused by signal transmission, the development of integrated lock-in amplifiers
becomes essential.
In this thesis, an analog lock-in amplifier is developed. This lock-in amplifier
consists of an instrumentation amplifier, OP amplifier, active resistor, switch capacitor
filter, phase shifter, and multiplier.
The fundamental theory of the lock-in amplifier will be discussed in Chapter 2.
Also in that chapter, the principles of the "phase sensitive detector, the modulator, and the
demodulator will be introduced, as well as the lock-in amplifier. The circuit design of
each part of the lock-in amplifier will be presented in detail in Chapter 3. All the results of
this lock-in amplifier design will be shown in Chapter 4. Finally in Chapter 5, conclusions
about this design are drawn, and some recommendations are given for further research.

CHAPTER 2
BASIC THEORY OF LOCK-IN AMPLIFIERS
2.1 Basic concepts of lock-in recovery
Lock-in amplifiers are characterized by a wide dynamic range which gives the
ability to measure signals that are accompanied by relatively high levels of noise and
interference. The lock-in amplifier is an exceptionally useful instrument for extracting
signals from high levels of noise, even when the noise and signal frequency are very close
to the same value.
The heart of the lock-in amplifier is a phase-sensitive detector. A phase-sensitive
detector gives preferential treatment to the desired signal based on information about the
signal's phase. However, a bandpass filter also makes a large contribution to the
reduction of unwanted signals and to signal recovery.
In typical applications, the desired signal is chopped or otherwise amplitude
modulated at a much higher frequency. The signal recovery application of lock-in
amplifiers usually involves the measurement of an amplitude variation and, to a lesser
extent, phase variation of a periodic signal. Lock-in amplifiers are most commonly used
with slowly varying signals. Time scales for signal variation are commonly on the order
of seconds or longer[2].
A general experimental system for a lock-in amplifier is shown in Figure 2.1. The
system can be electrical, mechanical, optical, biological, or some combination of such
systems[l].

excitation
response signal sensor Modulated signal
noise
Lock-in
Amplifier
response signal
(demodulated)
Figure 2.1: A general experiment system of lock-in amplifier
2.2 Basic lock-in amplifiers
The lock-in amplifier is an extremely important and powerful measuring tool. It not
only can demodulate the modulated signal but also recover an input signal disappeared in
the high noise. The block diagram of a basic lock-in amplifier is shown in Figure 2.2.
2.2.1 The signal channel
As shown in Figure 2.2, lock-in amplifiers are usually provided with an optional
range of preamplifiers. The objective here is not only to enhance the gain, but also to
provide an optimum noise match to the signal source. In this way, the noise, whose
frequency is close to the signal frequency, is not enhanced at the expense of the signal
because of an excessive noise contribution from the amplifier. Frequently, lock-in
amplifiers are also provided with an array of filters for this purpose. If a substantial
fraction of the noise and interference is not eliminated in this way, then the amplifier could

e driven into saturation at an undesirably low gain factor. The resulting distortion would
degrade system performance seriously[7]. .
A sharp bandpass filter is frequently used to improve noise immunity. This can be
done because frequencies other than that of the carrier and its sideband are filtered out
with the bandpass fiher. Thus, the SNR can be enhanced before the demodulator.
Multiplier detector
input" filter •*" low-pass filter rt~^ out
preamp
time constant
signal channel
sensitivity
reference input
reference channel
Figure 2.2: A basic lock-in amplifier
2.2.2 The multiplier detector (synchronous detector)
The synchronous detector includes, at least, a multiplier and a lowpass filter. The
objective of the detector is to offer a wide dynamic range to maximize signal recovery

capability. For practical reasons, the multiplier of many commercial products is driven by
a squarewave switching waveform, instead of a sinusoid wave.
The low-pass filter serves several functions. First, it eliminates the secondharmonic
signal that is produced by the multiplier. The filter also integrates some of the
random noise that ends up in the output of the multiplier.
The simple block diagram of a synchronous detector is shown in Figure. 2.3. The
only unwanted components which can give rise to spurious output are those which
originate in the immediate vicinity of the reference frequency, confined to the transmission
'windows' defined by the characteristics of the low-pass filter[l][2][7].
s(0 + n(/)
I
output
r(0 >( X ) • low-pass filter ; • Voit)
mit) \
Figure 2.3: Synchronous detector
The synchronous detector derives its name from the reference carrier signal used
to demodulate the modulated carrier. As the diagram in Figure 2.3 shows, the operation of
a synchronous detector can be summarized by the following mathematical relationships.
From Figure 2.3, the input signal can be defined in terms of amplitude Vs, central

fi"equency/^, and phase (ps expressed as Equation (2.1). Also, a reference signal r(/) can be
defined with amplitude V;., central frequency/., and phase (j)r as express in Equation (2.2).
s(/) = Vscos [ 2;/,/ +^,] (2.1)
rit) -^Y,COSi 27lfrt+(/>r) (2.2)
mit) = (l/2)VsVr { cos [ 2n(f,^fr)
t)+ ^.^ A
+ cos[2K(f,-fr)t^(l>,-(!>,]}. (2.3)
Where mit) is the output signal after the multiplier.
Assume fs=fr, s^ (j>r, and the cut-off frequency of lowpass filter is less than/, then
after lowpass filtering. Equation (2.3) can be express as:
Vo= KVsV.cos [ 2n( frfr) t + ^.- ^. ]
= KVsV,. (2.4)
where K is defined as a constant scaled by the factor of lowpass filter and multiplier.
Equation (2.4) reveals that if r ovfs^fr, the output voltage will be reduced. To
prevent losing gain, a phase shifter is needed to assure that the phase of the reference and
signal channel are the same. Furthermore, the reference signal fi"equency,/., should be
chosen as the same as the modulating signal,/.
2.2.3 The reference channel
The phase-sensitive detector requires a reference channel which supplies the
precise modulating waveform required for the signal detector. The reference signal is
normally a sinusoidal wave or a square wave. The discussion in section 2.2.2 assumes that
7

the reference channel supplies an ideal sinusoidal wave. Sometimes the multiplier is a
square wave. The square wave form can be expressed as:
rit) = 4/71 { cos i2nfrt + Or) - 1/3 cos [3 (2;?/;/ +0,)]
+ l/5cos[5(2;//+0,)]-.. } (2.5)
at frequency/.
Then,
mit) = i l/2Vs/7r) { cos (2;r(/ +fs)t+ 0r)
-(1/3) cos [67rifr + fs)t+0r]
+ ( 1/5 ) cos [10;r(/ + f,) t + 0^)] - .. ]. (2.6)
If the bandpass filter is operated in a narrow-band mode to strongly attenuate any
input signal at higher harmonics, then the result is the same as the sinusoidal reference in
the section 2.2.2. If the narrow-band filter does not provide enough attenuation, the
phase sensitive detector will also have a phase-sensitive d.c. output in response to the
signal at other harmonic frequencies and possibly cause some measurement ambiguities.
To suppress the effect of the harmonic response, a tuned filter can be applied directly to
the phase-sensitive detector [1][7].
Furthermore, the phase-shift controller is necessary because the input and
8

eference signal are always out of phase when they reach the multiplier. The phase-shift
controller is usually provided with a continuously variable adjustment.
2.3 Noise rejection
As the diagram in Figure 2.3 shows, the response of a synchronous detector to an
amplitude-modulated signal at modulating fi-equency/o (oo = 2;/) with random noise after
the signal channel can be written as:
v,«(0 = msit)cos(iiot + nit) (2.7)
where wXO is defined as a input signal before modulation and «(/) is defined as a noise
signal. Since the noise spectrum is centered on the signal frequency/o and band-limited by
the band-pass filter, the noise signal can be written, in terms of random modulations, Rit)
and ^0. that vary very slowly in comparison with coscDot, as:
nit) = Rit) cos [ CDot + (p(t)]
= «,(/)coscoo/ - «^(/)sincoo/. (2.8)
where n,it) = Rit) cos^/) ( defined as in-phase noise ) and «(/) (defined as
quadrature noise).
The input voltage to the synchronous detector becomes:
v,niO = [ f^XO + «(0 ] coscoo/ - «g(Osincoo/. (2.9)
If a reference voltage v/?(/) = F^cosOo/ is introduced to the system, then the multiplication
products can be given as:

..(Ov,(o = ;". '^\-:{:> .('\ 1 r
y J _
- (
\ •
^r /:,,f/)5'n2o:o^
2. - - -. ti
io'.v--^ai3 ii':e: f a-i- -
- \.. L .. l_/ • ^ntj Ci:
th- c!.:i:-.::
f;') = i i/
- 7 ^
a. -; .l_ :-'~5 cf me:.::-:cj?.:^ v^Ivie.: cf/;:XO '^-
'^c-r'^:^(:)/"r:v:.
.'>
^c'2.12) sh.
-1 -i-i..
,'' 1 •. "3 ,1 • • ^
w ' - -. ^ A _ 'v.. . i v.. >_i L.' W > C • '» : Iw . C. * .
ne mr'.:.
• . . . , *
'Ny.., '"^ [ ;rr;':^cos^cc -C / .:-^^"\ =
; 7?r(t;//r(0j. \ - • • - ^
Hence, ±e s* "1 i _ r •". _ " ~" • . - i 11, I vy
;r is:
•".' 1 _ ^ .
.i"..! t•^:; 5igna.-:c-nc:r:c :•:. •nr'):-ovec.
Wlien i^2 ^''^ ^?i ( '•-'hi:^ Bj is th^ baad\vi'i:2 c-" :he 21LC" and E: is the ba'idwidth
ihe i'ou: nci;-: }, tn^: n:c:j:i~:qi.:ar^> vai'.ii cf rhe noisa fcK: vx-inq Ihc lo'. '-ra,^s aiti;: en:: b

NO = 2WNB^. (2.15)
where W^ is defined as the spectral density of the bandpass filter. The output signal-tonoise
ratio SNRo and input signal-to-noise ratio SNRjcm be written as:
SNRo = m,\t) I 2 WMBO (2.16)
and
SNRj = m\t) I 2WMBJ. (2.17)
Therefore, the signal-to-noise improvement factor becomes:
SNR^ I SNRi = Bj I Bo. (2.18)
If the input noise is band limited around the signal fi"equency,it is necessary to
provide noise filters centered on the signal frequency to ensure a high SNR before
detection[2][8].
2.4 The implementation of a lock-in amplifier
The basic block diagram of the lock-in amplifier implemented in this paper is
shown in Figure 2.4[9].
The design and implementation specification is described as follows.
1. The instrumentation amplifier.
To reduce possible common mode noise, a differential instrumentation amplifier is
used as the pre-amplifier. The differential gain of the pre-amplifier is 30.
11

unbalance
signal in
instrumentation
ampUtude
ha\ar\ce.

in the linear range, a gain controller is also needed.
4. The multiplier.
The main purpose of the multiplier is to demodulate the input signal from the
carrier. The linear range of the input signal of the multiplier should be maintained higher
than IV to be efficient. The frequency response range of the multiplier should be higher
than 20k Hz.
The lock-in amplifier is used to detect a low frequency signal which is modulated
to a higher frequency. Even the modulated frequency is very noisy. However, if the
original signal has added low fi-equencynoise before modulation, the lock-in amplifier can
substantially reduce that noise. When the noise frequency is very close to the modulating
signal, a lock-in amplifier still can improve the signal-to-noise ratio (as shown in section
2.4), but the signal recovery ability is decided by the bandwidth of bandpass filter.
Therefore, optimizing the filters and modulating frequency becomes essential.
13

CHAPTER 3
LOCK-IN AMPLIFIER DESIGN
The main blocks of the lock-in amplifier are an instrument amplifier, a band-pass
filter, a phase shifter, a multiplier, and a lowpass filter. The block diagram of the lock-in
amplifier is shown in Figure 2.4. The complete schematic of the circuit is shown in Figure
3.2. The detailed subcircuits for this lock-in amplifier are shown in Figures D. 1 to D.8 in
Appendix D. The actual component values along with significant voltage specifications
and signal levels are discussed in this chapter.
3.1 Op amplifier
An op amp is one of the most important parts of the lock-in amplifier since it is
used in eveiy part of the lock-in amplifier. An ideal op amp has infinite gain, infinite linear
range, zero offset voltage, high common mode rejection ratio ( CMRR ), infinite input
impedance and zero output impedance. Unfortunately, the ideal op amp does not exist.
The following block diagram illustrates the operation of a practical op-amp.
v^
V...
Differential input
amplifier
Level shift
Differential -to-single-ended
Gain stage
Output buffer stage
Figure 3.1: The block diagram of an op-amp
14

The circuit fijnctions that lead to near-ideal overall performance are:
• Level shifting.
• Differential -to -single -ended conversion.
• Added Gain.
• Output buffer stage.
Level shifting is needed to compensate for the dc voltage change occurring in the
input stage and thus to obtain the appropriate dc bias for the following stages. In some
circuits, the input stage has a differential output that is converted to a single-ended output
for the subsequent stage. Usually the gain provided by the input stage is not enough to
meet the specifications. Under this condition, an additional gain stage is needed.
The output buffer stage provides a low output impedance and a large output
current to drive the load of the op amp. Normally, it does not improve the voltage gain.
Usually if the op amp is an internal component of a switched capacitor filter, the output
load is a small capacitor, and the output buffer stage is not required to provide a very large
current or very low output impedance. However, if the op amp is the filter output, it may
need to drive a large capacitor or a small resistiv-e load. In this case, the output buffer
should be designed with a low output resistance for driving a big capacitor or to provide a
large current for a small resistive load. The major considerations for an op-amp design are
frequency response, input/output swing, gain, CMRR, and load driving capability.
Since the largest capacitor in the switched capacitor filter of the lock-in amplifier is
100 pf, a source follower is included at the output of the op amp. This source follower is
only used in the switched capacitor filters to drive the large internal capacitors.
15

The circuit diagram of operational amplifiers used in the lock-in amplifier are
shown in Figures D.7 and D.8. The difference between these two circuits is that the
circuit in Figure D.8 is used in the switched capacitor filters has an additional source
follower with a buffered output stage to drive the heavy load. The detailed circuit design
of the op amps is discussed in the following sections.
3.1.1 The differential input amplifier stage
In Figure D.7, Ml to MIO form a folded cascode amplifier, which includes a
differential input amplifier stage and a differential-to-single-ended conversion stage. The
key point of this circuit design is that the current of M5 should be greater than either Ml
or M3 since M5 provides the current for both Ml and M3. The same reasoning is applied
to M6. The basic operation and formulas are shown in Appendix A.
The advantages of this circuit are:
• It does not need level shifting to shift the dc voltage.
• It is a high gain output circuit.
• It reduces the non-dominant pole since it does not need level shifting.
It is particularly suitable for achieving wide and stable closed loop bandwidths with large
capacity loads, such as required in high-frequency switch capacitor filters.
The disadvantage of this circuit is the reduced output voltage swing of the
cascoded devices. The Mbl to Mb6 circuit was designed to improve the output voltage
swing.
16

i?5
II! >^
bQfldDQSS fler
^ m
foffii&rdef
I
0
R1 CI
^
Ik
R3C3
i- -t—M
„ , II 1 I
4—4-
^/l?,^ ''H^'
,1 (I
Vo
< I
Vo
T
lOffMSS f'llltr
9P
KM>
Figure 3.2: The schematic of the lock-in amplifier
17

3.1.2 Output stage
A class AB push-pull output stage is used in the circuit. The primary advantage of
this output stage is that the maximum sourcing/sinking current is not limited by the bias
current, although the small signal output resistance is high. The detailed operation and
formulas are shown Appendix A.
The major disadvantage of this output stage is that the output resistance is in the
order of kD. For driving big capacitor, a low resistance output buffer stage is needed.
There are several different methods for designing a low resistance output stage, such as a
source follower output stage (shown in Figure D.8) or negative feedback with error
amplifiers. Error amplifiers can provide a better linear range than source followers, but
they increase the circuit size and reduce the fi-equencyresponse. Two large resistors can
be used in place of the error amplifiers to assure a good linear range. However, this is not
a good implementation for VLSI design. Hence, a source follower is added to the output
buffer in this circuit [5] [6].
3.2 Active resistor
A large number of resistors are used in the lock-in amplifier. There are several
ways to design resistors in VLSI such as active resistors, diffusion resistors, polysilicon
resistors, and switched capacitor active resistors. Switched capacitor circuits are usually
applied with RC time constants and in dynamic circuits. For high impedance and gross
values of resistive components, either diffusion or polysilicon resistors are usually used.
Usually an active load is used in place of a resistor in VLSI design. However, the range of
18

the linear region is the limiting factor for accurate and symmetry circuits. In this case,
simple transistor active resistors are not used due to their small linear range.
Another way to design an active resistor is shown in Figure 3.4. The
implementation of Figure 3.4 is shown as Figure 3.5. The basic concept of the active
resistor is shown in Appendix B. From Appendix B, the voltage size of the linear range is
limited as: V < ( Vc - VT ). This shows that the higher voltage value of Vc, the larger the
voltage size of the linear range is. The measured data from the circuit of Figure 3.5 is
shown in Figure B. I. The data shows that it is hard to obtain the desired linear region
with a ± 5V power supply design.
Therefore, another method is used to improve the linear range as shown in
Figure D.6. The additional p- mode transistors, M7 and M8, are added to compensate for
the nonlinear range of the n-mode transistors M3 and M4. It is not difficult to obtain the
resistive linear range by simply adjusting the W/L ratio. The simulation result of Figure
D.6 is shown in Figure B.2.
3.3 Instrumentation amplifier
The main application of an instrumentation amplifier is to measure small
differential output voltage from a sensor under the presence of strong common-mode
input vohages. The three op amps shown in Figure 3.6 make up an instrumentation
amplifier. The deduction of the Vo is shown in Appendix C. The gain of the
instrumentation amplifier is shown as:
Ao = Vo/(V2-Vi)= {l+(2R2/Ri)}(R4/R3). (3.1)
19

The advantages of this instrumentation amplifier includes high input impedance and
high CMRR. Plus, it is easy to adjust the output gain by simply changing resistance Rl
without changing the bridge resistances. The implementation of a VLSI design in this
circuit necessitates the use of the active resistor shown in Figure D.6 to replace all
resistances. For the sake of symmetry, the linear and symmetric character of the active
resistor is an important issue in the design of the VLSI devices[5][6].
3.4 Switched capacitor filter
Since resistors are difficult to use in a VLSI circuit, switched capacitors are used in
the design of active filters. The parallel switched capacitor realization of a continuous
resistor is shown in Figure 3.7.
The transistors which act like switches, are controlled by the clock. The charge,
which flows into Ci at clock period 1 , is equal to
Q(to+T/2) = CV. (3.2)
The charge at the clock period 2 equals
Q (to + T ) = CV2 - CVi = C ( V2 - Vi ). (3.3)
After the second clock pulse of the clock 1, Ci will be recharged to
Q(to + 3T /2 ) = CVi - CV2 = C ( Vi - V2 ). (3.4)
From Equations 3.3 and 3.4, the resistance of the parallel switched capacitor resistor can
be defined as
R = (V,-V2)/I, = (V2-V,)/l2. (3.5)
20

— <
-(•
- * •
ModN'
l(—1
t
^
'1—1
1
<
WodD'
^

Figure 3.5: The implementation of Figure 3.4.
22

Figure 3.6: The instrumentation amplifier implementation by three op-amp

n
Ciccn
T
Ml
Clocl«r2
i
W2
12
o
VI
ir
CI
V2
6
'
Figure 3.7: Parallel switched capacitor realization of a continuous resistor
R
6^ 6"
Figure 3.8: The equivalent circuit of the continuous resistor
clock.
i clock 2
•^t-to
111 T 3T/2 2T 5/2T 37
t-to
Figure 3.9: Clock waveforms for the switched capacitor.
24

Since I = dq/dt, it is easy to get
(Vi-V2)/li(aver) = T/C. (3.6)
So
R= (T / C) = Tc /C = 1/ if, C). (3.7)
The main purpose of the switched capacitor is to reduce the size of the IC and to
obtain RC time constants. The advantages of the switched capacitor realization of
resistors can be observed by comparing the RC product of a resistor designated as Ri and
a capacitor designated as C2. It can be assumed that the product of Ri and C2 forms the
time constant ,1, given as
x = RiC2. (3.8)
Then the accuracy of x as a function of Ri and C2 can be expressed as:
di / T = ( dRi / Rl) + ( dC2 / C2). (3.9)
Assuming that Ri is replaced by a parallel switched capacitor equivalent, equation 3.8
becomes
x = (l/f;)*(C2/Ci) = TcC2/Ci (3.10)
Then the accuracy of x can be expressed as
dx / X = dT, / Tc -^ dC2 / C2 - dCi / Ci. (3.11)
Therefore , it is easy to see that if the clock is perfectly accurate, equation 3.11 will
become
dx/x = dC2/C2-dCi/C,. (3.12)
Because the two capacitor Ci and C2 are buih close together using the same technology,
the model of Equafion 3.12 should provide greater accuracy than Equation 3.9.
25

Therefore, the bandpass filter and lowpass filter are designed as switched capacitor filters
and are shown in Figures D.2 and D.5.
The fihers used in this system are 4'*' order butterworth bandpass and lowpass
filters. The central frequency for the band-pass fiher is 10 kHz, the bandwidth is 5.0 kHz
and the Q is 2.0. The cut off frequency of the low-pass filter is about 1 kHz. Since the
switching frequency fc should be much faster than the frequency of the input signal and the
pulse period should be large enough for the charge time of the switched capacitors, the
switching frequency of fc = 1 MHz is chosen, and the time period of the pulse is
0.3ps[3][4].
The 160kQ-100pf combination determines the central frequency of the bandpass
fiher. According to Equation (3.6) a 6.25pf capacitor is chosen to make the equivalent
value of the switch capacitor resistor equal to 160k. For the same reason, the 1 MQ and
Ipf combination determine the cut-off frequency of the lowpass filter as Ik Hz. The Ipf
capacitor is selected to make the equivalent value of the switch capacitor resistor equal to
IMQ.
3.5 Phase shifter
When the input signal reaches the multiplier, it will not match the phase of the
reference signal. To prevent the loss of gain in the system, the phase relationship should
be kept when both signals reach the synchronous demodulator. The phase shifter with gain
adjustment as shown in Figure D.3 is applied to correct the phase and to make the
26

eference signal the same phase as the input signal. A basic Wien bridge phase shifter is
used and is shown in Figure 3.10. From Figure 3.10 the loop gain can be expressed as
L(co) = [R2(l+R4/R3)]
X { Ri+R2+R2(C2/Ci) +j [ C0R1R2C2 - (l/coCi) ] y' (3.13)
from equation (3.13), the shifted angle 0 can be express as
e = tan^ [ - (C0R1R2C2 - 1/coCi) / (Rl + R2 + R2C2/C1). (3.14)
By adjusting the values of R and C, the phase and gain can be changed. After the signal
channel, the input signal is 126° ahead of the original signal. The circuit shown in Figure
3.10 can not correct the phase that much. Therefore the circuit shown in Figure D.3 is
used (the detailed component values are marked). To prevent the op amps from being
driving to saturation and improve the signal gain, the variable resistor R6 is used. This
keeps the signal in the maximum input voltage range of the muhiplier, ensuring that the
multiplier works in the linear range.
3.6 MultipHer
The four-quadrant Gilbert multiplier cell is used as a demodulator. The basic
circuit of the four-quadrant Gilbert multipUer cell is shown in Figure 3.11. The complete
implementation is shown in Figure D.4. The transistors Mvl to Mv4 are used to convert
the output currents to voltage and to improve the gain and linear range of the Gilbert
multiplier cell. The op-amp is used to convert the two-ended outputs to a single-ended
output and to increase the gain of multiplier. An analysis of the circuit yields :
Vout = K„V,V2 (3.15)
27

where K„ is related to R,, Ry, R^ and !«[5].
The multiplier and the low-pass filterare combined as a synchronous detector, the heart of
a lock-in amplifier.
28

R3
R4
'0
OP
11
^
Rl
CI
—WV * * II * 1—1—^
V-
V4
M
^CouT--
R2
•C2
f <
{. (
*0 ^0
Figure 3.10 A basic Wien bridge phase shifter
29

Figure 3.11: The basic circuit of four-quadrant Gilbert muhiplier cell
30

CHAPTER 4
SIMULATIONS AND ANALYSIS
The prototype circuit was simulated by using the model of MOSIS CMOS 2-\im
n-well process. The parameters are shown in Figure 4.1. The block diagram of the total
circuit is shown in Chapter 2, and the total circuit is discussed in Chapter 3.
The simulation results will be discussed part-by-part following the diagram shown
in Figure 2.4. The resuhs of the op-amp which is used throughout the circuits will be
measured first.
4.1 Simulation resuhs of OP amplifier
One of the most important characteristics of an op amp's performance is its
operation in the open-loop mode. However, due to the high differential gain of the op
amp, it is difficuh to measure an op amp in the open-loop mode, and it is also difficult to
simulate an op amp in open-loop. There are two methods shown in Figure 4.2 to simulate
the open-loop gain. Applying the approach in Figure 4.2 to measure the open-loop gain is
only practical for simulation. The resuh of the open-loop gain by using the circuit of
Figure 4.2 is shown in Figure 4.4. The circuit shown in Figure 4.3 is a better way to
measure the open-loop gain. This method works well for both simulation and physical
measurement. In the configuration shown in Figure 4.3, the reciprocal RC time constant
should be set about 10 to 100 times less than the anticipated dominant pole of the
31

.MODEL ModNNMOS LEVEL=2 PHI=0.700000 TOX=4.2400E-08 XJ=0.200000U
TPG=1
+ VTO=0.8184 DELTA=4.0370E-K)0 LD=3.4300E-07 KP=4.5103E-05
+ UO=553.8 UEXP=1.2310E-01 UCRIT=9.6810E+04 RSH=1.4910E-01
+ GAMMA=0.5799NSUB=6.7190E+15 NFS=1.0890E+11 VMAX=5.9760E+04
+ LAMBDA=3.3160E-02 LAMBDA=3.3160E-02 CGDO=4.1902E-10
+ CGSO=4.1902E-10 CGBO=3.4911E-10 CJ=1.2010E-04 MJ=0.6285
+ CJSW=4.7113E-10 MJSW=0.3275 PB=0.800000
* Weff = Wdrawn - Deha_W
* The suggested Delta_W is 1.5426E-08
.MODEL ModP PMOS LEVEL=2 PHI=0.700000 TOX=4.2400E-08 XJ=0.200000U
TPG=-1
+ VTO=-0.9477 DELTA=4.6250E+00 LD=3.6240E-07 KP=1.6761E-05 '
+ UO=205.8 UEXP=2.8980E-01 UCRIT=8.3070E+04 RSH=1.1050E-01
+ GAMMA=0.6899NSUB=9.5090E+15 NFS=1.1000E+11 VMAX=9.9990E+05
+ LAMBDA=4.6050E-02 LAMBDA=4.6050E-02 CGDO=4.4272E-10
+ CGSO=4.4272E-10 CGBO=3.9342E-10 CJ=3.0933E-04 MJ=0.6176
+ CJSW=2.8778E-10 MJSW=0.4045 PB=0.800000
* Weff = Wdrawn - Delta_W
* The suggested Deha_W is -3.0100E-07
Figure 4.1: The parameter of MOSIS CMOS 2-\im N-well process
32

Vdci
Via
Vout
yof5F
Vss
^ 0
^o
o
Figure 4.2: Open-loop mode with offset compensation
Figure 4.3: A method of measuring open-loop characteristics with dc
bias stability
33

op amp. Under these conditions, the op amp has total dc feedback, which stabilizes the
bias. The dc value of Vout will be exactly the same as the dc value of V^. This result is
shown in Figure E. 1.
The true open-loop frequency response characteristics will not be observed until
the frequency reaches approximately 10 times that of 1/RC. Above this frequency, the
ratio of Vout to V^ is essentially the open-loop gain of the op amp. The resuh of the openloop
gain by using the circuit of Figure 4.3 is shown in Figure 4.5. Also from the
measurement resuhs shown in Figure 4.4 and Figure 4.5, it is found that the open-loop
gain is about 80 dB. The open-loop transfer curve, output swing limits, phase margin,
dominant pole, and unity-gain bandwidth can be simulated or measured by the open-loop
configuration. If the phase at o = GB (unit gain bandwidth) is larger than -180°, then the
system will be stable. It is also known that the larger the phase margin, the more stable
the circuit becomes. Usually at least a 45° margin is required. Figure 4.5 shows that the
phase margin is about 45 °. Figure 4.4 shows that the dominant pole is around 600 Hz
while the unity-gain bandwidth is around 6M Hz. For a central frequency at 10k Hz, the
frequency domain fits the requirements. The open-loop transfer curve and output swing
limits are shown in Figure E.2. All of the above simulation resuhs are simulated with
RL=lknandCL=10pf
According to the definition of CMRR, the common mode rejection can be
measured by the circuit shown in Figures 4.6 and 4.7. The resuh of CMRR is about 74 dB
which is shown in Figure 4.8.
34

As shown in Figure E.4, the approximate slew rate of the op amp is about +SR =
6V/ps and -SR = 7V/ps. Also the settling time of the rising edge is about 1.28ps and
1.68ps for the falling edge. The test method for measuring slew rate is shown in Figure
E.3. The load capacitor is 30 pf
4.2 The simulation resuh of instrumentation amplifier
To test the instrumentation amphfier, the most important measurement is CMRR.
Figure 4.9 shows that the CMRR of the mstrumentation amplifier is about 120 dB. Also
Figure 4.10 shows that the gain of the instrumentation amphfier is about 30, while the
frequency fits the requirements, and the output signal has good symmetric characters.
4.3 The switched capacitor filters
There are two switched capacitor fihers in the lock-in amplifier. One is a bandpass
iker whose central frequency is 10 kHz. The other is a lowpass filter whose cut-off
frequency is Ik Hz. The sampling frequencyof the switch capacitor, f^ is 1 MHz.
The simulation results of bandpass fiher are shown from Figure 4.11 to Figure
4.13. The simulation results show that the central frequency of the bandpass filter is about
12 kHz and the bandwidth at 3 dB is about 5.2 kHz. The Q of the bandpass fiher is about
2.3.
The simulation results of the lowpass filter are shown in Figure 4.14 to Figure
4.16. The results show that the 3 dB point of the lowpass fiher is around Ik Hz, and high

SNR also occurs. Figure 4.9 shows that the phase of the input signal is shifted.
Therefore, the phase correction before the muhiplier is needed.
4.4. The muhiplier
From Figures 4.14 to 4.15, the Unear range of muhipher is found between -2V and
+2V, and the output vohage is Vout ~ 2 V^i Vin2. Also the bandwidth of the muhiplier is
about 50 kHz as shown in Figure 4.16.
4.5 The simulation resuhs of the whole system
After testing the system part-by-part, it is apparent that the operation of every part
of the system meets the requirement. Therefore, an input with a noise signal is set up to
test the whole system. Figure 4.17(a) shows the input signal, and Figure 4.17(b) shows
the amplitude modulation of the input signal. The wideband noise is shown in Figure 4.18.
After the lowpass filter of the lock-in amplifier, the noise is suppressed. The signal-tonoise
ratio (SNR) in the system is 1:6. This result is shown in Figure 4.19. The
comparison of the results between Figure 4.17(a) and Figure 4.19 reveals that the signal is
recovered. However, the signal after the lock-in amplifier is inverted.
Figure 4.20 shows a really high noise example (SNR=1:10). In Figure 4.20 the
signal indeed disappears in the noise. Figure 4.21 shows that the result is the same as in
the SNR = 1:6 case. Figure 4.22 shows that in case of the SNR = 1:1, the signal is
completely recovered.
36

The simulated resuhs of the whole system reveal that the lock-in amplifier obtains
an excellent quality.
37

n • ,m.
' C:\LIS2T\TEST\T0LG1.SCH
Pace/Time run: 12/18/95 01:31:52
(A) Open-loop Characceriscics
100
Temperacure: 27.0
.i
50-!
(685.7 47,82.76'^.)
\
\
\
v
H85-747.-29.413)
-50-1
\
•100-"
\
-ISO--
(7'^0009M,-17
v
•200 + T
lOmHz 1.0H2 100Hz_ lOKH:
[-V;20'iogl0( V(OP.Vouc)/ V(Vin) ) LllVP(OP.Vouc)
Frequency
---r
1.0MH2
i
100MH2
M: (8.0370, -378.503m) A2 : (10.000m. 33.965) DIFF (A) : ( 3 . 0270,-84 . 343 )
Dace: December 18, 1995 Page 1 Time: 01:37:39
Figure 4.4: The measurement resuh of open-loop gain
margin by using the cu"cuh of Figure 4 3
38

• C:\LIS2T\TEST\TOLG.SCH
Daca/Ttme run: 12/16/95 18:45:31
100
(A) Open-loop gain wich dc bias
scabilicy
Temperacure: 27.0
80 -
T
.^t
60
/ i \
40
20
-2 0 -t-- r r -"-- r i
l.OmHz l.OHz l.OKHz 1.OMHz 1.OGHz
GT|20'ioglO{ V(HBl.Vouc)/ V(Vin))
Frequency
J
Al: (11.856K.33.246) A2: (1.0000m, -199•134u) DIFF(A) : (11.a56K.93.246) |
Dace: December 16. ITTS Page 1 Time: 18:43:03
Figure 4.5: The measurement result of the open-loop gain and phase
39

Figure 4.6: Op-amp with only common-mode input vohage
OP
IVin_,cl
t
° i
CJ
JT
vad
V- H'^^-v^
YP"'^^^^
^^^--^11
> Vcc
*^, A
^^ ^p
Vd
o
Figure 4.7: Op-amp with differential-mode input
40

n^r^/Ti , ' C:\LIS2T\TEST\TCMRR.SCH
Pace/Time run: 12/18/95 03:07:43 Temperacure: 27.0
(A) Test oe CMRR
-1.515V--
I
1
i
/
/
y
-1.520V-^ J-
^::..V(vd)
jOJuV ---- —
280uV
o V(vc)
75.2-7 •
74.8-j
74.4
\
I
(478.^4u,74.J83)
I /
I /
1/
I'
'
SEL».
74.0-f- --•
.J.
0_s 0.2ms 0.4ms 0.6ms
L2.|20*logl0( V(0P2.VouC)/ V(OPl.Vouc))
Time
1
0.8ms
{
1.0ms
Al: (478.014u,74.383) A2:(0.000.-1.5194) DIFF(A) : (478.014u.75.903 )
Dace: December 18, 1995 Page 1 Time: UJ:09:3 3
Figure 4.8: The simulation resuh of CMRR
41

,^^^,„.
• C:\LIS2T\TEST\TCMRR.SCH
Dace/Time run: 12/18/95 04:18:17 Temperacure: 27.0
(A) CMRR oJ inscrumemcacion ampliCier
113.0
112.5T
(1.1944u,112.067)
CMRR
112.0
111.5-i ;
I . '
111.0+ r r--
Os 2us 4us 6us
- 20'iogl0( V(OP2.U7.Vouc)/ V(0P1.U7.Vouc))
Time
-- T - - - • {
Dace: December 13, 1995 Page 1 Time: 04:33:32
8us
lOus
Figure 4.9: CMRR of instrumentation amplifier
42

...J
...J
''^i >•* t X a/'i.«^»» o» < 3 a t * X
i /
i
i
; **'; V ( \ri.r»»
i
i
K
L\
o *
dive
\ \
\
\ \
•%
\
\
/
/
• /
/
/
1 ^
/ .
/ .
/
/
/
* /
• \ :
\ \-
• \
/
• \
s
X o Oua
(
o >
T r * n w X « n e
• O • NX.X«znrNTK«TVTX «(. . SCM
o £ Xn « c x*\jirT«*r\c «k e X ort
.X i. \....
( X-T 4 . » X>^ U . 3 . 0 S 0 3 ) /
.' \ • /
. / . . \ . . / .
/ \ /
/ - \ /
/ • \ /
> V'.**''! 0 3 . ( 0 . 0 3 0 . 0 . a DO) D Z K K t O ) t ( 3 3 * * . * 3 0 \ u . — 3.1. 3 » 7 >
:='-.c7 — I^
An^»xxex«r
. ' 1 \
1 *
/ - 1 \
•' • 1 \
\- 1 /
• \ 1 /
. ( Va • .laaau. -i .xo>-r
3 O O ^ *
Figure 4.10: The resuh analysis of instrumentation amplifier
43

Dace/Time run: 12/18/95 07:39:26
C:\LISZT\BF\BF1.SCH
(C) The General frequency and SNR analysis
1.0
« V(ONOISE)/ V(INOISE)
lOOnV-
/ I
1...J..
.y\
OV-^-
3 V(ONOISE)
lOKV-
:> V(INOISE)
l.O-r
I ', , (|15 J30iJC^Z2.-fi.4^)_
SEL>>i
0-H
10H2
100H2
[][|V.(vouc)/ V(vinl)
1.0KH2
Frequency
/I
.-.-4...
10KH2
CI:(9.363K,638•563m) C2: (10.023,1.061 Op) DIFF(C) : (9.353K,6 38.563m)
Dace: December 18, 1995 Page 1
Figure 4.11:
The frequency and noise response of bandpass filter
44

_,^^,_.
• C:\LISZT\BF\BF.SCH
Pace/Time run: 12/19/95 10:30:10 Temperacure: 27.0
(A) The oucpuc response for inpuc sinal is lOJcHz
l.OV
'i I
0.5V-;' i.
/':
ill
( ii
m.
uw
M li
°^K^i il \\ i\ \\ i
-0.5V-
; \^ :
: I
1 ;
Wll
: i •
( :
i i
f;
i / ;
i I !
11
SEL»;
;'
-l.OV-I- ^ 1: •
= V(vinl)
2.0V-r-
» V(vouc)
; I
1 ;
i ':
I
nil
i i.
?11
m
i-i i :•
.' I : • •
;•
ii! :
i I
m
f ' i i
II \
m /Hi
Ml ;•
(4
I i
1 i
I i
.i I
-!(
\u y u i.
I :
if
: f
\ i i
I I I
; / \
\ i i
i / :
(ill
Ul =.
Mil
I -, I
i\\
H
1
i I ;
i l l I
hf I
1 !/ i
Of
.-.V
\':
i.M i.
i 1
W i
: i
I
\ : I >
jU ?
! : I -J
i \i i:
J i'
; .. I
', J I
. - . v . J
1. Ov -, ,^^ . A. . / \. • M. . / \. . / \. . / \.
i
Wliwi\in\miri\ir!\
' v^v;
V/ • •= p/ •.• i fv7 .•l': fv/ \i f\7 .1' h' • V k/ ••••V- f'/ '• v fv/ • -v
-l.OV-"
-2.0V-I- r--- --r
Os 0.2ms 0.4ms 0.6ms
5 V(voucl) • V(vouc2) • V(vouc3) .. V{vouc)
Time
T --T T •
^
0.3ms
1.0ms
Dace: December 19, 1995 Page 1 Time: 10:50:08
Figure 4.12: The output response of input signal frequency at 10k Hz
45

» / T i. w «
L . OV
.^
7C
^ * / a a / » 3 O 7 • O 3 . 9 7
;\
LT\MO«X«S mv N » ^ . aOM
I A> t
B» . OA.-r
• ^»>>yw^ m^^» «
Tx"
a "y . o
o . sv -;. J.
•i :
• 1 1
-O . Sv ..
i f
\ (
• f .
•
\ .' '
'. /
• • >^ ( >^ xn X )
A 0,vt^^ ...— . — - . . « . ...
1 I
\ :'
1 /
I ,*
t .
; ! \ i
•. (
u J ir._. •>;
i J
i (
/. I .'
ov .* --
\
/ :
/ \
\
/ \
a O r^'^ -^ — — — - — - — — — • _ . » ^ _ _ « _ _ — _ . _ « . « _ » . . . _ . . ^ - — - . » - « _ - . - • • _ _ _ ,
0 « aOu,« AOw»a « ©"U"* X O 0\A«
»•'•'*'••«- a a , .L » » 3 n« • OT.X3

' C:\LISZT\LF\LF.SCH
Dace/Time run: 12/18/95 09:07:58
(A) The oucpuc frequency response of lowpass filcer
2.0--
5 V(CNOISE)/ V(INOISE)
40mV-.
OV-•
5 V(INOISE)
20nV-
OV-
" V(ONOISE)
2.0V-.
SEL»
QV + -
10H2
•:• V(VOUC)
100H2
(987.428,1.01"&»-
l.OKHz
Frequency
lOKH;
Dace: December 18, 1995 Page 1
Figure 4.14: The frequency and noise response of lowpass filter
47

Dace/Time run: 12/18/95 09:34:32
• C:\LISZT\LF\LF.SCH
(A)
The oucpuc
response
of
inpuc
frequency
ac l)cH2
' / \
1 * ^
1 t \
t \
' *.
1 ' ^
/ 1
/ \
If \
ov-f . . \
1 1
= V(vinl)
• /
/
• /
• /
i
1
\ , f
t
\ (
» .' *
* *
1
» /
• /
1 ,'
* f a
\ :
\
\ . /
• •> . • f
\ /
"•
> 1
1 ,
> <
\..A
/••
\
\
\
\
\
(1.5837m,873.•633m)
y
•
; /
/
ov-| '•
\
\
t
\
%
V
«
t
\
\ , /
\ /
\ /
/ . . \.
/
/
/
/
/
/
. / .
. . . ^ ' • \
(2.9937m ,'-1.0947)
\
N. ' •''
SEL»;
.Os
:: V(VOUC)
1.0ms
2.0ms
Time
3.0ms
Dace: December 18, 1995 Page 1
Figure 4.15: The lowpass fiher output response of input signal frequency at
Ik Hz
48

n • ,'»
' C:\LISZT\M0SIS\LF\TLF1 SCH
Pace/Time run: 01/16/96 12:18:49 ^^r M L H .bCM Temperacure: 27.0
(A) TLFl.DAT
l.OV.
0.5V-;;
••
( :
:' i
I I
I :
I
! i
I i
i
i
i
I .
; I
/1
I \
I i
! i
i !
OV
! i
f
i
I
i
il-
-O.SV--
' I !
SEL>>i
-l.OV-^
•> v(vinl: + )
40mV-
1 i'
; i
i i
• I
I i.
.: j.
i :
: i'
I i.
'• t
i (
! I
I
I
i I- 1 i:
I
1 : .
'•
1
1 .
. '
1 : -
. ^- - - . .
: i
\ j
I
-^*— . -
I
• : *
: ; 1
\ i;
: * 1
I . 1
\!:
_ .i'_ J
,r"*^^_
OV -y.JW***'^
\
•40mV.
\
-80mV-
\
\
\
•120mV + 1
Os
0.2ms
e V(Vouc)
0.4ms
Time
- - -I
0 .6ms
., ,
0.8ms 1.0ms
Dace: Januar/ 16, 1996 Page 1 Ti.me: 12:26:5:
Figure 4.16: The lowpass fiher output response of input signal frequency at 10k Hz
49

0« c » /TX>^»
»-v^». xa^aa^»^ o« . ?^ >^f *^'^^x°"^gvxui.TN MOUT . act.
X.OV-; ., .
' tt sA^ ^ • a T . o
>~\ ^-;. , ---
/ N 7" "/^\ -:
SSI.....:
- X . o\r -«
X . oyy — — -,*—
VivlT."!"" '*" ~ \..'.
'/"
' X . OV
3 . o\r
.v^.
•.
^
'A -,'>
r \
•'•%
X . OV ..
1 »
ovr -*.^ V.
O m
" V(Vouc)
V -^ ^ VI.
3 OOui
o«c«i o—... :
• X . OV - ^\..c -.
- V Ivxn)
x.

Pace/Time run: 12/18/95 10:16:07
• C:\LISZT\MULT\MULT.SCH
(A) DC cransfer characceriscics of
5.0V T-
mulciplier
• \
/
\
\
\
\
/
/
\
X
\
OV
\ \
w /.
. / \
/ \
/ \
/ . \
\
\
/
/
-5.0V + -«---
-6..0V
-4.0V
: : • » : . * V(VOUC)
-2.0V
OV
V V8
2.0V
DaCe: December 18, 1995
Page 1
Figure 4.18: The DC transfer characteristics of multiplier
51

n^ra/Tf,^ «, * C:\LISZT\MOSIS\MULT\MULT.SCH
Dace/Time run: 01/16/96 10:14:10
Temperacure: 27.0
SEL»
0-
•> V(Vouc)/(V(Vin)'V(Vref) )
2. OV -cm
1.5V-,
l.OV-
0.5V
OV-f-
10H2
•^ V(VOUC)
1.0KH2
Frequency
100KH2
10MH2
Dace: January 16, 1996 Page 1 Time: 10:16:44
Figure 4.19: Ac characteristics of multiplier
52

c
J2
3
O
E
Urn
"a.
E
ea
-a
c
13
c
cp
'v5
"3
Q.
c
<
o
fN
'^'
(U
u>
3
SO
c
>
>
>
£
>
o
53

*o
c
-a
c
E
>
e
o
>
o
u
10
o
CO
54

£
I
(J
S,
tz
c
>
o
k.
3
CO
iZ
55

CO
S
o
CM
ca
B
vo
ca
e
(N
a
B
u
u
3
0
a
>
f-
>
a
o
o
>
o
A
A
•J
u
CO
CO
o
>
c
o
a:
z.
00
'o
c
CO
IS
c
"3
c
CN
'^'

m
o
-"^
U
3
CO
57

c/o
CO
3
*o
c
-o
c
cd
U
no
ed
cd
C
CO
•55
>
o
CN
u.
3
CO
IZ
58

CHAPTER 5
SUMMARY
From the previous descussion, h is seen that every part of this system works well
and meets the requirement. The advantages of this integrated lock-in amphfier are: the
instrumentation amplifier has high input impedance and high CMRR, and the output signal
has good symmetric characteristics because the active resistor can provide a linear range
of about 3V; the muhipher works m the high hnear range from -2V to +2V. The
simulation resuhs of the whole system show that this lock-in amplifier can obtam the high
performance even with the SNR =1:10.
For most commercial types, a fiih lock-in amplifier would include: (1) a tuned
amplifier, called the signal amphfier, which is combined with gain adjustable amplifiers and
variable filters; (2) a phase shifter to bring the reference signal (i.e., the modulation) into
the optimum phase relation with the signal; (3) an internal voltage controlled oscillator;
(4) a synchronous detector which is combined with a muhipher and a lowpass filter with
adjustable time constant. On comparison to some commercial products, the lock-in system
in this thesis is an implementation of a basic type of the lock-in amplifier which is
designed for fitting certain requirements.
To be of any practically commercial type, a lock-in amplifier must be able to give a
fiih-scale response to a synchronous signal and yet be able to accommodate residual noise
fluctuation due to noise transmitted by the low-pass filter. Figure 5.1 shows an extended
59

version of the one shown in Figure 2.3 which can improve the basic type of lock-in
amplifier.
For practical reasons, a square wave is used as the reference of the multiplier.
Therefore, a two-phase lock-m amphfier as shown in Figure 5.2 is used to suppress
harmonic responses, but the behavior of the output signal is similar to the results produced
when multiplied by a sinewave.
Due to it's senshivity, the lock-in amplifier has been used widely for retrieving
signals from noise in the modem technology. Today, VLSI technology has been
developing rapidly, hs participation in the lock-in amphfier design can extend the
application of lock-in amplifiers, especially m the communication and image processing
fields.
60

signal
input
> -
decade
multiplier
y
••
option
filter
»
sensitivity
band-pass
filter
1
y
1:2:5
multiplier -
^N. simal
v^top.s.d
signal
phase-sensitive
detector inputs
output
reference
reference •
input
logger
evt
int
2f
O 90°. 180°
270°
squarewave
generator
reference
to p.s.d.
internal ^ \
oscillator V._x^
777
oscillator
output
2f
variable
phase
quadrants
The reference channel incorporates an optional internal oscillator and a
frequency double to permit phase-sensitive detection at twice the applied
reference frequenc>'
Figure 5.1; Block diagram of an extended lock-in amplifier
61

signal
input
signal channel

REFERENCES
[1] M. L. Meade, Lock-in Amplifiers: Principles and Applications, Peter Peregrinus Ltd
London, UK 1983. • s .
[2] Richard Wolfson, 'The lock-in amplifier: A student experiment,'Mm. J. Phys., Vol
59, No. 6, June 1991.
[3] Philhp E. Allen, Edgar Sanchez-Sinencio, Switched Capacitor Circuits, Van
Nostrand Reinhold Company, New York.
[4] P. V. Ananda Mohan, V. Ramachandran, M. N. S. Swamy, Switched Capacitor
Filters - Theory, analysis and design. Prentice Hall, UK 1995.
[5] Randall L. Geiger, Phihip E. Allen, Noel R. Strader, VTSI Design Techniques For
Analog and Digital Circuits, McGraw-Hill, New York 1990.
[6] Mohammed Ismail, Terri Fiez, Analog VLSI Signal atid Information Processing,
McGraw-Hill, New York 1994.
[7] John H. Scofield, 'Trequency-domain description of a lock-in ampIifier,'M/w. J.
Am. J. Phys., Vol. 62, No. 2, February 1994.
[8] Andreas Mandehs, "Signal-to-noise ratio in lock-in amplifier synchronous detection:
A generalized communications systems approach with apphcations to frequency,time,
and hybrid (rate window) photothermal measurements," Rev. Scl. Instrum., Vol. 65,
No.ll, November 1994.
[9] Murah Kittappa, "Variable capachive transducer", M.S. Thesis, Electrical
Engineering, Texas Tech U., December, 1992.
63

APPENDIX A
THE OPERATION OF THE OP-AMPS
A.l Introduction
The op-amps which are used in this lock-in amplifier can be separated into two
parts: a differential mput amplifier stage and a output stage.
The differential input amplifier stage shown in Chapter 3 is called a folded cascode
amplifier, which includes a differential input amplifier stage and a differential-to-single
ended conversion stage. The output stage is called a class AB push-pull output stage.
The advantages and disadvantages of the circuits have been mentioned in Chapter 3. The
basic operation of the differential input amplifier stage will be discussed m A-2, and the
basic operation of the class AB push puU output stage wiU be discussed in A-3.
A.2 The basic operation of folded cascode amplifiers
In Figure D.7, the dc current lo, in Ml 1, is the source of Ml and M2. Since the
gate vohage of Ml 1 is a fixed bias, it operates as a simple current source. The matched
sources, M5 and M6, provide current l' to node A and node B, hence M3 and M4 will
carry equal currents
I = r-IJ2.
(A.l)
A differential input vohage AVin- = AVi„ / 2, apphed to the gates of Ml and M2, will offset
their drain current to tgmiAV/ 2. Since the current I' of M5 and M6 remains constant, I
of M3 and M4 will change by ±AIo. The mirror ( M7 to MIO ) current changes in M7 to
64

M9 and M8 to MIO. Hence, the output vohage increment is g„„RoAV^ where Ro is the
output impedance of the node at Vo, and M7 and M9 are working as the current sink
shown in Figure A. 1.
Figure A. 1: Equivalent circuit of Ro
This circuk ( Figure A.1) can be modeled by a small-signal circuit of Figure A.2.
Correspondingly, the output impedance can be written as:
Ro = AV / AI = rds [1+ ( &n+gmb+gds)R) = rds(l+gjl)
(A.2)
If R is replaced by a transistor M2, then
Ro = AV / AI = rdsl [1+ ( gml +gmbl+gdsl)rds2) = rdsl(l+gn,irds2).
(A.3)
65

gmVgs
G mbs^'bs
© © rds SH*"
-f •-
V
R
Figure A.2: Equivalent circuit of Figure A. 1
From the smah signal model of a folded cascode circuit, as shown in Figure A.3,
the open loop gain Ao can be expressed as:
Ao= Vo / Vid = gmir'out =
gml gm8 ^dsS TdslO
(A.4)
where r'outwas given by the simplification of Ro.
After combining elements in the small signal model of Figure A.4, the output
resistance of the folded cascode circuit can be expressed as:
rout= T'out II rds4 [l+(l+gm4 rds4)rd^rds4/(rds2+rds4}
= ( gmsrdssrdsio ) II [(gm4 rd^)(rds2 II rds4)]- (A.5)
From the expression of equation (A. 5), it is easy to find that the folded cascode circuit is a
high output impedance circuit.
The frequency performance of the CMOS folded cascode op amplifier can be
simply expressed as
66

VO(S)A^ID(S) = AoOi/ (S+coi) = GB / S+oi
(A.6)
where coi is the dommant pole of the chcuit is given by coi = 1 / RO«.CL.
The operation of this output circuit, shown in Figure 3.8, is determined by the bias
vohage in the gates of Mo3 and Mo4, which decide the bias currents in the output devices
Mo6 and Mo8. When the mput vohage Vi„ increases, the current of Mol increases, and
Mo2 decreases. These devices mirror the output current so that the current of device
Qm1('v1d/2')
(t)
1/Qm3
Vos3
(±)
gm3vcs3 r'ln
* *
(t)
timHv\6/7) 1 /qrri4
rds4
1 •-AMr-^
i-i.
V(3s4
grrsJvgs.^
5) I (D i'^^
r'&ut
Figure A.3: The small signal model of folded cascode amphfier
rds4
• '
>'ds2 > •'ds6 Vqs-4
qrn4vqs.4
i-'OUi
Vo
l_±.
Figure A.4: The equivalent output resistance circuh of folded cascode amplifier
67

Mo8 increases which provides the sinking capability for the output current. For the same
reasons, when Vin decreases, Mo6 wiU source the output current. The output signal swing
is limited to within a VT value of Vdd and Vss.
The bandwidth is given as
oi = co-3dB = ( gout+ GL) / ( COUI+CL) - 1 / ( RLCL ).
(A-7)
68

APPENDIX B
THE BASIC CONCEPT OF THE ACTIVE RESISTORS
Bl Introduction
The main function of an active resistor is to improve the valid voltage range of the
hnear region. The following section shows the analysis of a basic active resistor, the
results of the basic active resistor and the improved active resistor used in this thesis.
From Figure 3.3, h is easy to obtain:
B.2 The basic deduction
IDI = Kx( Wi / Li ) [ ( VGSI - VTI ) VDSI - ( V'DSI / 2 ) ]
= Kx( Wi/Li) [ ( VDSI + Vc- VTI ) VDSI- ( V'DSI / 2 ) ]
= KN(WI/LI)[(V'DSI/2) + (VC-VTI) VDSI] (B.l)
and
ID2 = KN- ( W2 / L2 ) [ ( VGS2 - VT2 ) VDS2 " ( V'DS2 / 2 ) ]
= K'N ( W2 / L2) [ (VC - VT2 ) VDS2 - ( V'DS2 / 2 ) ] (B.2)
Since VDSI = VDS2 = V, so
I = IDI + ID2 = 2K NW / L ( VC - VT ) VDS
(B.3)
and
r, = 5VDs/ei=l/[2KN.(W/L)(Vc-VT)] (B4)
Because VDS should be less than Vos - VTIO ensure that the transistors are working in the
ohmic region,
69

V

Date/Time run: 01/l6/c,fi .^,^._^\^^-^^^^^'^\^0SlS\R\7P..SCH
(A) V-I
200UA-,
remperature: 27.0
\
\
\
\
\
\
\
\
• \
\
\
OA.
\
\
\
\
\
\
\
\
\
\
\
\
\
lOOuA-
-lOOuA-
\
\
\
-200aA-l
-2.0V
I(V)
-l.OV
-o.ov
V V
l.OV
\
\
^,
2.0V
Date: January 16, 1996
Page 1 .me: 11:24:42
Figure B.2 The simulation resuh of Figure D.6.
71

APPENDIX C
THE FORMULA REDUCTION OF THE INSTRUMENTATION AMPLIFIER
C.l Introduction
The instrumentation amphfier provides the high mput impedance and the high
common rejection necessary for the lock-in amphfier. A popular 3 op-amp configuration
is used in this circuh. The analysis of the circmt is shown m the following section.
C.2 The output voltage of the instrumentation amplifier
From Figure 3.5, h is obtained as following:
node a:
(Vc-Vb)/R2 + (Va-Vb)/Rl = 0,
Vb(l/Ri + l/R2) = (Vc/R2) + (V3/Ri)
(C.l)
node b:
(Vb-Vd)/R2 + (Vb-Va)/Ri = 0,
Vb(l/Ri + 1/R2) = ( Va/Ri) + (Vd/R2)
(C.2)
node c:
(Vc-Vf)/R3 + (Vc-Va)/R2 = 0,
Vc(l/R2+1/R3) = ( Va/R2) + (Vf/R3)
(C.3)
node e:
Ve /R4 + (Ve-Vd)/R3 = 0,
Ve(l/R3+1/R4)= Vd/R3
(^^^
72

node f
(Vf-Vo)/R4 + (Vf-V,)/R3 = 0,
Vf(l/R3+l/IU) = ( Vo/R4) + (Ve/R3)
(C.5)
Since the gains of the op amplifiers are very high, Vb = V2, V, = Vi, Vc = Vf can be
assumed. Therefore, from node f, Vf is shown as
Vf={R3/(R3+R4)}Vo+{R4/(R3+R4)} Vc = Ve,
(C.6)
and from node e, Ve is shown as
Ve={R4/(R3 + R4)}Vd.
(C.7)
Equation C.8 can be obtained by equating two expressions equations. C.6 and C.7,
Vd= (R3/R4)Vo + Vc.
(C.8)
By putting equation. C.8 in node b, equation C.9 is obtained.
Ve={(Rl+R2)/Rl}V2-(R2/Rl)(Vi-R3/R4)Vo.
(C.9)
From node a:
Vc={(Ri + R2)/Ri}Vi-(R2/Ri)V2.
(CIO)
Finally, equation C.l 1 is shown below.
Vo= {l+(2R2/Rl)}(R4/R3)(V2-Vi).
(C.ll)
73

APPENDIX D
THE SUBCIRCUITS OF THE LOCK-IN AMPLIFIER
74

Figure D. 1: Instrumentation amplifier
75

* m
u
CO
•o
c
02
Q

Figure D.3: Phase shifter
77

3
d
78

- ao a.
z
^tr-
3r>
-Ai^
ao
c«
o
2 -
O
3
.-^dr
3Q .
IN •'
Ml«»^
-^l=^-^^
a
: ^
o
3
Q
IZ
2 " T '
_J \^
" g • 1^—I
o
2 - •-ilf^^
^^r-
2 o >
o
L^
a
o
1
-—\r^
3^
a?
5^
3 ^
••-*-•—^

Y3
MsdP
^MP
M>dr
IVfisI
IVb^
Biaj'fi
i—Hi^
Ml
Mirir
Rr>-
M>
Ml|_
^
i«s

iQ—"
3
JD
3
O.
"3
o
c/]
cd
3
I
j=
c/)
3
0.
k.
O
Q
3
ao
IZ
81

liT4.
"cnir
23.
o _ t *
* 1 3
juO-^^tu
117 IT
.32 3 T*T ~
3
£
itr
« i
4- '
\ D • ^ ar-i
« I a
s
%
o
a
' 13
%
o
a
-^ -0
lir
JfL
-lii
I
a
JTU.
JQ^"
3
3
O
a
b>
o
o
3
O
C/5
•n r?
E
C

APPENDIX E
OUTPUT PLOTS
83

• C:\LISZT\TEST\TOLG.SCH
Dace/Time run: 12/16/95 18:42:41
1.6mV
(A) The dc feedback
Temperature: 27.0
1.2mV
0.8mV
1.00004mV^
l.OOOOOmV-S
SEL»
0.4mV
n V(Vin)
1.00008mV-r-
0.99996mV-
0.99 992mV + T---
Os
100ms
n V(HBl.Vouc)
— -1 —
200ms 300ms 400ms
Time
H
500ms
Dace: December 16, 1995
Page 1 .me: 18:45:13
Figure E. 1: The measure result od the dc feedback
84

Date/Time run: 12/18/95 02:2'o:V9^^'^^'^^'^^^'^^^^^-^^"
Temperacure: 27.0
(A) The open-loop cransfer
6.OV-r-------:..r. .....'. ^ ^^^^^ ^"^ °"^P"^ swing limices
4.0V-i
(15.p00m.4.5686)
2.0V-;
OV
(0.000,57.152u)
i/
f'
«che open-loop
I
cansfer curve
•2.0V-.
-4.0V-I
I
(-15.S00m,-4.8224)
•6.0V-f
-5.0V
[£|V(OP.VOUC)
I
OV
V Vin
^
5.0V
M: (-20.OOOm,-4.8328) A2 : (1 • 965C , 4 . 6823 ) DIFF1.^) : (-1. 9850,-9 . 515;
Dace: December 18, 1955 Page 1 Time: 02:25:38
Figure E.2: The open-loop transfer curve and output swing limits
85

Figure E.3: The simulation method of slew rate and setting time
86

* C:\LISZT\NOP\TEST\TSL.SCH
Dace/Time run: 12/18/95 03:22:49 Temperacure: 27.0
2 . OV - •
(A) Slew race cind seccing
cime
OV
-2.0V-'-
= V{Vin)
(6.2833U,2.0056)
2. OV T.
I'.
/'X.
l.OV-
-l.OV-
4.0V-
.-SR
1 ;
OV-
• \
(1.6833 u,-2.0076)
-2 . OV-• ; , 1 •'y'sr-r .
+ SR
(5.0379U,-1-9532)
-^!
Seccing
time
SEL».
-4.0V-t-
--•--
Os
2us
5 V(C4:2)
Dace: December 18, 1995
4us
Page 1
6us
Time
— r -
8us
lOus
^
12us
Time: 03:41:45
Figure E.4: Simulation result of slew rate and settmg rate
87

PERMISSION TO COPY
In presenting this thesis in partial fulfillment of the
requirements for a master's degree at Texas Tech University or
Texas Tech University Health Sciences Center. I agree that the Library
and my major department shall make it freely available for research
purposes.
Permission to copy this thesis for scholarly purposes may
be granted by the Director of the Library or my major professor.
It
is understood that any copying or publication of this thesis for
financial gain shall not be allowed without my further written
permission and that any user may be liable for copyright infringement.
Agree
(Permission is granted.)
^le.:L Co A^-_i £\ c^G
student's Signature
Date
Disagree
(Permission is not granted.)
Student's Signature
Date