MEMS Solution for Semiconductor Probing - Semiconductor Wafer ...
MEMS Solution for Semiconductor Probing - Semiconductor Wafer ...
MEMS Solution for Semiconductor Probing - Semiconductor Wafer ...
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矽 晶 源 高 科 股 份 有 限 公 司<br />
SCS Hightech Inc.<br />
<strong>MEMS</strong> <strong>Solution</strong> <strong>for</strong> <strong>Semiconductor</strong> <strong>Probing</strong><br />
South-Western Testing Workshop Presentation<br />
Presented by Dr. Howard Hsu<br />
06-06-2005
Presentation Overview<br />
Introduction<br />
- Device Geometry vs. IC Characteristics<br />
- Device Geometry vs. Pad Layout Rule and Package Technology<br />
- Classical <strong>Probing</strong> Technology is Insufficient at These Circumstances<br />
- Mechanical <strong>Probing</strong> Has Shown Productivity Degradation in Volume Production<br />
- <strong>MEMS</strong> VPC <strong>Solution</strong><br />
<strong>Probing</strong> Mechanism Comparison – Classical vs. <strong>MEMS</strong><br />
- Structural Differences<br />
- Material Combination & Technology Development<br />
- Mechanism Practices<br />
- Per<strong>for</strong>mance Comparison<br />
Development Challenges & <strong>Solution</strong>s <strong>for</strong> <strong>MEMS</strong> <strong>Probing</strong><br />
- Test, Assembly, and Operation<br />
- Reliability<br />
- IC Concerns<br />
<strong>MEMS</strong> <strong>Probing</strong> Technology Roadmap<br />
- Compliant <strong>Probing</strong> Structure<br />
- Tighter Control of Electrical Connection<br />
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<strong>MEMS</strong> <strong>Solution</strong> <strong>for</strong> <strong>Semiconductor</strong> <strong>Probing</strong><br />
Introduction
Introduction<br />
Device Geometry vs. IC Characteristics<br />
Process<br />
Technology<br />
製 程 技 術<br />
Components<br />
元 件<br />
Package<br />
封 裝<br />
Testing<br />
測 試<br />
SOI Capacitor<br />
Low k – dielectric ~ 2.2<br />
Stepper / Photo down to 0.065<br />
um<br />
Power – Increase<br />
Speed greater than 300 MHz<br />
Number of transistors –<br />
Increase<br />
Flip Chip Package<br />
Unferfill Development<br />
Pb-Free Solder Bump<br />
Vertical Probe Card<br />
<strong>Wafer</strong> Level Burn In<br />
KGD<br />
2003-2005<br />
2005<br />
Copper Process<br />
Low Resistance & Electronic migration<br />
High conductivity & Thermal Conductivity<br />
Low power consume & voltage, Energy storage<br />
Low leakage, capacitor effects, thermal conductivity,<br />
power consumption, and higher integration ability.<br />
Smaller transistor, large quantity, faster speed.<br />
Number of function, I/O, power, and Vdd & Vss are<br />
increasing.<br />
Speed faster than 300 MHz, package no wire bond.<br />
Number of I/Os increases too fast, there<strong>for</strong>e Array<br />
Design is the major trend.<br />
Materials, Reliability, MCM<br />
COB<br />
BBUL<br />
Remarks 備 註<br />
I/O pins over 1000<br />
High speed test<br />
Burn-in and test be<strong>for</strong>e package<br />
4
Introduction<br />
Device Geometry vs. Pad Layout Rule and Package Technology<br />
Device Technology is going further…<br />
Above 0.35um<br />
~2000<br />
0.35um ~ 0.18um<br />
2000~2002<br />
0.18um ~ 0.13um<br />
2002~2004<br />
0.13um below<br />
2004~<br />
IC Pad Layout Rule is getting more and more critical…<br />
Pad Pitch over 200um Pad Pitch over 200um Pad Pitch under 100um<br />
Linear Bump Design Stagger Bump Design Array Bump Design<br />
Package Technology has to be changed in order to fit the progress…<br />
Wire Bonding Package<br />
Flip chip package<br />
5
Introduction<br />
Classical <strong>Probing</strong> Technology is Insufficient at These Circumstances<br />
• Array Bump <strong>Probing</strong><br />
- Bump pitch will need to go lower than 150um<br />
- Maintenance free probe card<br />
- No burning tips<br />
- Short lead-time <strong>for</strong> order delivery<br />
- Consistent probing; no need to re-probe<br />
- High frequency probing<br />
• Aluminum Pad <strong>Probing</strong><br />
- Multiple sites<br />
- Small pad pitch ~ 50um<br />
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Introduction<br />
Mechanical <strong>Probing</strong> Has Shown Productivity Degradation in Volume Production<br />
Long repair time<br />
Pad Scratch<br />
Low probing life<br />
Burning Tips<br />
Results huge customer service ef<strong>for</strong>ts!!!<br />
Higher noise<br />
Long<br />
offline cleaning<br />
Low productivity<br />
Expensive<br />
rework<br />
Results a higher cost and lower efficiency!!!<br />
7
Introduction<br />
<strong>MEMS</strong> VPC <strong>Solution</strong><br />
Probe Tip<br />
Dimension<br />
Major Material<br />
Path Resistance<br />
Leakage<br />
<strong>MEMS</strong> Prove Card Specifications<br />
Probe Tip Height<br />
Max. <strong>Probing</strong> Area<br />
Min. <strong>Probing</strong> Pitch<br />
Accuracy<br />
Planarity<br />
Max. Current<br />
Shear Force<br />
Impendence Match<br />
1 st order Lead-time<br />
Repeat order LT<br />
8 ~ 12 um<br />
Up to 100um<br />
0 ~ 4 inch<br />
120um array, 35um LDI<br />
1um<br />
< 1.5um<br />
1 A<br />
100g / pin<br />
Nickel, Copper, and Silver<br />
2 ohm whole path<br />
50 ohm plus minus 5 ohm<br />
Smaller than 10nA at 5 volts<br />
6~8 weeks (design related)<br />
< 2 weeks<br />
Here is the solution!!<br />
Vertical Probe card <strong>for</strong> Aglient 93000<br />
Vertical Probe Card <strong>for</strong><br />
Cadence Type<br />
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<strong>MEMS</strong> <strong>Solution</strong> <strong>for</strong> <strong>Semiconductor</strong> <strong>Probing</strong><br />
<strong>Probing</strong> Mechanism Comparison – Classical vs. <strong>MEMS</strong>
<strong>Probing</strong> Mechanism Comparison – Classical vs. <strong>MEMS</strong><br />
Structure Differences<br />
Classical Vertical Type Probe Card<br />
- <strong>Probing</strong> tip will de<strong>for</strong>m cause open issue<br />
- Use PCB substrate<br />
- Need cleaning both online and offline<br />
<strong>MEMS</strong> Vertical Type Probe Card<br />
- Rigid tip will never de<strong>for</strong>m<br />
- Use ceramic substrate<br />
- Excellent co-planarity w/o manual adjustment<br />
- No cleaning, no re-probing, and no repairing<br />
10
<strong>Probing</strong> Mechanism Comparison – Classical vs. <strong>MEMS</strong><br />
Material Combination<br />
Material content of each part<br />
Automated<br />
Layout<br />
Nickel Tip<br />
Tip<br />
Copper RDL<br />
LTCC<br />
Substrate<br />
Copper<br />
Contact Pads<br />
RDL<br />
Via Area<br />
Ceramic Substrate<br />
Contact Pads<br />
Inter-relation of all process parameters: Chemicals, Temp., Plasma,<br />
double side process…. etc<br />
11
<strong>Probing</strong> Mechanism Comparison – Classical vs. <strong>MEMS</strong><br />
Technology Development<br />
<strong>MEMS</strong> VPC:<br />
Use the same process to fabricate the sub-micron level rigid tips.<br />
Can be applied to small pitch ~35um multiple die sorting.<br />
10um<br />
50um<br />
Classical VPC:<br />
Use the mechanical technology – minimum pitch is ~150um <strong>for</strong> array VPC<br />
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<strong>Probing</strong> Mechanism Comparison – Classical vs. <strong>MEMS</strong><br />
Technology Development<br />
Use the same process technology to fabricate the sub-micron level rigid tips <strong>for</strong> LCD<br />
driver IC probing.<br />
45um<br />
The 45um pitch rigid tip of dual-site<br />
LCD Driver IC probe card photo<br />
under microscope.<br />
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<strong>Probing</strong> Mechanism Comparison – Classical vs. <strong>MEMS</strong><br />
Mechanism<br />
Classical Vertical <strong>Probing</strong><br />
<strong>MEMS</strong> Vertical <strong>Probing</strong><br />
Be<strong>for</strong>e <strong>Probing</strong><br />
After <strong>Probing</strong><br />
Alignment is correct<br />
Tip sloping<br />
Residues<br />
Pressed bump<br />
Alignment is NOT<br />
correct<br />
Tip no change<br />
No residue<br />
Dimple<br />
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<strong>Probing</strong> Mechanism Comparison – Classical vs. <strong>MEMS</strong><br />
Per<strong>for</strong>mance<br />
Pad Pitch<br />
Classical C type Probe Card<br />
> 150 um<br />
SCS Diamond Vespa<br />
<strong>MEMS</strong> VPC<br />
Under 120 um<br />
Volume lead time<br />
First order<br />
Volume lead time<br />
Repeat order<br />
Multiple Site<br />
<strong>Probing</strong><br />
LDI probing<br />
Reprobing<br />
6 ~ 8 weeks<br />
4 weeks<br />
Depends on pad pitch<br />
Not available (other types,<br />
such as cantilever)<br />
Need<br />
5 ~ 6 weeks<br />
2 weeks<br />
Bumped pad only <strong>for</strong> now<br />
Already in evaluation sample<br />
No need<br />
Tip cleaning<br />
Need, because residue<br />
No need, nor online maintenance<br />
Comparison Table <strong>for</strong> different probe card<br />
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<strong>Probing</strong> Mechanism Comparison – Classical vs. <strong>MEMS</strong><br />
Per<strong>for</strong>mance<br />
<strong>MEMS</strong> Vertical Probe Card:Has passed several qualifications in Taiwan. Electrical<br />
per<strong>for</strong>mance (up to 3GHz) is superior to classical manufactured probe cards.<br />
3<br />
2.5<br />
Tester internal signal quality<br />
SCS<br />
Level (V)<br />
2<br />
1.5<br />
1<br />
C type<br />
Step 1<br />
Step 2<br />
Step 3<br />
0.5<br />
0<br />
100<br />
250<br />
350<br />
450<br />
550<br />
625<br />
Freq2 (MHz)<br />
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<strong>MEMS</strong> <strong>Solution</strong> <strong>for</strong> <strong>Semiconductor</strong> <strong>Probing</strong><br />
Development Challenges & <strong>Solution</strong>s For <strong>MEMS</strong> <strong>Probing</strong>
Development Challenges & <strong>Solution</strong>s For <strong>MEMS</strong> <strong>Probing</strong><br />
Test, Assembly, and Operation<br />
Testing<br />
Alignment focus issues – tip head is 10um<br />
SOP training <strong>for</strong> using <strong>MEMS</strong> probe card.<br />
Load Board<br />
Parallelism between PCB and LTCC<br />
Requires high stand-off.<br />
Tester Head Unit<br />
Solder<br />
Bump<br />
<strong>Wafer</strong><br />
Tester<br />
Load Board<br />
Chuck<br />
<strong>Probing</strong> Pressure<br />
About ~25g per tip with our tip head size.<br />
Tip shape<br />
Long neck cone shape <strong>for</strong> nonuni<strong>for</strong>mity<br />
of the bumps.<br />
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Development Challenges & <strong>Solution</strong>s For <strong>MEMS</strong> <strong>Probing</strong><br />
Reliability<br />
Durability <strong>for</strong> <strong>Probing</strong> ICs<br />
Excellent probing consistency (eliminate re-probing)<br />
Excellent probing life time – some model probed over 1.3M, other around 1M.<br />
Excellent maintenance – No need to repair anymore because lead time is short.<br />
Subject: SCS <strong>MEMS</strong> VPC <strong>for</strong> 8” wafers(633 pins)<br />
Tester/Prober: Agilent 93000/P600, P12/TEL<br />
Clean sheet: Enhanced 3M type C (type C + polish paper/pink type)<br />
Tool: Olympus microscope with micro meter<br />
Reading: Check pin high twice( from ULTCC to tip) <strong>for</strong> average.<br />
Be<strong>for</strong>e After 150K times After 350K times<br />
Result:<br />
- With clean process, the wear out rate is around 3~6 um after 12k times.<br />
19<br />
- Probe without clean process, there is almost no wear out (pin-height) after 350k insertions.
Development Challenges & <strong>Solution</strong>s For <strong>MEMS</strong> <strong>Probing</strong><br />
IC Concerns<br />
Rigid Tip<br />
After the tip probes into the bump, it will<br />
produce a “dimple” that looks like a crater.<br />
Dimple<br />
This has been notified and IC has also been<br />
checked out with reliability qualification.<br />
Dimple Reliability<br />
The reliability issue has been passed by a famous Taiwan foundries and<br />
packaging house.<br />
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<strong>MEMS</strong> <strong>Solution</strong> <strong>for</strong> <strong>Semiconductor</strong> <strong>Probing</strong><br />
<strong>MEMS</strong> <strong>Probing</strong> Technology Roadmap
<strong>MEMS</strong> <strong>Probing</strong> Technology Roadmap<br />
Compliant probing structure<br />
Tester Head Unit<br />
Tester<br />
Solder<br />
Bump<br />
Load Board<br />
<strong>Wafer</strong><br />
Ceramic<br />
Rigid Tip<br />
Chuck<br />
Compliant layer<br />
<strong>Wafer</strong><br />
To control the tip pressure<br />
New material needed!! For aluminum pads!!<br />
Thin-film RDL<br />
Aluminum Pad<br />
22
<strong>MEMS</strong> <strong>Probing</strong> Technology Roadmap<br />
Compliant probing structure<br />
Compliant layer<br />
To provide adjustment <strong>for</strong> improving contact uni<strong>for</strong>mity.<br />
Ceramic<br />
wafer<br />
wafer wafer wafer<br />
Aluminum Pads<br />
This layer is soft, re<strong>for</strong>m while the pressure applied.<br />
23
<strong>MEMS</strong> Product R&D Roadmap<br />
Tighter Control of Electrical Connection – Ceramic Section<br />
Improvement of the LTCC to improve the per<strong>for</strong>mance of the probe card<br />
Line width 75um<br />
Center to Center 125um<br />
Layer 1<br />
Layer 2<br />
Layer 3<br />
Layer 4<br />
Layer 5<br />
Layer N<br />
Catch Pad 75um<br />
Tape Thickness ~ 200um<br />
after co-fired<br />
Line Thickness < 10um<br />
after co-fired<br />
Printing<br />
Ground Thickness
End of Presentation<br />
Q & A<br />
SCS Hightech Inc. Website: http://www.scs.com.tw/, TEL +886-3-349-8999, FAX +886-3-346-8998, 2005 All Rights Reserved.<br />
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