ELVeN: Effective Layered Verification of Networks on chips

<strong>Effective</strong> <strong>Layered</strong> <strong>Verification</strong> <strong>of</strong>
<strong>Networks</strong> on chips
Bas Joosten
Julien Schmaltz
Freek Verbeek
Bernard van Gastel
Tuesday, 6March, 12

About me
• Education:
–Bachelor Applied Physics
–Master Applied Mathematics
• Hobbies
–Sailing
–Music
–Ampersand
Tuesday, 6March, 12

About me
• Education:
–Bachelor Applied Physics
–Master Applied Mathematics
• Hobbies
–Sailing
–Music
–Ampersand
–GeNoC (since Jan 2012)
Tuesday, 6March, 12

Future Work
xMAS
language
specify
Model
Instantiated Theorems
Functional Correctness
Starvation
Freedom
Evacuation
Memory
Consistency
Verilog
Instantiated Theorems
Tuesday, 6March, 12

Verifying hardware
xMAS
language
specify
Model
Instantiated Theorems
Functional Correctness
Starvation
Freedom
Evacuation
Memory
Consistency
Verilog
Instantiated Theorems
Tuesday, 6March, 12

Example: (one-bit) network
with two (simple) queues
irdy
D
Q
D
Q
irdy
Clk
Q
Clk
Q
trdy
trdy
AND
AND
AND
OR
OR
data
D
Q
D
Q
data
Clk
Q
Clk
Q
Tuesday, 6March, 12

Example: (one-bit) network
with two (simple) queues
Tuesday, 6March, 12

irdy
D
Q
D
Q
irdy
Clk
Q
Clk
Q
trdy
trdy
AND
AND
AND
OR
OR
data
D
Q
D
Q
data
Clk
Q
Clk
Q
Tuesday, 6March, 12

irdy
D
Q
D
Q
irdy
Clk
Q
Clk
Q
trdy
trdy
AND
AND
AND
OR
OR
data
D
Q
D
Q
data
Clk
Q
Clk
Q
Tuesday, 6March, 12

irdy
D
Q
D
Q
irdy
Clk
Q
Clk
Q
trdy
trdy
AND
AND
AND
OR
OR
data
D
Q
D
Q
data
Clk
Q
Clk
Q
Tuesday, 6March, 12

irdy
D
Clk
0
Q
Q
D
Clk
0
Q
Q
irdy
trdy
trdy
AND
AND
AND
OR
OR
data
D
Clk
0
Q
Q
D
Clk
0
Q
Q
data
Tuesday, 6March, 12

irdy
D
Clk
1
Q
Q
D
Clk
0
Q
Q
irdy
trdy
trdy
AND
AND
AND
OR
OR
data
D
Clk
1
Q
Q
D
Clk
0
Q
Q
data
Tuesday, 6March, 12

irdy
D
Clk
0
Q
Q
D
Clk
1
Q
Q
irdy
trdy
trdy
AND
AND
AND
OR
OR
data
D
Clk
1
Q
Q
D
Clk
1
Q
Q
data
Tuesday, 6March, 12

irdy
D
Clk
0
Q
Q
D
Clk
0
Q
Q
irdy
trdy
trdy
AND
AND
AND
OR
OR
data
D
Clk
1
Q
Q
D
Clk
1
Q
Q
data
Tuesday, 6March, 12

irdy
D
Clk
0
Q
Q
D
Clk
0
Q
Q
irdy
trdy
trdy
AND
AND
AND
OR
OR
data
D
Clk
0
Q
Q
D
Clk
0
Q
Q
data
Tuesday, 6March, 12

Approach
VeriLog-states
irdy
D
Clk
Q
Q
D
Clk
Q
Q
irdy
xMAS-states
trdy
trdy
AND
AND
AND
OR
OR
data
D
Q
D
Q
data
Clk
Q
Clk
Q
Tuesday, 6March, 12

Approach
VeriLog-states
irdy
D
Clk
Q
Q
D
Clk
Q
Q
irdy
xMAS-states
trdy
trdy
AND
AND
AND
OR
OR
data
D
Q
D
Q
data
Clk
Q
Clk
Q
some mapping
Tuesday, 6March, 12

Approach
Verilog HDL
xMAS
irdy
D
Q
D
Q
irdy
Clk
Q
Clk
Q
trdy
trdy
AND
OR
AND
OR
AND
Equivalence
data
D
Q
D
Q
data
Clk
Q
Clk
Q
Tuesday, 6March, 12

Approach
Verilog HDL
xMAS
irdy
D
Q
D
Q
irdy
Clk
Q
Clk
Q
trdy
trdy
AND
OR
AND
OR
AND
Equivalence
data
D
Q
D
Q
data
Clk
Q
Clk
Q
Some property
Tuesday, 6March, 12

Approach
Verilog HDL
xMAS
irdy
D
Q
D
Q
irdy
Clk
Q
Clk
Q
trdy
trdy
AND
OR
AND
OR
AND
Equivalence
data
D
Q
D
Q
data
Clk
Q
Clk
Q
Some property
Some property
Tuesday, 6March, 12

Approach
Verilog HDL
xMAS
irdy
D
Q
D
Q
irdy
Clk
Q
Clk
Q
trdy
trdy
AND
OR
AND
OR
AND
Equivalence
data
D
Q
D
Q
data
Clk
Q
Clk
Q
Some property
Some property
Tuesday, 6March, 12

Conclusions
• Design and verify NoCs
–Design with high-level languages
–Verify low-level implementations
Tuesday, 6March, 12