und Sensorsysteme auf der Basis von PN-Sequenzen - Technische ...

emt.tu.ilmenau.de

und Sensorsysteme auf der Basis von PN-Sequenzen - Technische ...

Ultrabreitband-Funktechniken

für

Kommunikation, Lokalisierung und Sensorik

SPP 1202 UKoLoS, , DFG, Berlin, 15. February, 2007

RF-Ha

Hardware Components for UWB

Localisation and Sensing

Ha L

S


Ha L S

HaLoS Presentation

Alternative Concepts for the

Monolithic Integration of Wideband

Localisation and Sensor Devices

based on PN-Sequences

Lehrstuhl für

Integrierte

Analogschaltungen

Y. Borokhovych 2 ; H. Gustat 2 ; S. Heinen 1 ; M. Kmec 3 ; R. Krämer

2 ;

M. Robens 1 ; C. Scheytt 2 ; J. Sachs 3 ; B. Sewiolo 4 ; R. Weigel 4 ; R.

Wunderlich 1 ;

2

1

Rheinisch-Westf

Westfälische Technische Hochschule Aachen

2

Brandenburgische Technische Universität t Cottbus

3

Technische Universität t Ilmenau

4

Friedrich-Alexander

Alexander-Universität t Erlangen-Nürnberg

rnberg


Ha L S

Outline

Lehrstuhl für

Integrierte

Analogschaltungen

• Introduction to HaLoS-Project

• Some UWB-system design aspects

• Introduction to SiGe:C-technology

• High speed ADC & DAC

• Analogue low noise components

• Power components

• Conclusions

3


Ha L S

HaLoS Consortium

Prof. Dr.-Ing. Stefan Heinen

Chair of Integrated Analog Circuits and Radio Frequency Systems

Rheinisch-Westf

Westfälische Technische Hochschule Aachen

Prof. Dr.-Ing. Rolf Krämer

Chair of (Wireless) Systems

Brandenburgische Technische Universität t Cottbus

Lehrstuhl für

Integrierte

Analogschaltungen

Lehrstuhl für

Integrierte

Analogschaltungen

Dr.-Ing. J. Sachs

Institute for Information Technology

Technische Universität t Ilmenau

4

Prof. Dr.-Ing. Dr.-Ing. habil Robert Weigel

Institute for Electronics Engineering

Friedrich-Alexander University of Erlangen-Nürnberg

rnberg


Ha L S

Visions and Rationale of HaLoS

• UWB Localization and Sensing

• Requirements differ from requirements for

communication

• Benefit from multi-octave bandwidth

Lehrstuhl für

Integrierte

Analogschaltungen

• Spectral limits do not apply

• New UWB concepts for flexible use

• New low-power UWB circuits and ultra-high speed

digital components and IP

• Innovative mixed-mode mode integration

5


Ha L S

Design Challenges within HaLoS

• System design and evaluation for different application scenarios

• High-speed

– ultra-wideband mixed signal integration

• On-chip cross talk

• Low noise figure over a large bandwidth

• Wideband matching of input- and output ports

Lehrstuhl für

Integrierte

Analogschaltungen

• Low power consumption of sub-systems

systems

• Active cancelling of narrow band interference

• On-chip interfaces between sub-systems

systems

6

15 GHz M-sequence M

generator

TU-Ilmenau


Ha L S

Intended HaLoS Project Strategy

Combine expertise of leading German research groups

HaLoS

EMT

• Sequence Generation

and Synchronization

1 MA

• UWB System

Lehrstuhl für

Integrierte

Analogschaltungen

IAS

LTE

UWB RX

High 2 Speed MA Digital

2 UWB MA

TX

7

UWB

SYS

Converters

1 MA

Library


Ha L S

Re-structured

HaLoS Project Strategy

Reduced funding required re-structuring and shift

/ reduction of work tasks:

• 66 % of planned man-power

• reduced money for chip manufacturing and

consumables

Lehrstuhl für

Integrierte

Analogschaltungen

⇒ renouncement on high performance SiGe-technology

⇒ replacement of digital high speed part by commercial FPGA

evaluation board (resulting in a reduced operational speed)

⇒ reduced activities in design of PN-sequence generator and

synchronisation

⇒ reduced number of elements in the UWB library

8


Ha L S

Re-structured

HaLoS Project Strategy

Lehrstuhl für

Integrierte

Analogschaltungen

IAS

Analog, , linear low noise

components

(receiver)

EMT

• High-speed digital (FPGA)

• UWB System

• Sequence Generation

and Synchronization

HaLoS

LTE

Power components

(linear, pulsed)

9

UWB

SYS

Converters

(ADC & DAC)

Library


Ha L S

HaLoS Project Set-up

UWB-Application

(e.g. other UkoLoS projects)

Lehrstuhl für

Integrierte

Analogschaltungen

10

desirable

specifications

Phase 1

Phase 2/3

UWB-system conception

EMRL – WP1

EMT - WP2

SYS - WP3

IAS - WP4

LTE - WP5

UWB-Library WP7

Combined

integration

of subsystems

Full system integration

EMT- WP6

Combined

integration

of subsystems

feasible

specifications

feedback on

feasible

parameters

of sub-systems

WP1: UWB-system conceptions

WP2: Sequence generation and

synchronization (reduced)

WP3: High speed A/D- and D/A converters

WP4: UWB-receiver

frontend

WP5: UWB-transmitter

frontend

WP6: High speed pre-processing

processing (FPGA)

WP7: UWB-library


Ha L S

Outline

• Introduction to HaLoS-Project

• Some UWB-system design aspects

• Design Corset/Design Goals

• Figures of Merit

• Power saving by PRBS-stimulation

• Power saving by difference sampling

Lehrstuhl für

Integrierte

Analogschaltungen

• Introduction to SiGe:C-technology

• High speed ADC & DAC

• Analogue low noise components

• Power components

• Conclusions

11


Ha L S

The UWB System Design Corset

Power dissipation

Power emission

Ambiguity range;

Frequency resolution

Lehrstuhl für

Integrierte

Analogschaltungen

Time stability

(Jitter, drift)

Data throughput

UWB

Electronics

Number of

measurement

channels

Update rate;

Measurement speed

Bandwidth

Operational band

Signal to noise ratio

Dynamic range

Adaptability to

various applications

12


Ha L S

Signal to Noise Ratio

Lehrstuhl für

Integrierte

Analogschaltungen

power spectral density

[dBm/Hz]

Simplified Spectrum

B

signal

perturbation

frequency [Hz]

Ψ 0

N

SNR

=

E

N

acc

Accumulated

signal energy:

E ≈ ηΨ0B

acc T acc

Average

signal power

13

T acc

η

time to accumulate the energy

efficiency of data gathering

(sub-sampling)


Ha L S

Accumulation Time T acc

(for quasi stationary measurement)

v

moved antenna

2T acc

B v <

max

c

Lehrstuhl für

Integrierte

Analogschaltungen

v

moved target

4T acc

B v <

max

c

v

multiple scattering

2kT acc

B v <

max

c

14

c

v max

k

speed of light

max. dislocation speed

number of reflections


Ha L S

Receiver Design Considerations

• Respect the required bandwidth

Lehrstuhl für

Integrierte

Analogschaltungen

• Maximise SNR by lowering the sub-

sampling factor - increasing the data

capturing rate (i.e. increase efficiency of

the receiver)

• Use maximum allowable accumulation

time (e.g. by averaging) – also reduces

data rate

15

• Respect power dissipation limits


Ha L S

Figures of Merit

Describe efficiency of components

ADC/DAC:

FoM = 2

P

ENOB fs

ADC: about 1…5 pJ /conversion (BW dependent)

DAC: roughly 3 … 10 times less than ADC

Lehrstuhl für

Integrierte

Analogschaltungen

Amplifiers:

??

FoM =

power dissipation

gain ∗dynamic range ∗ bandwidth

16

Digital systems:

??

FoM =

power dissipation

word length ∗ clock rate


Ha L S

Strategies for Power Saving

Reduce the FoM-Value

• Question of Semiconductor Technology

• Question of Circuit design (designer experience)

Lehrstuhl für

Integrierte

Analogschaltungen

Play with ENOB, , dynamic range and word

length

• Question of device concept

use spread wideband signals

gather update signal rather the whole signal

• Question of measurement scenario/application

17


Ha L S

M-Sequence (PRBS) Approach

Stimulus

RF-clock

f c

Shift

Register f c /2

to the sensor

Lehrstuhl für

Integrierte

Analogschaltungen

Binary

divider

Sensor response

Signal

processing

Averaging

ADC

T&H

from the sensor

18


Ha L S

M-Sequence

– Time shape

Idealised 4 th order M-SequenceM

one period

T

0

= N t c

V MS

Lehrstuhl für

Integrierte

Analogschaltungen

time

t c = 1/f c

one chip

(unit delay of shift register)

Number of chips:

N = 2 n -1

19

Time-Bandwidth-Product:

TB ≈ n

2 −1


Ha L S

Optimum Spectral Coverage

Period of stimulus = 1 µs s = 1/B 0

Ψ0 = − 40 dBm/MHz

B =1 0

MHz

Lehrstuhl für

Integrierte

Analogschaltungen

number of data points

10 4

10 3

10 5 shift register length

bandwidth 2 GHz

bandwidth 8 GHz

bandwidth 4

GHz

20

10 2

8 10 12 14 16


Ha L S

Signal Amplitude

Period of stimulus = 1 µs s = 1/B 0

Ψ0 = − 40 dBm/MHz

B =1 0

MHz

Lehrstuhl für

Integrierte

Analogschaltungen

amplitude [V] at 50 Ohms

10 -1

-13 dBm

10 0 shift register length

5 dBm

-1 dBm

-7 dBm

total power

21

10 -2

8 10 12 14 16


Ha L S

Data Gathering by sub-sampling

sampling

Prerequisites: • Periodic signal

• Equivalent sampling rate f s,eq = f c

• Operational bandwidth DC … f c /2

One needs one sample per chip of the M-

Sequence independent from the order of

capturing → interleaved sampling.

Lehrstuhl für

Integrierte

Analogschaltungen

22

Sampling control by binary divider:

• Simple, robust, very time stabel (low drift/jitter)

• Absolute equidistant sampling interval

• Simple to adjust to ADC speed

Note: Sub-sampling reduces receiver efficiency,

but saves hardware costs and power.

Efficiency:

η ≈ 2

−m

m – number of binary stages


Ha L S

Power Saving by optimised Data Handling

Observation: usually huge mismatch between

time scale of wave interaction (order of ns) ↔

changes within scenario under test (order > ms)

Small increments between consecutive

measurements

Lehrstuhl für

Integrierte

Analogschaltungen

Application specific degrees of freedom:

23

• How many Bits the ADC does really need?

• What dynamic range amplifiers must really have?

• What is the word length of high-speed digital

processing, which is really required?


Ha L S

Measurement Example: Through Wall Radar

Breathing person behind wall

Radar data

(measurement data after matched Filtering)

Lehrstuhl für

Integrierte

Analogschaltungen

propagation time [ns]

0

10

20

30

40

50

Static signal!

0 5 10 15 20 25 30 35 40

0.02

0.01

0

-0.01

-0.02

observation time [s]

24


Ha L S

Measurement Example: Through Wall Radar

Lehrstuhl für

Integrierte

Analogschaltungen

propagation time [ns]

14

16

18

20

22

24

Radar data with background removed

5 10 15 20 25 30 35 40

observation time [s]

x 10 -3

1.5

1

0.5

0

-0.5

-1

-1.5

25


Ha L S

Measurement Example: Through Wall Radar

Lehrstuhl für

Integrierte

Analogschaltungen

Measurement data with background removed

Measurement data with background removed

(no matched filtering applied, residual of M-sequence shown)

propagation time [ns]

0

10

20

30

40

50

0 5 10 15 20 25 30 35 40

observation time [s]

x 10 -5

1.5

1

0.5

0

-0.5

-1

-1.5

26


Ha L S

Receiver burden

Amplitude Probability Distribution

Lehrstuhl für

Integrierte

Analogschaltungen

magnitude [dB]

0

-10

-20

-30

-40

-50

-60

Compression

gain

Impulse response

Possible reduction

of receiver dynamic

Measured signal

-70

-80

Difference signal

-90

27

-100

1e-008 0.1 5 50 90 99

probability [%]


Ha L S

Outline

Lehrstuhl für

Integrierte

Analogschaltungen

• Introduction to HaLoS-Project

• Some UWB-system design aspects

• Introduction to SiGe:C-technology

• Overview

• Low cost: SGB25VD

• High performance: SG25H1

• Complementary: SG25H2

• Multi-Purpose: SG25H3

• High speed ADC & DAC

• Analogue low noise components

• Power components

• Conclusions

28


Ha L S

SiGe-Technology: Portfolio at IHP

Technology

Object

SGB25VD

SG25H1

“Low-Cost” BiCMOS w/ LV/MV/HV HBTs

and LDMOS

„High Performance“ BiCMOS

Lehrstuhl für

Integrierte

Analogschaltungen

SG25H2

SG25H3

“Complementary” BiCMOS

w/ npn + pnp HBTs

„Multi Purpose“ BiCMOS w/ LV/MV/HV HBTs

LV : low breakdown voltage

MV : medium breakdown voltage

HV : high breakdown voltage

29

• 0.13µm SG13H1 (250/300 GHz) about to start


Ha L S

SiGe-Technology: CMOS platform with SiGe:C HBT

Lehrstuhl für

Integrierte

Analogschaltungen

State-of-the-art

RF CMOS

process

4 Al metal layers;

including MIM

capacitor

3 µm thick 5 th Al

layer optional

Cross-section of 200 GHz SiGe:C BiCMOS

technology SG25H1 (incl. optional metal 5)

30


Ha L S

SiGe:C BiCMOS with minimal mask count (SGB25VD)

• Low-cost SiGe BiCMOS: CMOS + 1 additional mask

• HBT differentiation by collector implants

Lehrstuhl für

Integrierte

Analogschaltungen

Device Parameter Value

all Current gain 190

BV EBO > 2.5 V

Peak f T / f max 30 / 70 GHz

NPN-HV BV CEO

7 V

BV CBO > 20 V

Peak f T / f max 50 / 95 GHz

NPN-MV BV CEO 4.2 V

BV CBO 16 V

Peak f T /f max 80 / 95 GHz

NPN-LV BV CEO 2.4 V

7.0 V

BV CBO

NPN-HV

NPN-MV

SIC

Coll.

Well

SIC

Coll.

Well

Deep P Implant (SC)

emitter

base

n-

Well

n-

Well

collector

S

C

31

NPN-LV

SIC

Coll.

Well

n-

Well

S

C


Ha L S

High-performance

SiGe:C BiCMOS (SG25H1)

• One active region (no STI stripe

between emitter and collector

contact) R C

, C CS

low

• Fastest IHP technology

Lehrstuhl für

Integrierte

Analogschaltungen

32

SG25H1 HBT parameters

Device Parameter Value Unit Remark

Beta 200 @ V = 0.7 V

BE

Peak f T / f max 190 / 190 GHz @ V CE = 1.5 V

NPN200

CBO

BV CEO 1.9 V Extrapolated )

BV 4.5 V @ 0.1 µA

BV EBO 2.0 V @ I EB = 1 µA

NPN201

Beta 200 @ V BE = 0.7 V

Peak f T / f max 180 / 220 GHz @ V CE = 1.5 V

BV CEO 1.9 V Extrapolated

BV CBO 4.5 V @ 0.1 µA

BV EBO > 1.5 V @ I EB = 1 µA


Ha L S

High performance Complementary BiCMOS (SG25H2)

• Same low-R C , low-C CS collector construction

as in SG25H1

• Fastest C-BiCMOS technology worldwide

Lehrstuhl für

Integrierte

Analogschaltungen

33


Ha L S

High performance Complementary BiCMOS (SG25H2)

Lehrstuhl für

Integrierte

Analogschaltungen

SG25H2 HBT parameters

Device Parameter Value Unit Remark

NPN200

Beta 200 @ V BE = 0.7 V

Peak f T / f max 170 / 170 GHz @ V CE = 1.5 V

BV CEO 1.9 V Extrapolated a)

BV CBO 4.5 V @ 0.1 µA

BV EBO 2.0 V @ I EB = 1 µA

PNP90

Beta 100 @ V EB = 0.7 V

Peak f T / f max 90 / 120 GHz @ V EC = 1.5 V

BV CEO -2.8 V Extrapolated a)

BV CBO -4.0 V @ 0.1 µA

BV EBO -3.0 V @ I BE = 1 µA

a)

Extrapolated from the I C /A E = (0.3-0.75)mA/µm 2 part of the V CE (I C ) characteristics

34


Ha L S

High-performance low-cost

SiGe BiCMOS (SG25H3)

• Various HBT types by collector variations,

including f max =180 GHz or BV CEO = 7 V

• CMOS flow + 6 additional masks

Lehrstuhl für

Integrierte

Analogschaltungen

35

SG25H3 HBT parameters

Device Parameter Value Unit Remark

all

Current gain 150 @ V BE = 0.7 V

BV EBO 3.0 V @ I EB = 1 µA

Peak f T / f max 120 / 140 GHz @ V CE = 1.5 V

npnH3shp1 BV CEO 2.3 V Extrapolated

BV CBO 5.0 V @ 0.1 µA

Peak f T / f max 110 / 180 GHz @ V CE = 1.5 V

npnH3PI BV CEO 2.3 V Extrapolated

BV CBO 5.0 V @ 0.1 µA

Peak f T / f max 45 / 140 GHz @ V CE = 1.5 V

npnH3MV BV CEO 5.0 V Extrapolated

BV CBO 15.5 V @ 0.1 µA

Peak f T /f max 25 / 80 GHz @ V CE = 1.5 V

npnH3HV BV CEO 7.0 V Extrapolated

BV CBO 21.0 V @ 0.1 µA


Ha L S

Outline

Lehrstuhl für

Integrierte

Analogschaltungen

• Introduction to HaLoS-Project

• Some UWB-system design aspects

• Introduction to SiGe:C-technology

• High speed ADC & DAC

• Goals

• THA structure

• Quantizer architecture

• Summary

• Analogue low noise

components

• Power components

• Conclusions

36


Ha L S

Goals for ADCs in UWB applications

Lehrstuhl für

Integrierte

Analogschaltungen

• Ultra-high sampling rate:

• High bandwidth (ERBW):

• Low resolution (ENOB):

• Min. power consumption:

UWB HaLoS

general goals

>1 2.5 GS/s

>0.5 4.5 GHz

1-5 4 bit


Ha L S

UWB ADC: Structural design choices

Lehrstuhl für

Integrierte

Analogschaltungen

THA variants

Architecture

variants

38


Ha L S

UWB ADC: THA structure

High-speed THA circuits

Diode bridge

Switched amplifier

Single amplifier

Multiple amplifiers

Lehrstuhl für

Integrierte

Analogschaltungen

Switched emitter follower (SEF)

npn

npn/pnp

SEF

Switched

diff. outputs

39

Simple & fast: Lowest power candidates


Ha L S

UWB ADC: THA structure

High-speed THA circuits

Diode bridge

• 1995 Razavi: 0.2G 10b

Switched amplifier

Single amplifier

Multiple amplifiers

Lehrstuhl für

Integrierte

Analogschaltungen

40

Switched emitter follower (SEF)

npn

• 1992 Vorenkamp,

Verdaasdonk: 0.12G 10b

• 2004 Lee et al.: 10G 5b

1Vpp

• 2006 Borokhovych et al.:

10G 7b 1Vpp

npn/pnp

• 2006 Halder et al.:

10G 8b 2Vpp

(Sim.)

(Designs in IHP technology)

SEF

• 2000 Fiocchi

et al.

• 2005 Lu et al.:

10G 8b 1Vpp

Switched

diff. outputs

• 1997

Baumheinrich,

Pregardier:

1G 10b

Starting point for HaLoS THA

(BW+, Power-)


Ha L S

UWB ADC: Quantizer architecture

High-speed amplitude quantizers

Full Flash

Analog Gray

encoding

Flash +

Folding

Lehrstuhl für

Integrierte

Analogschaltungen

41


Ha L S

UWB ADC: Quantizer architecture

High-speed amplitude quantizers

Full Flash

Analog Gray

encoding

Flash +

Folding

[Corcoran 1984]

• Max. speed

• Less speed

• Less speed

Lehrstuhl für

Integrierte

Analogschaltungen

• Power ~ 2 N

• Lower FOM

• Popular

• Good for low

resolution N

• Power ~ 2 N-1

• Better FOM

• Unusual

• Good for

2 < N < 4..8

• Power ~ 2 C +2 N-C

• Better FOM for

larger N

• Popular

• Good for

N > 6..8

42

Under investigation for HaLoS


Ha L S

UWB ADC: Bandwidth/Power trade-off

Common Full

Flash ADC

• Reference ladder at Vref

(differerential)

Lehrstuhl für

Integrierte

Analogschaltungen

• Vin: single-ended signal

• High bandwidth

• High noise (kick-back

from clock etc.)

• Single-ended noise

suppression

requires high power

43


Ha L S

UWB ADC: Bandwidth/Power trade-off

Differential

Full Flash

ADC

• Resistor ladder at Vin

(differerential)

• Vref: defined by Iladder

and 2 Resolution * Rtap

Lehrstuhl für

Integrierte

Analogschaltungen

• Bandwidth limited

by Rtap *Ccomp_in

• Inherently good noise

suppression

• Low Rtap for high BW:

- Realisation in metal

- Requires high Iladder

• Possibly reduced input

swing: Needs more

comparator power

or less clock rate

44


Ha L S

UWB ADC: Bandwidth/Power trade-off

Lehrstuhl für

Integrierte

Analogschaltungen

45

Analog Gray

encoding

Corcoran 1984,

Colleran 1993

• Analog encoding

• Only N comparators

needed

• No resistor ladder

V in

• Vref: defined by VA ..VZ

• Bandwidth limited

by RC *CLSB_out

• Stronger BW limit is fT :

Signal BW is multiplied

by 2 N

• Useful if signal

BW


Ha L S

UWB ADC: Summary

Lehrstuhl für

Integrierte

Analogschaltungen

46

• HaLoS UWB-ADC goal is to go beyond state of art

in terms of low power

• Switched Emitter Followers do well for Track-and

and-Hold

Amplifier; f s =2.5 GHz can be achieved, ERBW = 4.5

GHz is challenging at low-power

• Various trade-offs in the parameter space

• Input bandwidth (BW) vs. power dissipation

• Input swing vs. noise and bandwidth

• Input swing vs. clock rate and power

• Noise suppression vs. power

• Power constraint: ERBW, f s , ENOB

• New solutions to maintain BW at lowered power are

under investigation at BTU


Ha L S

Outline

Lehrstuhl für

Integrierte

Analogschaltungen

47

• Introduction to HaLoS-Project

• Some UWB-system design aspects

• Introduction to SiGe:C-technology

• High speed ADC & DAC

• Analogue low noise components

• Broadband Low Noise Amplifier

Approaches in Literature

• LNA with Matching Networks

• Resistively Degenerated Common

Emitter LNA

• Common Base LNA

• Comparison

• Outlook: Promising Approaches

• Power components

• Conclusions


Ha L S

Comparison: Values by Literature

Lehrstuhl für

Integrierte

Analogschaltungen

Source BW (GHz) G max (dB) NF (dB) S 11 (dB) P (mW) G Ripple (dB)

A. Ismail

A. Abidi

A. Bevilacqua

A. Niknejad

C. Kim, M. Jung

S. Lee

P. Datta

M. Fischer

S. Vishwarkarma

S. Jung, Y. Joo

H. Knapp

D. Zöschg

J. Lee

J. D. Cressler

3-10 21.0

3.1-6.1 17.0

2.5-4.5

2.5-7.4


Ha L S

LNA with Matching Networks

• Reference Structure by P. K. Datta and G. Fischer

• Input- and Output Matching by Resonant Networks

Lehrstuhl für

Integrierte

Analogschaltungen

49


Ha L S

LNA with Matching Networks

Lehrstuhl für

Integrierte

Analogschaltungen

50

BW (GHz) I DC (mA) V CC (V) G V (dB) NF (dB) P 1dB (dBm) S 11 (dB)

2-10.6 10.44 2.5 15.7-12.7 3.3-4.0 -22.6


Ha L S

Resistively Degenerated Common Emitter LNA

• Reference Structure by H. Knapp, D. Zöschg, , T. Meister, K.

Aufinger, , S. Boguth and L. Treitinger

• Improved Matching and Flat Gain Response Achieved

Using Shunt Feedback via Emitter Follower T 2

Lehrstuhl für

Integrierte

Analogschaltungen

51


Ha L S

Resistively Degenerated Common Emitter LNA

Lehrstuhl für

Integrierte

Analogschaltungen

52

BW (GHz) I DC (mA) V CC (V) G V (dB) NF (dB) P 1dB (dBm) S 11 (dB)

2-15 3.4 3.3 17-14 2.8-3.4 -16.6


Ha L S

Differential Common Base (CB) LNA

• Flat Gain Response by Using a Resonant Load

• Input Matching by Adapting g m and R e

Lehrstuhl für

Integrierte

Analogschaltungen

53


Ha L S

Differential Common Base (CB) LNA

Lehrstuhl für

Integrierte

Analogschaltungen

54

BW (GHz) I DC (mA) V CC (V) G V (dB) NF (dB) P 1dB (dBm) S 11 (dB)

1-12 2.2 2.5 15-12 3.8-4.4 -13.6


Ha L S

Differential Common Emitter (CE) Amplifier

• Standard Differential Pair with Cascode Devices and

Resonant Load

• Employed Only in a Cascade of Common Base, Common

Emitter and Common Collector Amplifiers

Lehrstuhl für

Integrierte

Analogschaltungen

55


Ha L S

Combination: CB, CE and Common Collector Amplifier

Lehrstuhl für

Integrierte

Analogschaltungen

56

BW (GHz) I DC (mA) V CC (V) G V (dB) NF (dB) P 1dB (dBm) S 11 (dB)

1-15 7.56 2.5 25-22 4.9-7.5 -28.2


Ha L S

Comparison: Simulation Results

Lehrstuhl für

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Source BW (GHz) G V (dB) NF (dB) S 11 (dB) P (mW)

P. Datta

M. Fischer

2-10.6 15.7-12.7 3.3-4.0


Ha L S

Outlook: Promising Approaches

Lehrstuhl für

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• Common Base Amplifier

• Bandpass Based Resonantly Tuned

Amplifier

4Reference Structures by

- A. Bevilacqua and A. M.

Niknejad

- A. Ismail and A. A. Abidi

• Multiple Resistive Feedback LNA

4Reference Structures by

- M.-C. Chiang, S.-S. Lu, C.-C.

Meng, , S.-A. Yu, S.-C. Yang and

Y.-J. Chan

- M. Shi, B. Shi and Y. W. Chia

- J. Lee and J. D. Cressler

58


Ha L S

Outline

Lehrstuhl für

Integrierte

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• Introduction to HaLoS-Project

• Some UWB-system design aspects

• Introduction to SiGe:C-technology

• High speed ADC & DAC

• Analogue low noise components

• Power components

• Literatur Research: Status Quo

• Applications in HALOS

• Broadband PA Modes and

Architectures

• Design Challenges

• Outlook

• Conclusions

59


Ha L S

Comparison: Status Quo

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Cascaded emitterfollower in SiGe *

0 - 60 GHz, 16 dB diff. gain

3 dBm linear output power

power consume 770 mW

chip size 550 µm x 550 µm

Traveling Wave Amplifier in CMOS **

3 dB corner frequency 8 GHz

max. 17 dB gain

3.5 dBm linear output power

power consume 100 mW

fig. 1*

fig. 2**

60

* [Per04] A 60 GHz Broadband Amplifier in SiGe Bipolar Technology

** [Gre04] Fully Integrated Distributed Amplifier in CMOS Technology

optimized for UWB Transmitters


Ha L S

Applications

Digital M-Sequence

Radar

„DC“ to 5 GHz

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MSCW-Radar

M-Sequence modulated

Continous Wave Radar

3 GHz to 10 GHz

→ fractional/relative bandwidth >100 %

61

* [Sac04] Basics of Ultra Wideband Technique


Ha L S

Linear PA Modes

Class A

R

opt

=

V

I

max

max

−V

operating angle Θ = 360°

theoretical PAE 50 %

practical PAE 20-30 %

K

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Class B

operating angle Θ = 180°

theoretical max. PAE 78,5 %

Class AB

operating angle 180°< Θ < 360°

fig. 1*

62 * [Vir04] Broadband Microwave Amplifiers

fig. 2*


Ha L S

UWB PA-Architectures

Architectures

Broadband Feedback and Lossy Matched Amplifiers *

+ less complex than traveling wave circuits

+ higher PAE

+ cost effective

+ lower chip size

- low output power

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Distributed Amplifiers (DAs)

(Traveling

Wave, Cascaded Single Stage) *

+ very wide bandwidth

+ inherent circuit stability characteristics

- low output power and PAE-performance

63

* [Vir04] Broadband Microwave Amplifiers


Ha L S

TWA Principles

Lecher Line

β = ω ⋅

ω

v = = β

Z l

=

L'

C'

L'C'

1

L'

C'

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Distributed Amplifier

input/output capacitors of the HBT and inductors/capacitors

match to source and load impedance over the desired bandwidth


almost constant group delay because of the linear phase v

64


Ha L S

High Power DA Topologies

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Capacitively Coupled Distributed

Amplifer*

highest voltage swing at the first

gain stage



simultanous gain compression by

varying the base capacitances

larger transistors possible without

lowering the cut-off frequency

Tapered Distributed Amplifier *

PAEmax(ClassA-TWA) = 25%



force the total transistor output

current in forward direction

first gain stage with Z0, second gain

stage with Z0/2, third with Z0/3 …

fig. 1*

fig. 2*

65

* [Rob01] RFIC and MMIC design and technology


Ha L S

UWB PA Challenges

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Amplifier must see the optimum impedance

Z opt over the whole frequency range

Load-Line Matching


Load-Pull Simulation

(Contour plot for npnVH cascode

configuration at 4 GHz and 12 GHz)

SiGe Substrate Losses must be minimized

High quality inductors and transmission

lines


Loss Compensation by using „Attenuation

Compensation Techniques“ *

Low Input Impedance of HBTs für TWAs

4 GHz

66

* [Kob94] A Novel HBT Distributed Amplifier Design Topology

Based on Attenuation Compensation Techniques

12 GHz


Ha L S

Outlook

• Comparism of reference structures in SiGe Bipolar

Broadband Feedback

Traveling Wave

Cascaded Single Stage Distributed Amplifier

• Optimization of passive components

High Quality Inductors

Biasing Networks

Lehrstuhl für

Integrierte

Analogschaltungen

67


Ha L S

Conclusions

UWB concepts for localisation and sensing

Portable applications → low power consumption →

integrated hardware required

UWB library of components: flexible systems for

different application needs

Fundamental research

Lehrstuhl für

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Analogschaltungen

Broadband circuitry: LNA, PA

High speed ADC: novel concepts for high BW / P ratio

efficient receiver concepts: difference sampling

Integration level for UWB

68

Only by cooperation of competent research groups

Enabling new and innovative UWB applications

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