Power Management Design Guide for Altera® FPGAs and CPLDs ...
Power Management Design Guide for Altera® FPGAs and CPLDs ...
Power Management Design Guide for Altera® FPGAs and CPLDs ...
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<strong>Power</strong> <strong>Management</strong> <strong>Design</strong> <strong>Guide</strong> <strong>for</strong><br />
Altera ® <strong>FPGAs</strong> <strong>and</strong> <strong>CPLDs</strong><br />
Fall 2005<br />
Altera devices covered:<br />
Stratix ® II FPGA family<br />
Stratix ® FPGA family<br />
Cyclone FPGA family<br />
MAX ® II CPLD family<br />
Also features National’s FPGA solutions <strong>for</strong>:<br />
• Communications interface, including LVDS<br />
• High-speed data conversion<br />
• High-speed, low-power analog signal conditioning<br />
www.national.com/see/alterafpga<br />
N a t i o n a l<br />
Semiconductor<br />
The Sight & Sound of In<strong>for</strong>mation
Featured power products<br />
LM5070 <strong>Power</strong>-over-Ethernet single-chip solution<br />
• Fully compliant with IEEE 802.3af PoE st<strong>and</strong>ards<br />
• Delivers up to 14W of power from regular<br />
CAT-5 Ethernet cable<br />
• <strong>Power</strong>s all Altera Cyclone <strong>and</strong> most Stratix <strong>and</strong><br />
Stratix II FPGA designs without the need <strong>for</strong> wall<br />
adapters, batteries or any external power supply<br />
• Industrial temperature range<br />
• Evaluation boards <strong>and</strong> reference designs available<br />
• Available in TSSOP-16 <strong>and</strong> tiny, thermally<br />
enhanced LLP-16 packaging<br />
LM5070 <strong>Power</strong>-over-Ethernet powered device system<br />
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LM3670/71 600 mA SOT-23 synchronous buck regulators<br />
• Requires only 3 external components<br />
• High switching frequency, ceramic capacitors<br />
<strong>and</strong> SOT23-5 package enables an extremely<br />
small total solution<br />
• 600 mA, 2 MHz (LM3671) <strong>and</strong><br />
350 mA, 1 MHz (LM3670) versions available<br />
• Can achieve 95% efficiency with just a 2.2 µH<br />
small inductor<br />
• Automatic PWM-PFM mode switching enables<br />
longer battery life <strong>and</strong> extended st<strong>and</strong>-by times<br />
• Fixed output voltage <strong>and</strong> adjustable versions<br />
available<br />
• Industrial temperature range<br />
• Ideal <strong>for</strong> CPLD <strong>and</strong> low-power FPGA supplies<br />
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LM3671 Simple block diagram<br />
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LM3671 Efficiency vs. load current<br />
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ii
Contents<br />
Featured power products <strong>for</strong> <strong>FPGAs</strong> & <strong>CPLDs</strong><br />
LM5070 <strong>Power</strong>-over-Ethernet single-chip solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii<br />
LM3670/71 600 mA SOT-23 synchronous buck regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii<br />
LM2743 Low-voltage synchronous buck controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4<br />
LM2647 Dual synchronous buck controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6<br />
LM2798, LM3352, LM2770 Inductorless switching regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25<br />
LP385x/7x High-per<strong>for</strong>mance CMOS LDOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25<br />
How to use this guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2<br />
Selecting the best power architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3<br />
National power solutions <strong>for</strong> Stratix II <strong>FPGAs</strong><br />
Stratix II <strong>FPGAs</strong> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4<br />
Stratix II power requirements summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5<br />
National power solutions <strong>for</strong> Stratix II <strong>FPGAs</strong> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5<br />
National power solutions <strong>for</strong> Stratix <strong>FPGAs</strong><br />
Stratix <strong>FPGAs</strong> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6<br />
Stratix power requirements summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7<br />
National power solutions <strong>for</strong> Stratix <strong>FPGAs</strong> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7<br />
National power solutions <strong>for</strong> Cyclone <strong>FPGAs</strong><br />
Cyclone <strong>FPGAs</strong> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8<br />
Cyclone power requirements summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9<br />
National power solutions <strong>for</strong> Cyclone <strong>FPGAs</strong> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9<br />
National power solutions <strong>for</strong> MAX II <strong>CPLDs</strong><br />
MAX II <strong>CPLDs</strong> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10<br />
National power solutions <strong>for</strong> MAX II <strong>CPLDs</strong> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-11<br />
MAX II power requirements summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11<br />
<strong>Design</strong> considerations <strong>for</strong> powering <strong>FPGAs</strong> & <strong>CPLDs</strong> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-13<br />
Reference designs <strong>for</strong> Altera <strong>FPGAs</strong> & <strong>CPLDs</strong> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-19<br />
Other technologies <strong>for</strong> FPGA/CPLD-based designs<br />
DDR memory solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20<br />
Discrete LVDS buffers <strong>and</strong> transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20<br />
High-speed data conversion ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21<br />
High-speed, low-power amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21<br />
Product summary<br />
Recommended V CCINT <strong>and</strong> V CCIO regulators summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22<br />
Select voltage supervisors/power-on-reset ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23<br />
Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23<br />
<strong>Design</strong> tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24<br />
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Back<br />
For comments or feedback on this guide please email:<br />
FPGA.<strong>Power</strong>.Tools@nsc.com<br />
1
How to use this guide<br />
Introduction<br />
National Semiconductor — working in close collaboration<br />
with Altera — has developed this comprehensive design<br />
guide <strong>for</strong> design engineers who are utilizing Altera’s latest<br />
<strong>FPGAs</strong> <strong>and</strong> <strong>CPLDs</strong>, to help them easily select <strong>and</strong> implement<br />
the best power management solutions <strong>for</strong> their designs.<br />
This design guide presents National’s power supply solutions<br />
down to specific part numbers with multiple reference<br />
designs illustrating how these power management ICs<br />
are used in actual applications. This guide recommends<br />
the optimal National products <strong>for</strong> select Altera devices<br />
based on the device’s specified power consumption in<br />
specific applications. The reference designs were created by<br />
National <strong>and</strong> verified by Altera, combining the experience<br />
<strong>and</strong> knowledge of both companies to ensure that the<br />
highest-per<strong>for</strong>ming, most-reliable power solutions are<br />
being offered <strong>for</strong> the latest, most-powerful Altera devices.<br />
Additional in<strong>for</strong>mation is available on National’s website,<br />
including bills of material <strong>and</strong> test data <strong>for</strong> the reference<br />
designs, along with detailed in<strong>for</strong>mation on other National<br />
solutions <strong>for</strong> Altera <strong>FPGAs</strong>, from LVDS transceivers<br />
to high-speed ADC <strong>and</strong> integrated Bluetooth ® wireless<br />
modules. For more in<strong>for</strong>mation, visit:<br />
www.national.com/see/alterafpga<br />
How to use this guide<br />
This design guide is organized into two major sections:<br />
selection guide tables <strong>and</strong> reference design schematics. The<br />
use of this guide is a simple two-step process.<br />
1. In the selection guide, find the Altera FPGA or<br />
CPLD to be used in the design. Review the power<br />
consumption data <strong>for</strong> the device <strong>and</strong> select a National<br />
regulator <strong>for</strong> powering V CCINT <strong>and</strong> V CCIO .<br />
2. Go to the Reference <strong>Design</strong> section to find complete<br />
Altera FPGA-based power supplies using the<br />
recommended National product ID.<br />
This design guide also provides in<strong>for</strong>mation on additional<br />
National ICs <strong>for</strong> <strong>FPGAs</strong>, from core power management<br />
(including DDR <strong>and</strong> DDR-II memory regulators <strong>and</strong> active<br />
termination), <strong>and</strong> voltage supervisors to st<strong>and</strong>-alone LVDS<br />
interface <strong>and</strong> buffers, <strong>and</strong> other related analog <strong>and</strong> mixedsignal<br />
technologies, including high-speed analog-to-digital<br />
converters (ADCs) <strong>and</strong> high-speed operational amplifiers.<br />
Step 1:<br />
Review the power requirements<br />
<strong>for</strong> your specific device<br />
Step 2:<br />
Choose the best National solution based<br />
on your specific operating conditions<br />
EP2S15<br />
V CCINT (V core) 1.20V<br />
I CCINT max (I core) 2A<br />
V CCIO options (V I/O) 3.3, 2.5, 1.8, 1.5V<br />
I CCIO max (I I/O) 10A (all 8 banks)<br />
V CCINT<br />
V CCINT = 1.2V<br />
V IN = 12V<br />
I CCINT < 1000 mA (LDO) Not applicable 1<br />
I CCINT < 1000 mA (SW)<br />
LM2734<br />
I CCINT < 3A<br />
LM2673-Adj<br />
I CCINT < 5A LM2679-Adj 2 or LM2743 3<br />
I CCINT < 7A LM2743 or 1 / 2 LM2647 4<br />
I CCINT < 9A LM2743 or 1 / 2 LM2647 4<br />
I CCINT < 12A LM2743 or 1 / 2 LM2647 4<br />
I CCINT < 16A LM2743 or 1 / 2 LM2647 4<br />
2
Selecting the best power architecture<br />
What is the best power architecture to use?<br />
Linear regulators<br />
Linear regulators are some of the simplest, easiest-to-use<br />
regulators available. To operate, these devices typically need<br />
only two external components — an input <strong>and</strong> an output<br />
capacitor. They also feature very clean low-noise outputs. The<br />
main disadvantage of the linear regulator architecture is power<br />
dissipation. When using a linear regulator, the power that is<br />
no longer needed at the output is simply dissipated as heat.<br />
When this dissipated power is less than 1W or 2W (max.),<br />
the solution can be surface-mounted <strong>and</strong> implemented<br />
without a heatsink if using an adequate package <strong>for</strong> the<br />
regulator. However, <strong>for</strong> dissipated power P D > 2W, a linear<br />
regulator architecture is usually not recommended because<br />
temperature rise, system efficiency, <strong>and</strong> overall solution space<br />
are better addressed using a different topology.<br />
For linear regulators, dissipated power can be estimated<br />
as (V IN – V OUT ) * I OUT . For a 5.0V to 3.3V conversion<br />
at 500 mA, P D is roughly (5.0 – 3.3) * 0.5 = 0.85W.<br />
Typically, linear regulators do not offer an option to adjust<br />
the turn-on rate (softstart) <strong>and</strong> thus may require additional<br />
external circuitry to implement this functionality.<br />
Switching regulators<br />
Switching regulators offer a consistent efficiency (typically<br />
85% to 95%) under most operating conditions (V IN , V OUT ,<br />
I OUT ). Unlike their linear counterparts, these devices offer<br />
high efficiency, low heat dissipation, <strong>and</strong> the ability to stepup<br />
or step-down a voltage. Generally, a switching regulator<br />
uses an inductor in addition to input/output capacitors.<br />
Other external components might also be needed based on<br />
the specific topology used <strong>and</strong> functionality required.<br />
Buck regulators<br />
Buck regulators are the simplest step-down switching<br />
regulators to use. They offer good efficiency <strong>and</strong> low<br />
external component count (diode, inductor, <strong>and</strong> input/<br />
output capacitors, at a minimum). Most National<br />
buck regulators (particularly those from the SIMPLE<br />
SWITCHER ® family) offer free online design tools, as<br />
well as electrical <strong>and</strong> thermal simulation.<br />
Synchronous buck converters<br />
Synchronous-rectification buck converters are a variation<br />
of st<strong>and</strong>ard buck regulators. The main difference is that<br />
the diode placed between the switch node <strong>and</strong> ground<br />
(catch diode) is replaced with a second active switch<br />
(MOSFET or bipolar transistor), reducing the power loss<br />
at this element. This is an important enhancement when<br />
the output current is high <strong>and</strong> when the diode dissipates a<br />
significant amount of power as heat. For output currents >5A,<br />
a synchronous buck converter is always recommended.<br />
As with st<strong>and</strong>ard buck regulators, synchronous buck<br />
converters are offered with monolithic (integrated) pass<br />
transistors or can use external ones. The advantage of using<br />
an external pass device (MOSFET or Bipolar) is more<br />
evident <strong>for</strong> output currents >3A, when there is a need to<br />
get very low RDS ON pass devices, distribute heat dissipation<br />
in more than one element around the board, <strong>and</strong> attain a<br />
cost-effective solution.<br />
Figure 1 shows a summary <strong>and</strong> a comparison of the three<br />
main power architecture solutions discussed above that are<br />
suitable <strong>for</strong> FPGA power.<br />
Buck Synchronous buck Linear regulator<br />
Function: Step-down (V OUT < V IN )<br />
When to use: Typically when V IN is 3x to 5x V OUT<br />
<strong>and</strong> I OUT is > 0.5A <strong>and</strong> < 5A<br />
Characteristics: Easy to design <strong>and</strong> good efficiency<br />
<strong>for</strong> the above-mentioned typical V IN /V OUT /I OUT<br />
conditions<br />
Devices to use: All buck integrated regulators<br />
<strong>and</strong> controllers<br />
Function: Step-down (V OUT < V IN )<br />
When to use: When high efficiency is required with<br />
high-output current (> 5A) or low duty cycles (V IN ><br />
5 x V OUT <strong>and</strong>/or I OUT < 0.5A)<br />
Characteristics: A second switch replaces the diode<br />
in the basic buck topology, reducing losses in the<br />
conditions mentioned above<br />
Devices to use: Any “synchronous rectification”<br />
buck integrated regulator or controller<br />
Figure 1. Step-down configurations<br />
Function: Step-down (V OUT < V IN )<br />
When to use: Typically when I OUT < 1A, ultra<br />
low-dropout, <strong>and</strong> low-noise applications)<br />
Characteristics: Excellent option where fixed<br />
output, low current, <strong>and</strong> low voltage drops are<br />
required. Easy to implement<br />
Devices to use: Any low-dropout, linear regulator<br />
Comments: Great <strong>for</strong> micropower applications<br />
3
National power solutions <strong>for</strong> Stratix II <strong>FPGAs</strong><br />
Stratix II <strong>FPGAs</strong><br />
Stratix II <strong>FPGAs</strong> are Altera’s highest-density, highestper<strong>for</strong>mance<br />
devices. Built on a 90-nm process technology,<br />
they incorporate a new logic structure that on average<br />
delivers 50% faster core per<strong>for</strong>mance with more than twice<br />
the logic capacity <strong>and</strong> costs 40% less than first-generation<br />
Stratix devices. Support is implemented <strong>for</strong> internal clock<br />
frequency rates of up to 500 MHz <strong>and</strong> typical design<br />
per<strong>for</strong>mance at over 250 MHz.<br />
Based on a 1.2V SRAM process, Stratix II devices are available<br />
in densities ranging from 15,600 to 179,400 equivalent<br />
logic elements (LEs) <strong>and</strong> up to 9 Mbits of on-chip RAM.<br />
Stratix II devices offer up to 384 (18-bit x 18-bit) embedded<br />
multipliers in highly optimized digital signal processing<br />
(DSP) blocks <strong>and</strong> source-synchronous differential signaling<br />
with dedicated dynamic phase alignment (DPA) circuitry<br />
operating at up to 1 Gbps.<br />
The core of these <strong>FPGAs</strong> needs to be powered from a 1.20V<br />
source. This voltage (V CCINT ) should always be within<br />
1.15V <strong>and</strong> 1.25V during regular operation. Core current<br />
consumption (I CCINT ) depends upon utilization of the part<br />
(such as clock speed <strong>and</strong> internal elements used).<br />
The I/O banks of this FPGA family are compatible with<br />
multiple st<strong>and</strong>ards, thus the supply voltage (V CCIO ) can<br />
either be 1.5V, 1.8V, 2.5V or 3.3V <strong>for</strong> one or more banks.<br />
Current consumption <strong>for</strong> the I/Os also depends upon the<br />
utilization of these elements, however <strong>for</strong> all I/O banks<br />
operating together, the max I CCIO <strong>for</strong> the Stratix II FGPA<br />
is 10A (independent of the V CCIO voltage used).<br />
Another power management consideration that needs<br />
to be addressed is the monotonic rise of V CCINT . This<br />
consideration is critical <strong>for</strong> the correct operation of the<br />
FPGA. While many power supplies take this requirement<br />
into consideration, it is recommended to further support<br />
this requirement by the use of adequate bulk capacitance<br />
in the power supply.<br />
LM2743 Low-voltage synchronous buck controller<br />
• Highly efficient 2A to 25A solution in SMD<br />
• Input voltage from 1V to 16V<br />
• Adjustable output voltage as low as 0.6V<br />
• <strong>Power</strong>-good flag <strong>and</strong> output enable<br />
• Output under-voltage <strong>and</strong> over-voltage flag<br />
• 1.5% reference accuracy over temperature<br />
• Current limit without sense resistor<br />
• Programmable softstart<br />
• Switching frequency from 50 kHz to 2 MHz<br />
• Available in small TSSOP-14 packaging<br />
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LM2743 Typical application diagram<br />
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Ideal <strong>for</strong> operation from 3.3V or 5V supplies in FPGA, DSP, <strong>and</strong><br />
other high-current core regulator applications<br />
4
Stratix II <strong>FPGAs</strong><br />
Stratix II power requirements summary<br />
EP2S15 EP2S30 EP2S60 EP2S90 EP2S130 EP2S180<br />
V CCINT (V core) 1.20V 1.20V 1.20V 1.20V 1.20V 1.20V<br />
I CCINT max (I core)<br />
Dynamic power consumption is design dependent. For accurate estimates, use Altera’s suite of <strong>Power</strong>Play power estimation tools.<br />
For more in<strong>for</strong>mation: www.altera.com/support/devices/estimator/pow-powerplay.html<br />
V CCIO options (V I/O) 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V<br />
National power solutions<br />
<strong>for</strong> Stratix II <strong>FPGAs</strong><br />
V IN = 3.3V V IN = 5V V IN = 12V 5<br />
V CCINT<br />
V CCINT = 1.2V<br />
I CCINT < 1000 mA (LDO) LP3875-Adj Not applicable 1 Not applicable 1<br />
I CCINT < 1000 mA (SW) LM2734 LM2734 LM2734<br />
I CCINT < 3A LM3475 LM3475 LM2673-Adj<br />
I CCINT < 5A LM2743 LM2743 LM2679-Adj 2 or LM2743 3<br />
I CCINT > 6A LM2743 LM2743 or 1 / 2 LM2657 4 LM2743 or 1 / 2 LM2657 4<br />
V CCIO<br />
V CCIO = 1.5V<br />
V CCIO = 1.8V<br />
V CCIO = 2.5V<br />
V CCIO = 3.3V<br />
I CCIO < 500 mA (LDO) LP3874-Adj LP3874-Adj Not applicable 1<br />
I CCIO < 500 mA (SW) LM3671-1.5 LM3671-1.5 LM2736<br />
I CCIO < 1000 mA (LDO) LP3875-Adj Not applicable 1 Not applicable 1<br />
I CCIO < 1000 mA (SW) LM2734 LM2734 LM2734<br />
I CCIO < 3A LM3475 LM2599-Adj 2 or LM2650-Adj 3 LM2673-Adj 2 or LM2650-Adj 3<br />
I CCIO < 5A LM2743 LM2743 LM2679-Adj<br />
I CCIO > 6A LM2743 LM2743 or 1 / 2 LM2657 4 LM2743 or 1 / 2 LM2657 4<br />
I CCIO < 500 mA (LDO) LP3874-1.8 LP3874-1.8 Not applicable 1<br />
I CCIO < 500 mA (SW) LM3671-1.8 LM3671-1.8 LM2736<br />
I CCIO < 1000 mA (LDO) LP3875-1.8 Not applicable 1 Not applicable 1<br />
I CCIO < 1000 mA (SW) LM2734 LM2734 LM2734<br />
I CCIO < 3A LM3475 LM2599-Adj 2 or LM2650-Adj 3 LM2673-Adj 2 or LM2650-Adj 3<br />
I CCIO < 5A LM2743 LM2743 LM2679-Adj<br />
I CCIO > 6A LM2743 LM2743 or 1 / 2 LM2657 4 LM2743 or 1 / 2 LM2657 4<br />
I CCIO < 500 mA (LDO) LP3874-2.5 LP3874-2.5 Not applicable 1<br />
I CCIO < 500 mA (SW) LM3671-Adj LM3671-Adj LM2736<br />
I CCIO < 1000 mA (LDO) LP3875-2.5 LP3875-2.5 Not applicable 1<br />
I CCIO < 1000 mA (SW) LM2734 LM2734 LM2734<br />
I CCIO < 3A LM3475 LM2599-Adj 2 or LM2650-Adj 3 LM2673-Adj 2 or LM2650-Adj 3<br />
I CCIO < 5A LM2743 LM2743 LM2679-Adj<br />
I CCIO > 6A LM2743 LM2743 or 1 / 2 LM2657 4 LM2743 or 1 / 2 LM2657 4<br />
I CCIO < 500 mA (LDO) — LP3874-3.3 Not applicable 1<br />
I CCIO < 500 mA (SW) — LM3671-Adj LM2736<br />
I CCIO < 1000 mA (LDO) — LP3875-3.3 Not applicable 1<br />
I CCIO < 1000 mA (SW) — LM2734 LM2734<br />
I CCIO < 3A — LM2599-3.3 2 or LM2650-Adj 3 LM2673-3.3 2 or LM2650-Adj 3<br />
I CCIO < 5A — LM2743 LM2679-3.3<br />
I CCIO > 6A — LM2743 or 1 / 2 LM2657 4 LM2743 or 1 / 2 LM2657 4<br />
V CCPD<br />
V CCPD = 3.3V<br />
I CCPD < 300 mA (LDO) — LP3981-3.3 Not applicable 1<br />
I CCPD < 300 mA (SW) — LM3670-3.3 LM2736<br />
1<br />
LDO option not applicable due to thermal constraints (heat dissipation) <strong>for</strong> the given operating conditions.<br />
2<br />
Buck regulator. Good efficiency, simple implementation, with WEBENCH design tools available.<br />
3<br />
Synchronous buck converter. Maximum efficiency, no external diode required.<br />
4<br />
One half of a dual converter, such as the LM2657, can be used to power V CCINT while the other half can be used to power V CCIO .<br />
5<br />
These solutions can be used with input voltages from 8V to 14V.<br />
5
National power solutions <strong>for</strong> Stratix <strong>FPGAs</strong><br />
Stratix <strong>FPGAs</strong><br />
The Stratix FPGA family is optimized to address the<br />
challenges of high-b<strong>and</strong>width systems. Stratix devices offer<br />
very high core per<strong>for</strong>mance, memory capacity, architectural<br />
efficiencies, <strong>and</strong> time-to-market advantages. Stratix devices<br />
offer dedicated functionality <strong>for</strong> clock management <strong>and</strong><br />
digital signal processing (DSP) applications, as well as<br />
support <strong>for</strong> differential <strong>and</strong> single-ended I/O st<strong>and</strong>ards.<br />
In addition, Stratix devices offer on-chip termination <strong>and</strong><br />
remote system upgrade capabilities.<br />
Based on a 1.5V, 0.13-µm, all-layer copper SRAM process,<br />
Stratix devices are available in densities ranging from<br />
10,570 to 79,040 logic elements (LEs) <strong>and</strong> up to 7 Mbits<br />
of RAM. Stratix devices offer up to 22 DSP blocks with<br />
up to 176 (9-bit x 9-bit) embedded multipliers, optimized<br />
complex applications that require high data throughput.<br />
The core of these <strong>FPGAs</strong> needs to be powered from a 1.5V<br />
source. Core current consumption (I CCINT ) depends upon<br />
utilization of the part (such as clock speed <strong>and</strong> internal<br />
elements used), but maximum values range from 1.5A to<br />
10A (approx.) depending on the specific Stratix device<br />
used. To calculate the most accurate power consumption<br />
values needed by a specific design, use Altera’s <strong>Power</strong><br />
Calculator tool (see www.national.com/see/alterafpga). As<br />
a general rule, choose a V CCINT power supply whose I OUT<br />
(I CCINT ) capability is within the I CCINT inrush <strong>and</strong> I CCINT<br />
maximum values given in this guide <strong>for</strong> the specific Altera<br />
device used.<br />
Another power management consideration that needs<br />
to be addressed is the monotonic rise of V CCINT . This<br />
consideration is critical <strong>for</strong> the correct operation of the<br />
FPGA. While many power supplies take this requirement<br />
into consideration, it is recommended to further support<br />
this requirement by the use of adequate bulk capacitance<br />
in the power supply.<br />
LM2647 Dual synchronous buck controller<br />
• Input voltage range from 5.5V to 28V<br />
• Synchronous dual-channel interleaved<br />
switching<br />
• PWM or pulse-skip modes<br />
• Low-side MOSFET current sensing<br />
• Adjustable output voltage down to 0.6V<br />
• <strong>Power</strong>-good flag <strong>and</strong> chip enable<br />
• Under-voltage lockout hysteresis<br />
• Over-voltage/under-voltage protection<br />
• Softstart <strong>and</strong> soft-shutdown<br />
• Switching frequency adjustable from<br />
200 kHz to 500 kHz<br />
• Available in TSSOP-28 <strong>and</strong> tiny,<br />
thermally enhanced LLP-28 packaging<br />
LM2647 Efficiency curve<br />
Ideal <strong>for</strong> powering high-current V CCINT <strong>and</strong> V CCIO <strong>FPGAs</strong> from the<br />
same switching controller<br />
6
Stratix <strong>FPGAs</strong><br />
Stratix power requirements summary<br />
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80<br />
V CCINT (V core) 1.5V 1.5V 1.5V 1.5V 1.5V 1.5V 1.5V<br />
I CCINT max 5 (I core) 1.5A 3.5A 4A 5.5A 6A 7.5A 10A<br />
I CCINT inrush<br />
(startup inrush max)<br />
700 mA 1.2A 1.5A 1.9A 2.3A 2.6A 3A<br />
V CCIO options (V I/O) 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V<br />
I CCIO max (I I/O) 12A (all 8 banks) 12A (all 8 banks) 12A (all 8 banks) 12A (all 8 banks) 12A (all 8 banks) 12A (all 8 banks) 12A (all 8 banks)<br />
National power solutions<br />
<strong>for</strong> Stratix <strong>FPGAs</strong><br />
V IN = 3.3V V IN = 5V V IN = 12V 6<br />
V CCINT<br />
V CCINT = 1.5V<br />
I CCINT < 1000 mA (SW) LM2734 LM2734 LM2734<br />
I CCINT < 1000 mA (LDO) LP3875-Adj Not applicable 1 Not applicable 1<br />
I CCINT < 3A LM3475 LM2599-Adj 2 or LM2650-Adj 3 LM2673-Adj 2 or LM2650-Adj 3<br />
I CCINT < 5A LM2743 LM2743 LM2679-Adj 2 or LM2743 3<br />
I CCINT < 7.5A LM2743 LM2743 LM2743 or 1 / 2 LM5642 4<br />
I CCINT < 10A LM2743 LM2743 LM2743 or 1 / 2 LM5642 4<br />
V CCIO<br />
V CCIO = 1.5V<br />
V CCIO = 1.8V<br />
V CCIO = 2.5V<br />
V CCIO = 3.3V<br />
I CCIO < 500 mA (LDO) LP3874-Adj LP3874-Adj Not applicable 1<br />
I CCIO < 500 mA (SW) LM3671-1.5 LM3671-1.5 LM2736<br />
I CCIO < 1000 mA (LDO) LP3875-Adj Not applicable 1 Not applicable 1<br />
I CCIO < 1000 mA (SW) LM2734 LM2734 LM2734<br />
I CCIO < 3A LM3475 LM2599-Adj 2 or LM2650-Adj 3 LM2673-Adj 2 or LM2650-Adj 3<br />
I CCIO < 5A LM2743 LM2743 LM2679-Adj 2 or LM2743 3<br />
I CCIO > 6A LM2743 LM2743 LM2743 or 1 / 2 LM5642 4<br />
I CCIO < 500 mA (LDO) LP3874-1.8 LP3874-1.8 Not applicable 1<br />
I CCIO < 500 mA (SW) LM3671-1.8 LM3671-1.8 LM2736<br />
I CCIO < 1000 mA (LDO) LP3875-1.8 Not applicable 1 Not applicable 1<br />
I CCIO < 1000 mA (SW) LM2734 LM2734 LM2734<br />
I CCIO < 3A LM3475 LM2599-Adj 2 or LM2650-Adj 3 LM2673-Adj 2 or LM2650-Adj 3<br />
I CCIO < 5A LM2743 LM2743 LM2679-Adj 2 or LM2743 3<br />
I CCIO > 6A LM2743 LM2743 LM2743 or 1 / 2 LM5642 4<br />
I CCIO < 500 mA (LDO) LP3874-2.5 LP3874-2.5 Not applicable 1<br />
I CCIO < 500 mA (SW) LM3671-Adj LM3671-Adj LM2736<br />
I CCIO < 1000 mA (LDO) LP3875-2.5 LP3875-2.5 Not applicable 1<br />
I CCIO < 1000 mA (SW) LM2734 LM2734 LM2734<br />
I CCIO < 3A LM3475 LM2599-Adj 2 or LM2650-Adj 3 LM2673-Adj 2 or LM2650-Adj 3<br />
I CCIO < 5A LM2743 LM2743 LM2679-Adj 2 or LM2743 3<br />
I CCIO > 6A LM2743 LM2743 LM2743 or 1 / 2 LM5642 4<br />
I CCIO < 500 mA (LDO) — LP3874-3.3 Not applicable 1<br />
I CCIO < 500 mA (SW) — LM3671-Adj LM2736<br />
I CCIO < 1000 mA (LDO) — LP3875-3.3 Not applicable 1<br />
I CCIO < 1000 mA (SW) — LM2734 LM2734<br />
I CCIO < 3A — LM2599-3.3 2 or LM2650-Adj 3 LM2673-3.3 2 or LM2650-Adj 3<br />
I CCIO < 5A — LM2743 LM2679-Adj 2 or LM2743 3<br />
I CCIO > 6A — LM2743 LM2743 or 1 / 2 LM5642 4<br />
1<br />
LDO option not applicable due to thermal constraints (heat dissipation) <strong>for</strong> the given operating conditions.<br />
2<br />
Buck regulator. Good efficiency, simple implementation, with WEBENCH design tools available.<br />
3<br />
Synchronous buck converter. Maximum efficiency, no external diode required.<br />
4<br />
One half of a dual converter, such as the LM5642, can be used to power V CCINT while the other half can be used to power V CCIO .<br />
5<br />
Estimated values. Actual power consumption figures are dependant upon a broad number of operating conditions. Use Altera’s <strong>Power</strong><br />
Calculator tool <strong>for</strong> the most accurate calculation of the power requirements <strong>for</strong> your specific design.<br />
6<br />
These solutions can be used with input voltages from 8V to 14V.<br />
7
National power solutions <strong>for</strong> Cyclone <strong>FPGAs</strong><br />
Cyclone <strong>FPGAs</strong><br />
Altera’s Cyclone series of <strong>FPGAs</strong> provides the benefits of<br />
programmable logic at price points competitive with ASICs<br />
<strong>and</strong> ASSPs. Built from the ground up based on extensive<br />
input from hundreds of customers, these low-cost devices<br />
provide high-volume, application-focused features such as<br />
embedded memory, external memory interfaces, <strong>and</strong> clock<br />
management circuitry. Based on the cost-optimized all-layer<br />
copper 1.5V SRAM process, Cyclone <strong>FPGAs</strong> are available<br />
in densities ranging from 2,910 to 20,060 logic elements<br />
(LEs) with up to 294,912 bits of embedded RAM.<br />
Cyclone <strong>FPGAs</strong> support a variety of single-ended I/O<br />
st<strong>and</strong>ards such as LVTTL, LVCMOS, PCI, <strong>and</strong> SSTL-2/3<br />
<strong>and</strong> offer differential I/O support via the LVDS <strong>and</strong> RSDS<br />
I/O st<strong>and</strong>ards on up to 129 channels. Each channel is<br />
capable of operating LVDS signals at up to 640 Mbps.<br />
Cyclone devices feature dedicated circuitry to implement<br />
double data rate (DDR) SDRAM <strong>and</strong> FCRAM interfaces.<br />
LM2734/36 1A SOT-23 buck regulators<br />
• Complete, easy-to-use switcher solution has<br />
smallest footprint <strong>and</strong> highest power density in<br />
the industry<br />
• State-of-the-art 13 ns minimum ON-time allows<br />
<strong>for</strong> high conversion ratios without the need to<br />
reduce switching frequency or increase solution size<br />
• Choice of switching frequencies allows designers<br />
to trade off efficiency against solution size <strong>and</strong> EMI<br />
• Current mode control improves phase margin, line<br />
regulation <strong>and</strong> rejection of transients<br />
• PWM provides a predictable, easily filtered<br />
switching frequency <strong>for</strong> reduced output noise<br />
• Internal softstart circuitry, cycle-by-cycle, thermal<br />
shutdown, <strong>and</strong> over-voltage protection<br />
• Available in TSOT-23 packaging (1.0 mm height)<br />
The core of these <strong>FPGAs</strong> needs to be powered from a 1.5V<br />
source. Core current consumption (I CCINT ) depends upon<br />
utilization of the part (such as clock speed <strong>and</strong> internal<br />
elements used), but maximum values range from 0.75A<br />
to 5A (approx.) depending on the specific Cyclone device<br />
used. To calculate the most accurate power consumption<br />
values needed by a specific design, use Altera’s <strong>Power</strong><br />
Calculator tool (see www.national.com/see/alterafpga). As<br />
a general rule, choose a V CCINT power supply whose I OUT<br />
(I CCINT ) capability is within the I CCINT inrush <strong>and</strong> I CCINT<br />
maximum values given in this guide <strong>for</strong> the specific Altera<br />
device used.<br />
Another power management consideration is the monotonic<br />
rise of V CCINT . This consideration is critical <strong>for</strong> the correct<br />
operation of the FPGA. While many power supplies take<br />
this requirement into consideration, it is recommended to<br />
further support this requirement by the use of adequate<br />
bulk capacitance in the power supply.<br />
<br />
<br />
<br />
<br />
<br />
<br />
<br />
LM2734 Simple block diagram<br />
<br />
<br />
<br />
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<br />
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<br />
<br />
<br />
<br />
<br />
<br />
<br />
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<br />
<br />
Feature LM2734 LM2736<br />
Input range 3.0V to 20V 3.0V to 18V<br />
Output load 1A 750 mA<br />
Output range 0.8V to 18V 1.25V to 16V<br />
Internal references 0.8V, 2% 1.25V, 2%<br />
Operating frequency<br />
550 kHz / 1.6 MHz / 3 MHz<br />
<br />
<br />
<br />
<br />
8
Cyclone <strong>FPGAs</strong><br />
Cyclone power requirements summary<br />
EP1C3 EP1C4 EP1C6 EP1C12 EP1C20<br />
V CCINT (V core) 1.5V 1.5V 1.5V 1.5V 1.5V<br />
I CCINT max 5 (I core) 750 mA 1A 1.5A 3A 5A<br />
I CCINT inrush (startup inrush max) 300 mA 400 mA 500 mA 900 mA 1.2A<br />
V CCIO options (V I/O) 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V<br />
I CCIO max (I I/O) 6A (all 4 banks) 6A (all 4 banks) 6A (all 4 banks) 6A (all 4 banks) 6A (all 4 banks)<br />
National power solutions<br />
<strong>for</strong> Cyclone <strong>FPGAs</strong><br />
V IN = 3.3V V IN = 5V V IN = 12V 6<br />
V CCINT<br />
V CCINT = 1.5V<br />
I CCINT < 500 mA (LDO) LP3874-Adj LP3874-Adj Not applicable 1<br />
I CCINT < 500 mA (SW) LM3671-1.5 LM3671-1.5 LM2736<br />
I CCINT < 1000 mA (LDO) LP3875-Adj Not applicable 1 Not applicable 1<br />
I CCINT < 1000 mA (SW) LM2734 LM2734 LM2734<br />
I CCINT < 3A LM3475 LM2599- Adj 2 or LM2650-Adj 3 LM2673-Adj 2 or LM2650-Adj 3<br />
I CCINT < 5A LM2743 LM2743 LM2679-Adj 2 or LM2743 3<br />
V CCIO<br />
V CCIO = 1.5V<br />
V CCIO = 1.8V<br />
V CCIO = 2.5V<br />
V CCIO = 3.3V<br />
I CCIO < 500 mA (LDO) LP3874-Adj LP3874-Adj Not applicable 1<br />
I CCIO < 500 mA (SW) LM3671-1.5 LM3671-1.5 LM2736<br />
I CCIO < 1000 mA (LDO) LP3875-Adj Not applicable 1 Not applicable 1<br />
I CCIO < 1000 mA (SW) LM2734 LM2734 LM2734<br />
I CCIO < 3A LM3475 LM2599-Adj 2 or LM2650-Adj 3 LM2673-Adj 2 or LM2650-Adj 3<br />
I CCIO < 5A LM2743 LM2743 LM2679-Adj 2 or LM2743 3<br />
I CCIO < 6A LM2743 LM2743 LM2743 or 1 / 2 LM5642 4<br />
I CCIO < 500 mA (LDO) LP3874-1.8 LP3874-1.8 Not applicable 1<br />
I CCIO < 500 mA (SW) LM3671-1.8 LM3671-1.8 LM2736<br />
I CCIO < 1000 mA (LDO) LP3875-1.8 Not applicable 1 Not applicable 1<br />
I CCIO < 1000 mA (SW) LM2734 LM2734 LM2734<br />
I CCIO < 3A LM3475 LM2599-Adj 2 or LM2650-Adj 3 LM2673-Adj 2 or LM2650-Adj 3<br />
I CCIO < 5A LM2743 LM2743 LM2679-Adj 2 or LM2743 3<br />
I CCIO < 6A LM2743 LM2743 LM2743 or 1 / 2 LM5642 4<br />
I CCIO < 500 mA (LDO) LP3874-2.5 LP3874-2.5 Not applicable 1<br />
I CCIO < 500 mA (SW) LM3671-Adj LM3671-Adj LM2736<br />
I CCIO < 1000 mA (LDO) LP3875-2.5 LP3875-2.5 Not applicable 1<br />
I CCIO < 1000 mA (SW) LM2734 LM2734 LM2734<br />
I CCIO < 3A LM3475 LM2599-Adj 2 or LM2650-Adj 3 LM2673-Ad j2 or LM2650-Adj 3<br />
I CCIO < 5A LM2743 LM2743 LM2679-Adj 2 or LM2743 3<br />
I CCIO < 6A LM2743 LM2743 LM2743 or 1 / 2 LM5642 4<br />
I CCIO < 500 mA (LDO) — LP3874-3.3 Not applicable 1<br />
I CCIO < 500 mA (SW) — LM3671-Adj LM2736<br />
I CCIO < 1000 mA (LDO) — LP3875-3.3 Not applicable 1<br />
I CCIO < 1000 mA (SW) — LM2734 LM2734<br />
I CCIO < 3A — LM2599-3.3 2 or LM2650-Adj 3 LM2673-3.3 2 or LM2650-Adj 3<br />
I CCIO < 5A — LM2743 LM2679-Adj 2 or LM2743 3<br />
I CCIO < 6A — LM2743 LM2743 or 1 / 2 LM5642 4<br />
1<br />
LDO option not applicable due to thermal constraints (heat dissipation) <strong>for</strong> the given operating conditions.<br />
2<br />
Buck regulator. Good efficiency, simple implementation, with WEBENCH design tools available.<br />
3<br />
Synchronous buck converter. Maximum efficiency, no external diode required.<br />
4<br />
One half of a dual converter, such as the LM5642, can be used to power V CCINT while the other half can be used to power V CCIO .<br />
5<br />
Estimated values. Actual power consumption figures are dependant upon a broad number of operating conditions.<br />
Use Altera’s <strong>Power</strong> Calculator tool <strong>for</strong> the most accurate calculation of the power requirements <strong>for</strong> your specific design.<br />
6<br />
These solutions can be used with input voltages from 8V to 14V.<br />
9
National power solutions <strong>for</strong> MAX II <strong>CPLDs</strong><br />
MAX II <strong>CPLDs</strong><br />
The MAX II CPLD family is a non-volatile, instant-on<br />
programmable logic family with a new CPLD architecture,<br />
which allows significant power <strong>and</strong> density enhancements<br />
from previous MAX devices. Based on a 0.18-µm Flash<br />
process, the MAX II devices offer densities ranging from 240<br />
to 2,210 logic elements (LEs) <strong>and</strong> up to 272 user I/O pins.<br />
The core of these <strong>CPLDs</strong> (V CCINT ) needs to be powered from<br />
a 1.8V source. The non-G versions of MAX II devices have<br />
an internal voltage regulator <strong>and</strong> the V CCINT pin can accept<br />
either 3.3V or 2.5V. This internal regulator steps down<br />
the voltage to the needed 1.8V. On the G-version MAX II<br />
<strong>CPLDs</strong>, the internal regulator is bypassed <strong>and</strong> V CCINT needs<br />
to be only 1.8V. Core current consumption (I CCINT ) depends<br />
upon utilization of the part (such as clock speed <strong>and</strong> internal<br />
elements used), but typical values range from 30 mA to 75<br />
mA with maximum values in the 75 mA to 400 mA range.<br />
Typically, operating core current (I CCINT ) <strong>for</strong> MAX II devices<br />
National power solutions<br />
<strong>for</strong> MAX II <strong>CPLDs</strong><br />
will be 10 mA less in the 1.8V G versions. The I/O current<br />
(I CCIO ) also depends upon the device utilization, with typical<br />
values in the 100 mA to 200 mA range. Maximum values can<br />
reach 225 mA per bank or 900 mA total <strong>for</strong> up to four banks.<br />
To calculate the most accurate power consumption values<br />
needed by your specific design, we recommend using<br />
Altera’s <strong>Power</strong> Calculator tool, available online. A good rule<br />
of thumb is to choose a V CCINT power supply whose I OUT<br />
(I CCINT ) capability is within the I CCINT inrush <strong>and</strong> I CCINT<br />
maximum values. As opposed to <strong>FPGAs</strong>, these <strong>CPLDs</strong> do<br />
not have specific requirements <strong>for</strong> monotonic voltage rise or<br />
V CCINT rise times. Since MAX II <strong>CPLDs</strong> consume low power,<br />
the use of LDOs <strong>and</strong> inductorless switching regulators is<br />
recommended. For LDOs, it is advised to check the thermal<br />
dissipation capability of the part based on the package <strong>and</strong><br />
the operating conditions. It is not enough to check V IN , V OUT<br />
<strong>and</strong> I OUT alone <strong>for</strong> selecting LDOs. The LDOs recommended<br />
in the following tables address thermal dissipation capabilities.<br />
V IN = 3.3V V IN = 5V V IN = 12V<br />
V CCINT<br />
V CCINT = 1.8V<br />
V CCINT = 2.5V<br />
V CCINT = 3.3V<br />
I CCIO < 100 mA (LDO) LP3990-1.8 LP3990-1.8 LP2992-1.8 5<br />
I CCIO < 100 mA (SW) LM2798-1.8 4 LM2798-1.8 4 LM2736<br />
I CCIO < 150 mA (LDO) LP3990-1.8 LP3982-1.8 LP2992-1.8 5<br />
I CCIO < 150 mA (SW) LM3670-1.8 3 LM3670-1.8 3 LM2736<br />
I CCIO < 200 mA (LDO) LP3982-1.8 LP3982-1.8 Not applicable 1<br />
I CCIO < 200 mA (SW) LM3670-1.8 3 LM3670-1.8 3 LM2736<br />
I CCIO < 300 mA (LDO) LP3982-1.8 LP8345-1.8 Not applicable 1<br />
I CCIO < 300 mA (SW) LM3670-1.8 3 LM3670-1.8 3 LM2736<br />
I CCIO < 500 mA (LDO) LP8345-1.8 LP3874-1.8 Not applicable 1<br />
I CCIO < 500 mA (SW) LM3671-1.8 3 LM3671-1.8 3 LM2736<br />
I CCIO < 100 mA (LDO) LP3990-2.5 LP3990-2.5 LM2937-2.5 or LP2992-2.5 5<br />
I CCIO < 100 mA (SW) LM3352-2.5 4 LM3352-2.5 4 LM2736<br />
I CCIO < 150 mA (LDO) LP3990-2.5 LP3982-2.5 LM2937-2.5 or LP2992-2.5 5<br />
I CCIO < 150 mA (SW) LM3352-2.5 4 LM3352-2.5 4 LM2736<br />
I CCIO < 200 mA (LDO) LP3982-2.5 LP3982-2.5 LM2937-2.5 or LP2992-2.5 5<br />
I CCIO < 200 mA (SW) LM3352-2.5 4 LM3352-2.5 4 LM2736<br />
I CCIO < 300 mA (LDO) LP3982-2.5 LP8345-2.5 Not applicable 1<br />
I CCIO < 300 mA (SW) LM3670-2.5 3 LM3670-2.5 3 LM2736<br />
I CCIO < 500 mA (LDO) LP2989-2.5 LP3874-2.5 Not applicable 1<br />
I CCIO < 500 mA (SW) LM3671-Adj 3 LM3671-Adj 3 LM2736<br />
I CCIO < 100 mA (LDO) — LP3990-3.3 LM2937-3.3 or LP2986-3.3 5<br />
I CCIO < 100 mA (SW) — LM3352-3.3 4 LM2736<br />
I CCIO < 150 mA (LDO) — LP3990-3.3 LM2937-3.3 or LP2986-3.3 5<br />
I CCIO < 150 mA (SW) — LM3352-3.3 4 LM2736<br />
I CCIO < 200 mA (LDO) — LP3982-3.3 LM2937-3.3 or LP2986-3.3 5<br />
I CCIO < 200 mA (SW) — LM3352-3.3 4 LM2736<br />
I CCIO < 300 mA (LDO) — LP3982-3.3 Not applicable 1<br />
I CCIO < 300 mA (SW) — LM3670-3.3 3 LM2736<br />
I CCIO < 500 mA (LDO) — LP8345-3.3 Not applicable 1<br />
I CCIO < 500 mA (SW) — LM3671-Adj 3 LM2736<br />
10
MAX II <strong>CPLDs</strong><br />
MAX II power requirements summary<br />
EPM240 EPM240G EPM570 EPM570G EPM1270 EPM1270G EPM2210 EPM2210G<br />
V CCINT (V core) 3.3 or 2.5V 1.8V 3.3 or 2.5V 1.8V 3.3 or 2.5V 1.8V 3.3 or 2.5V 1.8V<br />
I CCINT max 5 (I core) 75 mA 75 mA 125 mA 125 mA 250 mA 250 mA 400 mA 400 mA<br />
I CCINT inrush<br />
(startup inrush max)<br />
65 mA 55 mA 65 mA 55 mA 65 mA 55 mA 65 mA 55 mA<br />
V CCIO options (V I/O) 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V 3.3, 2.5, 1.8, 1.5V<br />
I CCIO max (I I/O)<br />
450 mA<br />
(both banks)<br />
450 mA<br />
(both banks)<br />
450 mA<br />
(both banks)<br />
450 mA<br />
(both banks)<br />
900 mA<br />
(all 4 banks)<br />
900 mA<br />
(all 4 banks)<br />
900 mA<br />
(all 4 banks)<br />
900 mA<br />
(all 4 banks)<br />
National power solutions<br />
<strong>for</strong> MAX II <strong>CPLDs</strong> (cont.)<br />
V IN = 3.3V V IN = 5V V IN = 12V 6<br />
V CCIO<br />
V CCIO = 1.5V<br />
V CCIO = 1.8V<br />
V CCIO = 2.5V<br />
V CCIO = 3.3V<br />
I CCIO < 100 mA (LDO) LP3990-1.5 LP3990-1.5 LP2986-Adj 5<br />
I CCIO < 100 mA (SW) LM2798-1.5 4 LM2798-1.5 4 LM2736<br />
I CCIO < 200 mA (LDO) LP3982-Adj LP3982-Adj Not applicable 1<br />
I CCIO < 200 mA (SW) LM2770-1.5 4 LM2770-1.5 4 LM2736<br />
I CCIO < 300 mA (LDO) LP3982-Adj LP8345-Adj Not applicable 1<br />
I CCIO < 300 mA (SW) LM3670-1.5 3 LM3670-1.5 3 LM2736<br />
I CCIO < 500 mA LM3671-1.5 3 LM3671-1.5 3 LM2736<br />
I CCIO < 750 mA LM2736 LM2736 LM2736<br />
I CCIO < 1A LM2734 LM2734 LM2734<br />
I CCIO < 100 mA (LDO) LP3990-1.8 LP3990-1.8 LP2992-1.8 5<br />
I CCIO < 100 mA (SW) LM2798-1.8 4 LM2798-1.8 4 LM2736<br />
I CCIO < 200 mA (LDO) LP3982-1.8 LP3982-1.8 Not applicable 1<br />
I CCIO < 200 mA (SW) LM3670-1.8 3 LM3670-1.8 3 LM2736<br />
I CCIO < 300 mA (LDO) LP3982-1.8 LP8345-1.8 Not applicable 1<br />
I CCIO < 300 mA (SW) LM3670-1.8 3 LM3670-1.8 3 LM2736<br />
I CCIO < 500 mA LM3671-1.8 3 LM3671-1.8 3 LM2736<br />
I CCIO < 750 mA LM2736 LM2736 LM2736<br />
I CCIO < 1A LM2734 LM2734 LM2734<br />
I CCIO < 100 mA (LDO) LP3990-2.5 LP3990-2.5 LM2937-2.5 or LP2992-2.5 5<br />
I CCIO < 100 mA (SW) LM3352-2.5 4 LM3352-2.5 4 LM2736<br />
I CCIO < 200 mA (LDO) LP3982-2.5 LP3982-2.5 LM2937-2.5 or LP2992-2.5 5<br />
I CCIO < 200 mA (SW) LM3352-2.5 4 LM3352-2.5 4 LM2736<br />
I CCIO < 300 mA (LDO) LP3982-2.5 LP8345-2.5 Not applicable 1<br />
I CCIO < 300 mA (SW) LM3670-2.5 3 LM3670-2.5 3 LM2736<br />
I CCIO < 500 mA LP2989-2.5 LM3671-Adj 3 LM2736<br />
I CCIO < 750 mA LM2736 LM2736 LM2736<br />
I CCIO < 1A LM2734 LM2734 LM2734<br />
I CCIO < 100 mA (LDO) — LP3990-3.3 LM2937-3.3 or LP2986-3.3 5<br />
I CCIO < 100 mA (SW) — LM3352-3.3 4 LM2736<br />
I CCIO < 200 mA (LDO) — LP3982-3.3 LM2937-3.3 or LP2986-3.3 5<br />
I CCIO < 200 mA (SW) — LM3352-3.3 4 LM2736<br />
I CCIO < 300 mA (LDO) — LP3982-3.3 Not applicable 1<br />
I CCIO < 300 mA (SW) — LM3670-3.3 3 LM2736<br />
I CCIO < 500 mA — LP8345-3.3 LM2736<br />
I CCIO < 750 mA — LM2736 LM2736<br />
I CCIO < 1A — LM2734 LM2734<br />
1<br />
LDO option not applicable due to thermal constraints (heat dissipation) <strong>for</strong> the given operating conditions.<br />
2<br />
Buck regulator. Good efficiency, simple implementation, with WEBENCH design tools available.<br />
3<br />
Synchronous buck converter. Maximum efficiency, no external diode required.<br />
4<br />
Inductorless switching regulator.<br />
5<br />
Use LLP package <strong>for</strong> adequate thermal dissipation.<br />
6<br />
These solutions can be used with input voltages from 8V to 14V.<br />
11
<strong>Design</strong> considerations <strong>for</strong> powering <strong>FPGAs</strong> & <strong>CPLDs</strong><br />
Bulk capacitance<br />
In any power supply, the output capacitors are a vital<br />
element <strong>for</strong> adequate per<strong>for</strong>mance. They are used to<br />
control the output voltage ripple (ΔV OUT ) <strong>and</strong> to supply<br />
load current during fast load transients. Various types<br />
of capacitors may be used. However, the ceramic type<br />
often do not have the large capacitance needed to supply<br />
current <strong>for</strong> load transients, <strong>and</strong> tantalums tend to be more<br />
expensive than aluminum electrolytic.<br />
Adding bulk capacitance to the output of high-current<br />
switching supplies is always recommended <strong>and</strong> is also very<br />
important <strong>for</strong> adequate FPGA per<strong>for</strong>mance. Bulk capacitance<br />
helps provide current during start-up transients, thus<br />
supporting an adequate monotonic voltage rise in highcurrent<br />
power supplies. More in-depth recommendations<br />
on the use <strong>and</strong> benefits of bulk capacitance in FPGA<br />
power supplies are available in Altera’s application note<br />
AN-355 (see page 23 <strong>for</strong> download in<strong>for</strong>mation).<br />
Layout<br />
FPGA power design can involve very high currents (5A,<br />
10A, <strong>and</strong> 15A are common) flowing in the traces of the<br />
PCB. When these larger currents are present <strong>and</strong> change<br />
over time in a switching pattern with sharp edges, it is easy<br />
to realize that noise, induced voltages, <strong>and</strong> EMI may be<br />
present <strong>and</strong> may cause undesirable behavior in the power<br />
supply if proper care is not taken. This is why proper layout<br />
is critical in every switching regulator design. Rapidly<br />
switching currents associated with wiring inductance can<br />
also generate voltage transients which may cause additional<br />
problems. For minimal inductance <strong>and</strong> ground loops,<br />
the PCB traces conducting high current <strong>and</strong>/or switching<br />
wave<strong>for</strong>ms should be kept as short as possible.<br />
For best results, external components should be located as<br />
close to the switcher IC as possible, using ground-plane<br />
construction or single-point grounding. If open core<br />
inductors are used, special care must be taken as to the<br />
location <strong>and</strong> positioning of this type of inductor. Allowing<br />
the inductor flux to intersect sensitive feedback IC ground<br />
path <strong>and</strong> C OUT wiring can cause problems.<br />
When using a switching regulator or controller with an<br />
adjustable output, special care must be taken as to the<br />
location of the feedback resistors <strong>and</strong> the associated wiring.<br />
Physically locate both resistors near the IC <strong>and</strong> route the<br />
wiring away from the inductor, especially an open core<br />
type of inductor. Ferrite bobbin or stick inductors have<br />
magnetic lines of flux flowing through the air from one<br />
end of the bobbin to the other end. These magnetic lines<br />
of flux will induce a voltage into any wire or PC board<br />
copper trace that comes within the inductor’s magnetic field.<br />
The strength of the magnetic field, the orientation <strong>and</strong><br />
location of the PC copper trace to the magnetic field, <strong>and</strong><br />
the distance between the copper trace <strong>and</strong> the inductor<br />
determine the amount of voltage generated in the copper<br />
trace. For a deeper underst<strong>and</strong>ing of buck converters<br />
<strong>and</strong> PCB layout guidelines around them, see National’s<br />
application notes AN-1149 <strong>and</strong> AN-1229 (see page 23 <strong>for</strong><br />
download in<strong>for</strong>mation).<br />
Softstart<br />
As with most digital systems, <strong>FPGAs</strong> need their supply voltage<br />
to rise from zero to full voltage within a specified period of<br />
time. Altera <strong>FPGAs</strong> are very flexible <strong>and</strong> the requirements<br />
are not difficult to meet, but start-up timing still needs to<br />
be observed. For example, Stratix II <strong>FPGAs</strong> need V CCINT to<br />
rise in a window anywhere from 30 µs to 100 ms. To achieve<br />
that controlled rise time, softstart in the power supply must<br />
be used. Most switching regulators <strong>and</strong> controllers already<br />
have softstart incorporated, either internally fixed or externally<br />
programmable. When user programmable, a softstart pin (SS)<br />
is available <strong>and</strong> softstart timing is typically adjusted by placing<br />
a small capacitor between that pin <strong>and</strong> ground. Depending on<br />
the capacitor value, the softstart time will change.<br />
In<strong>for</strong>mation on which capacitor values to use <strong>and</strong> how to<br />
calculate the needed value to achieve a particular ramp-up<br />
time is described on each switching regulator’s datasheet.<br />
For linear regulators where softstart is not typically an<br />
internally implemented function, an external pass device<br />
is used along with a resistor <strong>and</strong> a capacitor to achieve this<br />
same effect.<br />
12
Monotonic voltage rise<br />
Although not typically required in <strong>CPLDs</strong>, most <strong>FPGAs</strong><br />
need the supply voltage to turn on steadily <strong>and</strong> gradually.<br />
This is called monotonic voltage rise <strong>and</strong> is needed <strong>for</strong><br />
internal elements in the FPGA to turn on sequentially as<br />
the input voltage rises. As these elements are turning on<br />
during the ramp-up period, the “load” to the power supply<br />
will not be constant, so it is important that the power<br />
supply chosen regulates its output voltage not only during<br />
steady state but also during ramp up. As mentioned be<strong>for</strong>e,<br />
bulk capacitance is also a very important element <strong>for</strong><br />
ensuring that the power supply has an adequate monotonic<br />
rise <strong>for</strong> powering <strong>FPGAs</strong>.<br />
The figure below shows the monotonic rise achieved in<br />
V OUT when using National’s LM2743 switching controller<br />
to power a Stratix II FPGA. The LM2743 power supply<br />
design used <strong>for</strong> this graph is included in the reference<br />
design section of this guide.<br />
<br />
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<br />
LM2743 V OUT monotonic rise<br />
<br />
<br />
Selecting the best power solution <strong>for</strong> Altera devices<br />
Depending on the operating conditions <strong>and</strong> the specific<br />
Altera device used, all three of the power topologies<br />
previously mentioned (linear, buck, <strong>and</strong> synchronous buck)<br />
come into play. As seen throughout the selection tables, a<br />
choice of either an LDO or a switching regulator solution<br />
is provided <strong>for</strong> relatively small output currents in <strong>FPGAs</strong><br />
(500 mA <strong>and</strong> 1A). The exception is when the input-tooutput<br />
voltage ratio is high <strong>and</strong> an LDO solution is no<br />
longer suitable because of high thermal dissipation (e.g.,<br />
12V to 3.3V @ 500 mA or 5V to 1.2V @ 1A). For output<br />
currents >5A, synchronous buck controllers are always<br />
recommended as they provide the best option in terms of<br />
efficiency, heat dissipation, per<strong>for</strong>mance, <strong>and</strong> cost.<br />
<strong>CPLDs</strong> are low-power devices. As seen in the MAX II<br />
solutions table, most of the power supplies recommended<br />
are LDOs <strong>and</strong> monolithic (integrated) switching regulators<br />
because typical current requirements are always below<br />
1A. One alternative <strong>for</strong> high efficiency <strong>and</strong> simple, hasslefree<br />
design is to use inductorless switching regulators.<br />
These devices provide efficiencies in the 80% range, thus<br />
dissipating very small amounts of power as heat. As implied<br />
by their name, these devices do not require an inductor<br />
(only small external capacitors) <strong>and</strong> are as easy to use as<br />
linear regulators. Inductorless switching regulators are a good<br />
option <strong>for</strong> powering loads in the 10 mA to 250 mA range.<br />
For all digital supplies needed by the FPGA (such as<br />
V CCINT <strong>and</strong> V CCIO ), either a switching or a linear solution<br />
is sufficient. When the supply is powering an analog FPGA<br />
block (V CCPLL , <strong>for</strong> example) a linear solution is usually<br />
recommended as it has a cleaner low-noise output.<br />
<br />
13
Reference designs<br />
Stratix II & Stratix <strong>FPGAs</strong><br />
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Stratix II/Stratix* Complete <strong>Power</strong> Supply Reference <strong>Design</strong><br />
(5V in, 1.20V @ 9A, 2.5V @ 6A <strong>and</strong> 3.3V @ 0.3A out)<br />
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This reference design features the high-current, low inputvoltage<br />
LM2743 synchronous buck switching controller<br />
<strong>and</strong> the low-power LP3981 LDO to offer a complete<br />
power supply solution <strong>for</strong> a typical Stratix II application.<br />
The LM2743 can be used <strong>for</strong> output currents from 1A<br />
up to 25A. Output voltage on this part can be adjusted<br />
anywhere down to 0.6V. For this Stratix II design, the<br />
output voltage has been programmed in the LM2743 to<br />
supply 1.20V <strong>for</strong> V CCINT <strong>and</strong> 2.5V <strong>for</strong> V CCIO . This same<br />
reference design can be used <strong>for</strong> Stratix <strong>FPGAs</strong> by simply<br />
changing V CCINT to 1.5V. This can be done by changing<br />
R8 from 2 kΩ to 1.33 kΩ.<br />
In the following pages you will find various V CCINT <strong>and</strong><br />
V CCIO reference designs that can be used in different<br />
combinations to provide the most adequate power supply<br />
solution <strong>for</strong> different I CCINT <strong>and</strong> I CCIO requirements when<br />
powering Altera’s Stratix II, Stratix, <strong>and</strong> Cylcone <strong>FPGAs</strong>.<br />
For additional in<strong>for</strong>mation on these reference designs,<br />
such as complete bills of material, test wave<strong>for</strong>ms, <strong>and</strong><br />
per<strong>for</strong>mance reports, visit:<br />
www.national.com/see/alterafpga<br />
14
Stratix II & Stratix <strong>FPGAs</strong><br />
<br />
Stratix II/Stratix/Cyclone V CCINT <strong>Power</strong> Supply Reference <strong>Design</strong><br />
(3.3V in, 1.20V* out @ 4A)<br />
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This V CCINT LM2743-based reference designs shows how an<br />
up-to-4A V CORE solution <strong>for</strong> Stratix II can be implemented<br />
from a 3.3V source. Because the LM2743 has a V CC from<br />
3.0V to 6.0V, no special considerations need to be taken to<br />
have this circuit work from 3.3V directly. While ideal <strong>for</strong><br />
powering the EP2S15 Stratix II FPGA, this design can also<br />
be utilized to power various Stratix <strong>and</strong> Cyclone devices,<br />
such as the EP1S10, EP1S20, EP1S25 <strong>and</strong> EP1C12 by<br />
changing the LM2743 output voltage (V CCINT ) from 1.20V<br />
to 1.5V. This is done simply by changing R6 from 2 kΩ to<br />
1.33 kΩ.<br />
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Stratix II/Stratix V CCINT <strong>Power</strong> Supply Reference <strong>Design</strong><br />
(12V in, 1.2V*out @ 9A)<br />
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This other LM2743-based V CCINT reference design shows<br />
how a Stratix II or Stratix FPGA can be powered at<br />
high current (up to 9A) from a 12V supply. Because the<br />
LM2743 has a V IN range from 1V to 16V, the 12V input<br />
voltage in this application is taken directly to the power<br />
train of this switching converter <strong>for</strong>med by the power<br />
MOSFETs <strong>and</strong> the inductor. The LM2743 is biased from<br />
a 5V rail at merely 1 mA typical or 3 mA maximum.<br />
The I CCINT (I OUT ) from this design is ideally suited to power<br />
the EP2S90 <strong>and</strong> the EP2S60 Stratix II <strong>FPGAs</strong>. This design<br />
can also power the EP1S60 <strong>and</strong> EP1S80 Stratix devices if<br />
V CCINT is programmed to 1.5V. This is done by changing<br />
R6 in this design to 1.33 kΩ.<br />
For additional in<strong>for</strong>mation on these reference designs,<br />
such as complete bills of material, test wave<strong>for</strong>ms, <strong>and</strong><br />
per<strong>for</strong>mance reports, visit:<br />
www.national.com/see/alterafpga<br />
15
Reference designs<br />
Stratix II & Stratix <strong>FPGAs</strong><br />
<br />
Stratix II V CCINT <strong>Power</strong> Supply Reference <strong>Design</strong><br />
(5V in, 1.20V out @ 16A)<br />
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This third LM2743-based V CCINT reference design features<br />
a high-current I CCINT output with an up to 16A capability<br />
to ideally power the EP2S180 <strong>and</strong> the EP2S130 Stratix II<br />
<strong>FPGAs</strong>. It can also be used to power the EP1S80 Stratix<br />
device, making the V CCINT 1.5V. As previously described in<br />
the “<strong>Power</strong>ing FPGA <strong>Design</strong> Considerations” section, it is<br />
highly recommended to place proper bulk capacitance in<br />
the output of the power supply when large I CCINT current<br />
is involved. This is needed <strong>for</strong> the adequate per<strong>for</strong>mance<br />
of the FPGA during load transient conditions <strong>and</strong> also to<br />
help in proper start-up of the device during power up.<br />
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Stratix II/Stratix V CCIO 3A to 10A <strong>Power</strong> Supply Reference <strong>Design</strong><br />
(5V in, 1.8V out @ 10A)<br />
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The I/O banks in <strong>FPGAs</strong> can be powered at different<br />
V CCIO voltages depending on the I/O st<strong>and</strong>ard at which<br />
they will be used. Different I/O banks in the same FPGA<br />
may be powered with different V CCIO voltages to work on<br />
different I/O st<strong>and</strong>ards simultaneously.<br />
The present LM2743-based design shows a high-current<br />
power supply to power V CCIO at a typical 1.8V <strong>and</strong> has an<br />
I OUT capability of up to 10A. Such high current is needed<br />
by Stratix II or Stratix <strong>FPGAs</strong> when all banks (up to 8) are<br />
fully utilized <strong>and</strong> powered from the same V CCIO . However,<br />
this same power supply is adequate <strong>for</strong> powering I/O banks<br />
that require current (I CCIO ) anywhere from 3A to 10A.<br />
For additional in<strong>for</strong>mation on these reference designs,<br />
such as complete bills of material, test wave<strong>for</strong>ms, <strong>and</strong><br />
per<strong>for</strong>mance reports, visit:<br />
www.national.com/see/alterafpga<br />
16
Stratix II & Stratix <strong>FPGAs</strong><br />
<br />
Stratix II/Stratix/Cyclone V CCIO 3A to 10A <strong>Power</strong> Supply Reference <strong>Design</strong><br />
(5V in, 3.3V out @ 10A)<br />
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This synchronous buck design featuring the LM2743<br />
shows a high-current power supply to power V CCIO at the<br />
very common 3.3V rail from a 5V supply. It has an I OUT<br />
capability of up to 10A, however the design can be used in<br />
any application needing from 1A to 10A of current. For<br />
3A <strong>and</strong> up, the use of a synchronous buck controller (such<br />
as this one) is highly recommended.<br />
<br />
Stratix II/Stratix/Cyclone V CCIO 3A to 10A <strong>Power</strong> Supply Reference <strong>Design</strong><br />
(12V in, 3.3V out @ 10A)<br />
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This flexible LM2743-based design shows a high-current<br />
power supply to power V CCIO at the very common 3.3V rail<br />
from a 12V supply. It has an I OUT capability of up to 10A,<br />
however it can be used in any application needing from 1A<br />
to 10A of current. For 3A <strong>and</strong> up, the use of a synchronous<br />
buck controller (such as the LM2743) is ideal.<br />
For additional in<strong>for</strong>mation on these reference designs,<br />
such as complete bills of material, test wave<strong>for</strong>ms, <strong>and</strong><br />
per<strong>for</strong>mance reports, visit:<br />
www.national.com/see/alterafpga<br />
17
Reference designs<br />
Cyclone <strong>FPGAs</strong><br />
This complete reference design<br />
is based on National’s smallest<br />
new switching regulators. The<br />
LM2734 features up to 1A<br />
I OUT from a tiny Thin SOT-23<br />
package, while the LM3671<br />
(also in SOT-23) provides onboard<br />
synchronous rectification<br />
<strong>for</strong> maximum efficiency <strong>and</strong><br />
the least number of external<br />
components. Both devices are<br />
available in high switching<br />
frequencies <strong>for</strong> small designs<br />
using tiny, passive elements.<br />
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Cyclone Complete <strong>Power</strong> Supply Reference <strong>Design</strong><br />
(3.3V in, 1.5V @ 1A <strong>and</strong> 1.8V @ 600 mA out)<br />
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Cyclone Complete <strong>Power</strong> Supply Reference <strong>Design</strong><br />
(5V in, 1.5V @ 1.5A <strong>and</strong> 2.5V @ 600 mA out)<br />
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This complete reference design<br />
<strong>for</strong> Cyclone <strong>FPGAs</strong> utilizes the<br />
LM3671 <strong>and</strong> LM2651. Both<br />
synchronous buck switching<br />
regulators provide ultrahigh<br />
efficiency <strong>and</strong> require<br />
minimal external components.<br />
By changing R5, V CCIO can<br />
be adjusted to fit different<br />
requirements than 2.5V I/O<br />
st<strong>and</strong>ards.<br />
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This complete reference design<br />
can be used <strong>for</strong> virtually any<br />
Cyclone FPGA. The wide V IN<br />
range (8V to 40V) allows the<br />
use of many industrial rails (12V,<br />
24V, 36V) as well as unregulated<br />
“wall warts.” Based on National’s<br />
SIMPLE SWITCHER ® regulator<br />
family, the LM267x provides 5A<br />
<strong>and</strong> 3A, while other members of<br />
the family have output currents<br />
of 2A, 1A, <strong>and</strong> 0.5A. The<br />
LM267x family is available in<br />
LLP packaging <strong>and</strong> WEBENCH<br />
design tools are available.<br />
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Cyclone Complete <strong>Power</strong> Supply Reference <strong>Design</strong><br />
(12V in, 1.5V @ 5A <strong>and</strong> 3.3V @ 3A out)<br />
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18
MAX II <strong>CPLDs</strong><br />
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MAX II Complete <strong>Power</strong> Supply Reference <strong>Design</strong><br />
(High-efficiency inductorless switching regulator based)<br />
(5V in, 2.5V out @ 200 mA)<br />
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This complete MAX II design features the<br />
LM3352, one of National’s inductorless<br />
high-efficiency switching regulators. With<br />
only tiny ceramic capacitors as external<br />
components, this device provides the required<br />
voltage to power both V CCINT <strong>and</strong> V CCIO with<br />
significantly better efficiency than that of<br />
LDOs. This IC also features useful automatic<br />
step-up <strong>and</strong> step-down capability.<br />
This complete MAX-II G reference design<br />
features two of the newest National regulators<br />
<strong>for</strong> portable power applications, the LP3990<br />
LDO <strong>and</strong> the LM2798 inductorless, highefficiency<br />
switching regulator to provide<br />
robust per<strong>for</strong>mance <strong>and</strong> a very small size<br />
solution. While an LDO is adequate <strong>for</strong> a<br />
5V to 3.3V conversion at low current, when<br />
output voltage is as low as 1.8V the use of a<br />
different architecture is needed to maintain high<br />
efficiency <strong>and</strong> to properly dissipate power in a<br />
tiny package without the usual temperature rise.<br />
MAX II-G Complete <strong>Power</strong> Supply Reference <strong>Design</strong><br />
(High-efficiency inductorless switching regulator based <strong>for</strong> V CCINT )<br />
(5V in, 1.8V out @ 120 mA <strong>and</strong> 3.3V @ 150 mA out)<br />
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MAX II Complete <strong>Power</strong> Supply Reference <strong>Design</strong><br />
(Linear regualtor based)<br />
(5V in, 2.5V out @ 0.4A)<br />
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For additional in<strong>for</strong>mation on these reference designs, such as complete<br />
bills of material, test wave<strong>for</strong>ms, <strong>and</strong> per<strong>for</strong>mance reports, visit:<br />
www.national.com/see/alterafpga<br />
This reference design <strong>for</strong> the MAX II CPLD<br />
utilizes an LP3871 LDO to step down the<br />
voltage from a 5V supply to 2.5V. This power<br />
supply has been put together <strong>for</strong> a MAX II<br />
device in an application driving a 2.5V I/O<br />
st<strong>and</strong>ard (V CCIO ). Since the MAX II (non-G<br />
version) can accept a V CCINT of either 3.3V or<br />
2.5V, a single power supply is being built with<br />
the LP3871 <strong>and</strong> leveraged <strong>for</strong> powering both<br />
V CCINT <strong>and</strong> V CCIO , providing a very compact<br />
<strong>and</strong> easy-to-implement solution.<br />
This design is fulfilling a 400 mA combined<br />
I CCINT <strong>and</strong> I CCIO current need (enough current<br />
<strong>for</strong> most MAX II designs). It can also be used<br />
<strong>for</strong> lower I CCINT currents <strong>and</strong> with proper<br />
thermal dissipation, this same design can<br />
output up to 800 mA utilizing only SMD<br />
components without any heatsink.<br />
19
Other technologies <strong>for</strong> FPGA/CPLD-based designs<br />
DDR memory solutions<br />
Product ID<br />
V IN range<br />
(P VIN )<br />
Sink/source<br />
I OUT (A)<br />
St<strong>and</strong>ards<br />
Temp<br />
range (°C)<br />
Other features/comments<br />
Packaging<br />
Memory supply (V DD /V DDQ ) regulators<br />
LM2727 2.2 to 16 0.5 to 20 cont. DDR & DDR-II -40 to 125 Suspend to disk shutdown; UVP & OVP latch-off TSSOP-14<br />
LM2737 2.2 to 16 0.5 to 20 cont. DDR & DDR-II -40 to 125 Suspend to disk shutdown TSSOP-14<br />
Memory termination (V TT ) <strong>and</strong> reference (V REF ) regulators — linear<br />
LP2996 1.5 to 5.5 3 peak, 1.5 cont. DDR & DDR-II 0 to 125 Suspend to RAM shutdown SO-8, LLP-16, PSOP-8<br />
LP2997 1.5 to 5.5 1.5 peak, 0.5 cont. DDR-II 0 to 125 Suspend to RAM shutdown SO-8, PSOP-8<br />
Memory termination (V TT ) <strong>and</strong> reference (V REF ) regulators — switching<br />
LM2744 1 to 16 0.5 to 25 cont. DDR & DDR-II -40 to 125 Suspend to RAM shutdown TSSOP-14<br />
Discrete LVDS buffers <strong>and</strong> transceivers<br />
Save FPGA I/O resources<br />
FPGA LVDS I/O resources are too valuable to waste on<br />
duplicate signals. The DS90LV110 makes up to 10 copies of<br />
your FPGA LVDS clock or data signals <strong>and</strong> distributes the<br />
high quality signals to multiple destinations. In addition, the<br />
family of LVDS-to-LVDS switches provide active <strong>and</strong> backup<br />
channels to enable highly available systems.<br />
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Redundant cable drive application<br />
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Improve LVDS per<strong>for</strong>mance <strong>and</strong> ESD protection<br />
Boost FPGA reach <strong>and</strong> rate with enhanced signal integrity<br />
<strong>and</strong> lower jitter. The SCAN90CP02 offers programmable<br />
pre-emphasis to drive CAT-5 cables. These products also<br />
deliver superior ESD protection. <strong>Design</strong>ers can improve ESD<br />
protection by 2.5 kV to 6.5 kV by providing isolation <strong>for</strong><br />
sensitive programmable devices.<br />
DS90LV110 1:10 LVDS clock distributor<br />
<br />
<br />
Simplified FPGA programming<br />
The SCANSTA111/112 SCAN chain mux simplifies FPGA<br />
programming by managing multiple JTAG chains.<br />
LVDS interface devices to complement <strong>FPGAs</strong><br />
Product ID Description Max speed Packaging<br />
DS90CP22 2 x 2 LVDS-to-LVDS Crosspoint switch with >5 kV ESD 800 Mbps/channel SO-16, TSSOP-16<br />
SCAN90CP02 2 x 2 LVDS-to-LVDS Crosspoint switch with pre-emphasis, IEEE 1149.6 <strong>and</strong> >6.5 kV ESD 1.5 Gbps/channel LLP-28, LQFP-32<br />
SCAN50C400 Quad multi-rate, 1.25, 2.5, <strong>and</strong> 5.0 Gbps SerDes with 3.5 kV ESD 40 Gbps EBGA-440<br />
DS90CP04 4 x 4 LVDS-to-LVDS Crosspoint switch 2.5 Gbps/channel LLP-32<br />
DS90LV001 Stub hider LVDS/PECL to LVDS buffer with >2.5 kV ESD 800 Mbps LLP-8, SO-8<br />
DS92001 Signal booster LVDS/LVPECL to Bus LVDS buffer with >2.5 kV ESD 400 Mbps LLP-8, SO-8<br />
EQ50F100 2.5 Gbps to 6.125 Gbps equalizer <strong>for</strong> CML technology with 8 kV ESD 6.125 Gbps LLP-6<br />
DS90LV110A 1:10 LVDS clock distributor with >4 kV ESD 400 Mbps TSSOP-28<br />
20
High-speed data conversion ICs<br />
Product ID<br />
Resolution<br />
Speed<br />
(MSPS)<br />
Input<br />
channels<br />
Accuracy<br />
(INL) SINAD SNR SFDR THD Packaging<br />
ADC081000 8 1000 1 ±0.35 47 48 58.5 -57 TQFP-128<br />
ADC08200 8 200 1 ±1.0 46 46 60 -60 TSSOP-24<br />
ADC08L060 8 60 1 ±0.5 47.4 48 59.1 -56.9 TSSOP-24<br />
ADC1173 8 15 1 ±0.5 47.7 48.7 55 -54 SO-24, TSSOP-24<br />
ADC081S101 8 1 1 ±0.05 49.7 49.7 69 -77 SOT23-6, LLP-6<br />
ADC10080 10 80 1 ±0.5 59 59.2 78.8 -74.5 TSSOP-28<br />
ADC10065 10 65 1 ±0.3 59 59.3 80 -72 TSSOP-28<br />
ADC10D040 10 40 2 ±0.65 59 60 72 -69 TSSOP-28<br />
ADC101S101 10 1 1 ±0.2 61.7 62 78 -77 SOT23-6, LLP-6<br />
ADC12L080 12 80 1 ±1.2 66 66 80 -77 TQFP-32<br />
ADC12DL066 12 66 2 ±1.8 66 66 81 -78 TQFP-64<br />
ADC12D040 12 40 2 ±0.7 68 68 80 -78 TQFP-64<br />
ADC121S101 12 1 1 ±0.4 72 72.5 82 -82 SOT23-6, LLP-6<br />
ADC78H90 12 0.5 8 ±1.0 73 73 88 -86 TSSOP-16<br />
High-speed, low-power amplifiers<br />
Product<br />
ID<br />
SSBW<br />
(MHz)<br />
A V<br />
V/V<br />
Slew<br />
rate<br />
V/µs<br />
Spec.<br />
range (V)<br />
2nd/3rd HD<br />
into R L = 100Ω<br />
I OUT<br />
typ<br />
(mA)<br />
Voltage<br />
noise<br />
(nV/Hz)<br />
Key features<br />
Packaging<br />
LMH6609<br />
900 MHz high-output current voltage<br />
feedback<br />
900 1 1400 ±3.3 to ±6 -63/-57 at 20 MHz 90 3.1 SO-8, SOT23-5<br />
LMH6559 Ultra-high slew rate, closed-loop buffer 1750 1 4580 3 to ±5 -58/-53 at 20 MHz 74 2.8 SO-8, SOT23-5<br />
LMH6624 Ultra-low noise, wideb<strong>and</strong> 1500/95 1/20 350 ±2.5 to ±6 -63/-80 at 10 MHz 100 0.92 SO-8, SOT23-5, CERDIP-8<br />
LMH6642 130 MHz, 75 mA rail-to-rail output 130 1 135 3 to 12.8 -62 at 5 MHz 75 17 SO-8, SOT23-5<br />
LMH6645 Rail-to-rail input/output, low power 55 1 22 2.5 to 12 — 20 17 SO-8, SOT23-5<br />
LMH6654 Low noise, 250 MHz, low power 250 1 200 ±2.5 to ±6 -80/-85 at 5 MHz 80 4.5 SO-8, SOT23-5<br />
LMH6657 270 MHz single supply, CMIR < 0V 270 1 700 3 to 12 -70/-57 at 5 MHz 110 11 SC70-5, SOT23-5<br />
LMH6702 Ultra-low distortion, wide b<strong>and</strong>width 720 2 3100 ±5 to ±6 -63/-70 at 60 MHz 80 1.83 SO-8, SOT23-5, CERDIP-8<br />
LMH6714 Wideb<strong>and</strong> video 400 2 1800 ±5 to ±6 -58/-70 at 20 MHz 70 3.4 SO-8, SOT23-5, CERDIP-8<br />
LMH6723 370 MHz, 1 mA high-output current 260 2 600 4.5 to 12 -65/-63 at 5 MHz 110 4.3 SO-8, SOT23-5<br />
LMH6732 Adjustable supply current 540 2 2700 ±4.5 to ±6 -60/-64 at 20 MHz 115 2.5 SO-8, SOT23-6<br />
LM7171 30V, very high slew rate, A V = +2 (min) 220 2 4100 ±5.5 to ±15 -75/-55 at 5 MHz 100 14 SO-8, SOT23-5, CERDIP-8<br />
For more design in<strong>for</strong>mation, please refer to these guides at www.national.com/guides<br />
LVDS Owner’s Manual<br />
Broadcast Video Owner’s Manual<br />
Ultra-fast ADCs <strong>and</strong> Amplifiers <strong>Guide</strong><br />
For more LVDS in<strong>for</strong>mation:<br />
LVDS.national.com<br />
For more interface in<strong>for</strong>mation:<br />
national.com/appinfo/interface<br />
For more ADC or amplifiers in<strong>for</strong>mation:<br />
national.com/adc<br />
amplifiers.national.com<br />
21
Product summary<br />
Recommended regulators<br />
Recommended V CCINT <strong>and</strong> V CCIO regulators summary<br />
Product<br />
ID<br />
V IN<br />
V OUT options <strong>for</strong> <strong>FPGAs</strong>/<br />
<strong>CPLDs</strong><br />
Min Max<br />
Inductorless switching regulators<br />
I OUT max<br />
Shutdown<br />
Sync.<br />
buck F SW (kHz) Comments Packaging<br />
LM2788 2.6 5.5 1.5, 1.8, 2.0 120 mA ✔ — 500 — MSOP-8<br />
LM2798 2.6 5.5 1.5, 1.8, 2.0 120 mA ✔ — 500 <strong>Power</strong> good flag MSOP-10<br />
LM3352 2.5 5.5 2.5, 3.0, 3.3 200 mA ✔ — 900 — TSSOP-16<br />
LM2770 2.7 5.5 1.2, 1.5 250 mA ✔ — 700 Sleep mode LLP-10<br />
Switching buck regulators<br />
LM3670 2.5 5.5<br />
1.2, 1.5, 1.8, 2.5, 3.3 & Adj (0.7V<br />
& up)<br />
350 mA ✔ ✔ 1000 — SOT23-5<br />
LM2619 2.8 5.5 Adj (1.5V & up) 500 mA ✔ ✔ 500 to 1000 — TSSOP-14<br />
LM2671 8 40 3.3 & Adj (1.21 & up) 500 mA ✔ — 260 to 400 WEBENCH Tool SO-8, LLP-16, DIP-8<br />
LM3671 2.5 5.5 1.2, 1.5, 1.8 & Adj (0.5V & up) 600 mA ✔ ✔ 2000 — SOT23-5<br />
LM2736 3 18 Adj (1.25V & up) 750 mA ✔ — 550, 1600, 3000 WEBENCH Tool SOT23-5<br />
LM2734 3 20 Adj (0.8V & up) 1000 mA ✔ — 550, 1600, 3000 WEBENCH Tool SOT23-5<br />
LM2651 4 14 1.8, 2.5, 3.3 & Adj (1.24 & up) 1500 mA ✔ ✔ 300 WEBENCH Tool TSSOP-16<br />
LM2653 4 14 Adj (1.2V & up) 1500 mA ✔ ✔ 300 <strong>Power</strong> good flag TSSOP-16<br />
LM2655 4 14 3.3 & Adj (1.23 & up) 2500 mA ✔ ✔ 300 — TSSOP-16<br />
LM2599 4.5 40 3.3 & Adj (1.23 & up) 3000 mA ✔ — 150 WEBENCH Tool TO263-7, TO220-7<br />
LM2650 4.5 18 Adj (1.25 & up) 3000 mA ✔ ✔ 90 to 300 Sync clock SO-24<br />
LM2673 8 40 3.3 & Adj (1.21 & up) 3000 mA — — 260 WEBENCH Tool TO263-7, LLP-14, TO220-7<br />
LM2679 8 40 3.3 & Adj (1.21 & up) 5000 mA — — 260 WEBENCH Tool TO263-7, LLP-14, TO220-7<br />
Synchronous buck controllers<br />
LM3475 2.7 10 Adj (0.8V & up) 1A to 3A ✔ — DC to 2000 — SOT23-5<br />
LM2743 1 16 Adj (0.6V & up) 1A to 20A ✔ ✔ 50 to 2000 Single controller TSSOP-14<br />
LM2647 5.5 28 Adj (0.6V & up) 1A to 20A ✔ ✔ 200 to 500 Dual controller TSSOP-28, LLP-28<br />
LM5642 4.5 36 Adj (1.25V & up) 1A to 20A ✔ ✔ 150 to 250 Dual controller TSSOP-28<br />
LM2633 4.5 30 Adj (0.9V & up) 1A to 20A ✔ ✔ 250 Dual + LDO TSSOP-48<br />
LM2645 4.5 30 Adj (1.25V & up) 1A to 20A ✔ ✔ 200, 300 Dual + LDO + 3.3V TSSOP-48<br />
Linear regulators<br />
LP3990 2 6 1.2, 1.5, 1.8, 2.5, 3.3 150 mA ✔ — — 0.47 µF C OUT SOT23-5, LLP-6, micro SMD-4<br />
LP2986 2.1 16 3.3 & Adj (1.24 & up) 200 mA ✔ — — <strong>Power</strong> good flag LLP-8, MSOP-8, SO-8<br />
LP2992 2.5 16 1.5, 1.8, 2.5, 3.0, 3.3 250 mA ✔ — — <strong>Power</strong> good flag SOT23-5, LLP-6<br />
LP3981 2.7 6 2.5, 3.3 300 mA ✔ — — Low noise LDO SO-8, LLP-6<br />
LP3982 2.5 6 1.8, 2.5, 3.0, 3.3 & Adj (1.25 & up) 300 mA ✔ — — <strong>Power</strong> good flag SO-8, LLP-8<br />
LM2937 4.75 26 2.5, 3.3 500 mA — — — Transient protection SOT223-4, TO263-3, TO220-3<br />
LP2989 2.1 16 1.8, 2.5, 3.3 500 mA ✔ — — <strong>Power</strong> good flag MSOP-8, SO-8, LLP-8<br />
LP8345 2.7 10 1.8, 2.5, 3.3 & Adj (1.25 & up) 500 mA — — — — TO252-3, LLP-6<br />
LP3874 2.5 7 1.2, 1.8, 2.5, 3.3 & Adj (1.2 & up) 800 mA ✔ — — Sense pin SOT223-5, TO263-5, TO220-5<br />
LP3875 2.5 7 1.2, 1.8, 2.5, 3.3 & Adj (1.2 & up) 1500 mA ✔ — — Sense pin SOT223-5, TO263-5, TO220-5<br />
22
Select voltage supervisors/power-on-reset ICs<br />
& application notes<br />
Select voltage supervisors/power-on-reset ICs<br />
Product<br />
ID<br />
Voltage rails<br />
supervised<br />
Reset flag<br />
active<br />
Reset timeout<br />
period<br />
Low-line<br />
output<br />
Manual<br />
reset<br />
<strong>Power</strong><br />
fail comp<br />
Watchdog<br />
POR Packaging<br />
LM3704 2.35, 2.5, 2.8, 3.3, 5.0 1 Low 1.4, 28, 200, 1600 ms 2 ✔ ✔ ✔ — ✔ micro SMD-9, MSOP-10<br />
LM3705 2.5, 3.3, 5.0 1 High 1.4, 28, 200, 1600 ms 2 ✔ ✔ ✔ — ✔ micro SMD-9, MSOP-10<br />
LM3710 2.5, 3.3, 4.8, 5.0 1 Low 1.4, 28, 200, 1600 ms 2 ✔ ✔ ✔ ✔ ✔ micro SMD-9, MSOP-10<br />
LM3711 2.5, 3.3, 5.0 1 High 1.4, 28, 200, 1600 ms 2 ✔ ✔ ✔ ✔ ✔ micro SMD-9, MSOP-10<br />
LM3722/24 2.5, 3.3, 5.0 Low 190 ms — ✔ — — ✔ SOT23-5<br />
LM3723 2.5, 3.3, 5.0 High 190 ms — ✔ — — ✔ SOT23-5<br />
LP3470 2.8, 3.1, 3.3, 3.9, 4.3, 4.7, 5.0 1 Low Adj w/ external cap. — — — — ✔ SOT23-5<br />
LMC6953 3.3 <strong>and</strong> 5.0 (Dual) Low Adj w/ external cap. — ✔ — — ✔ SO-8<br />
LM8365 2.5, 3.0, 3.3, 5.0 Low Adj w/ external cap. — — — — ✔ SOT23-5<br />
1<br />
For custom reset threshold voltages between 2.2V <strong>and</strong> 5V in 10 mV increments, contact National Semiconductor.<br />
2<br />
Factory programmed options. Some of these options are available upon request. Please contact your National sales representative <strong>for</strong> more in<strong>for</strong>mation.<br />
Select Altera application notes<br />
AN-74 Evaluating power <strong>for</strong> Altera devices<br />
AN-107 Using Altera devices in multiple voltage systems<br />
AN-355 Stratix II device system power considerations<br />
AN-358 Thermal management <strong>for</strong> 90 nm <strong>FPGAs</strong><br />
To view or download these application notes, visit:<br />
www.national.com/see/alterafpga<br />
Select National application notes<br />
Linear regulators<br />
AN-1148 Linear regulators: Theory of operation <strong>and</strong> compensation<br />
AN-1254 DDR-SDRAM termination simplified using a linear regulator<br />
Packaging technology<br />
AN-1028 Maximum power enhancement techniques <strong>for</strong> power packages<br />
AN-1187 Leadless leadframe package (LLP)<br />
AN-1201 LLP-8 thermal per<strong>for</strong>mance <strong>and</strong> design guidelines<br />
Plastic-misc Plastic package dimensional/thermal data<br />
Switching regulators <strong>and</strong> controllers<br />
AN-556 Introduction to power supplies<br />
AN-558 Introduction to power MOSFETs <strong>and</strong> their applications<br />
AN-643 EMI/RFI board design<br />
AN-1149 Layout guidelines <strong>for</strong> switching power supplies<br />
AN-1197 Selecting inductors <strong>for</strong> buck converters<br />
AN-1229 SIMPLE SWITCHER PCB layout guidelines<br />
AN-1246 Stresses in wide-input DC-DC converters<br />
Other<br />
AN-1200 Mixed signal testing using the IEEE 1149.4 STA400<br />
AN-1312 SCAN bridge (STA111/STA112) timing<br />
AN-1327 Simplified programming of Altera <strong>FPGAs</strong> using a SCANSTA111/112 SCAN chain mux<br />
23
<strong>Design</strong> tools<br />
<strong>Power</strong> Expert automated power solutions finder <strong>for</strong> Altera <strong>FPGAs</strong> <strong>and</strong> <strong>CPLDs</strong><br />
Step 1. Choose Altera FPGA<br />
• Select the Altera FPGA you are using<br />
• The specific device’s power requirements are presented<br />
<strong>for</strong> your review.<br />
Step 2. Choose your operating conditions<br />
• Choose your operating conditions (i.e., input voltage,<br />
I/O voltage)<br />
• Using a slide bar, set the FPGA operating current within<br />
the allowable range — dissipated power is calculated <strong>for</strong> you.<br />
Step 3. Choose a National power solution<br />
• Choose the National solution desired — most efficient or more simple.<br />
• Review the National products that fit your design requirements<br />
<strong>and</strong> click on the links to view datasheets, design with WEBENCH<br />
tools (if available <strong>for</strong> the device), <strong>and</strong> download a sample<br />
reference design.<br />
To download this tool <strong>and</strong> view more in<strong>for</strong>mation, visit:<br />
www.national.com/see/alterafpga<br />
WEBENCH ® online design <strong>and</strong> prototyping environment<br />
Step 1. Select It<br />
• Input your design requirements<br />
• Choose a recommended part from a<br />
customized list<br />
Step 2. <strong>Design</strong> It<br />
• Adjust components <strong>and</strong> exercise<br />
operating values such as power<br />
dissipation, current flow, offset voltage,<br />
drift, <strong>and</strong> frequency response<br />
• Exchange parts to compare<br />
per<strong>for</strong>mance, size, <strong>and</strong> cost<br />
• Use recommended components or<br />
create a custom BOM<br />
Step 3. Analyze It<br />
• Stimulate your circuit <strong>and</strong> evaluate per<strong>for</strong>mance<br />
using electrical <strong>and</strong> thermal simulations<br />
• Overlay alternate circuits <strong>and</strong> compare results<br />
to get optimal per<strong>for</strong>mance<br />
Step 4. Build It<br />
• Request samples <strong>and</strong> purchase<br />
parts or demo boards<br />
• Receive your custom prototyping<br />
kit the next business day<br />
• Download your automatically<br />
generated CAD files, assembly<br />
details, test instructions,<br />
<strong>and</strong> complete per<strong>for</strong>mance<br />
characteristics — instantly!<br />
Step 5. Test It<br />
• Download your custom test<br />
vectors to verify your real board<br />
versus virtual results<br />
• Per<strong>for</strong>m board-level tests<br />
using National Instruments’<br />
SignalExpress software<br />
To use this tool <strong>and</strong> view more<br />
in<strong>for</strong>mation, visit:<br />
webench.national.com<br />
24
Featured power management solutions<br />
Switching regulators<br />
LM2798, LM3352, LM2770 Inductorless switching regulators<br />
• 1.2, 1.5, 1.8, 2.5, 3.0 <strong>and</strong> 3.3V out<br />
• Step-down <strong>and</strong>/or step-up<br />
• Up to 250 mA I OUT<br />
• High efficiency (80%)<br />
• No inductor required, uses small ceramic caps<br />
• Always stable: no compensation required<br />
• High switching frequency<br />
• Ideal <strong>for</strong> high-efficiency CPLD power <strong>and</strong> batteryoperated<br />
devices<br />
LM2798 Simple block diagram<br />
V OUT = 1.5V, 1.8V, or 2.0V<br />
V IN = 2.6V to 5.5V<br />
I OUT up to 120 mA<br />
10 µF<br />
V IN<br />
C1+<br />
V OUT<br />
C2+<br />
10 µF<br />
1 µF 1 µF<br />
C1- LM2798 C2-<br />
EN<br />
BATOK<br />
POK<br />
GND<br />
LP385x/7x High-per<strong>for</strong>mance CMOS LDOs<br />
• Ultra-low dropout voltage (280 mV @ 1.5A,<br />
450 mV @ 3A max at 25°C)<br />
• Stable with 10 µF ceramic caps (LP385x)<br />
• Option <strong>for</strong> sense pin (LP3855/56) <strong>and</strong> error flag<br />
(LP3852/53)<br />
<br />
LP3853 Typical application diagram<br />
<br />
<br />
• Low ground-pin current (4 mA @ 3A)<br />
• On/off control<br />
• Over-temperature/over-current protection<br />
• Available in TO263-5, TO220-5, <strong>and</strong> SOT223-5<br />
packaging<br />
Output current Product ID V OUT options V OUT accuracy V IN range<br />
Single input rail (<strong>for</strong> V IN ≥ 2.5V)<br />
Dropout voltage<br />
full load (mV)<br />
Packaging<br />
800 mA LP3871/74 1.8, 2.5, 3.3, 5.0, Adj* 1.5% 2.5 to 7.0 300 TO263-5, TO220-5, SOT223-5<br />
1.5A LP3852/55 1.8, 2.5, 3.3, 5.0, Adj* 1.5% 2.5 to 7.0 280 TO263-5, TO220-5, SOT223-5<br />
1.5A LP3872/75 1.8, 2.5, 3.3, 5.0, Adj* 1.5% 2.5 to 7.0 450 TO263-5, TO220-5, SOT223-5<br />
3A LP3853/56 1.8, 2.5, 3.3, 5.0, Adj* 1.5% 2.5 to 7.0 450 TO263-5, TO220-5<br />
3A LP3873/76 1.8, 2.5, 3.3, 5.0, Adj* 1.5% 2.5 to 7.0 1000 TO263-5, TO220-5<br />
Dual input rail (<strong>for</strong> V IN ≥ 1.5V)<br />
800 mA LP3881 1.2, 1.5, 1.8, Adj 1.5% V OUT + V DO > 5.5 120 TO263-5, TO220-5<br />
800 mA LP3891 1.2, 1.5, 1.8, Adj 1.5% V OUT + V DO > 5.5 300 TO263-5, TO220-5<br />
1.5A LP3882 1.2, 1.5, 1.8, Adj 1.5% V OUT + V DO > 5.5 170 TO263-5, TO220-5<br />
1.5A LP3892 1.2, 1.5, 1.8, Adj 1.5% V OUT + V DO > 5.5 320 TO263-5, TO220-5<br />
3A LP3883 1.2, 1.5, 1.8 1.5% V OUT + V DO > 5.5 270 TO263-5, TO220-5<br />
3A LP3893 1.2, 1.5, 1.8 1.5% V OUT + V DO > 5.5 650 TO263-5, TO220-5<br />
*Adj available in LP3855/56/74/75/76<br />
25
National Semiconductor continually exp<strong>and</strong>s its product portfolio to offer the broadest range of<br />
power management <strong>and</strong> other analog solutions in the industry. For more in<strong>for</strong>mation on National’s<br />
solutions <strong>for</strong> Altera <strong>FPGAs</strong> <strong>and</strong> <strong>CPLDs</strong>, visit us today at www.national.com/see/alterafpga<br />
Americas<br />
Email: new.feedback@nsc.com<br />
Phone: 1-800-272-9959<br />
Europe<br />
Fax: +49 (0) 180-530 85 86<br />
Email: europe.support@nsc.com<br />
Phone:<br />
Deutsch +49 (0) 69 9508 6208<br />
English +44 (0) 870 24 0 2171<br />
Français +33 (0) 1 41 91 87 90<br />
Asia Pacific<br />
Email: ap.support@nsc.com<br />
Japan<br />
Fax: 81-3-5639-7507<br />
Email: jpn.feedback@nsc.com<br />
Phone: 81-3-5639-7560<br />
Packaging<br />
LLP ®<br />
(Leadless leadframe)<br />
JA 40 to 60°C/W<br />
National’s LLP ® provides excellent power dissipation<br />
capability in a very small package footprint. Unlike<br />
conventional leaded plastic packages, the LLP contains<br />
pads on the bottom of the package <strong>for</strong> PCB mounting.<br />
micro SMD<br />
(small <strong>and</strong> large bump)<br />
JA 220 to 290°C/W<br />
MDIP<br />
(Molded dual-in-line package)<br />
JA 30 to 90°C/W<br />
MSOP<br />
(Mini 8-lead)<br />
JA 220°C/W<br />
PSOP-8<br />
JA 43°C/W<br />
SO<br />
(Small outline<br />
molded/ceramic)<br />
JA 100 to 190°C/W<br />
SOT-223<br />
(<strong>Power</strong> surface mount)<br />
JA 60 to 110°C/W<br />
SOT-23<br />
JA 120 to 290°C/W<br />
TO-220<br />
JA 45 to 65°C/W<br />
TO-252<br />
(DPAK)<br />
JA 60 to 90°C/W<br />
TO-263<br />
(<strong>Power</strong> surface mount)<br />
JA 35 to 60°C/W<br />
TSSOP<br />
JA 40 to 150 °C/W<br />
N a t i o n a l<br />
Semiconductor<br />
The Sight & Sound of In<strong>for</strong>mation<br />
© National Semiconductor Corporation, March 2005. National Semiconductor, , LLP, WEBENCH, LMH, <strong>and</strong> SIMPLE SWTICHER are registered trademarks of National Semiconductor. Altera, Stratix,<br />
Stratix II, Cyclone <strong>and</strong> MAX II are trademarks of Altera Corporation. Bluetooth is a registered trademark of Bluetooth SIG, Inc. <strong>and</strong> is used under license by National Semiconductor.<br />
Signal Express is a trademark of National Instruments. All rights reserved.<br />
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