10Gbps Optical Receiver and VCSEL Driver in 0.13um CMOS ...

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and feedback TIAs. The goal when designing a TIA, is to provide a low input impedance in order to meet the bandwidth requirements, while also providing low noise and high gain. The characteristics and performance of these two topologies will be discussed below. Open Loop TIAs Open loop TIAs generally use common gate topology since this device is capable of providing a low input impedance. A typical common gate TIA is shown in Fig 2.6. The transistor M 1 is the common gate transistor with a resistive load R D , while current source I D provides a bias current. Since all of the photodiode current passes through the load resistance, R D , the transimpedance gain is equal to R D . The input resistance of this amplifier is given: R in r + R ≈ (2.6) 01 D 1 ≈ 1+ g m1r01 g m1 where r 0 is the drain to source resistance, g m1 is the transconductance. This equation assumes that internal resistance of current source, I D , is sufficient large. This is an important result because the bandwidth is independent of the transimpedance gain set by R D . In reality, if R D is increased too much, the output pole formed with the parasitic output capacitance of the common gate transistor will determine the bandwidth. 13
Figure 2.6 Common-Gate TIA The unfortunate downside of this TIA is that the noise current produced by the load resistance R D and the bias current source I D are directly referred to the input with a unity factor. The noise contributions from these two sources have trade-off with each other. The load resistor can be increased in order to reduce its noise contribution. In order to maintain the proper biasing conditions, the bias current would need to be reduced which would increase the noise contribution of I D . If the bias current is maintained, the supply voltage would need to be increased. In order to reduce the noise contribution from the bias current source, the bias current can be increased. Again, to maintain the bias conditions, the load resistor would need to be decreased, which would increase the noise contribution from the load resistor. If the load resistor is kept the same, the supply voltage would again need to be increased to maintain the transistor in saturation. Improving the noise 14
Page 1 and 2: 10-Gb/s Optical Receiver and VCSEL
Page 4 and 5: Contents Figure Index______________
Page 6 and 7: Figure 2.12 (a) Common-Gate and (b)
Page 8 and 9: Table Index Table 1. Measurement Re
Page 10 and 11: low-noise characteristics. However,
Page 12 and 13: Chapter Ⅰ Introduction 1.1 Optica
Page 14 and 15: An optical communication system gen
Page 16 and 17: Chapter Ⅱ 10-Gb/s Optical Receive
Page 18 and 19: performance of receiver. The photod
Page 20 and 21: Photodiode C PD I in TIA + V out -
Page 22 and 23: sensitivity of the whole receiver.
Page 26 and 27: performance of this device comes at
Page 28 and 29: + V in - + + LA - - + V out - Figur
Page 30 and 31: 2.2 10-Gb/s Optical Receiver Analog
Page 32 and 33: inversely proportional to BW 3-dB .
Page 34 and 35: common-gate configuration. For exam
Page 36 and 37: 2.14 shows schematic of DC offset c
Page 38 and 39: ω 3− dB GBW Our work Figure 2.16
Page 40 and 41: in Fig 2.20. Optical receiver maint
Page 42 and 43: 3.1 Background 3.1.1 VCSEL CHAPTER
Page 44 and 45: electrical and optical dBs. As indi
Page 46 and 47: 3.2 Design of VCSEL Driver 3.2.1 Pr
Page 48 and 49: 3.3 Simulation Results Figure 3.6 E
Page 50 and 51: (b) Figure 4.1 Microphotographs of
Page 52 and 53: MM410C (optical power monitor and a
Page 54 and 55: transimpedance amplifiers and limit
Page 56 and 57: (d) Figure 4.4 Eye Patterns of the
Page 58 and 59: CHAPTER Ⅴ Conclusion In this diss
Page 60 and 61: Bibliography [1] Wei-Zen Chen and D
Page 62 and 63: [12] Behnam Analui and Ali Hajimiri
Page 64 and 65: 국문요약 CMOS 0.13-μm 공정
Page 66: 다. 본 연구에서 설계된 광

10Gbps Optical Receiver and VCSEL Driver in 0.13um CMOS ...

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