UFS UniPro and PHY Tutorial - Arasan

UFS PHY & UniPro ®
Yuping Chung
Arasan Chip Systems
San Jose, CA
Taiwan Mobile Memory Workshop
Oct. 12, 2011

Agenda
1. MIPI and UFS in Mobile Devices
2. M-PHY - Physical Layer
3. UniPro ® Link layer

mipi – A Mobile Device Interconnect
Platform
IEEE
1149.7
GBT
Display
WLAN, WigIG
WirelessHD, etc
Bluetooth, GPS
FM Radio, NFC
LLI/SSIC/UniPort
Application
Processor (host)
DSI
CSI
Camera
Speakers
Microphones
SLIMbus
LLI UniPort
LLI UniPort
UFS
Companion
or
Bridge Chip
Storage
Baseband /
Modem
SPMI
Switch
Power Amp
DigRF
Power
Management
UniPort = M-PHY + UniPro
Tuner
RFFE
RFIC
UniPort = D-PHY + UniPro
Source: mipi Alliances

“One PHY to Bind Them All”
Objectives
1. Low pin count
2. Long-distance (m) and short-distance (mm) applications
3. Wide range of speed: ~3 Mbps to ~5 Gbps
4. Power efficient w/ burst-mode
5. Clocking: shared or non-shared reference clocks
6. EMI friendly

Device Manager
(QueryRequest)
UFS Architecture
Application Layer
UFS CommandSet Layer (UCS)
UFS Native
Command Set
Simplified SCSI
Command Set
Future
Extension..
Task Manager
UIO_
SAP
UDM_
SAP
UTP_CMD_SAP
UFS Transport Protocol Layer (UTP)
UIC_SAP
UFS InterConnect Layer (UIC)
MIPI UniPro
MIPI M-PHY
UTP_TM_SAP
Source: JEDEC

UFS InterConnect Layer (UIC)
UniPro ® & M-PHY
Device Manager
(QueryRequest)
UIO_
SAP
UFS InterConnect Layer (UIC)
L4 = Transport
L3 = Network
L2 = Data Link
L1.5 = PHY adapter
L1 = M-PHY
MIPI UniPro
MIPI M-PHY

Universal Flash Storage – UFS
Interconnect Layer
Application Processor
(Host)
Storage
(device)
UniPro
M-PHY
M-PHY
UniPro
Application
Processor
(host)
L4 = Transport
L3 = Network
L2 = Data Link
L1.5 = Phy adapt
PLL
HS-Tx
LS -Tx
R T
-
R
T
TX
Dp
Dn
UFS
Clock Data
Recovery Unit
HS-RX-
LS -Rx
Squelch
Detector
R T
PLL
-
R
T
RX
Analog
Dp
Dn
L4 = Transport
L3 = Network
L2 = Data Link
L1.5 = Phy adapt

LINE: copper or optical
MODULE
+ +
- LINE
-
MODULE

LANE: unidirectional
M-TX
LANE
+ +
- LINE
-
M-RX

SUB-LINK: Group of Lanes in same direction
M-TX
M-TX
SUB-LINK
LANE
+ +
- LINE
-
LANE
+ +
-
-
LINE
M-RX
M-RX
M-RX
M-RX
SUB-LINK
+ +
- LINE
-
+ +
- LINE
-
M-TX
M-TX

M-Port: A set of M-TX + M-RX
M-Port
M-Port
M-TX
M-TX
LANE
+ +
- LINE
-
LANE
+ +
-
-
LINE
M-RX
M-RX
M-RX
M-RX
+ +
- LINE
-
+ +
- LINE
-
M-TX
M-TX

LINK: 2 sub-links w/ opposite directions + Lane
Management
LINK
HOST
Lane Management
M-Port
M-TX
M-TX
M-RX
M-RX
SUB-LINK
LANE
+ +
- LINE
-
LANE
+ +
-
-
LINE
SUB-LINK
+ +
- LINE
-
+ +
- LINE
-
M-Port
M-RX
M-RX
M-TX
M-TX
DEVICE
Lane Management

UFS M-PHY Interface Features
1. Separate Power Supply for I/O & Core
– VCCQ: 1.2V – logic, controller, I/O
– VCCQ2: 1.8 – controller & I/O
– Supply: 1.8V/3.3V; NVM
2. Signaling Amplitude
– 400mVp/240mVp (not terminated)
– 200mVp/120mVp (terminated)
3. Signaling schemes
– PWM (Pulse Width Modulation)
– NRZ (Not Return to Zero)

UFS M-PHY Interface Features (con’t)
4. Multiple Gears
– LS: PWM Gear 1-4 supported, Gear 5-7 optional, Gear
0 not supported
– HS: Gear 1 mandatory, Gear 2/3 optional
5. Coding – 8b10b
6. Power Management States
– Stall (HS), Sleep (LS), Hibern8, Disabled, Unpowered
7. Reliability – bit error rate (BER) less than 10 -10

Main properties of M-PHY
UFS M-PHY Features Mode Detail
No. of Pins / Lane 2
Lanes supported
Direction
Min. Configuration
Medium
Singaling Scheme
Bit Rate
Ref. Clock
Ref. Clock Freq.
Symbol Encoding
type 1
type 2
HS
LS
LS
Up to 4 Lanes
Unidirectional
Dual-simplex, 1 lane each, 4 wires
0-30 cm PCB micro coax,

M-PHY Line Signaling Properties
Low-swing, DC-coupled Differential Signaling
M-TX
0.4V
Z OUT=50
Z OUT=50
Small Amplitude
240mVpk – not terminated
120mVpk – resistor terminated
M-RX
Large Amplitude
400mVpk – not terminated
200mVpk – resistor terminated
R T
R T

Signaling Schemes
1. PWM
- Pulse Width Modulation
- Type 1 MODULE
2. NRZ
- Not Return to Zero
- Type 2 MODULE
DIF-P
Logic 1
DIF-N
DIF-P
Logic 0
DIF-N
0 0 1 0 1 1

Multiple Gears
HIGH SPEED
Gear Bit Rate Imlementaition
1 1.25 Gbps Mandatory
LOW SPEED
Gear Bit Rate Implementation
0 below Gear 1 not supported
2 2.5 Gbps Optional
3 ~5 Gbps Future Revision
1 3 to 9 Mbps
2 6 to 18 Mbps
3 12 to 36 Mbps
4 24 to 72 Mbps
5 48 to 144 Mbps
6 96 to 288 Mbps
7 192 to 576 Mbps
Mandatory
Optional

8b10b Coding
8-bit data
3b4b
Sub-block
f
H G F
g h
i
E D C B A
a
b c d e
i
5b6b
Sub-block
1. Data Symbol
– Each byte = 5b6b + 3b4b sub-block encoding
– Differences of 1’ and 0’s is not more than one
2. Control Symbol
10-bit coding
– Special symbols that do not occur in the data symbol set
– eg. K28.1 001111 0101

Power Management States
STALL
SLEEP
HIBERN8
DISABLED
UNPOWERED
For HS-MODE; Power Saving without sever penalty
on HS-BURST start-up time
For LS-MODE; Lowest power consumption for all
ACTIVED states
Ultra-low power consumption while maintaining
configuration settings
Operation is disabled by RESET signal;
configuration reset to default values
Power supply to MODULE is withdrawn;
configuration settings are lost

Shared Clocks: “With or Without You”
SM
PLL
CODER
SERI
TXIO
RXIO
Ph&DR
DECODE
DECODE
Ph&DR
RXIO
TXIO
SERI
CODER
SM
PLL
SM
PLL
CODER
SERI
TXIO
RXIO
Clk&DR
DECODE
DECODE
Clk&DR
RXIO
TXIO
SERI
CODER
SM
PLL
With
shared Clock reference signal
Without
shared Clock reference signal

Example of Implementation

M-PHY IP Features
• Specification: MPHY Rev 1.0
• Single Power Supply: I/O & Core
• Differential Signaling: Small Amplitude and
Large Amplitude
• 8b10b line coding, as defined by MPHY
• High reliability – BER of 10 -10
• Two signaling schemes supported
– Low-speed mode with PWM signaling scheme
– High-Speed burst mode

M-PHY IP Features
• Supports high speed data transfer G1A/B and G2A/B with data rates
of up to 2915.2 Mb/s
• Supports MPHY Type-I system
• Support for reference clock frequencies of 19.2MHz / 26MHz /
38.4MHz / 52MHz
• Reference clock shared between Host and device
• Supports low speed transfer G1-G6 with a bit rate of up to 288 Mb/s
• PWM signaling for Low speed data

M-PHY IP Features (Con’t)
• Supports error detection mechanism for sequence errors and contentions
• Data lanes support transfer of data in high speed mode.
• Supports LS burst, HS burst, STALL, SLEEP, HIBERN8 states.
• Supports squelch detection
• Activates and disconnects high speed terminators for reception and
transmission.
• Supports standard PHY transceiver compliant to MIPI Specification
• Supports standard PIF interface compliant to MIPI Specification
• On-chip clock generation configurable for either transmitter or a receiver

Analog M-PHY Type I
Analog
PHY configurable
• Up to 4 lanes
• HS Rx/Tx
•Universal (UniPro/UFS)
Ref Clock
•Rx Only or Tx Only (CSI3)
19.2/26/38.4/52 (MHz)
HS Gear 1 and 2
PWM 1 thru 6
PLL
Squelch Detector
Clock data recovery at HS
Clock Data
Recovery Unit
HS-RX -
LS -Rx
Squelch
Detector
PLL
HS-Tx
R T
PLL
R
-
R T
T
RX
Dp
Dn
Dp
Dn
LS -Tx
-
R T
TX

Digital M-PHY
Local Reset
RX- Data
interface
RX- control
interface
M-RX
Registers
Protocol
Checker
Error
Detector
local ref clock
Data Recovery
Unit [PWM]
De-Serialzer
&
8b10b decoder
NRZ Decoder
State Monitor
• Protocol Interface (PIF)
• Supported on the application side
• Clock divider generates clock for PIF
• Mode Support
• High speed Mode (HS)
• Low speed Mode (LS)
• Data Lanes
• Unidirectional
M-TX
• 8b10b encoding
PIF
TX- Data
interface
ROM
Registers
PWM bit coding
• PWM coding at LS mode (Type i)
• Activates and disconnects
• HS terminators for reception
TX- control
interface
November 30, 2011
Protocol
generator
Serialzer
&
8b10b encoder
NRZ encoder
State Driver
• LS terminators for reception
(Optional)
• Error detection for running digital
sum and symbol coding errors

Agenda
1. MIPI and UFS in Mobile Devices
2. M-PHY - Physical Layer
3. UniPro ® Link layer

UFS UniPro 1.4 Overview
(Unified Protocol)

mipi – A Mobile Device Interconnect
IEEE
1149.7
GBT
Display
WLAN, WigIG
WirelessHD, etc
Bluetooth, GPS
FM Radio, NFC
LLI/SSIC/UniPort
Application
Processor (host)
DSI
CSI
Camera
Speakers
Microphones
SLIMbus
LLI UniPort
LLI UniPort
UFS
Companion
or
Bridge Chip
Storage
Baseband /
Modem
SPMI
Switch
Power Amp
DigRF
Power
Management
UniPort = M-PHY + UniPro
Tuner
RFFE
RFIC
UniPort = D-PHY + UniPro
Source: mipi Alliances

Universal Flash Storage – UFS
Interconnect Layer
Application Processor
(Host)
Storage
(device)
Application
Processor
(host)
UniPro
L4 = Transport
L3 = Network
L2 = Data Link
L1.5 = Phy adapt
M-PHY
PLL
HS-Tx
LS -Tx
R T
-
R
T
TX
Dp
Dn
UniPort =
M-PHY + UniPro
UFS
UniPort =
M-PHY + UniPro
M-PHY
Clock Data
Recovery Unit
HS-RX-
LS -Rx
Squelch
Detector
R T
PLL
-
R
T
RX
Analog
Dp
Dn
UniPro
L4 = Transport
L3 = Network
L2 = Data Link
L1.5 = Phy adapt
Storage
Device

Device Manager
(QueryRequest)
UFS Architecture
Application Layer
UFS CommandSet Layer (UCS)
UFS Native
Command Set
Simplified SCSI
Command Set
Future
Extension..
Task Manager
UIO_
SAP
UDM_
SAP
UTP_CMD_SAP
UFS Transport Protocol Layer (UTP)
UIC_SAP
UFS InterConnect Layer (UIC)
MIPI UniPro
MIPI M-PHY
UTP_TM_SAP

UFS InterConnect Layer (UIC)
UniPro ® & M-PHY
Device Manager
(QueryRequest)
UIO_
SAP
UFS InterConnect Layer (UIC)
L4 = Transport
L3 = Network
L2 = Data Link
L1.5 = PHY adapter
L1 = M-PHY
MIPI UniPro
MIPI M-PHY

UniPro (“Unified Protocol”)
A layered protocol stack for
LA - Reuse-able
device-independent
Application-specific
protocols
(LA)
L4 - Multiplex-able packets, connections
L3 - Network-able
L2 - Reliable
L2 - Latency aware
routing
retries, flow control
preemption
L1.5 - Scalable multi-lane
L1.5 - PHY-independent abstraction
L1 - Low power
low swing, CMOS modes
Scope of UniPro Standards
Device Management Entity
(DME)
Transport (L4)
Network (L3)
Data Link (L2)
PHY Adapter
(L1.5)
L1 - High speeddifferential, serial, strip line
PHY (L1)
…data exchange between
components in a mobile device.
Medium

UFS UniPro Function and Data Flow
• Packet-based interconnect are tightly aligned
Layer
Data Unit
[ LA = Application ]
Message
Network / Transport Layer
Tx: Segmentation & packet composition
L4 = Transport
Segment
Rx: Reassembly and decomposition
L3 = Network
Packet
Data Link Layer
Tx: Frame composition and CRC generation
L2 = Data Link
Frame
Rx: Frame decomposition and CRC checker
PHY Adapter
Symbol generation/degeneration
Power Management
L1.5 = Phy adapt
L1 = M-PHY
17-bit Symbol
Coded Symbol

UFS UniPro (Data) Payload
• Maximum payload size per Packet is (slightly more than) 256 Bytes
– Overhead per Packet is currently 8 Bytes
– Application normally doesn’t bother about Packet boundaries (auto segmentation)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
ESC_DL
CTRL_ID=SOF TC Reserved
0
L3s=1
DestDeviceID
L4s=1 DestCPortID
0
0
0
0
0
0
L4 Payload
L4 Payload
L4 Payload
L4 Payload
L4 Payload
L4 Payload
L4 Payload
L4 Payload
L4 Payload
L4 Payload
L4 Payload
L4 Payload
1
0
ESC_DL
CTRL_ID=EOF
CCITT CRC-16
Frame Seq. Number
FCT EOM
[ LA = Application ]
C-PORT
L4 = Transport
L3 = Network
L2 = Data Link
L1.5 = PHY adapter
L1 = M-PHY
Note: Color coded matching each layer

L1.5 Features
[ LA = Application ]
L4 = Transport
L3 = Network
L2 = Data Link
L1.5 = Phy adapt
L1 = M-PHY
1. Supports up to 4 data lanes per direction;
Detect data lanes connected, how they are
connected, and assign numbering
2. Transmission and reception of L2 control &
data symbols, and L1 PHY symbols
3. Symbol encoding for byte stream – 8b10b
encoding scheme
4. Initialization & Re-initialization of PHY Tx
path

L1.5 Features (con’t)
[ LA = Application ]
L4 = Transport
L3 = Network
L2 = Data Link
L1.5 = Phy adapt
L1 = M-PHY
5. Abstracts M-PHY Power States
L1.5 Power Management Mapping
L1.5
Power Mode
L1
Power State
comment
Fast_Mode = STALL_STATE When in FAST_STATE
Slow_Mode = SLEEP_STATE (LS) When in SLOW_STATE
Hibernate_Mode = HIBERN8_STATE Ultra-lower power
DISABLED_STATE
Off_Mode = UNPOWERED_STATE
FastAuto_Mode
SlowAuto_Mode
As if in
FAST/SLOW_STATE but
with latency due to wake
up from SLEEP_STATE to
FAST_STATE

1. 17-bit logical symbols
L1.5 Symbol, PACP Frame
[ LA = Application ]
L4 = Transport
L3 = Network
L2 = Data Link
L1.5 = Phy adapt
L1 = M-PHY
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
0
L1.5 payload
L1.5 payload
1= Control Symbol
0= Data Symbol
2. PACP Frames used to communicate between L1.5 at one end to L1.5 at
the other end of the link
• Very specialized usage – low-level reset, remote Get/Set, PHY testing
etc
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
ESC_PA
EscParam_PA = PACP_BEGIN
0
0
0
0
PACP_FunctionID
Parameters
. . . . . .
CRC-16

L2 Features
[ LA = Application ]
L4 = Transport
L3 = Network
L2 = Data Link
L1.5 = Phy adapt
L1 = M-PHY
Major responsibility is to provide RELIABLE links and
PRIORITIZE data traffic
1.Frame composition / decomposition
2.Flow Control – Credit based flow control to prevent overflow
3.16-bit CRC generation, verification, and error detection
– AFC – Acknowledgement and Flow Control, data
– NAC - Negative Acknowledgement Control, i.e. CRC error
4.2 Traffic Class (TC) by priority based arbitration
– UFS requires on TC0 (best effort)
5.Tx retry buffer and Rx buffer (Size Configurable)

L2 Data Frames
• Cluster 17-bit symbols in to Data FRAME
– 1-symbol header, 2-symbol trailer (including CRC-16), & up to 144 17-bit
symbols
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
0
0
0
0
0
0
0
ESC_DL
CTRL_ID=SOF
L2 Payload
L2 Payload
L2 Payload
L2 Payload
L2 Payload
. . . . . .
L2 Payload
TC Reserved
1
0
ESC_DL
CTRL_ID=EOF
CCITT CRC-16
Frame Seq. Number
[ LA = Application ]
C-PORT
L4 = Transport
L3 = Network
L2 = Data Link
L1.5 = PHY adapter
L1 = M-PHY

L2 Control Frames
[ LA = Application ]
L4 = Transport
L3 = Network
L2 = Data Link
L1.5 = Phy adapt
L1 = M-PHY
1. Allow L2 to talk to peer L2 for flow control and error handling
2. L2 Flow Controls – Credit-based flow control
3. AFC & NAC Control Frames
AFC – Acknowledgement and Flow Control – things are going well
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
ESC_DL AFC TC CReq
0
0
Frame Seq. Number Reserved
CCITT CRC-16
Credit value
Reserved
NAC – Negative Acknowledgement and Control – result of transmission errors
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
ESC_DL
NAC
Reserved
0 CCITT CRC-16
CReq

L3 - Network Layer
Allow data to be routed to proper destination
• Packet composition / decomposition –
– Information passed down to L2 – encapsulated between L2 header
and trailer
• Device ID –
– 7-bit destination address
– Up to 128 Devices supported
[ LA = Application ]
L4 = Transport
L3 = Network
L2 = Data Link
L1.5 = Phy adapt
L1 = M-PHY
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
ESC_DL
SOF TC Reserved
0
L3s=1
DestDeviceID_Enc
L3 Payload
0
0
L3 Payload
L3 Payload
L3 Payload
L3 Payload
1
0
ESC_DL
EOF_EVEN
CCITT CRC-16
Frame Seq. Number

[ LA = Application ]
L4 = Transport
L3 = Network
L2 = Data Link
L4 - Transport Layer
L1.5 = Phy adapt
L1 = M-PHY
Transport Layer supports multiple bidirectional
connections between endpoint devices.
– Cport – interface between L4 and ApplicatIon Layer (LA)
– Responsible for “spliting” or segmenting Message to
Segments
– End-to-End flow control ensures transmitting CPort never
sends more data than receiving CPort can absorb to
prevent data loss

L4 Segment
– When passed down to L3, L4 Segment is prefixed with L3 header
to form a single L3 Packet
– L3 Packet is then encapsulated by L3 between L2 header and an
L2 trailer to form a single L2 Frame
• Maximum payload size per Packet is 272 Bytes
16 15
–
14
Overhead
13 12
per
11
Packet
10 9is currently
8 7
86 Bytes
5 4 3 2 1 0
1
ESC_DL
SOF TC Reserved
0
L3s=1
DestDeviceID
L4s=1 DestCPortID FCT EOM
C-PORT
0
L4 Payload
L4 Payload
0
L4 Payload
L4 Payload
L4 = Transport
0
L4 Payload
L4 Payload
L3 = Network
. . . . . . .
0
L2 = Data Link
0
L4 Payload
L4 Payload
0
L4 Payload
L4 Payload
L1 = M-PHY
1
ESC_DL
EOF_EVEN Frame Seq. Number
0
CCITT CRC-16
[ LA = Application ]
L1.5 = PHY adapter
Note: Color coded matching each layer

DME – Device management Entity
Controls all layers in UniPro
1. Provide access to control parameters in all layers
2. Manages power mode transition
3. Handles boot-up, hibernate, and reset of the
entire UniPro stack
Scope of UniPro Standards
Device Management Entity
(DME)
Application-specific
protocols
(LA)
Transport (L4)
Network (L3)
Data Link (L2)
PHY Adapter
(L1.5)
PHY (L1)
Medium

UniPro Usage Model

Usage Models: Simple point-to-point
UniPro
Display
Application
Processor
Graphics
Coprocessor
I2C
Camera

Usage Models: Switch model
Camera2
Display
UniPro
UniPro
UniPro
Highspeed
Modem
switch
Application
Processor
switch
Graphics
Coprocessor
Camera1

Example of Implementation
Unified Protocol

UFS UniPro SW Stack
CustomDriver
Interface Layer
UniPro Stack Layer
Hardware Interface Layer
O S
W
R
A
P
P
E
R
O S
C
A
L
L
S
Modular
Independent
Portable
Structured API
OS Wrappers
OS Independency

Hardware Interface Layer
• System Bus Management
• Host Controller Register
• Interrupt Handling
• Direct Memory Access
• Multiple Device Management
CustomDriver
Interface Layer
UniPro Stack Layer
Hardware Interface Layer
O
S
W
R
A
P
P
E
R
O
S
C
A
L
L
S
• Debug Support

UniPro Stack Layer
• Device and Client Management
• Data Reception and Transmission
• Data Buffer Management for each
device
• Port Configuration
• Client Interface
• Information Elements
• Debug Support
CustomDriver
Interface Layer
UniPro Stack Layer
Hardware Interface Layer
O
S
W
R
A
P
P
E
R
O
S
C
A
L
L
S

UFS UniPro Development System
UFS Host FPGA platform – Interfaces and connectivity
Linux System
UFS Host FPGA
UFS Host
Driver
PCIe API
Interface
P
C
I
e
I
/
F
U
N
I
P
R
O
U
F
S
M-
P
H
Y
M-Phy
UFS Device

UFS UniPro Certification Test

Questions?
Yuping Chung
Arasan Chip Systems
San Jose, CA
yuping.chung@arasan.com
Cell +1 (408)691-6086
Work +1 (408)282-1600 x133