Superconducting Technology Assessment - nitrd

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TABLE OF CONTENTS EXECUTIVE SUMMARY Assessment Objective and Findings 01 Limitations of Current Technology 02 Panel Tasked 02 RSFQ Technology Is Viable 03 Roadmap Created 04 Government Investment Crucial 05 Technical Issues 05 Conclusions 05 CHAPTER 01: INTRODUCTION 1.1 NSA Dependent on High-End Computing 07 1.2 Limitations of Conventional Technology for High-End Computing 08 1.2.1 Conventional Silicon Technology Not the Answer 08 1.2.2 Supercomputing RSFQ a Viable Alternative 08 1.3 What is RSFQ Circuitry? 09 1.3.1 Josephson Junctions 09 1.3.2 RSFQ Attributes 10 1.4 Summary of Panel’s Efforts 10 1.4.1 RSFQ Ready for Investment 11 1.4.2 RSFQ Can Leverage Microprocessor Technology 11 1.5 Roadmap Created and Government Investment Needed 11 1.5.1 Funding 13 1.6 Technical Issues 13 1.6.1 Supercomputing System Constraints on the Use of RSFQ 13 1.6.2 Fast, Low Latency Memory 15 1.6.3 High-Speed Input/Output 15 1.6.4 CAD Tools 15 1.6.5 Refrigeration 15 1.7 State of the Industry 15 1.8 Contents of Study 16 1.9 Chapter Summaries 16
CHAPTER 02: ARCHITECTURAL CONSIDERATIONS FOR SUPERCONDUCTOR RSFQ MICROPROCESSORS 2.1 Superconductor Microprocessors–Opportunities, Challenges, and Projections 25 2.2 Microprocessors – Current Status of RSFQ Microprocessor Design 28 2.2.1 SPELL Processors for the HTMT Petaflops System (1997-1999) 28 2.2.2 20-GHz, 8-bit FLUX-1 Microprocessor (2000-2002) 29 2.2.3 CORE1 Bit-serial Microprocessor Prototypes (2002-2005) 30 2.2.4 Proposal for an RSFQ Petaflops Computer in Japan (est. 2005-2015) 30 2.3 Microprocessors – Readiness 32 2.4 Microprocessors – Issues and Concerns 33 2.4.1 Clocking for 50 GHz RSFQ Processors 33 2.4.2 Long Processing Pipelines 33 2.4.3 On-chip Interconnect, Chip Area Reachable in a Single Cycle, and Register File Structures 33 2.4.4 Memory Hierarchy for Superconductor Processors and Systems 34 2.4.5 Memory Latency Tolerant Architectures 35 2.5 Microprocessors – Conclusions and Goals 36 2.6 Microprocessors – Roadmap and Milestones 37 2.7 Microprocessors – Funding 38 CHAPTER 03: SUPERCONDUCTIVE RSFQ PROCESSOR AND MEMORY TECHNOLOGY 3.1 RSFQ Processors 43 3.1.1 RSFQ Processors – Status 43 3.1.2 RSFQ Processors – Readiness for Major Investment 47 3.1.3 RSFQ Processors – Roadmap 49 3.1.4 RSFQ Processors – Investment Required 50 3.1.5 RSFQ Processors – Issues and Concerns 51 3.1.6 RSFQ Processors – Projected Future Capability 52 3.2 Memory 52 3.2.1 Memory – Hybrid Josephson-CMOS RAM 54 3.2.2 Memory – Single-Flux Quantum Memory 56 3.2.3 Memory – MRAM 59 3.2.4 Memory – Summation 66 3.3 CAD Tools and Design Methodologies 67 3.4 Summary 72
Page 1 and 2: SUPERCONDUCTING TECHNOLOGY ASSESSME
Page 3: Summary of Findings The STA conclud
Page 7 and 8: CHAPTER 06: SYSTEM INTEGRATION 6.1
Page 9 and 10: INDEX OF FIGURES CHAPTER 01: INTROD
Page 11 and 12: APPENDIX G: ISSUES AFFECTING RSFQ C
Page 13 and 14: CONTENTS OF CD EXECUTIVE SUMMARY CH
Page 15 and 16: LIMITATIONS OF CURRENT TECHNOLOGY C
Page 17 and 18: State of the Industry Today, expert
Page 19 and 20: 01 This document presents the resul
Page 21 and 22: 1.2 LIMITATIONS OF CONVENTIONAL TEC
Page 23 and 24: 1.3.2 RSFQ ATTRIBUTES Important att
Page 25 and 26: The end point of this roadmap defin
Page 27 and 28: CRYOGENIC ENVIRONMENT High-speed ne
Page 29 and 30: ■ ■ Chalmers University in Swed
Page 31 and 32: Random Access Memory Options Random
Page 33 and 34: Compact Package Feasible Thousands
Page 35 and 36: The major issue to be addressed wil
Page 37 and 38: 02 No radical execution paradigm sh
Page 39 and 40: The key challenges at the processor
Page 41 and 42: 2.2 MICROPROCESSORS - CURRENT STATU
Page 43 and 44: 2.2.3 CORE1 BIT-SERIAL MICROPROCESS
Page 45 and 46: Potential Problems The initial vers
Page 47 and 48: The microarchitecture of supercondu
Page 49 and 50: 2.5 MICROPROCESSORS - CONCLUSIONS A
Page 51: 2.7 MICROPROCESSORS - FUNDING In th
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SUPERCONDUCTIVE RSFQ PROCESSOR AND
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3.1 RSFQ PROCESSORS The panel devel
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TABLE 3.1-1. PUBLISHED SUPERCONDUCT
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S G G Chip-side microstrip S Carrie
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3.1.3 RSFQ PROCESSORS - ROADMAP The
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3.1.5 RSFQ PROCESSORS - ISSUES AND
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Since these memory concepts are so
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Simulations show that the input int
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SFQ RAM Status The results of five
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Investment for SFQ Memory The inves
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4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
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The roadmap identifies early analyt
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MRAM Major Issues and Concerns Mate
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3.3 CAD TOOLS AND DESIGN METHODOLOG
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Issues and Concerns Present simulat
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Investment The investment estimated
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04 By 2010 production capability fo
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Table 4-1 summarizes the roadmap fo
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4.1 SCE IC CHIP MANUFACTURING - SCO
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Significant activity in the area of
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4.3 SCE CHIP FABRICATION FOR HEC -
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The superconductive IC chip fabrica
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Table 4-6 shows how gate speed depe
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Parameter spreads in superconductiv
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TABLE 4-9. SCALING REQUIREMENTS FOR
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ELEMENT 2006 2007 2008 2009 2010 Pi
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A potential savings of ~40% in the
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05 Packaging and chip-to-chip inter
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TABLE 5-1. I/O TECHNOLOGIES FOR PET
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For further discussions of the opti
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5.1.3 OPTICAL INTERCONNECT TECHNOLO
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In this case, an optical receiver w
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Examples of what has been achieved
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5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
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Figure 5-4. Superconducting 16x16 c
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06 The design of secondary packagin
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For this study, the readiness of th
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6.1.3 MULTI-CHIP MODULES AND BOARDS
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TABLE 6-2. MCM FABRICATION TOOLS AN
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6.2.3. 3-D PACKAGING - ISSUES AND C
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Several companies have demonstrated
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In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ ■ ■ ■ Construct a detaile
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Appendix B
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GOVERNMENT George Cotter Director f
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Appendix C
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TERMS/DEFINITIONS IHEC LLNL JJ JPL
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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120 0.10 100 Write I (mA) 0.08 0.06
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Appendix I
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Table 1 Representative Nb and NbN-B
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ground plane may be located either
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Table 5 Reactive Ion Etch Parameter
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Table 6 Junction Array Summary of T
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shorts in the first wiring layer we
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B. Yield Yield measurements are an
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RSFQ logic will eventually find wid
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Intermediate Temperature stage Disp
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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