Superconducting Technology Assessment - nitrd

CHAPTER 02: ARCHITECTURAL CONSIDERATIONS
FOR SUPERCONDUCTOR RSFQ MICROPROCESSORS
2.1 Superconductor Microprocessors–Opportunities, Challenges, and Projections 25
2.2 Microprocessors – Current Status of RSFQ Microprocessor Design 28
2.2.1 SPELL Processors for the HTMT Petaflops System (1997-1999) 28
2.2.2 20-GHz, 8-bit FLUX-1 Microprocessor (2000-2002) 29
2.2.3 CORE1 Bit-serial Microprocessor Prototypes (2002-2005) 30
2.2.4 Proposal for an RSFQ Petaflops Computer in Japan (est. 2005-2015) 30
2.3 Microprocessors – Readiness 32
2.4 Microprocessors – Issues and Concerns 33
2.4.1 Clocking for 50 GHz RSFQ Processors 33
2.4.2 Long Processing Pipelines 33
2.4.3 On-chip Interconnect, Chip Area Reachable in a Single Cycle, and Register File Structures 33
2.4.4 Memory Hierarchy for Superconductor Processors and Systems 34
2.4.5 Memory Latency Tolerant Architectures 35
2.5 Microprocessors – Conclusions and Goals 36
2.6 Microprocessors – Roadmap and Milestones 37
2.7 Microprocessors – Funding 38
CHAPTER 03: SUPERCONDUCTIVE RSFQ PROCESSOR
AND MEMORY TECHNOLOGY
3.1 RSFQ Processors 43
3.1.1 RSFQ Processors – Status 43
3.1.2 RSFQ Processors – Readiness for Major Investment 47
3.1.3 RSFQ Processors – Roadmap 49
3.1.4 RSFQ Processors – Investment Required 50
3.1.5 RSFQ Processors – Issues and Concerns 51
3.1.6 RSFQ Processors – Projected Future Capability 52
3.2 Memory 52
3.2.1 Memory – Hybrid Josephson-CMOS RAM 54
3.2.2 Memory – Single-Flux Quantum Memory 56
3.2.3 Memory – MRAM 59
3.2.4 Memory – Summation 66
3.3 CAD Tools and Design Methodologies 67
3.4 Summary 72