Presentation Materials Including Discussion Notes - UCSD VLSI ...

Presentation Materials Including Discussion Notes - UCSD VLSI ...

EDA Roadmap Workshop

DAC, July 27, 2009

J. Antonio Carballo, IBM Andrew B. Kahng, UCSD

DAC Conference


First forum for discussion around EDA roadmapping issues

Including leaders from semicon companies, consortia, and academia


• Commence a dialog between teams roadmapping design technology

– Bring together a view towards a more explicit future interlock

• Analyze the need and state of the EDA sector's roadmapping efforts

– A concrete, actionable plan process, owners, schedule


DAC Conference

Agenda (I)

• 9:15am - 10:00am Plenary

– The ITRS Semiconductor Industry Roadmap --- Alan K. Allan (Intel)

• 10:00am - noon Session I: EDA Roadmaps and Perspectives

– The CATRENE (Europe) EDA Roadmap --- W. Rosenstiel (U. Tubingen)

– The STRJ/WG1 (Japan) EDA Roadmap --- (TBD)

– The ITRS Design / System Drivers Roadmap – Carballo/Kahng (ITRS)

– Synopsys Roadmap Perspective --- A. Domic (Synopsys)

– Cadence Roadmap Perspective --- D. Noice (Cadence)

– Mentor Roadmap Perspective --- R. Hum (Mentor)

– Design Technology Coalition Perspective --- J. Darringer (IBM) (tentative)

– SI2 Perspective --- S. Dasgupta (SI2)

– Mini-Panel Discussion: "Can We Roadmap EDA? For whom? Listening?


DAC Conference

Agenda (II)

• Noon - 1:30pm: Creating the Right EDA Industry Roadmap

– How does the EDA roadmap and process need to change ?

– Open discussion, everybody welcome

– Target outcome: Concrete, actionable ways to change

– Driving questions

1.Can there be an agreed “Roadmap for the EDA Industry” from now on?

2.What constituencies “own” / run this roadmap?

3.What process will ensure continuous / frequent interlock?

4.Can we commit to a yearly report? Who owns this report?

• How the roadmap is being used, and by whom

• Feedback for improving the next year's version


DAC Conference


• Synopsys

– Antun: Let’s not lose sight of the fact that EDA’s major success has been

the cell-based methodology → We

– 3-5 year technology roadmap; 1-3 year product roadmap (sufficient!)

– Internal / external; industry landscape; technical challenges

– {tech roadmap, business factors} ↔ {product, investment/partner,..} → { }

– Information sources → {EDA vendor roadmaps, EDA stds}

– Depends on roadmaps for electronics, semiconductor mfg, IC design

(from customers)

• Cadence

– Computing platform

– Multicore

– Core EDA Algorithms

– How might an EDA roadmap help? Computing platform. New levels of

abstraction, methodology/languages for large system verification and

implementation [driven by adv users]. How to model new physical issues

[driven by adv fabs]. Usefully direct academic research? (multi-CPU

scalable algs; compact models for new physical effects; abstraction

models that can be validated; algorithms that cross domains)


DAC Conference


• Content: What should the roadmap look like?

– Numbers (+ agreement + process for reaching agreement …)

– Timelines: When does a design technology “exist” or “go into

production”? e.g., “taped out for volume production” (Design does not

have well-defined criteria like those for other technologies.)

– Precompetitive vs. competitive; strategic vs. commodity

– Horizon (4-year EU; 3- to 5-year EDA companies) vs. ITRS 15-year scale

– EDA industry roadmap should be shorter (compact)

– (SD, Si2) Acknowledge actual life cycle of DT: EDA tools are often

commoditizations of what is developed internally


DAC Conference


• Must bring in economic value of the roadmap (CFC, Qualcomm)

– Who benefits? Who are stakeholders?

– To get commitment, must engineer and demonstrate economic value of


– Transform roadmap into requirements + certification (at end-user level)

• 3 rd -party certification == w.r.t. flow (cf. methodology roadmap) and

w.r.t. ROI

• Can speed adoption of new tools

• Comment: EDA software licenses prohibit ‘benchmarking’ (!)

– Historically, because ‘benchmarks’ yield different results, can be


– OTOH, benchmarks can be used differently on internal basis

– Two roadmaps: design methodology and design technology (tools)


DAC Conference


• Process: Engaging contributors

– Don’t scare away potential contributors

– Solution space: asynchronous, not F2F, colocated with other meeting

• Try phone conferences, for example

– “Feedback” by itself would be a good start!

– Open is good, but need ‘formalization’

– Agreements

• Will develop a yearly ‘reality check’ to be presented at DAC

– Shorter horizon, fewer pages than ITRS

– Owner: JAC/ABK

• As a group, we will meet F2F at DAC; via other media more frequently

• EDA companies and customers will give timely feedback (to be kept

anonymous as appropriate) to ‘survey’, ‘sanity check’ and ‘terminology’

questions from JAC/ABK


DAC Conference


• Standards

– Often comes from donations from IDMs or EDA companies

– People want to work on this when there is urgency (cf. low-power)

– This is related to commoditization 1-3 year horizon makes sense

– Cannot be too far ahead of ‘heartbeat’

– Comment (JAD): This is how we are today; maybe we should get out in

front of this (e.g., 3D)


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