Curriculum Vitae - UCSD VLSI CAD Laboratory - UC San Diego

vlsicad.ucsd.edu

Curriculum Vitae - UCSD VLSI CAD Laboratory - UC San Diego

Curriculum Vitae

Andrew B. Kahng

University of California, San Diego Phone: +1-858-822-4884

Depts. of CSE and ECE, Mailcode #0404

abk@ucsd.edu

La Jolla, CA 92093-0404

http://vlsicad.ucsd.edu/~abk/

Personal

b. October 3, 1963 San Diego, CA; United States Citizen

Education

Ph.D. in Computer Science, 1989, University of California at San Diego

M.S. in Computer Science, 1986, University of California at San Diego

A.B. in Applied Mathematics / Physics, 1984, Harvard College, Cambridge, MA

Professional Experience

Founder and CTO, Blaze DFM, Inc., Sunnyvale, CA (10/04 – 9/06)

o Consultant, Office of the Chief Technologist (9/06 – 10/07)

Professor, Departments of Computer Science and Engineering, and Electrical and Computer

Engineering, UC San Diego (1/01 – present)

o Executive Committee, ECE Department (7/10 – 6/11)

o Graduate Committee Chair, CSE Department (7/08 – 6/09)

o Associate Chair, CSE Department (7/03 – 10/04)

Professor, Department of Computer Science, UCLA (7/98 – 12/00)

o Vice-Chair (Graduate Studies) (7/98 – 12/00)

Visiting Scientist, Cadence Design Systems, Inc., San Jose (10/95 – 4/97)

Associate Professor, Department of Computer Science, UCLA (7/94 – 6/98)

Assistant Professor, Department of Computer Science, UCLA (7/89 – 6/94)

Graduate Fellow and Research Assistant, CSE Dept., UCSD (9/85 – 6/89)

o Research: Combinatorial optimization and graph algorithms, VLSI CAD, mathematical

programming, massive parallelism

UCSD Summer Session Faculty, CSE160AB “Foundations of Computer Science” (1986)

Research Engineer, VLSI CAD Analysis and Design Group, Burroughs Corporation, San Diego,

CA. Device physics, VLSI design automation. (6/83 – 6/86)

Selected Honors

Fellow, ACM (2012)

Endowed Chair in High-Performance Computing, UC San Diego, 2012 –

Richard Newton Industrial Impact Award (MARCO Gigascale Systems Research Center), 2011

Fellow, IEEE (2010)

First Place Award, Placement Contest (ACM International Symposium on Physical Design

2005)


6 Best Paper Awards (ACM/IEEE Design Automation Conference 1994, IEEE International

Symposium on Quality in Electronic Design 2001, Joint ACM/IEEE Asia South-Pacific Design

Automation Conference and VLSI Design Conference 2002, IEEE International Conference on

Computer Design 2005, SPIE BACUS Symposium 2005, IEEE International Symposium on

Quality in Electronic Design 2007)

14 Best Paper Nominations (ACM/IEEE Design Automation Conference 1992, 1994, 2012;

European Design Automation Conference 1992, 1994; IEEE Asia-South Pacific Design

Automation Conference 1999, 1999, 2002; International Symposium on Quality in Electronic

Design 2001, 2007; SPIE BACUS Symposium 2005; IEEE International Conference on

Computer Design 2005, IEEE International Conference on Computer-Aided Design 2005, 2008).

National Science Foundation Young Investigator Award, 1992

National Science Foundation Research Initiation Award, 1991

Distinguished Paper Award (IEEE International Conference on CAD 1990)

Powell Foundation Graduate Fellow

All-Star Team Member, College Bowl National Finals

Harvard College National Scholar

High school valedictorian; National Merit Scholar

San Diego Symphony Orchestra Young People's Concert: Piano Soloist

U.S.A. International Mathematics Olympiad Training Session (Annapolis, MD)

Selected Professional Activities

University

UCSD Academic Senate Committee on Research (2008-2009)

UC (system-wide) Senate Committee on Information Technology and Telecommunications

Policy (2003-2004; Vice-Chair 2004-2005; Chair 2005-2006)

UC (system-wide) Information Technology Leadership Council (2005-2006)

UC Senate Library Committee (ex-officio) (2005-2006)

UC Office of the President Task Force on Information Security (2006)

UCSD Academic Senate Committee on Academic Information Technology (2001-2002; Chair in

2002-2003)

Editorships

Regular column, “The Road Ahead”, IEEE Design and Test magazine (2002-present)

Research Highlights editorial board member for VLSI CAD area, Communications of the ACM

(2008-present)

Associate Editor, IEEE Trans. on VLSI Systems (2003-2004)

Board of Editors, J. Graph Algorithms and Applications

Board of Editors, Intl. J. of High Speed Electronics and Systems

Associate Editor, IEEE Trans. on Circuits and Systems I

Guest Co-Editor, Special Issue on Physical Design, IEEE Trans. on CAD (April 1998), Special

Issue on Interconnect Prediction, IEEE Trans .on VLSI Systems (June 2000), Special Issue on

Roadmaps for Design and Test, IEEE Design and Test (November-December 2001), Special

Issue on RTL-to-GDSII, IEEE Design and Test (January-February 2004), Special Issue on “Big

Chips”, IEEE Micro (July-August 2011).

Area Advisor for Digital Electronics, VLSI and Hardware Description Languages,

Comprehensive Dictionary of Electrical Engineering, P. Laplante, ed., CRC Press 1998


Service / Leadership

ACM/IEEE/EDAC Design Automation Conference: Technical Program Co-Chair 2004-2005,

New Initiatives Chair 2006, Panels Chair 2007, Vice Chair 2008, General Chair 2009, Past Chair

2010. Also: Technical Program Committee (and Session Organizer) 1995-2001; Panels

Committee 1998-2003, 2011-2012

International Technology Roadmap for Semiconductors: Chair of U.S. Design TWG and Design

International TWG, 2001 ITRS renewal, 2002 update, and 2003 renewal; Co-chair of U.S. and

International working groups, 2004-present

MARCO Gigascale Systems Research Center: Theme/thrust leader (Circuit Fabrics; Calibrating

Achievable Design; System-Level Living Roadmap), 1998-2006; executive committee member,

1998-present

P. O. Pistilli Undergraduate Scholarship for Advancement in Computer Science and Electrical

Engineering (for underrepresented groups (women, African-American, Hispanic, Native

American, disabled) in EE, CE and CS fields): committee member 2010; director 2011-present

ACM/IEEE International Symposium on Physical Design: Founder and General Chair, 1997;


steering committee 2000-2002

ACM International Workshop on System-Level Interconnect Prediction: Co-Founder and Co-

General Chair, 1999 (co-Program Chair, 2000; special sessions chair, 2001; organizing committee

2002-present)

IEEE DFM&Y Workshop: Co-Founder and Program Chair, 2006 (organizing committee 2007-

present)

IEEE DATC Electronic Design Processes Workshop: Program Chair, 2001; General Chair, 2002

IEEE Computer Society Fellow Evaluation Committee, 2010 and 2011

National Technology Roadmap for Semiconductors: Member, Design and Test Technical

Working Group (with responsibility for Physical Design), 1997; also 1998 and 1999

(International Technology Roadmap for Semiconductors) renewals

International Symposium on Quality Electronic Design (ISQED): General Chair, 2006

IEEE Intl. Conf. on Computer-Aided Design: Technical Program Committee, Session Chair and

Co-Chair, 1993-1995, 1998, 2000-2001 (subcommittee chair in 2001)

ACM/SIGDA Physical Design Workshop: Technical Program Committee and Session Chair,

1993; Technical Program Committee Chair, 1996

INFORMS Annual Meeting: Invited Session Organizer and Chair, 1997

Asia-Pacific Conference on Circuits and Systems:T echnical Program Committee, 1996

IEEE International Symposium on Circuits and Systems: Associate Chair, VLSI Track; Panelist,

CAD Track; Session Organizer/Chair (Meta-heuristics in VLSI Layout), 1996

3rd Canadian Workshop on Field-Programmable Devices: Technical Committee, 1996

European Design Automation Conference: Technical Committee, 1994

National Defense Science and Engineering Graduate Fellowship Program: Computer Science

Fellowship Panel (one of five members), 1993

Expert Panel on Electromagnetic Detection (organized by U.S. Army Research Office), Research

Triangle Park, NC, June 23-26, 1992.

IEEE ASIC Conference: Technical Program Committee, 1991-1993 (session chair/co-chair in

1991; subcommittee chair in 1992-1993)

Reviewer for NSF, UC MICRO, ARO, numerous other journals/conferences/symposia

Ph.D. Advising (23 Ph.D. graduates, listed in chronological order of graduation)

Gabriel Robins (IBM Fellowship, ACM Outstanding Dissertation Award Nominee, NSF Young

Investigator Award, Packard Fellowship, Munster Chair, now Professor at Univ. of Virginia)

Lars Hagen (IBM Fellowship, now at Cadence Design Systems, Inc.)


Kenneth D. Boese (GTE Fellowship, MICRO Fellowship, UCLA Dissertation Year Fellowship,

ACM Outstanding Dissertation Award Nominee, now at Cadence Design Systems, Inc.)

Charles J. Alpert (DAC Scholarship, UCLA Dissertation Year Fellowship, ACM Outstanding

Dissertation Award Nominee, now at IBM Austin Research Laboratory)

Sudhakar Muddu (founder Sanera (acquired by McData), founding team Rio Design

Automation (acquired by Magma Design Automation), founder Kazeon (acquired by EMC),

currently retired from EMC)

Chung-Wen Albert Tsao (DAC Scholarship, now at Cadence Design Systems, Inc.)

Dennis Jen-Hsin Huang (now at Cadence Design Systems, Inc.)

Kei Masuko

Igor L. Markov (now Associate Professor at Univ. of Michigan EECS Dept.)

Bao Liu (now Assistant Professor at Univ. of Texas at San Antonio)

Yu Chen (now at Cadence Design Systems, Inc.)

Stefanus Mantik (now at Cadence Design Systems, Inc.)

Xu Xu (now at Synopsys, Inc.)

Sherief Reda (now Assistant Professor at Brown University)

Qinke Wang (now at Synopsys, Inc.)

Puneet Gupta (EDAA Outstanding Dissertation Award, now Assistant Professor at UCLA EE

Department)

Chul-Hong Park (now at Samsung Electronics Corp.)

Puneet Sharma (now at Freescale, Inc.)

Rasit Topaloglu (now at IBM Microelectronics)

Swamy Muddu (now at GLOBALFOUNDRIES, Inc.)

Kambiz Samadi (now at Qualcomm CDMA Technologies, Inc.)

Kwangok Jeong (EDAA Outstanding Dissertation Award, now at Samsung Electronics Corp.)

Seokhyeong Kang (now at Qualcomm CDMA Technologies, Inc.)

Issued U.S. Patents

1. A. B. Kahng and S. Muddu, “Diffusion-Based Method and Apparatus for Determining Circuit

Interconnect Voltage Response”, U. S. Patent No. 6,047,117, April 4, 2000.

2. C. Albrecht, A. B. Kahng, I. I. Mandoiu and A. Z. Zelikovsky, “Floorplan Evaluation, Global

Routing, and Buffer Insertion for Integrated Circuits”, U. S. Patent No. 7,062,743, June 13, 2006.

3. A. B. Kahng, P. Gupta, D. Sylvester and J. Yang, “Method for Correcting a Mask Design Layout”,

U. S. Patent No. 7,149,999, December 12, 2006.

4. P. Gupta and A. B. Kahng, “Gate-Length Biasing for Digital Circuit Optimization”, U. S. Patent

No. 7,441,221, October 21, 2008.

5. A. B. Kahng, P. Gupta, D. Sylvester and J. Yang, “Method for Correcting a Mask Design Layout”,

U. S. Patent No. 7,614,032, November 3, 2009.

6. P. Gupta and A. B. Kahng, “System and Method for Varying the Starting Conditions for a

Resolution Enhancement Program to Improve the Probability That Design Goals Will Be Met”, U.

S. Patent No. 7,627,849, December 1, 2009.

7. P. Gupta, A. B. Kahng and C.-H. Park, “Method and System for Placing Layout Objects in a

Standard-Cell Layout”, U. S. Patent No. 7.640,522, December 29, 2009.

8. O. S. Nakagawa, A. B. Kahng and P. Wong, “Layout Description Having Enhanced Fill

Annotation”, U. S. Patent No. 7,676,772, March 9, 2010.

9. P. Gupta, A. Kahng and S. Shah, “Method and System for Integrated Circuit Optimization by

Using an Optimized Standard-Cell Library”, U. S. Patent No. 7,716,612, May 11, 2010.


10. P. Gupta, A. B. Kahng and D. Reed, “Method and System for Reshaping a Transistor Gate in an

Integrated Circuit to Achieve a Target Objective”, U. S. Patent No. 7,730,432, June 1, 2010.

11. P. Gupta and A. B. Kahng, “Method and System for Finding an Equivalent Circuit Representation

for One or More Elements in an Integrated Circuit”, U. S. Patent No. 7,743,349, June 22, 2010.

12. O. S. Nakagawa, A. B. Kahng, P. Wong and P. Gupta, “Arrangement of Fill Unit Elements in an

Integrated Circuit Interconnect Layer”, U. S. Patent No. 7,745,239, June 29, 2010.

13. P. Gupta and A. B. Kahng, “Method and System for Topography-Aware Reticle Enhancement”,

U. S. Patent No. 7,814,456, October 12, 2010.

14. C. W. Moon, P. Gupta, P. J. Donehue and A. B. Kahng, “Method of Designing a Digital Circuit

by Correlating Different Static Timing Analyzers”, U. S. Patent No. 7,823,098, October 26, 2010.

15. A. B. Kahng, P. Gupta and S. Shah, “System and Method for Performing Transistor-Level Static

Performance Analysis Using Cell-Level Static Analysis Tools”, U. S. Patent No. 7,865,856,

January 4, 2011.

16. A. B. Kahng and C.-H. Park, “Method, Apparatus and System for Designing an Integrated Circuit

Including Generating At Least One Auxiliary Pattern for Cell-Based Optical Proximity

Correction”, U. S. Patent No. 7,873,929, January 18, 2011.

17. A. B. Kahng, C.-H. Park and X. Xu, “Method and Apparatus for Detecting Lithographic Hotspots

in a Circuit Layout”, U. S. Patent No. 7,945,870, May 17, 2011.

18. P. Gupta, A. B. Kahng, P. Sharma and S. Muddu, “Method and System for Wafer Topography-

Aware Integrated Circuit Design Analysis and Optimization”, U. S. Patent No. 8,024,675,

September 20, 2011.

19. J. Cox, A. B. Kahng and P. Sharma, “Internet Telephony Through Hosts”, U. S. Patent No.

8,073,977, December 6, 2011.

20. A. B. Kahng, P. Gupta, D. Sylvester and J. Yang, “Tool for Modifying Mask Design Layout”, U.

S. Patent No. 8,103,981, January 24, 2012.

21. P. Gupta and A. B. Kahng, “Gate-Length Biasing for Digital Circuit Optimization”, U.S. Patent

No. 8,127,266, February 28, 2012.

22. P. Gupta and A. B. Kahng, “Methods for Gate-Length Biasing Using Annotation Data”, U.S.

Patent No. 8,185,865, May 22, 2012.

23. A. B. Kahng and H. Yao, “Layout Decomposition for Double Patterning Lithography”, U.S.

Patent No. 8,402,396, March 19, 2013.

24. P. Gupta and A. B. Kahng, “Standard Cells Having Transistors Annotated for Gate-Length

Biasing”, U.S. Patent No. 8,490,043, July 16, 2013.

Books and Book Chapters

1. A. B. Kahng, “Space-Filling Curve Techniques for VLSI CAD/CAM”, in Advanced Research in

VLSI, C. Seitz, ed. (papers from the Decennial Caltech Conf. on Advanced Research in VLSI),

MIT Press, March 1989, pp. 261-277.

2. (BOOK) A. B. Kahng and G. Robins, On Optimal Interconnections for VLSI, Kluwer Academic

Publishers, 1994.

3. C. Bandela, Y. Chen, A.B. Kahng, I.I. Mandoiu, and A.Z. Zelikovsky, “Multiple-Object XOR

Auctions With Buyer Preferences and Seller Priorities”, in Competitive Bidding and Auctions,

K.K. Lai and S. Wang (eds.), Kluwer Academic Publishers.

4. A. B. Kahng and S. Reda, “Digital Layout – Placement”, The CRC Handbook of EDA for IC

Design, CRC Press, 2005, G. Martin and L. Lavagno (eds.), Vol. 2, pp. 5-1 - 5-23.

5. A. B. Kahng and K. Samadi, “CMP Fill”, The Handbook of Algorithms for VLSI Physical Design,

C. J. Alpert, D. P. Mehta and S. S. Sapatnekar (eds.), CRC Press, 2008.

6. A. B. Kahng, I. I. Mandoiu, and A. Z. Zelikovsky, “Practical Approximations of Steiner Trees in

Uniform Orientation Metrics”, Handbook of Approximation Algorithms and Metaheuristics, T. E.

Gonzalez (ed.), Chapman & Hall / CRC Press, 2007, pp. 43-1 - 43-13.


7. C. Albrecht, A. B. Kahng, I. I. Mandoiu and A. Z. Zelikovsky, “Multicommodity Flow

Algorithms for Buffered Global Routing”, Handbook of Approximation Algorithms and

Metaheuristics, T. E. Gonzalez (ed.), Chapman & Hall / CRC Press, 2007, pp. 80-1 - 80-18.

8. A. B. Kahng, I. I. Mandoiu, S. Reda, X. Xu, and A. Z. Zelikovsky, “Computer-Aided

Optimization of DNA Array Design and Manufacturing,” Design Automation Methods and Tools

for Microfluidics-Based Biochips, K. Chakrabarty and J. Zeng (eds.), Springer Verlag, 2006, pp.

235-269.

9. A. B. Kahng, S. Reda and Q. Wang, “APlace: A High Quality, Large-Scale Analytical Placer,”

Modern Circuit Placement: Best Practices and Results, J. Cong and G.-J. Nam (eds.), Springer,

2007, pp. 163 – 187.

10. (BOOK) B. P. Wong, A. Mittal, G. W. Starr, F. Zach, V. Moroz and A. Kahng, Nano-CMOS

Design for Manufacturability, Wiley-Interscience, 2008.

11. (BOOK) A. B. Kahng, J. Lienig, I. L. Markov and J. Hu, VLSI Physical Design: From Graph

Partitioning to Timing Closure, Springer, 2010.

Journal Papers

1. T. C. Hu and A. B. Kahng, “All Trees Are Graceful (but some are more graceful than others)”,

Applied Geometry and Discrete Mathematics 4 (1991), pp. 355-358.

2. A. B. Kahng and G. Robins, “Optimal Algorithms for Extracting Spatial Regularity in Images”,

Pattern Recognition Letters 12 (1991), pp. 757-764.

3. J. Cong, A. B. Kahng, G. Robins, M. Sarrafzadeh and C. K. Wong, “Provably Good

Performance-Driven Global Routing”, IEEE Transactions on Computer-Aided Design 11(6), June

1992, pp. 739-752.

4. A. B. Kahng and G. Robins, “A New Class of Iterative Steiner Tree Heuristics with Good

Performance”, IEEE Transactions on Computer-Aided Design 11(7), July 1992, pp. 893-902.

5. L. Hagen and A. B. Kahng, “New Spectral Methods for Ratio Cut Partitioning and Clustering”,

IEEE Transactions on Computer-Aided Design 11(9), September 1992, pp. 1074-1085.

6. K. C. Chen, J. Cong, Y. Ding, A. B. Kahng and P. Trajmar, “DAG-MAP: Graph Based FPGA

Technology Mapping For Delay Optimization”, IEEE Design and Test, September 1992, pp. 7-

20.

7. T. C. Hu, A. B. Kahng and G. Robins, “Solution of the Discrete Plateau Problem”, Proc. National

Academy of Sciences 89(10), October 1992, pp. 9235-9236.

8. T. H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese and A. B. Kahng, “Zero Skew Clock Routing With

Minimum Wirelength”, IEEE Trans. on Circuits and Systems 39(11), November 1992, pp. 799-

814.

9. A. B. Kahng and G. Robins, “On Performance Bounds for a Class of Rectilinear Steiner Tree

Heuristics in Arbitrary Dimension”, IEEE Transactions on Computer-Aided Design 11(11),

November 1992, pp. 1462-1465.

10. J. Cong, A. B. Kahng and G. Robins, “Matching-Based Methods for High-Performance Clock

Routing”, IEEE Transactions on Computer-Aided Design 12(8), August 1993, pp. 1157-1169.

11. T. C. Hu, A. B. Kahng and G. Robins, “Optimal Robust Path Planning in General Environments”

IEEE Trans. on Robotics and Automation 9(6), December 1993, pp. 775-784.

12. L. Hagen, A. B. Kahng, F. Kurdahi and C. Ramachandran, “On the Intrinsic Rent Parameter and

New Spectra-Based Methods for Wireability Estimation”, IEEE Transactions on Computer-Aided

Design 13(1), January 1994, pp. 27-37.

13. K. D. Boese and A. B. Kahng, “Best-So-Far vs. Where-You-Are: Implications for Optimal Finite-

Time Annealing”, Systems and Control Letters 22, January 1994, pp. 71-78.

14. C. J. Alpert, J. Cong, A. B. Kahng, G. Robins and M. Sarrafzadeh, “On the Minimum Density

Interconnection Tree Problem”, VLSI Design 2(2) (1994), pp. 157-169.


15. K. D. Boese, A. B. Kahng and S. Muddu, “New Adaptive Multistart Techniques for

Combinatorial Global Optimizations”, Operations Research Letters 16(2) (1994), pp. 101-113.

16. T. C. Hu, A. B. Kahng and C. W. Tsao, “Old Bachelor Acceptance: A New Class of Non-

Monotone Threshold Accepting Methods” ORSA J. on Computing 7(4) (1995), pp. 417-425.

17. K. D. Boese, A. B. Kahng, B. McCoy and G. Robins, “Near-Optimal Critical Sink Routing Tree

Constructions”, IEEE Transactions on Computer-Aided Design 14(12) (1995), pp. 1417-1436.

(Nominated for Transactions Best Paper Award )

18. C. J. Alpert, T. C. Hu, J. H. Huang, A. B. Kahng and D. Karger, “Prim-Dijkstra Tradeoffs for

Improved Performance-Driven Global Routing”, IEEE Transactions on Computer-Aided Design

14(7) (1995), pp. 890-896.

19. C. J. Alpert and A. B. Kahng, “Recent Directions in Netlist Partitioning: A Survey”, Integration:

The VLSI Journal 19 (1995), pp. 1-81.

20. C. J. Alpert and A. B. Kahng, “Multi-Way Partitioning Via Geometric Embeddings, Orderings,

and Dynamic Programming”, IEEE Transactions on Computer-Aided Design 14(11) (1995), pp.

1342-1358.

21. A. B. Kahng, G. Robins and E. A. Walkup, “Optimal Algorithms for Substrate Testing in Multi-

Chip Modules”, Intl. J. on High-Speed Electronics and Systems 6(4) (1995), pp. 595-612.

22. A. B. Kahng and C. W. Tsao, “Planar-DME: A Single-Layer Zero-Skew Clock Tree Router”,

IEEE Transactions on Computer-Aided Design 15(1) (1996), pp. 8-19.

23. C. J. Alpert and A. B. Kahng, “A General Framework for Vertex Orderings, With Applications to

Circuit Clustering”, IEEE Trans. on VLSI Systems 4(2) (1996), pp. 240-246.

24. C. J. Alpert and A. B. Kahng, “Splitting an Ordering into a Partition to Minimize Diameter,” J.

Classification 14 (1997), pp. 51-74.

25. L. Hagen, J. H. Huang and A. B. Kahng, “On Implementation Choices for Iterative Improvement

Partitioning Algorithms”, IEEE Transactions on Computer-Aided Design 16(10) (1997), pp.

1199-1205.

26. Y. Cao, A. S. Fukunaga and A. B. Kahng, “Cooperative Mobile Robotics: Antecedents and

Directions”, Autonomous Robots 4(1) (1997), pp. 7-27.

27. A. B. Kahng and S. Muddu, “Analysis of RC Interconnections Under Ramp Input”, ACM Trans.

on Design Automation of Electronic Systems 2(2), April 1997, pp 168-192.

28. A. B. Kahng and C.-W. A. Tsao, “Practical Bounded-Skew Clock Routing”, J. VLSI Signal

Processing 16 (1997), pp. 199-215.

29. I. Hong, A. B. Kahng and B. R. Moon, “Improved Large-Step Markov Chain Variants for the

Symmetric TSP”, J. Heuristics 3(1) 1997, pp. 63-81.

30. L. Hagen and A. B. Kahng, “Combining Problem Reduction and Adaptive Multi-Start: A New

Technique for Superior Iterative Partitioning”, IEEE Transactions on Computer-Aided Design

16(7) (1997), pp. 709-717.

31. A. B. Kahng and S. Muddu, “An Analytical Delay Model for RLC Interconnects”, IEEE

Transactions on Computer-Aided Design 16(12) (1997), pp. 1507-1514.

32. J. Cong, A. B. Kahng, C. K. Koh and C.-W. A. Tsao, “Bounded-Skew Clock and Steiner

Routing”, ACM Trans. on Design Automation of Electronic Systems 3(3) (1998), pp. 341-388.

33. A. B. Kahng, G. Robins and E. A. Walkup, “How to Test a Tree”, Networks 32 (1998), pp. 189-

197.

34. C. J. Alpert, J. H. Huang and A. B. Kahng, “Multilevel Circuit Partitioning”, IEEE Transactions

on Computer-Aided Design 17(8) (1998), pp. 655-667.

35. J. Cong, A. B. Kahng and K. S. Leung, “Efficient Algorithms for the Shortest-Path Steiner

Arborescence Problem With Applications to VLSI Physical Design”, IEEE Transactions on

Computer-Aided Design 17(1) (1998), pp. 24-39.

36. C. J. Alpert, T. Chan, A. B. Kahng, I. Markov, P. Mulet, “Faster Minimization of Linear

Wirelength for Global Placement”, IEEE Transactions on Computer-Aided Design 17(1) (1998),

pp. 3-13.


37. C. J. Alpert, A. B. Kahng and D. S. Yao, “Spectral Partitioning With Multiple Eigenvectors”,

Discrete Applied Mathematics 90 (1999), pp. 3-26. Selected for inclusion in special volume,

Discrete Applied Mathematics, Editors' Choice, Edition 1999.

38. A. B. Kahng, S. Muddu and E. Sarto, “Tuning Strategies for Global Interconnects in High-

Performance Deep-Submicron ICs”, VLSI Design 10(1) (1999), pp. 21-34.

39. C. J. Alpert, A. E. Caldwell, T. F. Chan, D. J.-H. Huang, A. B. Kahng, I. L. Markov and M. S.

Moroz, “Analytic Engines Are Unnecessary in Top-Down Partitioning-Based Placement”, VLSI

Design 10(1) (1999), pp. 99-116.

40. A. B. Kahng, G. Robins, A. Singh and A. Zelikovsky, “Filling Algorithms and Analyses for

Layout Density Control”, IEEE Transactions on Computer-Aided Design 18(4) (1999), pp. 445-

462.

41. A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov and A. Zelikovsky, “On Wirelength

Estimations for Row-Based Placement”, IEEE Transactions on Computer-Aided Design 18(9),

(1999), pp. 1265-1278.

42. P. Berman, A. B. Kahng, D. Vidhani, H. Wang and A. Zelikovsky, “Optimal Phase Conflict

Removal for Layout of Dark Field Alternating Phase Shifting Masks”, IEEE Transactions on

Computer-Aided Design 19(2) (2000), pp. 175-187.

43. C. J. Alpert, A. E. Caldwell, A. B. Kahng and I. L. Markov, “Hypergraph Partitioning With Fixed

Vertices”, IEEE Transactions on Computer-Aided Design 19(2) (2000), pp. 267-272.

44. A. E. Caldwell, A. B. Kahng and I. L. Markov, “Iterative Partitioning With Varying Node

Weights”, VLSI Design 11(3) (2000), pp. 249-258.

45. A. E. Caldwell, A. B. Kahng and I. L. Markov, “Design and Implementation of Move-Based

Heuristics for VLSI Hypergraph Partitioning”, ACM Journal of Experimental Algorithms (vol. 5)

2000.

46. A. E. Caldwell, A. B. Kahng and I. L. Markov, “Optimal Partitioners and End-case Placers for

Standard-cell Layout”, IEEE Transactions on Computer-Aided Design 19(11) (2000), pp. 1304-

1313.

47. A. E. Caldwell, A. B. Kahng and I. L. Markov, “Toward CAD-IP Reuse: The MARCO GSRC

Bookshelf of Fundamental CAD Algorithms”, IEEE Design and Test of Computers 19(3) (2002),

pp. 70-79.

48. A. B. Kahng, S. Mantik and D. Stroobandt, “Toward Accurate Models of Achievable Routing”,

IEEE Transactions on Computer-Aided Design 20(5) (2001), pp. 648-659.

49. R. Baldick, A. B. Kahng, A. A. Kennings and I. L. Markov, “Efficient Optimization by

Modifying the Objective Function”, IEEE Trans. on Circuits and Systems 48(8) (2001), pp. 947-

957.

50. A. B. Kahng, J. Lach, W. H. Mangione-Smith, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker,

H. Wang and G. Wolfe, “Constraint-Based Watermarking Techniques for Design Intellectual

Property Protection”, IEEE Transactions on Computer-Aided Design 20(10) (2001), pp. 1236-

1252.

51. C.-K. Cheng, A. B. Kahng, B. Liu and D. Stroobandt, “Toward Better Wireload Models in the

Presence of Obstacles”, IEEE Transactions on VLSI Systems 10(2) (2002), pp. 177-188.

52. R. E. Bryant, K. T. Cheng, A. B. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J. M.

Rabaey and A. Sangiovanni-Vincentelli, “Limitations and Challenges of CAD Technology for

CMOS VLSI”, Proc. of IEEE 89(3) (2001), pp. 341-365.

53. F. F. Dragan, A. B. Kahng, I. I. Mandoiu, S. Muddu and A. Zelikovsky, “Provably Good Global

Buffering by Generalized Multiterminal Multicommodity Flow Approximation”, IEEE

Transactions on Computer-Aided Design 21(3) (2002), pp. 263-274.

54. C. J. Alpert, G. Gandham, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu, S.T. Quay, S.S.

Sapatnekar and A. J. Sullivan, “Buffered Steiner Trees for Difficult Instances” IEEE

Transactions on Computer-Aided Design 21(1) (2002), pp. 3-14.


55. A. Allan, D. Edenfeld, W. H. Joyner, A. B. Kahng, M. Rodgers and Y. Zorian, “2001 Roadmap

for Semiconductor Technology”, IEEE Computer, 35(1) (2002), pp. 42-53.

56. Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky, “Area Fill Synthesis for Uniform Layout

Density”, IEEE Transactions on Computer-Aided Design 21(10) (2002), pp. 1132-1147.

57. J. N. Cooper, R. B. Ellis and A. B. Kahng, “Asymmetric Binary Covering Codes”, Journal of

Combinatorial Theory, Series A 100(2) (2002), pp. 232-249.

58. C. Alpert, A. B. Kahng, B. Liu, I. I. Mandoiu and A. Zelikovsky, “Minimum Buffered Routing

with Bounded Capacitive Load for Slew Rate and Reliability Control”, IEEE Transactions on

Computer-Aided Design 22(3) (2003), pp. 241-253.

59. Y. Cao, C. Hu, X. Huang, A. B. Kahng, I. I. Markov, M. Oliver, D. Stroobandt and D. Sylvester,

“Improved a Priori Interconnect Predictions and Technology Extrapolation in the GTX System”,

IEEE Transactions on VLSI Systems 11(1) (2003), pp. 3-14.

60. C. Albrecht, A. B. Kahng, B. Liu, I. I. Mandoiu and A. Zelikovsky, “On the Skew-Bounded

Minimum-Buffer Routing Tree Problem”, IEEE Transactions on Computer-Aided Design 22(7)

(2003), pp. 937-945.

61. A. E. Caldwell, A. B. Kahng and I. L. Markov, “Hierarchical Whitespace Allocation in Top-down

Placement”, IEEE Transactions on Computer-Aided Design 22(11) (2003), pp. 1550-1556.

62. A. B. Kahng, B. Liu and I. I. Mandoiu, “Non-tree Routing for Reliability and Yield

Improvement”, IEEE Transactions on Computer-Aided Design 23(1) (2004), pp. 148-156.

63. D. Edenfeld, A. B. Kahng, M. Rodgers and Y. Zorian, “2003 Technology Roadmap for

Semiconductors”, IEEE Computer 37(1) (2004), pp. 47-56.

64. A. E. Caldwell, H.-J. Choi, A. B. Kahng, S. Mantik, M. Potkonjak, G. Qu and J. L. Wong,

“Effective Iterative Techniques for Fingerprinting Design IP”, IEEE Transactions on Computer-

Aided Design, 23(2) (2004), pp. 208-215.

65. A. B. Kahng, I. I. Mandoiu, P.A. Pevzner, S. Reda and A. Zelikovsky, “Scalable Heuristics for

Design of DNA Probe Arrays”, Journal of Computational Biology, 2004, 11(2-3), pp. 429-447.

66. A. B. Kahng and X. Xu, “Local Unidirectional Bias for Cutsize-Delay Tradeoff in Performance-

Driven Bipartition”, IEEE Transactions on Computer-Aided Design 23(4) (2004), pp. 464-471.

67. A. B. Kahng and S. Reda, “Match Twice and Stitch: A New TSP Tour Construction Heuristic”,

Operations Research Letters, 2004, 32(6), pp. 499-509. As of February 2005, the most

downloaded “hottest” article of Operations Research Letters: Science Direct.

68. H. Chen, C. K. Cheng, A. B. Kahng, I. I. Mandoiu, Q. Wang and B. Yao, “The Y-architecture for

On-Chip Interconnect: Analysis and Methodology”, IEEE Transactions on Computer-Aided

Design 24(4) (2005), pp. 588-599.

69. P. Gupta, A. B. Kahng, I. I. Mandoiu and P. Sharma, “Layout-Aware Scan Chain Synthesis for

Improved Path Delay Fault Coverage”, IEEE Transactions on Computer-Aided Design 24(7)

(2005), pp. 1104-1114.

70. Y. Chen, A. B. Kahng, G. Robins, A. Zelikovsky, and Y. Zheng, “Compressible Area Fill

Synthesis”, IEEE Transactions on Computer-Aided Design 24(8) (2005), pp. 1169-1187.

71. A. B. Kahng, and Q. Wang, “Implementation and Extensibility of an Analytic Placer”, IEEE

Transactions on Computer-Aided Design 24(5) (2005), pp. 734-747.

72. P. Gupta, A. B. Kahng and S. Mantik, “Routing-Aware Scan Chain Ordering”, ACM

Transactions on Design Automation of Electronic Systems 10(3) (2005), pp. 546-560.

73. A. B. Kahng and S. Reda, “New and Improved BIST Diagnosis Methods from Combinatorial

Group Testing Theory”, IEEE Transactions on Computer-Aided Design, 25 (3) (2006), pp. 533-

543.

74. A. B. Kahng and S. Reda, “Wirelength Minimization for Min-Cut Placements via Placement

Feedback”, IEEE Transactions on Computer-Aided Design 25(7) (2005), pp. 1301-1312.

75. A. B. Kahng, I. I. Mandoiu, S. Reda, X. Xu, and A. Zelikovsky, “Computer-Aided Optimization

of DNA Array Design and Manufacturing”, IEEE Transactions on Computer-Aided Design, 25

(2) (2006) 305-320.


76. S. Babin, A.B. Kahng, I.I. Mandoiu and S. Muddu, “Improving CD Accuracy and Throughput by

Subfield Scheduling in Electron Beam Mask Writing”, Journal of Vacuum Science and

Technology B 23(10) (2005), pp. 3094-3100.

77. C. Alpert, A. Kahng, G.-J. Nam, S. Reda and P. Villarrubia, “A Fast Hierarchical Quadratic

Placement Algorithm”, IEEE Transactions on Computer-Aided Design 25(4) (2006), pp. 678-691.

78. A. Kahng and S. Reda, “Zero-Change Netlist Transformations: A New Technique for Placement

Benchmarking”, IEEE Transactions on Computer-Aided Design 25(12) (2006), pp. 2806-2819.

79. P. Gupta, A. B. Kahng, P. Sharma and D. Sylvester, “Gate-Length Biasing for Runtime Leakage

Control”, IEEE Transactions on Computer-Aided Design 25(8) (2006), pp. 1475-1485.

80. P. Gupta, A. B. Kahng, C.-H. Park, K. Samadi and X. Xu, “Wafer Topography-Aware Optical

Proximity Correction”, IEEE Transactions on Computer-Aided Design 25(12) (2006), pp. 2747-

2756.

81. C. Chiang, A. B. Kahng, S. Sinha, X. Xu and A. Zelikovsky, “Fast and Efficient Bright-Field

AAPSM Conflict Detection and Correction”, IEEE Transactions on Computer-Aided Design

26(1) (2007), pp. 115-126.

82. A. B. Kahng, I. I. Mandoiu, X. Xu, and A. Zelikovsky, “Enhanced Design Flow and

Optimizations for Multi-Project Wafers”, IEEE Transactions on Computer-Aided Design 26(2)

(2007), pp. 301-311.

83. P. Gupta, A. B. Kahng and C.-H. Park, “Detailed Placement for Enhanced Control of Resist and

Etch CDs”, IEEE Transactions on Computer-Aided Design 26(12) (2007), pp. 2144-2157.

84. A. B. Kahng and K. Samadi, “CMP Fill Synthesis: A Survey of Recent Studies”, IEEE

Transactions on Computer-Aided Design 27(1) (2008), pp. 3-19.

85. L. He, A. B. Kahng, K. H. Tam and J. Xiong, “Simultaneous Buffer Insertion and Wire Sizing

Considering Systematic CMP Variation and Random Leff Variation”, IEEE Transactions on

Computer-Aided Design 26(5) 2007, pp. 845-857.

86. A. B. Kahng, B. Liu, and Q. Wang, “Stochastic Power/Ground Voltage Prediction and

Optimization via Analytical Placement”, IEEE Transactions on VLSI Systems 15(8) (2007), pp.

904-912.

87. A. B. Kahng, S. Muddu and P. Sharma, “Defocus-Aware Leakage Estimation and Control”, IEEE

Transactions on Computer-Aided Design 27(2) (2008), pp. 230-240.

88. A. B. Kahng, B. Liu and X. Xu, “Statistical Timing Analysis in the Presence of Signal-Integrity

Effects”, IEEE Transactions on Computer-Aided Design 26(10) (2007), pp. 1873-1877.

89. P. Gupta, A. B. Kahng, Y. Kim and D. Sylvester, “Self-Compensating Design for Reduction of

Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation”, IEEE Transactions

on Computer-Aided Design 26(9) (2007), pp. 1614-1624.

90. P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, “Performance-Driven Optical Proximity

Correction for Mask Cost Reduction”, to appear in SPIE J. Microlithography, Microfabrication

and Microsystems.

91. A. B. Kahng, S. Muddu and C-.H. Park, “Auxiliary Pattern-Based OPC for Better Printability,

Timing and Leakage Control”, SPIE J. Microlithography, Microfabrication and Microsystems

7(1) (2008), pp. 013002-1--013002-13.

92. A. B. Kahng and A. B. Kahng and R. O. Topaloglu, “DOE-Based Extraction of CMP, Active and

Via Fill Impact on Capacitances”, IEEE Transactions on Semiconductor Manufacturing 21(1)

(2008), pp. 22-32.

93. A. B. Kahng, C-.H. Park and X. Xu, “Fast Dual Graph-Based Hotspot Detection”, IEEE

Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(9) (2008), pp.

1635-1642.

94. A. B. Kahng, P. Sharma and R. O. Topaloglu, “Chip Optimization Through STI-Stress-Aware

Placement Perturbations and Fill Insertion”, IEEE Transactions on Computer-Aided Design of

Integrated Circuits and Systems 27(7) (2008), pp. 1241-1252.


95. L. Carloni, A. B. Kahng, S. Muddu, A. Pinto, K. Samadi and P. Sharma, “Accurate Predictive

Interconnect Modeling for System-Level Design”, IEEE Transactions on Very Large Scale

Integration (VLSI) Systems 18(4) (2010), pp. 679-684.

96. K. Jeong, A. B. Kahng and K. Samadi, “Impact of Guardband Reduction on Design Outcomes: A

Quantitative Approach”, IEEE Transactions on Semiconductor Manufacturing 22(4) (2009), pp.

552-565.

97. A. B. Kahng, C.-H. Park, P. Sharma and Q. Wang, “Lens Aberration Aware Placement for

Timing Yield”, ACM Trans. on Design Automation of Electronic Systems 14(1) (2009), pp. 16:1

– 16:26.

98. A. B. Kahng, C.-H. Park, X. Xu and H. Yao, “Layout Decomposition Approaches for Double

Patterning Lithography”, IEEE Transactions on Computer-Aided Design of Integrated Circuits

and Systems 29(6) (2010), pp. 939-952.

99. K. Jeong, A. B. Kahng, C.-H. Park and H. Yao, “Dose Map and Placement Co-Optimization for

Improved Timing Yield and Leakage Power”, IEEE Transactions on Computer-Aided Design of

Integrated Circuits and Systems 29(7) (2010), pp. 1070-1082.

100. M. Gupta, K. Jeong and A. B. Kahng, “Timing Yield-Aware Color Reassignment and Detailed

Placement Perturbation for Bimodal CD Distribution in Double Patterning Lithography”, IEEE

Transactions on Computer-Aided Design of Integrated Circuits and Systems 29(8) (2010), pp.

1229-1242.

101. P. Gupta, K. Jeong, A. B. Kahng and C.-H. Park, “Electrical Assessment of Lithographic Gate

Line-End Patterning”, SPIE J. Microlithography, Microfabrication and Microsystems 9(2) (2010),

pp. 023014-1–023014-19.

102. K. Jeong, A. B. Kahng, B. Lin and K. Samadi, “Accurate Machine Learning-Based On-Chip

Router Modeling”, IEEE Embedded Systems Letters 2(3) (2010), pp. 62-66.

103. A. B. Kahng, B. Li, L.-S. Peh and K. Samadi, “ORION 2.0: A Power-Area Simulator for

Interconnection Networks”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems

20(1) (2012), pp. 191-196.

104. K. Jeong, A. B. Kahng and C. J. Progler, “Cost-Driven Mask Strategies Considering Parametric

Yield, Defectivity and Production Volume”, SPIE J. Microlithography, Microfabrication and

Microsystems 10(3) (2011), pp. 033021-1–033021-12.

105. C.-K. Cheng, P. Du, X. Hu, A. B. Kahng, G. K. H. Pang, Y. Wang and N. Wong, “A Realistic

Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints”, IEEE

Transactions on Computer-Aided Design of Integrated Circuits and Systems 31(1) (2012), pp.

109-120. (Correct author listing of this paper as given in Corrigendum, vol. 31(3) (2012), p. 452.)

106. A. B. Kahng, S. H. Kang, R. Kumar and J. Sartori, “Recovery-Driven Design: Exploiting Error

Resilience in Design of Energy-Efficient Processors”, IEEE Transactions on Computer-Aided

Design of Integrated Circuits and Systems 31(3) (2012), pp. 404-417.

107. A. B. Kahng, S. Kang, R. Kumar and J. Sartori, “Enhancing the Efficiency of Energy-Constrained

DVFS Designs”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2012), to

appear.

108. A. B. Kahng, S. Kang, T. S. Rosing and R. Strong, “Many-Core Token-Based Adaptive Power

Gating”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32(8)

(2013), pp. 1288-1292.

109. T.-B. Chan, P. Gupta, A. B. Kahng and L. Lai, “Synthesis and Analysis of Design-Dependent

Ring Oscillator (DDRO) Performance Monitors”, IEEE Transactions on Very Large Scale

Integration (VLSI) Systems (2013), to appear.


Conference Papers

1. A. B. Kahng, “Fast Hypergraph Partition”, Proc. ACM/IEEE Design Automation Conf., June

1989, pp. 762-766.

2. A. B. Kahng, “Traveling Salesman Heuristics and Embedding Dimension in the Hopfield Model”,

Proc. IEEE/INNS Intl. Joint Conf. on Neural Networks, June 1989, pp. I-513 - I-520.

3. A. B. Kahng and G. Robins, “A New Class of Steiner Tree Heuristics with Good Performance:

the Iterated 1-Steiner Approach”, Proc. IEEE International Conf. on Computer-Aided Design,

November 1990, pp. 428-431 (Distinguished Paper Award; 18 awards out of 442 submissions).

4. A. B. Kahng, J. Cong and G. Robins, “High-Performance Clock Routing Based on Recursive

Geometric Matching”, Proc. ACM/IEEE Design Automation Conf., June 1991, pp. 322-327.

5. A. B. Kahng, “A Steiner Tree Construction for VLSI Routing”, Proc. IEEE/INNS Intl. Joint Conf.

on Neural Networks, July 1991, pp. I-133 - I-139.

6. A. B. Kahng and G. Robins, “Optimal Algorithms for Determining Regularity in Pointsets”, Proc.

Third Canadian Conf. on Computational Geometry, August 1991, pp. 167-170.

7. J. Cong, L. Hagen and A. B. Kahng, “Random Walks for Circuit Clustering”, Proc. 4th IEEE Intl.

ASIC Conf., September 1991, pp. 14.2.1 - 14.2.4.

8. J. Cong, A. B. Kahng and G. Robins, “On Clock Routing For General Cell Layouts”, Proc. 4th

IEEE Intl. ASIC Conf., September 1991, pp. 14.5.1 - 14.5.4.

9. J. Cong, A. B. Kahng, G. Robins, M. Sarrafzadeh and C. K. Wong, “Performance-Driven Global

Routing for Cell Based IC's”, Proc. IEEE Intl. Conf. on Computer Design, October 1991, pp.

170-173.

10. A. B. Kahng, “An Effective Analog Approach to Steiner Routing”, Proc. IEEE Intl. Conf. on

Computer Design, October 1991, pp. 166-169.

11. L. Hagen and A. B. Kahng, “Fast Spectral Methods for Ratio Cut Partitioning and Clustering”,

Proc. IEEE Intl. Conf. on Computer-Aided Design, November 1991, pp. 10-13.

12. A. B. Kahng, “Exploiting Fractalness in Error Surfaces: New Methods for Neural Network

Learning”, Proc. IEEE Intl. Symp. on Circuits and Systems, May 1992, pp. 41-44.

13. A. B. Kahng, G. Robins and E. Walkup, “New Results and Algorithms for MCM Substrate

Testing”, Proc. IEEE Intl. Symp. on Circuits and Systems, May 1992, pp. 1113-1116.

14. J. Cong, A. B. Kahng, G. Robins, M. Sarrafzadeh and C. K. Wong, “Provably Good Algorithms

for Performance-Driven Global Routing”, Proc. IEEE Intl. Symp. on Circuits and Systems, May

1992, pp. 2240-2243.

15. K. C. Chen, J. Cong, A. Kahng and P. Trajmar, “Graph Based FPGA Technology Mapping for

Delay Minimization”, Proc. IEEE Workshop on Field-Programmable Gate Arrays, March 1992,

pp. 77-81.

16. A. B. Kahng, “Random Structure of Error Surfaces: New Stochastic Learning Methods”, Invited

Paper, Proc. SPIE (Joint Conf. on Artificial Neural Networks: Science and Applications), 1710

(pt. 1, vol. 2) April 1992, pp. 768-779.

17. J. Cong, L. Hagen and A. B. Kahng, “Net Partitions Yield Better Module Partitions”, Proc. 29th

ACM/IEEE Design Automation Conf., June 1992, pp. 47-52 (nominated for Best Paper Award;

18 nominees out of 440 submissions).

18. L. Hagen, A. B. Kahng, F. Kurdahi and C. Ramachandran, “On the Intrinsic Rent Parameter and

New Spectra-Based Methods for Wireability Estimation”, Proc. European Design Automation

Conf., October 1992, pp. 202-208 (nominated for Best Paper Award; 6 nominees out of 335

submissions).

19. K. C. Chen, Y. Ding, J. Cong, A. Kahng and P. Trajmar, “An Improved Graph Based FPGA

Technology Mapping for Delay Minimization”, Proc. IEEE Intl. Conf. on Computer Design,

October 1992, pp. 154-158.

20. K. Boese and A. B. Kahng, “Zero-Skew Clock Routing Trees With Minimum Wirelength”, Proc.

IEEE 5th Intl. ASIC Conf., September 1992, pp. 1.1.1 - 1.1.5.


21. L. Hagen and A. B. Kahng, “Improving the Quadratic Objective Function in Module Placement”,

Proc. IEEE 5th Intl. ASIC Conf., September 1992, pp. 1.7.1 - 1.7.4.

22. L. Hagen and A. B. Kahng, “A New Approach to Effective Circuit Clustering”, Proc. IEEE Intl.

Conf. on Computer-Aided Design, November 1992, pp. 422-427.

23. K. D. Boese, J. Cong, A. B. Kahng, K. S. Leung and D. Zhou, “On High-Speed VLSI

Interconnects: Analysis and Design”, Proc. Asia-Pacific Conf. on Circuits and Systems,

December 1992, pp. 35-40.

24. K. D. Boese and A. B. Kahng, “Simulated Annealing of Neural Networks: the 'Cooling' Strategy

Revisited”, Proc. IEEE Intl. Conf. on Circuits and Systems, May 1993, pp. 2572-2575.

25. C. J. Alpert, J. Cong, A. B. Kahng, G. Robins and M. Sarrafzadeh, “Minimum Density

Interconnection Trees”, Proc. IEEE Intl. Conf. on Circuits and Systems, May 1993, pp. 1865-

1868.

26. C. J. Alpert, T. C. Hu, J. H. Huang and A. B. Kahng, “A Direct Combination of the Prim and

Dijkstra Constructions for Improved Performance-Driven Global Routing”, Proc. IEEE Intl.

Conf. on Circuits and Systems, May 1993, pp. 1869-1872.

27. C. J. Alpert and A. B. Kahng, “Geometric Embeddings for Faster (and Better) Multi-Way Netlist

Partitioning”, Proc. ACM/IEEE Design Automation Conf., June 1993, pp. 743-748.

28. K. D. Boese, A. B. Kahng and G. Robins, “High-Performance Routing Trees With Identified

Critical Sinks”, Proc. ACM/IEEE Design Automation Conf., June 1993, pp. 182-187.

29. K. D. Boese, A. B. Kahng, B. A. McCoy and G. Robins, “Toward Optimal Routing Trees”, Proc.

ACM SIGDA Physical Design Workshop, April 1993, pp. 44-51.

30. K. D. Boese, A. B. Kahng and C. W. Tsao, “Best-So-Far vs. Where-You-Are: New Perspectives

on Simulated Annealing for CAD”, Proc. European Design Automation Conf., September 1993,

pp. 78-83.

31. K. D. Boese, A. B. Kahng, B. A. McCoy and G. Robins, “Fidelity and Near-Optimality of

Elmore-Based Routing Constructions”, Proc. IEEE Intl. Conf. on Computer Design, October

1993, pp. 81-84.

32. C. J. Alpert and A. B. Kahng, “Multi-Way Partitioning Via Spacefilling Curves and Dynamic

Programming”, Proc. ACM/IEEE Design Automation Conf., June 1994, pp. 652-657. Best Paper

Award out of 439 submissions.

33. A. B. Kahng and S. Muddu, “Delay Analysis of VLSI Interconnections Using the Diffusion

Equation Model”, Proc. ACM/IEEE Design Automation Conf., June 1994, pp. 563-569.

34. K. D. Boese, A. B. Kahng, B. A. McCoy and G. Robins, “Rectilinear Steiner Trees with

Minimum Elmore Delay”, Proc. ACM/IEEE Design Automation Conf., June 1994, pp. 381-386.

35. A. B. Kahng and S. Muddu, “Optimal Equivalent Circuits for Interconnect Delay Calculations

Using Moments”, Proc. European Design Automation Conference, September 1994, pp. 164-

169.

36. A. B. Kahng and C.-W. A. Tsao, “Planar-DME: Improved Planar Zero-Skew Clock Routing with

Minimum Pathlength Delay”, Proc. European Design Automation Conference, September 1994,

pp. 440-445. (Nominated for Best Paper Award; 7 nominees out of 260 submissions.)

37. A. B. Kahng and C.-W. A. Tsao, “Low-Cost Planar Clock Trees With Exact Zero Elmore Delay

Skew”, Proc. IEEE Intl. Conf. on Computer-Aided Design, November 1994, pp. 213-218.

38. C. J. Alpert and A. B. Kahng, “A General Framework for Vertex Orderings, With Applications to

Netlist Clustering”, Proc. IEEE Intl. Conf. on Computer-Aided Design, November 1994, pp. 63-

67.

39. A. B. Kahng and S. Muddu, “Two-Pole Analysis of Interconnection Trees”, Proc. IEEE Multi-

Chip Module Conference, February 1995, pp. 105-110.

40. J. H. Huang and A. B. Kahng, “Multi-Way System Partitioning into Single or Multiple Type

FPGAs”, Proc. ACM Intl. Symp. on Field-Programmable Gate Arrays, February 1995, pp. 140-

145.


41. J. H. Huang and A. B. Kahng, “When Clusters Meet Partitions: New Density-Based Methods for

Circuit Decomposition”, Proc. European Design and Test Conference, March 1995, pp. 60-64.

42. K. D. Boese, D. E. Franklin and A. B. Kahng, “Training Minimal Artificial Neural Network

Architectures for Subsoil Object Detection”, Proc. SPIE Aerosense-95: Detection Technologies

for Mines and Minelike Targets, April 1995, pp. 900-911.

43. D. E. Franklin, A. B. Kahng and M. A. Lewis, “Distributed Sensing and Probing With Multiple

Search Agents: Toward System-Level Landmine Detection Solutions”, Proc. SPIE Aerosense-95:

Detection Technologies for Mines and Minelike Targets, April 1995, pp. 698-709.

44. L. Hagen, J. H. Huang and A. B. Kahng, “Quantified Suboptimality of VLSI Layout Heuristics”,

Proc. ACM/IEEE Design Automation Conf., June 1995, pp. 216-221.

45. J. H. Huang, A. B. Kahng and C.-W. A Tsao, “On the Bounded-Skew Routing Tree Problem”,

Proc. ACM/IEEE Design Automation Conf., June 1995, pp. 508-513.

46. Y. Cao, T.-W. Chen, M. Harris, A. B. Kahng, M. A. Lewis and A. D. Stechert, “A Remote

Robotics Laboratory on the Internet”, Proc. INET-95, June 1995, pp. 65-72.

47. A. B. Kahng and B. R. Moon, “Toward More Powerful Recombinations”, Proc. Intl. Conf. on

Genetic Algorithms, July 1995, pp. 96-103.

48. Y. Cao, A. S. Fukunaga, A. B. Kahng and F. Meng, “Cooperative Mobile Robotics: Antecedents

and Directions”, Proc. IEEE/RSJ Intl. Symp. on Intelligent Robotics and Systems, August 1995,

pp. 226-234.

49. L. Hagen, J. H. Huang and A. B. Kahng, “On Implementation Choices for Iterative Improvement

Partitioning Algorithms”, Proc. European Design Automation Conf., September 1995, pp. 144-

149.

50. J. Cong, A. B. Kahng, C. K. Koh and C.-W. A. Tsao, “Bounded-Skew Clock and Steiner Routing

Under Elmore Delay”, Proc. IEEE Intl. Conf. on Computer-Aided Design, November 1995, pp.

66-71.

51. A. S. Fukunaga and A. B. Kahng, “Improving the Performance of Evolutionary Optimization by

Dynamically Scaling the Evaluation Function”, Proc. IEEE Intl. Conf. on Evolutionary

Computation, November 1995, pp. I-182 - I-187.

52. I. Hong, A. B. Kahng and B. R. Moon, “Exploiting Synergies of Multiple Crossovers: Initial

Studies”, Proc. IEEE Intl. Conf. on Evolutionary Computation, November 1995, pp. I-245 - I-

250.

53. A. B. Kahng and S. Muddu, “Efficient Gate Delay Modeling for Large Interconnect Loads”, Proc.

IEEE Multi-Chip Module Conference, February 1996, pp. 202-207.

54. C. J. Alpert, L. Hagen and A. B. Kahng, “A Hybrid Multilevel/Genetic Approach for Circuit

Partitioning”, Proc. ACM SIGDA Physical Design Workshop, April 1996, pp. 100-105.

55. A. B. Kahng and S. Muddu, “An Analytical Delay Model for RLC Interconnects”, Proc. IEEE

Intl. Symp. on Circuits and Systems, May 1996, pp. IV/237-240.

56. A. B. Kahng and S. Muddu, “New Analyses of Distributed RC Interconnections”, Proc. IEEE Intl.

Symp. on Circuits and Systems, May 1996, pp. IV/241-244.

57. A. S. Fukunaga, J. H. Huang and A. B. Kahng, “Large-Step Markov Chain Variants for VLSI

Netlist Partitioning”, Proc. IEEE Intl. Symp. on Circuits and Systems, May 1996, pp. IV/496-

499.

58. C. J. Alpert and A. B. Kahng, “Simple Eigenvector-Based Circuit Clustering Can Be Effective”,

Proc. IEEE Intl. Symp. on Circuits and Systems, May 1996, pp. IV/683-686.

59. A. B. Kahng and S. Muddu, “Analysis of RC Interconnections Under Ramp Input”, Proc.

ACM/IEEE Design Automation Conference, June 1996, pp. 533-538.

60. A. B. Kahng, K. Masuko and S. Muddu, “Analytical Delay Models for VLSI Interconnections

Under Ramp Input”, Proc. ACM/IEEE Intl. Conference on Computer-Aided Design, November

1996, pp. 30-36.

61. A. B. Kahng and S. Muddu, “Delay Analysis of Coupled Transmission Lines”, Proc. Asia-Pacific

Conference on Circuits and Systems, November 1996, pp. 81-84.


62. A. B. Kahng and S. Muddu, “Gate Load Delay Computation Using Analytical Models”, Proc.

Asia-Pacific Conference on Circuits and Systems, November 1996, pp. 433-436.

63. C. J. Alpert, L. W. Hagen and A. B. Kahng, “A Hybrid Multilevel/Genetic Approach for Circuit

Partitioning”, Proc. Asia-Pacific Conference on Circuits and Systems, November 1996, pp. 298-

301.

64. A. B. Kahng, K. Masuko and S. Muddu, “Delay Models for MCM Interconnects When Response

is Non-Monotone”, Proc. IEEE Multi-Chip Module Conference, March 1997, pp. 102-107.

65. C. J. Alpert, T. Chan, D. J. Huang, A. B. Kahng, I. Markov, P. Mulet and K. Yan, “Faster

Minimization of Linear Wirelength for Global Placement”, Proc. ACM/IEEE Intl. Symp. on

Physical Design, April 1997, pp. 4-11.

66. D. J. Huang and A. B. Kahng, “Partitioning-Based Standard-Cell Global Placement with an Exact

Objective”, Proc. ACM/IEEE Intl. Symp. on Physical Design, April 1997, pp. 18-25.

67. J. Cong, A. B. Kahng and K.-S. Leung, “Efficient Heuristics for the Minimum Shortest Path

Steiner Arborescence Problem with Applications to VLSI Physical Design”, Proc. ACM/IEEE

Intl. Symp. on Physical Design, April 1997, pp. 88-95.

68. C. J. Alpert, D. J. Huang and A. B. Kahng, “Multilevel Circuit Partitioning”, Proc. ACM/IEEE

Design Automation Conference, June 1997, pp. 530-533.

69. J. Cong, L. He, A. B. Kahng, D. Noice, N. Shirali and S. H.-C. Yen, “Analysis and Justification

of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology”, Proc. ACM/IEEE Design

Automation Conference, June 1997, pp. 627-632.

70. A. B. Kahng and C.-W. A. Tsao, “More Practical Bounded-Skew Clock Routing”, Proc.

ACM/IEEE Design Automation Conference, June 1997, pp. 594-599.

71. W. Huang and A. B. Kahng, “A Layout Advisor for Timing-Critical Bus Routing”, Proc. IEEE

ASIC Conference, September 1997, pp. 210-214.

72. A. B. Kahng, S. Muddu, E. Sarto and R. Sharma, “Interconnect Tuning Strategies for High-

Performance ICs”, Proc. Design, Automation and Testing in Europe, February 1998. [Collected

in R. Lauwereins and J. Madsen, eds., Design, Automation, and Test in Europe: The Most

Influential Papers of 10 Years DATE, Springer, 2008.]

73. A. E. Caldwell, A. B. Kahng, S. Mantik and I. L. Markov, “Implications of Area-Array I/O for

Row-Based Placement Methodology”, Proc. IEEE Symp. on IC/Package Design Integration,

February 1998, pp. 93-98.

74. A. B. Kahng, G. Robins, A. Singh, H. Wang and A. Zelikovsky, “Filling and Slotting: Analysis

and Algorithms”, Proc. ACM/IEEE Intl. Symp. on Physical Design, April 1998, pp. 95-102.

75. A. B. Kahng and S. Muddu, “New Efficient Algorithms for Computing Effective Capacitance”,

Proc. ACM/IEEE Intl. Symp. on Physical Design, April 1998, pp. 147-151.

76. A. B. Kahng, “Futures for Partitioning in Physical Design”, Proc. ACM/IEEE Intl. Symp. on

Physical Design, April 1998, pp. 190-193.

77. A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov and A. Zelikovsky, “On Wirelength

Estimations for Row-Based Placement”, Proc. ACM/IEEE Intl. Symp. on Physical Design, April

1998, pp. 4-11.

78. A. B. Kahng, J. Lach, W. H. Mangione-Smith, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker,

H. Wang and G. Wolfe, “Watermarking Techniques for Intellectual Property Protection” Proc.

ACM/IEEE Design Automation Conference, June 1998, pp. 776-781.

79. A. B. Kahng, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang and G. Wolfe, “Robust

IP Watermarking Methodologies for Physical Design”, Proc. ACM/IEEE Design Automation

Conference, June 1998, pp. 782-787.

80. A. E. Caldwell, A. B. Kahng and I. L. Markov, “Relaxed Partitioning Balance Constraints in Top-

Down Placement”, Proc. IEEE ASIC Conference, September 1998, pp. 229-232.

81. A. B. Kahng, H. Wang and A. Zelikovsky, “Automated Layout and Phase Assignment

Techniques for Dark Field Alternating PSM”, Proc. 18th BACUS Symposium on Photomask

Technology and Management, September 1998, pp. 222-231.


82. A. B. Kahng, “IC Layout and Manufacturability: Critical Links and Design Flow Implications”,

Proc. IEEE Intl. Conf. on VLSI Design, Jan. 1999, pp. 100-105.

83. A. B. Kahng, G. Robins, A. Singh and A. Zelikovsky, “New and Exact Filling Algorithms for

Layout Density Control”, Proc. IEEE Intl. Conf. on VLSI Design, Jan. 1999, pp. 106-110.

84. A. B. Kahng, S. Muddu, E. Sarto, “Interconnect Optimization Strategies for High-Performance

VLSI Design”, Proc. IEEE Intl. Conf. on VLSI Design, Jan. 1999, pp. 464-469.

85. A. B. Kahng and S. Muddu, “Improved Effective Capacitance Computations for Use in Logic and

Layout Optimization”, Proc. IEEE Intl. Conf. on VLSI Design, Jan. 1999, pp. 578-582.

86. A. B. Kahng, G. Robins, A. Singh and A. Zelikovsky, “New Multilevel and Hierarchical

Algorithms for Layout Density Control”, Proc. Asia and South Pacific Design Automation Conf.,

Jan. 1999, pp. 221-224.

87. R. Baldick, A. B. Kahng, A. Kennings and I. L. Markov, “Function Smoothing with Applications

to VLSI Layout”, Proc. Asia and South Pacific Design Automation Conf., Jan. 1999, pp. 225-228.

Nominated for Best Paper Award.

88. A. B. Kahng, P. Tucker and A. Zelikovsky, “Optimization of Linear Placements for Wirelength

Minimization with Free Sites”, Proc. Asia and South Pacific Design Automation Conf., Jan. 1999,

pp. 241-244. Nominated for Best Paper Award.

89. A. E. Caldwell, A. B. Kahng and I. L. Markov, “Design and Implementation of the Fiduccia-

Mattheyses Heuristic for VLSI Netlist Partitioning”, Proc. Workshop on Algorithm Engineering

and Experimentation (ALENEX), Jan. 1999, pp. 177-193

90. P. Berman, A. B. Kahng, D. Vidhani, H. Wang and A. Zelikovsky, “Optimal Phase Conflict

Removal for Layout of Dark Field Alternating Phase Shifting Masks”, Proc. ACM Intl. Symp. on

Physical Design, April 1999, pp. 121-126.

91. A. E. Caldwell, A. B. Kahng and I. L. Markov, “Optimal Partitioners and End-Case Placers for

Standard-Cell Layout”, Proc. ACM Intl. Symp. on Physical Design, April 1999, pp. 90-96.

92. C. J. Alpert, A. E. Caldwell, A. B. Kahng and I. L. Markov, “Partitioning With Terminals: A

'New' Problem and New Benchmarks”, Proc. ACM Intl. Symp. on Physical Design, April 1999,

pp. 151-157.

93. A. B. Kahng and Y. C. Pati, “Subwavelength Optical Lithography: Challenges and Impact on

Physical Design”, Proc. ACM Intl. Symp. on Physical Design, April 1999, pp. 112-119.

94. A. E. Caldwell, A. B. Kahng, A. A. Kennings and I. L. Markov, “Hypergraph Partitioning for

VLSI CAD: Methodology for Reporting, and New Results”, Proc. ACM/IEEE Design

Automation Conf., June 1999, pp. 349-354.

95. A. E. Caldwell, A. B. Kahng and I. L. Markov, “Hypergraph Partitioning with Fixed Vertices”,

Proc. ACM/IEEE Design Automation Conf., June 1999, pp. 355-359.

96. A. E. Caldwell, H.-J. Choi, A. B. Kahng, S. Mantik, M. Potkonjak and G. Qu, “Effective Iterative

Techniques for Fingerprinting Design IP”, Proc. ACM/IEEE Design Automation Conf., June 1999,

pp. 843-848.

97. A. B. Kahng and Y. C. Pati, “Subwavelength Lithography and its Potential Impact on Design and

EDA”, Proc. ACM/IEEE Design Automation Conf., June 1999, pp. 799-804.

98. P. Berman, A. B. Kahng, D. Vidhani and A. Zelikovsky, “The T-Join Problem in Sparse Graphs:

Applications to Phase Assignment Problem in VLSI Mask Layout”, Proc. Workshop on

Algorithms and Data Structures (WADS), LNCS (vol. 1663), August 1999, pp. 25-36.

99. A. B. Kahng, S. Muddu and D. Vidhani, “Noise and Delay Uncertainty Studies for Coupled RC

Interconnects”, Proc. IEEE International ASIC/SOC Conference, September 1999, pp. 3-8.

100. Y. Chen, A. B. Kahng, G. Qu and A. Zelikovsky, “The Associative-Skew Clock Routing

Problem”, Proc. IEEE/ACM Intl. Conference on Computer-Aided Design, November 1999, pp.

168-172.

101. A. B. Kahng, D. Kirovski, S. Mantik, M. Potkonjak and J. L. Wong, “Copy Detection for

Intellectual Property Protection of VLSI Design”, Proc. IEEE/ACM Intl. Conference on

Computer-Aided Design, November 1999, pp. 600-604.


102. A. E. Caldwell, A. B. Kahng and I. L. Markov, “Improved Algorithms for Hypergraph

Bipartitioning”, Proc. Asia and South Pacific Design Automation Conf., Jan. 2000, pp. 661-666.

103. Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky, “Monte-Carlo Algorithms for Layout

Density Control”, Proc. Asia and South Pacific Design Automation Conf., Jan. 2000, pp. 523-

528.

104. A. B. Kahng, S. Mantik and D. Stroobandt, “Requirements for Models of Achievable Routing”,

Proc. ACM Intl. Symp. on Physical Design, April 2000, pp. 4-11.

105. A. B. Kahng, “Classical Floorplanning Harmful?” Proc. ACM Intl. Symp. on Physical Design,

April 2000, pp. 207-213.

106. A. B. Kahng and D. Stroobandt, “Wiring Layer Assignments with Consistent Stage Delays”, Proc.

ACM International Workshop on System-Level Interconnect Prediction, April 2000, pp. 115-122.

107. A. B. Kahng, S. Muddu and E. Sarto, “On Switch Factor Based Analysis of Coupled RC

Interconnects”, Proc. ACM/IEEE Design Automation Conf., June 2000, pp. 79-84.

108. A. E. Caldwell, A. B. Kahng and I. L. Markov, “Can Recursive Bisection Produce Routable

Placements?”, Proc. ACM/IEEE Design Automation Conf., June 2000, pp. 477-482.

109. Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky, “Practical Iterated Fill Synthesis for CMP

Uniformity”, Proc. ACM/IEEE Design Automation Conf., June 2000, pp. 671-674.

110. A. E. Caldwell, Y Cao, A. B. Kahng, F. Koushanfar, H. Lu, I. L. Markov, M. R. Oliver, D.

Stroobandt and D. Sylvester, “GTX: The MARCO GSRC Technology Extrapolation System”,

Proc. ACM/IEEE Design Automation Conf., June 2000, pp. 693-698.

111. S. Fenstermaker, D. George, A. B. Kahng, S. Mantik and B. Thielges, “METRICS: A System

Architecture for Design Process Optimization”, Proc. ACM/IEEE Design Automation Conf., June

2000, pp. 705-710.

112. A. B. Kahng and S. Mantik, “On Mismatches Between Incremental Optimizers and Instance

Perturbations in Physical Design Tools”, Proc. IEEE/ACM Intl. Conference on Computer-Aided

Design, November 2000, pp. 17-21.

113. Y. Cao, C. M. Hu, X. J. Huang, A. B. Kahng, S. Muddu, D. Stroobandt and D. Sylvester, “Effects

of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design”,

Proc. IEEE/ACM Intl. Conference on Computer-Aided Design, November 2000, pp. 56-61.

114. F. Dragan, A. B. Kahng, I. Mandoiu, S. Muddu and A. Zelikovsky, “Provably Good Global

Buffering Using an Available Buffer Block Plan”, Proc. IEEE/ACM Intl. Conference on

Computer-Aided Design, November 2000, pp. 104-109.

115. Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky, “Hierarchical Dummy Fill for Process

Uniformity”, Proc. Asia and South Pacific Design Automation Conf., Jan. 2001, pp. 139-144.

116. C. K. Cheng, A. B. Kahng, B. Liu and D. Stroobandt, “Toward Better Wireload Models in the

Presence of Obstacles”, Proc. Asia and South Pacific Design Automation Conf., Jan. 2001, pp.

527-532.

117. A. B. Kahng, S. Vaya and A. Zelikovsky, “New Graph Bipartizations for Double-Exposure,

Bright Field Alternating Phase-Shift Mask Layout”, Proc. Asia and South Pacific Design

Automation Conf., Jan. 2001, pp. 133-138.

118. F. Dragan, A. B. Kahng, I. Mandoiu, S. Muddu and A. Zelikovsky, “Provably Good Global

Buffering by Multiterminal Multicommodity Flow Approximation”, Proc. Asia and South Pacific

Design Automation Conf., Jan. 2001, pp. 120-125.

119. A. B. Kahng, “Design Technology Productivity in the DSM Era” Invited Paper, Proc. Asia and

South Pacific Design Automation Conf., Jan. 2001, pp. 443-448.

120. A. B. Kahng, S. Muddu, N. Pol and D. Vidhani, “Noise Model for Multiple Segmented Coupled

RC Interconnects”, Proc. International Symposium on Quality in Electronic Design , March

2001, pp. 145-150.

121. A. B. Kahng and S. Mantik, “A System for Automatic Recording and Prediction of Design

Quality Metrics”, Proc. International Symposium on Quality in Electronic Design, March 2001,

pp. 81-86. Best Paper Award.


122. C. K. Cheng, A. B. Kahng and B. Liu, “Interconnect Implications of Growth-Based Structural

Models for VLSI Circuits”, Proc. ACM International Workshop on System-Level Interconnect

Prediction, April 2001, pp. 99-106.

123. K. D. Boese, A. B. Kahng and S. Mantik, “On the Relevance of Wire Load Models”, Proc. ACM

International Workshop on System-Level Interconnect Prediction, April 2001, pp. 91-98.

124. C. J. Alpert, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu, S. T. Quay, S. S. Sapatnekar, A. J.

Sullivan and P. Villarrubia, “Buffered Steiner Trees for Difficult Instances”, Proc. ACM/IEEE

Intl. Symp. on Physical Design, April 2001, pp. 4-9.

125. F. Dragan, A. B. Kahng, I. Mandoiu, S. Muddu and A. Zelikovsky, “Practical Approximation

Algorithms for Separable Packing Linear Programs”, Proc. 7th International Workshop on

Algorithms and Data Structures, August 2001, pp. 325-337.

126. C. Albrecht, A. B. Kahng, B. Liu, I. Mandoiu and A. Zelikovsky, “On the Skew-Bounded

Minimum Buffer Routing Tree Problem”, Proc. The Tenth Workshop on Synthesis And System

Integration of Mixed Technologies, October 2001, pp. 250-256.

127. A. B. Kahng, R. Kastner, S. Mantik, M. Sarrafzadeh, and X. Yang, “Studies of Timing Structural

Properties for Early Evaluation of Circuit Design”, Proc. The Tenth Workshop on Synthesis and

System Integration of Mixed Technologies, October 2001, pp. 285-292.

128. C. Alpert, A. B. Kahng, B. Liu, I. Mandoiu and A. Zelikovsky, “Minimum-Buffered Routing of

Non-Critical Nets for Slew Rate and Reliability Control”, Proc. IEEE-ACM Intl. Conf. on

Computer-Aided Design, November 2001, pp. 408-415.

129. C. Albrecht, A. B. Kahng, I. Mandoiu and A. Zelikovsky, “Floorplan Evaluation with Timing-

Driven Global Wireplanning, Pin Assignment, and Buffer/Wire Sizing”, Proc. Intl. Conf. on

VLSI Design/ASPDAC, January 2002, pp. 580-587. Best Paper Award out of 269 submissions.

130. A. Kahng and S. Mantik, “Measurement of Inherent Noise in EDA Tools”, Proc. International

Symposium on Quality in Electronic Design, March 2002, pp. 206-211.

131. A. Kahng and G. Smith, “A New Design Cost Model for 2001 ITRS”, Proc. International

Symposium on Quality Electronic Design, March 2002, pp. 190-193.

132. Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky, “Monte-Carlo Methods for Chemical-

Mechanical Planarization on Multiple-Layer and Dual-Material Models”, Proc. SPIE Conference

on Design and Process Integration for Microelectronic Manufacturing, Santa Clara, March 2002,

pp. 421-432.

133. A. B. Kahng, “Design-Manufacturing Integration and Shared “Brick Walls” “, Proc. SPIE

Conference on Design and Process Integration for Microelectronic Manufacturing, Santa Clara,

March 2002, pp. 390-400.

134. Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky, “Closing the Smoothness and Uniformity

Gap in Area Fill Synthesis”, Proc. ACM/IEEE Intl. Symp. on Physical Design, April 2002, pp.

137-142.

135. A. B. Kahng, S. Mantik and I. L. Markov, “Min-Max Placements for Large-Scale Timing

Optimization”, Proc. ACM/IEEE Intl. Symp. on Physical Design, April 2002, pp. 143-148.

136. A. B. Kahng, “A Roadmap and Vision for Physical Design”, Proc. ACM/IEEE Intl. Symp. on

Physical Design, April 2002, pp. 112-117.

137. C. Bandela, Y. Chen, A. B. Kahng, I. I. Mandoiu and A. Zelikovsky, “Auctions with Buyer

Preferences”, Information Systems: The E-Business Challenge - Proc. 17th IFIP World

Computer Congress, Kluwer Academic Publishers, 2002, pp. 221-238.

138. Y. Cao, P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, “Design Sensitivities to Variability:

Extrapolation and Assessments in Nanometer VLSI”, Proc. IEEE ASIC/SoC Conference,

September 2002, pp. 411-415.

139. A. B. Kahng, I. I. Mandoiu, P. A. Pevzner, S. Reda, and A. A. Zelikovsky, “Border Length

Minimization in DNA Array Design”, Proc. 2nd Workshop on Algorithms in Bioinformatics

(WABI), September 2002, pp. 435-448.


140. A. B. Kahng, B. Liu, and I. I. Mandoiu, “Non-Tree Routing for Reliability and Yield

Improvement”, Proc. IEEE/ACM Intl. Conference on Computer-Aided Design, November 2002,

pp. 260-266.

141. A. B. Kahng, I. I. Mandoiu, and A. Zelikovsky, “Highly Scalable Algorithms for Rectilinear and

Octilinear Steiner Trees”, Proc. Asia and South Pacific Design Automation Conf., Jan. 2003, pp.

827-833.

142. P. Gupta, A. B. Kahng and S. Mantik, “Routing-Aware Scan Chain Ordering”, Proc. Asia and

South Pacific Design Automation Conf., Jan. 2003, pp. 857-862.

143. A. B. Kahng and B. Liu, “Q-Tree: A New Iterative Improvement Approach for Buffered

Interconnect Optimization”, Proc. IEEE Comp. Soc. Annual Symp. On VLSI, Feb. 2003, pp. 183-

188.

144. A. B. Kahng, R. Ellis, and Y. Zheng, “Compression Algorithms for Dummy Fill Layout Data”,

Proc. SPIE Conf. on Design and Process Integration for Microelectronic Manufacturing, Feb.

2003, pp. 233-245.

145. Y. Chen, P. Gupta, and A. B. Kahng, “Performance-Impact Limited Dummy Fill Insertion”, Proc.

SPIE Conf. on Design and Process Integration for Microelectronic Manufacturing, Feb. 2003, pp.

75-86.

146. D. Sylvester, P. Gupta, A. B. Kahng, and J. Yang, “Toward Performance-Driven Reduction of the

Cost of RET-Based Lithography Control” Invited Paper Proc. SPIE Conf. on Design and

Process Integration for Microelectronic Manufacturing, Feb. 2003, pp. 123-133.

147. S. V. Babin, A. B. Kahng, I. I. Mandoiu, and S. Muddu, “Subfield Scheduling for Throughput

Maximization in Electron-Beam Photomask Fabrication”, Emerging Lithographic Technologies

VII, R. L. Engelstad (ed.), Proc. SPIE #5037, Feb. 2003, pp. 934-942.

148. Y. Chen, A. B. Kahng, G. Robins, A. Zelikovsky, and Y. H. Zheng, “Area Fill Generation with

Inherent Data Volume Reduction”, Proc. Design Automation and Testing in Europe, March 2003,

pp. 868-873.

149. P. Dasgupta, A. B. Kahng, and S. Muddu, “A Novel Metric for Interconnect Architecture

Performance”, Proc. Design Automation and Testing in Europe, March 2003, pp. 448-453.

150. P. Gupta and A. B. Kahng, “Quantifying Error in Dynamic Power Estimation of CMOS Circuits”,

Proc. IEEE Intl. Symp. on Quality Electronic Design, March 2003, pp. 273-278.

151. P. Gupta, A. B. Kahng and S. Mantik, “A Proposal for Routing-Based Timing-Driven Scan Chain

Ordering”, Proc. IEEE Intl. Symp. on Quality Electronic Design, March 2003, pp. 339-343.

152. A. B. Kahng and I. L. Markov, “Impact of Interoperability on CAD-IP Reuse: An Academic

Viewpoint”, Proc. IEEE Intl. Symp. on Quality Electronic Design, March 2003, pp. 208-213.

153. H. Chen, C. K. Cheng, A. B. Kahng, I. Mandoiu and Q. Wang, “Estimation of Wirelength

Reduction for -Geometry vs. Manhattan Placement and Routing”, Proc. ACM International

Workshop on System-Level Interconnect Prediction, April 2003, pp. 71-76.

154. A. B. Kahng and X. Xu, “Accurate Pseudo-Constructive Wirelength and Congestion Estimation”,

Proc. ACM International Workshop on System-Level Interconnect Prediction, April 2003, pp. 61-

68.

155. A. B. Kahng, “Research Directions for Coevolution of Rules and Routers”, Invited Paper, Proc.

ACM/IEEE Intl. Symp. on Physical Design, April 2003, pp. 122-125.

156. A. B. Kahng and X. Xu, “Local Unidirectional Bias for Smooth Cutsize-Delay Tradeoff in

Performance-Driven Bipartitioning”, Proc. ACM/IEEE Intl. Symp. on Physical Design, April

2003, pp. 81-86.

157. A. B. Kahng, I. Mandoiu, P. Pevzner, S. Reda, and A. Zelikvosky, “ Engineering a Scalable

Placement Heuristic for DNA Probe Arrays”, Proc. Intl. Conf. on Research in Computational

Molecular Biology, April 2003, pp. 148-156.

158. S. V. Babin, A. B. Kahng, I. I. Mandoiu, and S. Muddu, “Resist Heating Dependence on Subfield

Scheduling in 50kV Electron Beam Maskmaking”, Photomask and Next-Generation Lithography

Mask Technology X, Proc. SPIE #5130, April 2003, pp. 718-726.


159. Y. Chen, P. Gupta and A. B. Kahng, “Performance-Impact Limited Area Fill Synthesis”, Proc.

ACM/IEEE Design Automation Conf., June 2003, pp. 22-27.

160. P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, “A Cost-Driven Lithographic Correction

Methodology Based on Off-the-Shelf Sizing Tools”, Proc. ACM/IEEE Design Automation Conf.,

June 2003, pp. 16-21.

161. H. Chen, C.-K. Cheng, N.-C. Chou, A. B. Kahng, J. F. MacDonald, P. Suaris, B. Yao and Z. Zhu,

“An Algebraic Multigrid Solver for Analytical Placement with Layout Based Clustering”, Proc.

ACM/IEEE Design Automation Conf., June 2003, pp. 794-799.

162. A. B. Kahng, I. I. Mandoiu, S. Reda, X. Xu, and A. Zelikovsky, “Design Flow Enhancements for

DNA Arrays”, Proc. IEEE Intl. Conf. on Computer Design, October 2003, pp. 116-123.

163. P. Gupta, A. B. Kahng, I. I. Mandoiu, and P. Sharma, “Layout-Aware Scan Chain Synthesis for

Improved Path Delay Fault Coverage”, Proc. IEEE/ACM Intl. Conference on Computer-Aided

Design, November 2003, pp. 754-759.

164. A. B. Kahng, I. I. Mandoiu, S. Reda, X. Xu, and A. Zelikovsky, “Evaluation of Placement

Techniques for DNA Probe Array Layout”, Proc. IEEE/ACM Intl. Conference on Computer-

Aided Design, November 2003, pp. 262-269.

165. H. Chen, C. K. Cheng, A. B. Kahng, I. I. Mandoiu, Q. Wang, and B. Yao, “The Y-Architecture

for On-Chip Interconnect: Analysis and Methodology”, Proc. IEEE/ACM Intl. Conference on

Computer-Aided Design, November 2003, pp. 13-19.

166. P. Gupta and A. B. Kahng, “Manufacturing-Aware Physical Design”, Proc. IEEE/ACM Intl.

Conference on Computer-Aided Design, November 2003, (embedded tutorial) pp. 681-687.

167. P. Gupta and A. B. Kahng, “Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive

Coupling”, Proc. IEEE Intl. Conf. on VLSI Design , Jan 2004, pp. 431-436.

168. H. Chen, C. K. Cheng, A. B. Kahng, M. Mori and Q. Wang, “Optimal Planning for Mesh-Based

Power Distribution”, Proc. Asia and South Pacific Design Automation Conf., Jan. 2004, pp. 444-

449.

169. A. B. Kahng and S. Reda, “Combinatorial Group Testing Methods for the BIST Diagnosis

Problem”, Proc. Asia and South Pacific Design Automation Conf., Jan. 2004, pp. 113-116.

170. P. Gupta, A.B. Kahng, Y. Kim, and D. Sylvester, “Investigation of Performance Metrics for

Interconnect Stack Architectures”, Proc. ACM International Workshop on System-Level

Interconnect Prediction, Feb. 2004, pp. 23-29.

171. A. B. Kahng, I. Markov and S. Reda, “Boosting: Min-Cut Placement with Improved Signal

Delay”, Proc. Design Automation and Testing in Europe, Feb. 2004, pp. 1098-1103.

172. A. B. Kahng, I. I. Mandoiu, Q. Wang, X. Xu, and A. Zelikovsky, “MultiProject Reticle

Floorplanning and Wafer Dicing”, Proc. ACM/IEEE Intl. Symp. on Physical Design, April 2004,

pp. 70-77.

173. A. B. Kahng, and Q. Wang, “Implementation and Extensibility of an Analytic Placer”, Proc.

ACM/IEEE Intl. Symp. on Physical Design, April 2004, pp. 18-25.

174. A. B. Kahng, I. L. Markov and S. Reda, “On Legalization of Row-Based Placements”, Proc.

ACM/IEEE GLSVLSI, April 2004, pp. 214-219.

175. A. B. Kahng and S. Reda, “Placement Feedback: A Concept and Method for Better Min-Cut

Placements”, Proc. ACM/IEEE Design Automation Conf., June 2004, pp.357-362.

176. P. Gupta, A. B. Kahng, P. Sharma and D. Sylvester, “Selective Gate-Length Biasing for Cost-

Effective Runtime Leakage Control”, Proc. ACM/IEEE Design Automation Conf., June 2004, pp.

327-330.

177. D. A. Antonelli, T. J. Dysart, D. Z. Chen, X. S. Hu, A. B. Kahng, P. M. Kogge and R. C. Murphy,

“Quantum-Dot Cellular Automata (QCA) Circuit Partitioning: Problem Modeling and Solutions”,

Proc. ACM/IEEE Design Automation Conf., June 2004, pp. 363-368.

178. L. Capodieci, P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, “Toward a Methodology for

Manufacturability Driven Design Rule Exploration”, Proc. ACM/IEEE Design Automation Conf.,

June 2004, pp. 311-316.


179. A. B. Kahng, X. Xu and A. Zelikovsky, “Yield- and Cost-Driven Fracturing for Variable Shaped-

Beam Mask Writing”, Proc. 24th BACUS Symposium on Photomask Technology and

Management, September 2004, pp. 360-371.

180. P. Gupta, A. B. Kahng, C.-H. Park, P. Sharma, D. Sylvester and J. Yang, “Joining the Design and

Mask Flows for Better and Cheaper Masks”, Proc. 24th BACUS Symposium on Photomask

Technology and Management, 5567, 318 (2004).

181. L. He, A. B. Kahng, K. H. Tam and J. Xiong, “Variability-Driven Considerations in the Design of

Integrated-Circuit Global Interconnects”, Proc. 21st Intl. VLSI Multilevel Interconnection

(VMIC) Conf., September 2004, pp. 214-221.

182. A. B. Kahng, and S. Reda, “Reticle Floorplanning With Guaranteed Yield for Multi-Project

Wafers”, Proc. ACM/IEEE Intl. Conf. on Computer Design, October 2004, pp. 106-110.

183. A. B. Kahng, and Q. Wang, “An Analytic Placer for Mixed-Size Placement and Timing-Driven

Placement”, Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2004, pp. 565-

572.

184. Y. Chen, A. B. Kahng, G. Robins, A. Zelikovsky, and Y. Zheng, “Evaluation of the New OASIS

Format for Layout Fill Compression”, Proc. 11th IEEE Intl. Conf. on Electronics, Circuits and

Systems, December 2004, pp. 377-382.

185. P. Gupta, A. B. Kahng and C.-H. Park, “Detailed Placement for Improved Depth of Focus and

CD Control”, Proc. Asia and South Pacific Design Automation Conf., Jan. 2005, pp. 343-348.

186. P. Gupta, A. B. Kahng and C.-H. Park, “Manufacturing-Aware Design Methodology for Assist

Feature Correctness”, Proc. SPIE Conf. on Design and Process Integration for Microelectronic

Manufacturing, Feb. 2005, pp. 131-140.

187. C. Chiang, A. B. Kahng, S. Sinha, X. Xu, and A. Zelikovsky, “Bright-field AAPSM Conflict

Detection and Correction”, Proc. Design Automation and Testing in Europe, March 2005, pp.

908-913.

188. P. Gupta, A. B. Kahng and P. Sharma, “A Practical Transistor-Level Threshold Voltage

Assignment Methodology”, Proc. IEEE International Symposium on Quality Electronic Design,

March 2005, pp. 261-265.

189. P. Gupta, A.B. Kahng, D. Sylvester and J. Yang, “Performance-Driven OPC for Mask Cost

Reduction”, Proc. IEEE International Symposium on Quality Electronic Design, March 2005, pp.

270-275.

190. L. He, A. B. Kahng, K. Tam and J. Xiong, “Design of Integrated-Circuit Interconnects with

Accurate Modeling of Chemical-Mechanical Planarization”, Proc. International Society for

Optical Engineering (SPIE) Symposium on Microlithography, 5756, 109 (2005).

191. A. B. Kahng and S. Reda, “Evaluation of Placer Suboptimality via Zero-Change

Transformations”, Proc. International Symposium on Physical Design, April 2005, pp 208-215.

192. C. Alpert, A. B. Kahng, G-J. Nam, S. Reda and P. Villarubia, “A Semi-Persistent Clustering

Technique for VLSI Circuit Placement”, Proc. International Symposium on Physical Design,

April 2005, pp. 200-207.

193. L. He, A. B. Kahng, K. Tam and J. Xiong, “Simultaneous Buffer Insertion and Wire Sizing

Considering Systematic CMP Variation and Random Leff Variation”, Proc. International

Symposium on Physical Design, April 2005, pp. 78-85.

194. A. B. Kahng, S. Reda and Q. Wang, “APlace: A General Analytic Placement Framework”, Proc.

International Symposium on Physical Design, April 2005, pp. 233-235.

195. P. Gupta, A. B. Kahng, C.-H. Park, Kambiz Samadi and Xu Xu, “Wafer Topography-Aware

Optical Proximity Correction for Better DOF Margin and CD Control”, Proc. Photomask and

Next-Generation Lithography Mask Technology X, April 2005, pp. 844-854.

196. P. Gupta, A. B. Kahng and C.-H. Park, “Improving OPC Quality Via Interactions Within the

Design-to-Manufacturing Flow”, Proc. Photomask and Next-Generation Lithography Mask

Technology X, April 2005, pp. 131-140.


197. Y.-S. Cheon, P.-H. Ho, A. B. Kahng, S. Reda and Q. Wang, “Power-Aware Placement”, Proc.

Design Automation Conference, June 2005, pp. 795-800.

198. P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, “Self-Compensating Design for Focus

Variation”, Proc. Design Automation Conference, June 2005, pp. 365-368.

199. A. B. Kahng, S. Muddu and P. Sharma, “Defocus-Aware Leakage Estimation and Control”, Proc.

International Symposium on Low Power Electronics and Design, August 2005, pp. 263-268.

200. P. Gupta, A. B. Kahng and C.-H. Park, “Enhanced Resist and Etch CD Control by Design

Perturbation”, Proc. 25th BACUS Symposium on Photomask Technology and Management, 5992,

59923P (2005).

201. P. Gupta, A. B. Kahng, S. Muddu, S. Nakagawa and C.-H. Park, “Modeling OPC Complexity for

Design for Manufacturability”, Proc. 25th BACUS Symposium on Photomask Technology and

Management, 5992, 59921W (2005).

202. A. B. Kahng, I. I. Mandoiu, X. Xu, and A. Zelikovsky, “Yield-Driven Multi-Project Reticle

Design and Wafer Dicing”, Proc. 25th BACUS Symposium on Photomask Technology and

Management, 5992, 599249 (2005). (1st place in Best Poster Awards and Best Paper Award)

(also appears in BACUS News March 2006, 22(3), pp. 1-10.)

203. A. B. Kahng, B. Liu and Q. Wang, “Supply Voltage Degradation Aware Analytical Placement”,

Proc. ACM/IEEE Intl. Conf. on Computer Design, October 2005, pp. 437-443. (Best Paper

Award; 5 awards out of 310 submissions)

204. P. Gupta, A. B. Kahng, O.S. Nakagawa and K. Samadi, “Closing the Loop in Interconnect

Analyses and Optimization: CMP Fill, Lithography and Timing”, Proc. 22nd Intl. VLSI/ULSI

Multilevel Interconnection (VMIC) Conf., October 2005, pp. 352-363.

205. A. B. Kahng and S. Reda, “Intrinsic Shortest Path Length: A New, Accurate A Priori Wirelength

Estimator”, Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2005, pp. 173-

180.

206. C. Chiang, A. B. Kahng, S. Sinha and X. Xu, “Fast and Efficient Phase Conflict Detection and

Correction in Standard-Cell Layouts”, Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design,

November 2005, pp. 149-156.

207. A. B. Kahng, S. Reda and Q. Wang, “Architecture and Details of a High Quality, Large-Scale

Analytical Placer”, Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2005, pp.

891-898. (Nominated for Best Paper Award)

208. P. Gupta and A.B. Kahng, “Efficient Design and Analysis of Robust Power Distribution Meshes”,

Proc. International Conference on VLSI Design, Jan. 2006, pp. 337-342.

209. A. B. Kahng, I. I. Mandoiu, X. Xu and A. Zelikovsky, “Multi-Project Reticle Design and Wafer

Dicing under Uncertain Demand”, Proc. European Mask and Lithography Conference, 6281,

628104 (2006). (Invited Paper)

210. P. Gupta, A. B. Kahng and P. Sharma, “Lithography Simulation-Based Full-chip Design

Analyses”, Proc. SPIE Conference on Design and Process Integration for Microelectronic

Manufacturing, 6156, 61560T (2006).

211. A. B. Kahng and R. O. Topaloglu, “Generation of Design Guarantees for Interconnect Matching”,

Proc. ACM International Workshop on System-Level Interconnect Prediction, March 2006, pp.

29-34.

212. A. B. Kahng and S. Reda, “A Tale of Two Nets: Studies of Wirelength Progression in Physical

Design”, Proc. ACM International Workshop on System-Level Interconnect Prediction, March

2006, pp. 17-24.

213. A. B. Kahng, B. Liu and X. Xu, “Statistical Crosstalk Aggressor Alignment Aware Interconnect

Delay Calculation”, Proc. ACM International Workshop on System-Level Interconnect Prediction,

March 2006, pp. 91-97.

214. A. B. Kahng, C.-H. Park, P. Sharma and Q. Wang, “Lens Aberration-Aware Timing-Driven

Placement”, Proc. Design Automation and Testing in Europe, March 2006, pp. 890-895.


215. A. B. Kahng, K. Samadi and P. Sharma, “Study of Floating Fill Impact on Interconnect

Capacitance”, Proc. International Symposium on Quality Electronic Design, April 2006, pp. 691-

696.

216. A. B. Kahng, B. Liu and X. Xu, “Constructing Current-Based Gate Models Based on Existing

Timing Library”, Proc. International Symposium on Quality Electronic Design, April 2006, pp.

37-42.

217. A. B. Kahng, B. Liu and S. Tan, “SMM: Scalable Analysis of Power Delivery Networks by

Stochastic Moment Matching”, Proc. International Symposium on Quality Electronic Design,

April 2006, pp. 638-643.

218. A. B. Kahng, S. Muddu and P. Sharma, “Impact of Gate-Length Biasing on Threshold-Voltage

Selection”, Proc. International Symposium on Quality Electronic Design, April 2006, pp. 747-

754.

219. A. B. Kahng, B. Liu and S. Tan, “Efficient Decoupling Capacitor Planning via Convex

Programming Methods”, Proc. ACM/IEEE Intl. Symp. on Physical Design, April 2006, pp. 102-

107.

220. A. B. Kahng and Q. Wang, “A Faster Implementation of APlace”, Proc. ACM/IEEE Intl. Symp.

Physical Design, 2006, pp. 218-220.

221. A. B. Kahng, X. Xu and A. Zelikovsky, “Fast Yield-Driven Fracture for Variable Shaped-Beam

Mask Writing”, Photomask and Next-Generation Lithography Mask Technology XI, Proc. SPIE

6283, 62832R, April 2006.

222. A. B. Kahng, B. Liu and X. Xu, “Statistical Gate Delay Calculation with Crosstalk Alignment

Consideration”, Proc. ACM/IEEE GLSVLSI, April 2006, pp. 223-228.

223. C. J. Alpert, A. B. Kahng, C. N. Sze and Q. Wang, “Timing-Driven Steiner Trees are (Practically)

Free”, Proc. ACM/IEEE Design Automation Conference, July 2006, pp. 389-392.

224. A. B. Kahng and C.-H. Park, “Auxiliary Pattern for Cell-Based OPC”, Proc. 27th BACUS

Symposium on Photomask Technology and Management, 6349, 63494S (2006).

225. A. B. Kahng, C.-H. Park and X. Xu, “Fast Dual-Graph Based Hot-Spot Detection”, Proc. 27th

BACUS Symposium on Photomask Technology and Management, 6281, 628104 (2006).

226. A. B. Kahng and X. Xu, “A General Framework for Multi-Flow, Multi-Layer, Multi-Project

Reticles Design”, Proc. 27th BACUS Symposium on Photomask Technology and Management,

6349, 63494A (2006).

227. A. Balasinski, A. B. Kahng, W. Sachs-Baker and X. Xu, “A Procedure and Program to Calculate

Shuttle Mask Advantage”, Proc. 27th BACUS Symposium on Photomask Technology and

Management, September 2006.

228. A. B. Kahng and R. O. Topaloglu, “Interconnect Matching Design Rule Inferring and

Optimization through Correlation Extraction”, Proc. International Conference of Computer

Design, October 2006.

229. A. B. Kahng, P. Sharma, and A. Zelikovsky, “Fill for Shallow Trench Isolation CMP”, Proc.

ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006.

230. J. Hu, A. B. Kahng, B. Liu, G. Venkataraman and X. Xu, “A Global Minimum Clock

Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield”, Proc. ASP-

DAC, January 2007, pp. 24-31.

231. A. B. Kahng and R. O. Topaloglu, “A DOE Set for Normalization-Based Extraction of Fill

Impact on Capacitances”, Proc. International Symposium on Quality Electronic Design, March

2007, pp. 467-474. (Best Paper Award)

232. A. B. Kahng, S. Reda and P. Sharma, “On-Line Adjustable Buffering for Runtime Power

Reduction”, Proc. International Symposium on Quality Electronic Design, March 2007, pp. 550-

555.

233. A. B. Kahng, S. Muddu and P. Sharma, “Detailed Placement for Leakage Reduction using

Systematic Through-Pitch Variation”, Proc. International Symposium on Low Power Electronics

and Design, 2007, pp. 110-115.


234. A. B. Kahng, “Key Directions and a Roadmap for Electrical Design for Manufacturability”,

invited paper, Proc. European Solid-State Circuits Conf., 2007.

235. A. B. Kahng and R. O. Topaloglu, “Performance-Aware CMP Fill Pattern Optimization”, invited

paper, Proc. Intl. VLSI/ULSI Multilevel Interconnection (VMIC) Conf., 2007, pp. 135-144.

236. A. B. Kahng, S-.M Kang, W. Li and B. Liu, “Analytical Thermal Placement for VLSI Lifetime

Improvement and Minimum Performance Variation”, Proc. International Conference of

Computer Design, 2007, pp. 71-77.

237. A. B. Kahng, “Opportunities in Future Physical Implementation and Manufacturing Handoff

Flows”, invited paper, Proc. International SoC Design Conf., 2007, pp. 46-50.

238. A. B. Kahng, P. Sharma and R. O. Topaloglu, “Exploiting STI Stress for Performance”, Proc.

ACM/IEEE Intl. Conf. on Computer-Aided Design, 2007, pp. 83-90.

239. P. Gupta, A. B. Kahng, Y. Kim, S. Shah, D. Sylvester, “Investigation of Diffusion Rounding for

Post-Lithography Analysis”, Proc. Asia and South Pacific Design Automation Conf., 2008, pp.

480-485.

240. L. Carloni, A. B. Kahng, S. Muddu, A. Pinto, K. Samadi and P. Sharma, “Interconnect Modeling

for Improved System-Level Design Optimization”, Proc. Asia and South Pacific Design

Automation Conf., 2008, pp. 258-264.

241. K. Jeong, A. B. Kahng and K. Samadi, “Quantified Impacts of Guardband Reduction on Design

Process Outcomes”, Proc. International Symposium on Quality Electronic Design, 2008, pp. 790-

897.

242. P. Gupta, K. Jeong, A. B. Kahng and C. -H. Park, “Electrical Metrics for Lithographic Line-End

Tapering”, Proc. Photomask and Next-Generation Lithography Mask Technology, 2008, pp.

70238A-1 - 70238A-12.

243. A. B. Kahng and S. Muddu, “Predictive Modeling of Lithography-Induced Linewidth Variation”,

Proc. Photomask and Next-Generation Lithography Mask Technology, 2008, pp. 70280M-1 -

70280M-14

244. K. Jeong, A. B. Kahng, C. -H. Park and H. Yao, “Dose Map and Placement Co-Optimization for

Timing Yield Enhancement and Leakage Power Reduction”, Proc. ACM/IEEE Design

Automation Conference, 2008, pp. 516-521.

245. P. Gupta and A. B. Kahng, “Bounded Lifetime Integrated Circuits”, Proc. ACM/IEEE Design

Automation Conference, 2008, pp. 347-348.

246. R. J. Greenway, K. Jeong, A. B. Kahng, C.-H. Park and J. S. Petersen, “32nm 1-D Regular Pitch

SRAM Bitcell Design for Interference-Assisted Lithography”, Proc. SPIE BACUS Symposium on

Photomask Technology and Management, 2008, vol. 7122, p. 71221L.

247. A. B. Kahng, C.-H. Park, X. Xu and H. Yao, “Double Patterning Lithography Aware Intelligent

Layout Decomposition”, Proc. SPIE BACUS Symposium on Photomask Technology and

Management, 2008, vol. 7122, p. 712221

248. A. B. Kahng, “Lithography and Design in Partnership: A New Roadmap”, Proc. SPIE BACUS

Symposium on Photomask Technology and Management, 2008 vol. 7122, p. 712202.

249. A. B. Kahng, K. Samadi and R. O. Topaloglu, “Recent Topics in CMP-Related IC Design for

Manufacturing”, Proc. Materials Research Society (Advanced Metallization Conference), 2008.

250. A. B. Kahng, C.-H. Park, X. Xu and H. Yao, “Layout Decomposition for Double Patterning

Lithography”, Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, 2008, pp. 465-472.

Nominated for Best Paper Award.

251. K. Jeong, A. B. Kahng and H. Yao, “On Modeling and Sensitivity of Via Count in SOC Physical

Implementation”, Proc. International SoC Conf., 2008, pp. 125-128.

252. A. B. Kahng and K. Samadi, “Communication Modeling for System-Level Design”, Proc.

International SoC Conf., 2008, pp. 138-143.

253. K. Jeong and A. B. Kahng, “Timing Analysis and Optimization Implications of Bimodal CD

Distribution in Double Patterning Lithography”, Proc. Asia and South Pacific Design Automation

Conf., 2009, pp. 486-491.


254. R. T. Greenway, R. Hendel, K. Jeong, A. B. Kahng, S. Mackay, J. S. Petersen, Z. Rao and M.

Smayling, “Interference Assisted Lithography for Patterning of 1D Gridded Design”, Proc. SPIE

Symposium on Advanced Lithography, 2009 7271, 72712U.

255. K. Jeong, A. B. Kahng and H. Yao, “Revisiting the Linear Programming Framework for Leakage

Power vs. Performance Optimization”, Proc. International Symposium on Quality Electronic

Design, 2009, pp. 127-134.

256. A. B. Kahng, B. Li, L.-S. Peh and K. Samadi, “ORION 2.0: A Fast and Accurate NoC Power and

Area Model for Early-Stage Design Space Exploration”, Proc. Design, Automation and Test in

Europe, 2009, pp. 423-428.

257. K. Jeong, A. B. Kahng and R. O. Topaloglu, “Is Overlay Error More Important Than Interconnect

Variations in Double Patterning?”, Proc. ACM International Workshop on System-Level

Interconnect Prediction, 2009, pp. 3-10.

258. A. Coskun, A. B. Kahng and T. S. Rosing, “Temperature- and Cost-Aware Design of 3D

Multiprocessor Architectures”, Proc. Euromicro DSD, 2009, pp. 183-190.

259. M. Gupta, K. Jeong and A. B. Kahng, “Timing Yield-Aware Color Reassignment and Detailed

Placement Perturbation for Double Patterning Lithography”, Proc. ACM/IEEE Intl. Conf. on

Computer-Aided Design, 2009, pp. 607-614.

260. K. Jeong and A. B. Kahng, “A Power-Constrained MPU Roadmap for the International

Technology Roadmap for Semiconductors (ITRS)”, Proc. International SoC Design Conf., 2009,

pp. 49-52. (Invited Paper).

261. K. Jeong, A. B. Kahng and K. Samadi, “Architectural-Level Prediction of Interconnect

Wirelength and Fanout”, Proc. International SoC Design Conf., 2009, pp. 53-56. (Invited Paper).

262. A. B. Kahng, S. Kang, R. Kumar and J. Sartori, “Slack Redistribution for Graceful Degradation

Under Voltage Overscaling”, Proc. Asia and South Pacific Design Automation Conf., 2010, pp.

825-831.

263. A. B. Kahng, B. Lin and K. Samadi, “Improved On-Chip Router Analytical Power and Area

Modeling”, Proc. Asia and South Pacific Design Automation Conf., 2010, pp. 241-246.

264. A. B. Kahng, S. Kang, R. Kumar and J. Sartori, “Designing a Processor From the Ground Up to

Allow Voltage/Reliability Tradeoffs”, Proc. International Symposium on High-Performance

Computer Architecture, 2010, pp. 119-129.

265. K. Jeong, A. B. Kahng and R. O. Topaloglu, “Assessing Chip-Level Impact of Double-Patterning

Lithography”, Proc. International Symposium on Quality Electronic Design, 2010, pp. 122-130.

266. K. Jeong and A. B. Kahng, “Methodology From Chaos in IC Implementation”, Proc.

International Symposium on Quality Electronic Design, 2010, pp. 885-892.

267. K. Jeong, A. B. Kahng and S. Kang, “Toward Effective Utilization of Timing Exceptions in

Design Optimization”, Proc. International Symposium on Quality Electronic Design, 2010, pp.

54-61.

268. C.-K. Cheng, A. B. Kahng, K. Samadi and A. Shayan, “Worst-Case Performance Prediction

Under Supply Voltage and Temperature Variation”, Proc. ACM System-Level Interconnect

Prediction Workshop, 2010, pp. 91-96.

269. A. B. Kahng, S. Kang, R. Kumar and J. Sartori, “Recovery-Driven Design: A Power

Minimization Methodology for Error-Tolerant Processor Modules”, Proc. ACM/IEEE Design

Automation Conference, 2010, pp. 825-830.

270. P. Gupta, A. B. Kahng, A. Kasibhatla and P. Sharma, “Eyecharts: Constructive Benchmarking of

Gate Sizing Heuristics”, Proc. ACM/IEEE Design Automation Conference, 2010, pp. 597-602.

271. A. B. Kahng, B. Lin, K. Samadi and R. S Ramanujam, “Trace-Driven Optimization of Networkson-Chip

Configurations”, Proc. ACM/IEEE Design Automation Conference, 2010, pp. 437-442.

272. A. B. Kahng, B. Lin, K. Samadi and R. S Ramanujam, “Efficient Trace-Driven Metaheuristics for

Optimization of Networks-on-Chip Configurations”, Proc. IEEE/ACM International Conference

on Computer-Aided Design, 2010, pp. 253-263.


273. K. Jeong, A. B. Kahng and C. J. Progler, "New Yield-Aware Mask Strategies", Proc. Photomask

and Next-Generation Lithography Mask Technology, 2011, pp. 80810P-1--80810P-12.

274. C.-K. Cheng, P. Du, A. B. Kahng, G. K. H. Pang, Y. Wang and N. Wong, “More Realistic Power

Grid Verification Based on Hierarchical Current and Power Constraints”, Proc. ACM Symp. on

Physical Design, 2011, pp. 159-166.

275. K. Jeong and A. B. Kahng, “Toward PDN Resource Estimation: A Law of Power Density”, Proc.

System-Level Interconnect Prediction, 2011, pp. 4.1.1-4.1.6.

276. S. K. Han, K. Jeong, A. B. Kahng and J. Lu, “Stability and Scalability in Global Routing”, Proc.

System-Level Interconnect Prediction, 2011, pp. 3.3.1-3.3.6.

277. A. B. Kahng and V. Srinivas, “Mobile System Considerations for SDRAM Interface

Trends”, Proc. System-Level Interconnect Prediction, 2011, 2.3.1-2.3.8.

278. T.-B. Chan, K. Jeong and A. B. Kahng, “Performance and Variability Driven Guidelines for

BEOL Layout Decomposition with LELE Double Patterning”, Proc. SPIE BACUS Symposium on

Photomask Technology, 2011, 8166, pp. 81663O-1–81663O-12.

279. A. B. Kahng, S. Kang, T. S. Rosing and R. Strong, “MAPG: Memory Access Power

Gating”, Proc. Design, Automation and Test in Europe, 2012, pp. 1054-1059.

280. T. B. Chan, P. Gupta, A. B. Kahng and L. Lai, “DDRO: A Novel Performance Monitoring

Methodology Based on Design-Dependent Ring Oscillators”, Proc. Intl. Symposium on Quality

Electronic Design, 2012, pp. 633-640.

281. T. B. Chan and A. B. Kahng, “Improved Path Clustering for Adaptive Path-Delay Testing”, Proc.

Intl. Symposium on Quality Electronic Design, 2012, pp. 13-20.

282. C. K. Cheng, P. Du, A. B. Kahng and S. Weng, “Low-Power Gated Bus Synthesis for 3D IC via

Rectilinear Shortest-Path Steiner Graph”, Proc. ACM/IEEE Intl. Symp. Physical Design, 2012,

pp. 105-112.

283. A. B. Kahng and S. Kang, “Construction of Realistic Gate Sizing Benchmarks With Known

Optimal Solutions”, Proc. ACM/IEEE Intl. Symp. Physical Design, 2012, pp. 153-160.

284. A. B. Kahng, B. Lin and S. Nath, “Explicit Modeling of Control and Data for Improved NoC

Router Estimation”, Proc. ACM/IEEE Design Automation Conference, 2012, pp. 392-397

(nominated for Best Paper Award; 7 nominees out of 744 submissions).

285. A. B. Kahng and S. Kang, “Accuracy-Configurable Adder for Approximate Arithmetic

Designs”, Proc. ACM/IEEE Design Automation Conference, 2012, pp. 820-825.

286. A. B. Kahng, S. Kang, T. S. Rosing and R. Strong, “TAP - Token-Based Adaptive Power

Gating”, Proc. International Symposium on Low Power Electronics and Design, 2012, pp. 203-

208.

287. J. Hu, A. B. Kahng, S. Kang, M. Kim and I. Markov, “Sensitivity-guided Metaheuristics for

Accurate Discrete Gate Sizing”, Proc. IEEE/ACM International Conference on Computer-Aided

Design, 2012, pp. 233-239.

288. T.-B. Chan and A. B. Kahng, “Tunable Sensors for Process-Aware Voltage Scaling”, Proc.

IEEE/ACM International Conference on Computer-Aided Design, 2012, pp. 7-14.

289. N. P. Jouppi, A. B. Kahng, N. Muralimanohar and V. Srinivas, “CACTI-DO: CACTI with Offchip

Power-Area-Timing Models”, Proc. IEEE/ACM International Conference on Computer-

Aided Design, 2012, pp. 294-301.

290. T.-B. Chan, A. B. Kahng, J. Li and S. Nath, “Optimization of Overdrive Signoff”, Proc. Asia and

South Pacific Design Automation Conf., 2013, pp. 344-349.

291. A. B. Kahng, S. Nath and T. S. Rosing, “On Potential Design Impacts of Electromigration

Awareness”, Proc. Asia and South Pacific Design Automation Conf., 2013, pp. 527-532.

292. T.-B. Chan and A. B. Kahng, “Post-Routing Back-End-of-Line Layout Optimization for

Improved Time-Dependent Dielectric Breakdown Reliability”, Proc. SPIE Symposium on

Advanced Lithography, 2013, 2013 8684, 86840L.

293. T.-B. Chan, W.-T. J. Chan and A. B. Kahng, “Impact of Adaptive Voltage Scaling on Aging-

Aware Signoff”, Proc. Design Automation and Test in Europe, 2013, pp. 1683-1688.


294. A. B. Kahng, S. Kang and B. Park, “Active-Mode Leakage Reduction with Data-Retained Power

Gating”, Proc. Design Automation and Test in Europe, 2013, pp. 1209-1214.

295. A. B. Kahng, B. Lin and S. Nath, “Enhanced Metamodeling Techniques for High-Dimensional IC

Design Estimation Problems”, Proc. Design Automation and Test in Europe, 2013, pp. 1861-

1866.

296. T.-B. Chan, A. B. Kahng and J. Li, “Reliability-Constrained Die Stacking Order in 3DICs Under

Manufacturing Variability”, Proc. Intl. Symp. on Quality Electronic Design, 2013, pp. 16-23.

297. T.-B. Chan, A. B. Kahng and J. Li, “Toward Quantifying the IC Design Value of Interconnect

Technology Improvements”, Proc. IEEE System-Level Interconnect Prediction, 2013.

298. A. B. Kahng, S. Kang, H. Lee, S. Nath and J. Wadhwani, “Learning-Based Approximation of

Interconnect Delay and Slew in Signoff Timing Tools”, Proc. IEEE System-Level Interconnect

Prediction, 2013.

299. A. B. Kahng, B. Lin and S. Nath, “High-Dimensional Metamodeling for Prediction of Clock Tree

Synthesis Outcomes”, Proc. IEEE System-Level Interconnect Prediction, 2013.

300. A. B. Kahng, S. Kang and H. Lee, “Smart Non-Default Routing for Clock Power

Reduction”, Proc. ACM/IEEE Design Automation Conference, 2013.

301. A. B. Kahng, “The ITRS Design Technology and System Drivers Roadmap: Process and

Status”, Proc. ACM/IEEE Design Automation Conference, 2013. (Invited Paper)

302. W.-T. J. Chan, A. B. Kahng, S. Kang, R. Kumar and J. Sartori, “Statistical Analysis and

Modeling for Error Composition in Approximate Computation Circuits”, Proc. IEEE Intl. Conf.

on Computer Design, 2013, to appear.

303. A. B. Kahng, S. Kang, H. Lee, I. L. Markov and P. Thapar, “High-Performance Gate Sizing with

a Signoff Timer”, Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, 2013, to appear.

304. A. B. Kahng, I. Kang and S. Nath, “Incremental Multiple-Scan Chain Ordering for ECO Flip-

Flop Insertion”, Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, 2013, to appear.

305. A. B. Kahng, “Lithography-Induced Limits to Scaling of Design Quality”, Proc. Design-Process-

Technology Co-optimization for Manufacturability VIII (SPIE Microlithography Symposium),

2014, to appear. (Invited Paper)

306. A. B. Kahng and I. Kang, “Co-Optimization of Memory BIST Grouping, Test Scheduling, and

Logic Placement”, Proc. Design Automation and Test in Europe, 2014, to appear.

307. S. S. Han, A. B. Kahng, S. Nath and A. Vidyanathan, “A Deep Learning Methodology to

Proliferate Golden Signoff Timing”, Proc. Design Automation and Test in Europe, 2014, to

appear.

308. G. Jerke and A. B. Kahng, “Mission Profile Aware IC Design – A Case Study”, Proc. Design

Automation and Test in Europe, 2014, to appear.

Reports

Over 90 technical reports issued at UCSD (10), UCLA (80) and the University of Virginia (4).

Three additional reports were submitted to ARO in October 1990, November 1991, and

November 1992; the first was named as one of eight outstanding reports out of 120 submitted by

faculty researchers sponsored in summer 1990 by ARO.

Selected Presentations

Full-Day Tutorial Organizer/Presenter: ACM/IEEE Design Automation Conference 1994, 1999,

2002, 2005 and 2006; IEEE ICCAD 1999, 2000 and 2005; IEEE ASIC 1998; IEEE ISQED 2000;

IEEE/ACM Asia South Pacific Design Automation Conference 2004, 2006 and 2007; Design

Automation and Test Europe 2006.


“On Structure and Scaling in Optimization”, May 17, 1991, Jacob Marschak Interdisciplinary

Colloquium on Mathematics in the Social Sciences”, abstract published in Mathematical Social

Sciences 22 (1991), pp. 182-183.

“On Circuit Partitioning and the Intrinsic Rent Parameter”, April 13, 1992, VLSI Colloquium, UC

Berkeley EECS Department.

“On Cost Surfaces and Stochastic Hill-Climbing Variants”, invited talk, April 29, 1992, ORSA

Annual Meeting, Orlando.

“New Directions in Practical Large-Scale Optimization”, May 3, 1993, VLSI Colloquium, UC

Berkeley EECS Department; June 22, 1993, UC Santa Cruz Computer Engineering Department

Colloquium. Also: Colloquium talks at UCSD Computer Science and Engineering Dept. (April

1994), UCLA Computer Science Dept. (May 1994), UCSB ECE Dept. (October 1994),

Northwestern Univ. EECS Dept. (April 1995), etc.

“Parallel Dynamic Adaptive Search Algorithms”, July 9, 1993, Mathematical Programming

Society Symposium on Parallel Optimization, Madison WI.

“New Ideas in Finite-Time Global Optimization”, invited talk, Dagstuhl-Seminar on

Combinatorial Methods for Integrated Circuit Design, October 22-28, 1993, Schloss Dagstuhl,

Germany.

“Non-Monotone Strategies in Hill-Climbing Optimization”, invited talk, November 2, 1993,

ORSA/TIMS National Meeting, Phoenix.

“Collective Action for Autonomous Robots”, invited talk, May 9, 1995, U.S. Army Sensor

Technology and Engineering Colloquium Series, Washington DC.

“Roadmaps Toward a Science of VLSI Design”, invited plenary talk, May 13, 1996, VLSI CAD

Track, IEEE Intl. Symposium on Circuits and Systems, Atlanta, May 1996. Also: Colloquium

talk at University of Virginia Computer Science Dept. (December 1996).

“Futures and Core Algorithm Technologies for Physical Design”, Distinguished Lecture Series,

June 19, 1997, Cadence Design Systems, Inc, San Jose CA. Also: Colloquium talks at IBM

Austin Research Laboratory (May 1997), University of Toronto EECG Dept. (June 1997),

University of Waterloo Computer Science Dept. (June 1997), NASA Ames Research Center (July

1997), etc.

“Futures for DSM Physical Implementation: Where is the Value, and Who Will Pay?”, keynote

address, July 12, 2000, 12th Japan DA Show, Tokyo.

“Design Technology Productivity in the DSM Era”, invited talk, February 2, 2001, Asia South-

Pacific Design Automation Conference, Yokohama.

“Design and Design Automation Advances in the 2001 ITRS”, MEDEA+ 2002 Opening Session

address, October 23, 2002.

“Scope and Goals of Future Design-Through-Mask Integrations”, invited talk, Advanced Reticle

Symposium, June 24, 2003.

“A Roadmap for Design and Design for Manufacturing”, invited talk, International SEMATECH

Yield Council, September 25, 2003.

“The Design-Manufacturing Roadmap”, keynote address, EDA Forum, Stuttgart, November 6,

2003.

CAD Research, Pay Now or Pay Later...”, panel presentation, ICCAD Monday Evening Panel,

November 6, 2006.

“New Technologies and Integrations at the Design-Manufacturing Interface", invited talk,

Applied Materials, Feb. 12, 2007.

“Communicating Variation to Designers”, invited presentation (and, panelist in subsequent panel

discussion), TAU Workshop, Austin, February 26, 2007.

“Do Digital Design and Variability Mix Like Oil and Water?”, panel presentation, ISQED, March

27, 2007.


“A Technology Roadmap for DFM”, invited presentation, Electronic Design Processes Workshop,

April 12, 2007.

“Moving Along the ITRS Roadmap to 45nm, 32nm and Beyond (A Design- and DFM-Centric

View)”, invited talk, Executive Track, DATE, April 19, 2007.

“Modeling for DFM”, invited presentation, SI2 Models on Runway workshop, June 4, 2007.

“On Next-Generation Flows and Methodologies for Physical Design and Manufacturing

Handoff”, invited talk, Qualcomm, August 23, 2007.

“Key Directions and a Roadmap for Electrical Design for Manufacturability”, invited

presentation, ESSCIRC-ESSDERC, Sept. 12, 2007.

“Opportunities in Future Physical Implementation and Manufacturing Handoff Flows”, invited

talk, TI, September 24, 2007; also AMD, October 10, 2007.

“The Future of Digital Devices”, panel presentation, ISOCC, October 15, 2007.

“Variability Mitigation in Highly Scaled CMOS: Challenges for EDA”, invited presentation (and,

panelist in subsequent panel discussion), IEDM Evening Panel, December 12, 2007.

“Improvement in 65/45nm Physical Implementation Flow and Methodology”, half-day tutorial,

ASP-DAC, January 21, 2008.

“Lithography and Design in Partnership: A New Roadmap”, plenary (keynote) presentation, SPIE

Microlithography Symposium, February 25, 2008.

“How to Get Real MAD (Manufacturing-Aware Design)”, invited presentation, ISPD, April 14,

2008.

“Recent Work on Design-Manufacturing Interface and Physical Implementation”, invited talk,

STMicroelectronics, November 17, 2008.

“Research at the Design-Manufacturing Interface”, invited talk, Samsung, November 26, 2008.

“Research on DFM / Lithography Issues”, invited talk, STARC, November 28, 2008.

“Design Beyond 32nm in Convergence Space”, STMicroelectronics Technology Council, March

9, 2009.

“Implications of Double Patterning Lithography on IP and Physical Design”, invited talk,

Freescale Semiconductor, March 10, 2010.

“Systematic Variation Mapping from Timing Path Delays Using Compressed Sensing”, IMPACT

Center seminar, April 21, 2010.

“On the Challenge of Estimating Designs”, invited talk, Intel Strategic CAD Lab, May 26, 2010.

“Challenges of Estimation and Projection in System Roadmapping”, GSRC webinar, June 29,

2010 (also invited talk, Texas Instruments, July 7, 2010).

UCSD DFM and Power-Aware PD Topics”, invited talk, Samsung, November 16, 2010.

“Futures at the Design-Manufacturing Interface”, KAIST EE Department, March 28, 2011.

“The Future of Signoff”, opening keynote address, TAU Workshop, March 31, 2011.

“Energy Efficiency and Resilience in Future ICs”, Yale EE Department, April 25, 2011.

“Multi-Patterning Optimizations for the Long Run”, ICCAD-2011 Workshop on Nanolithography

and IC Design/CAD in Extreme Scaling, November 11, 2011.

“IT and Society: How Far Into the Future Can We See?”, Workshop on IT and Future Society,

Jeju Island, Korea, November 16, 2011.

“Taming the Power Beast”, keynote address, Low-Power Design Summit, Broadcom Corporation,

May 10, 2012.

“More Than Moore in the ITRS”, DAC-2012 Workshop on More Than Moore Technologies,

June 3, 2012.

“DfX and Signoff: The Coming Challenges and Opportunities”, keynote address, ISVLSI-2012,

August 20, 2012.

“Design-Based ‘Equivalent Scaling’ to the Rescue of Moore’s Law”, ECE Dept. Colloquium, UC

Irvine, October 31, 2012.


“Design Margins, Scaling, and the Future of Moore’s Law”, Booz Allen Hamilton Distinguished

Colloquium, ECE Dept., University of Maryland, April 12, 2013. (Also: ECE Dept. Colloquium,

Boston University, April 29, 2013.)

“Margins, Signoff, and Opportunities for High-Value, Design-Based Scaling”, Tech Talk, Mentor

Graphics, July 12, 2013.

“Design Margin, Scaling, and the Future of Moore’s Law”, keynote address, ASICON 2013,

Shenzhen, October 29, 2013.

“Design Margin, Scaling, and the Future of Moore’s Law”, keynote address, Cisco Design

Innovation Conference, November 4, 2013.

“Lithography-Induced Limits to Scaling of Design Quality”, 22 nd Lithography Workshop, La

Quinta, November 11, 2013.


Courses Taught (W, S, F = Winter, Spring, Fall quarters)

UCLA (1989 – 2000)

CS 151A Computer System Architecture I S90, F90

CS 180 Introduction to Algorithms and Complexity Analysis S91, W92, W94, W95, W96, F97

CS 181 Introduction to Formal Languages and Automata Theory W93, W94, W95, W96, W98,

W99, W00

CS 209AK (research seminar) S90, F90, W91, S91, F91, W92, S92, F92, F94, W95, S95

CS 239 Cooperative Mobile Robotics F94

CS 259 High-Level Synthesis of VLSI Systems S94

CS 259AK Advanced Topics in VLSI Physical Design W98, W99

CS 259CK High-Level and Logic-Level Synthesis W93

CS 269 Autonomous Mobile Robots W95

CSE 259CK High-Level and Logic-Level Synthesis

CS 280A Algorithms: Principles of Design and Analysis F90, F91, F97, F98, F99

CS 280CO Algorithms: Combinatorial Optimization W90, W92, S94

CS 280G Algorithms: Graphs and Networks F93

CS 288S (seminar) Theoretical Computer Science F89, S90

Many CS 298 (research seminar), 199 (directed research – undergraduate), 596-599 (research and

exam preparation – M.S. and Ph.D.) offerings over the years.

UCSD (2001-2013)

ECE 20B Introduction to Electrical Engineering II (+ Lab) W02, W03, W04

ECE 260B VLSI Integrated Circuit and System Design W04, W07, W08, W09, W11, W12, W13

CSE 91 Perspectives in CSE F07, F08, W09

CSE 101 Design and Analysis of Algorithms W02, S07, F08, W08, W11, W12, W13

CSE 241A Introduction to Computing Circuitry W03, W07, W08, W09, W11, W12, W13

CSE 248 Algorithmic and Optimization Foundations of VLSI CAD S03, S04, S07, S11

CSE 249B Topics Seminar (VLSI/Architecture): IC Resilience W11, S11, F11; Clock

Distribution W12, F12, W13, S13; Design for Manufacturability/Physical Design F13

CSE 290 (seminar) VLSI Physical Design-Manufacturing Interface F06, W11

CSE 291 (seminar) VLSI Physical Implementation Methodology S02

CSE 291 (seminar) Heuristics and VLSI Design S01

Many CSE 99R (undergraduate independent study), CSE 197 (field study), CSE 294 (research

meeting), ECE 195 (undergraduate reader-tutor preceptorship), ECE 198-199 (undergraduate

group study and independent study), ECE 200 (graduate research conference), ECE 298-299

(graduate independent study, research), ECE 501 (graduate teaching preceptorship) offerings over

the years.

Research Funding at UCSD (2001-2012) Total of personal shares at UCSD exceeds $7.3M. All amounts given

allocate equal shares to co-PIs of multi-investigator SRC, UC Discovery and NSF awards.

GIFT: VLSI Design Tools, Methodologies and Education, 1/1/2001 – 5/31/2008, Numerical

Technologies, Inc., $50,000

GIFT: VLSI Design Tools, Methodologies and Education, 2/19/2003 –, Cadence Design Systems,

Inc., $42,000

GIFT: VLSI CAD and Design for Manufacturability, 3/15/2007 –, Samsung, $50,000

MARCO/DARPA: Research Center for Design and Test of Gigascale Integrated Systems (Kahng

portion), 9/1/2000 – 8/31/2003, $1,087,600


NSF: Toward Predictors and Predictabiity: Closing the Loop in Top-Down Physical Design,

11/1/2000 – 9/30/2006, $177,233

UC MICRO: Subwavelength Optical Lithography: Challenges & Impact on Physical Design,

1/1/2001 – 8/31/2004, Synopsys + UC MICRO match, $94,460 ($50,000 + $44,460)

UC MICRO: Technology Ground Truths and Future Requirements for Physical Design, 1/1/2001

– 8/8/2003, Cadence + Ammocore + UC MICRO match, $45,945 ($18,000 + $15,000 + $12,945)

SRC: A Framework for Adaptive and Power-Efficient Architectures (Kahng portion PI w/Calder,

Tullsen), 6/1/2001 – 7/31/2004, $107,000

SRC: Layout Planning of Mixed-Signal Systems on a Chip (Kahng portion PI w/Cheng),

7/1/2001 – 1/31/2005, $210,000

SRC: Layout Techniques for Cost Driven Control Lithography-Induced Variability (Kahng

portion w/UMich), 7/1/2001 – 1/31/2005, $188,699

UC MICRO: Technology Ground Truths and Fundamental Bounds for VLSI Systems

Implementation, 8/13/2001 – 12/31/2002, Ammocore + UC MICRO match, $36,000 ($20,000 +

$16,000)

MARCO/DARPA: GSRC System-Level Roadmapping and Design Infrastructure (Kahng

portion), 9/1/2003 – 10/31/2009, $1,228,691

NSF: New Directions for Advanced VLSI Manufacturability (Kahng portion PI w/UVA,GSU),

8/15/2004 – 7/31/2008, $120,000

STARC: UCSD DFM TEG and SSTA, 10/1/2005 – 9/30/2006, $165,000

STARC: Research on DFM Lithography Issues, 10/1/2006 – 9/30/2007, $180,000

STARC: Research on DFM Lithography Issues, 1/1/2008 – 12/31/2008, $180,000

UC Discovery: IMPACT: Integrated Modeling, Process, and Computation for Technology

(Kahng portion), 2/1/2008 – 1/31/2013, Industry + UC Discovery match, $511,496 ($181,681

Industry + $166,815 UC Discovery match; $163,000 supplementary funds in 2011-2012)

SRC: New Directions in Design-Aware Manufacturing (Kahng portion PI w/UCLA), 7/1/2008 –

11/30/2011, $180,000

NSF: Research on Benchmarking and Robustness of VLSI Sizing Optimizations (Kahng portion

PI w/UCLA), 8/1/2008 – 7/31/2011, NSF, $150,000

UC MICRO: Quantified Impact of Guardband Reduction on Design Process Outcomes,

8/15/2008 – 7/31/2010, Qualcomm + UC MICRO match, $58,500 ($50,000 + $8,500)

MARCO/DARPA: Physical Architecture Components: Models, Roadmaps and Integrations

(Kahng portion), 11/1/2009 – 10/31/2012, $280,000

UC Discovery: Power Delivery Pathfinding for 3D Through-Silicon Stacking (Kahng portion PI

w/Cheng), 7/1/2010 – 6/30/2011, Qualcomm + UC Discovery match, $42,500 ($25,000 +

$17,500)

SRC: New Directions in Architecture and Design of Scalable Energy Constrained SoCs (Kahng

portion w/UIUC), 8/1/2010 – 7/31/2013, $150,375

NSF: Research on Architecture-Level Estimation and Optimizations for Networks-on-Chip

Building Blocks (Kahng portion PI w/Lin), 9/1/2011 – 8/31/2014, $225,000

NSF: VLSI Design Predictability Improvement By New Statistical Techniques in Timing

Analysis, Delay ATPG, and Optimization (Kahng portion PI w/UTSA), 9/1/2011 – 8/31/2014,

$249,999

NSF SHF 3D Integration of Heterogeneous Dies (Kahng portion PI w/U. Michigan), 7/1/2012 –


6/30/2015, $365,809

GIFT: Qualcomm / UCSD CSE Industrial Affiliates Program, 9/15/2011 – 9/15/2012 (Kahng

portion w/Rosing), $75,000

DOE: Exascale Grand Challenge, 10/1/2011 – 9/30/2014, $300,000

Samsung: Research on Resilience and Power Optimizations, 2/15/2012 – 2/14/2013, $100,000


SRC: Design Guardbanding, Rules, and Design-Aware Process Monitoring (Kahng portion

w/UCLA), 4/1/2012 – 3/31/2015, $150,000

GIFT: Huawei, / UCSD CSE Industrial Affiliates Program, 5/1/2012 – 4/30/2013 (Kahng

portion w/Rosing), $50,143

Integrated Modeling, Process and Computation for Technology (IMPACT+) (Kahng portion),

5/1/2012 – 4/30/2016, $300,000

GIFT: NXP Semiconductors, 6/1/2012 – 5/31/2013, $70,000

NSF MRI: Universal Chip-Scale Photonic Testing Instrument (co-PI), 7/26/2012 – 7/25/2014,

$1,060,000

GIFT: NXP / UCSD CSE Industrial Affiliates Program, 5/21/2013 – 5/20/2014, $75,000

Samsung: Studies of Clock Network Estimation and Dynamic Power Reduction, 1/31/2013 –

1/30/2014, $100,000

Qualcomm Faculty-Mentor-Advisor (FMA) Award, 9/9/2013 – 9/8/2014, $70,600

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