4 years ago

What is DSP - Hardware Conference 2013

What is DSP - Hardware Conference 2013

Hierarchical Design

Hierarchical Design Methods Flip-Flop Cannot be be combined into into the the same same slice slice (must occupy 5 separate slices) Also Also more more power and and possibly more more difficult timing Hierarchical design methods can proliferate LUT usage on active-low control signals BRINGING YOU THE NEXT LEVEL IN EMBEDDED DEVELOPMENT _ 19 Control Signal Polarity ‣ Solution: Always code active high sets/resets and clock enables ‣ When directly asserted by an external pin, code an inverter in the top-level hierarchy of the design ‣ Alternative: Use flat design techniques ‣ Do not use partitions, KEEP_HIERARCHY, SYN_HIER=HARD, bottom-up synthesis, old EDIF files, etc. Best to describe active high control signals BRINGING YOU THE NEXT LEVEL IN EMBEDDED DEVELOPMENT _ 20

VHDL Example MACC B A B REG A REG M REG Q Z P REG P begin process(clk) begin if clk'event and clk = '1' then areg

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