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What is DSP - Hardware Conference 2013

What is DSP - Hardware Conference 2013

Virtex-5 5

Virtex-5 5 DSP48E Slice BCOUT ACOUT without pre-adder PCOUT B A C 18 25 48 0 1 0 1 B REG CE D Q 2-Deep A REG CE D Q 2-Deep C REG CE D Q 18 25 48 A:B M REG CE D Q 72 36 0 36 0 1 0 17-bit shift 17-bit shift X Y Z 7 OpMode ALUMode 4 CarryIn 48 48 = C or MC P REG CE D Q 48 P PATTERN DETECT BCIN ACIN Z -1 PCIN Z -2 MULT Z -1 ADD Z -1 48 BRINGING YOU THE NEXT LEVEL IN EMBEDDED DEVELOPMENT _ 7 BCOUT Virtex-6 6 DSP48 Slice ACOUT 18 with pre adder CARRY CASCOUT MULT SIGNOUT PCOUT B A D C BCIN ACIN 18 30 30 25 48 Dual B Register Dual A, D Register With Preadder 5 INMODE 18 30 48 18 25 A:B 25 X 18 NEW IN V6: New A and B Pipelines and New D Pre-adder MULT M 86 0 43 43 X 0 1 Y C’ C 0 >>17 Z >>17 7 OpMod e 3 CarryInSel CarryIn 6 P Carry Mux ADD CARRY CASCIN 4 ALUMode MULT SIGNIN 48 C’ = Pat Det Mux MC PATTERN P P 4 48 2 PCIN CARRY OUT P PATTERN_ DETECT BRINGING YOU THE NEXT LEVEL IN EMBEDDED DEVELOPMENT _ 8

Back to the FIR Filter Diagram of a typical FIR filter and implementation : It is a parallel computing process by nature. ‣ N number of taps. ‣ N multiplications should happen in parallel : X (n) Z -1 Z -1 k 0 Z -1 k 1 k 1 k 3 Z -1 Σ k N-1 Most DSP algorithms are using repetitive hardware blocks so benefit from the parallel and systolic nature of the FPGA’s DSP architecture. Y (n) BRINGING YOU THE NEXT LEVEL IN EMBEDDED DEVELOPMENT _ 9 MACC FIR Filter Filter Specification: Sampling Frequency = 0.6911 Mhz, Coefficients = 864 Dual Port Memory is used for data and coefficient storage. DSP48 Capture register still required, although can be reduced in size when rounding or truncation are used xn 25 Input Data 864 x 25 Data Addr we Control Coef Addr Coefficients 864 x 18 CE D Q 48 yn z -4 Max Sample Rate = Clock Rate Number of Taps BRINGING YOU THE NEXT LEVEL IN EMBEDDED DEVELOPMENT _ 10

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