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What is DSP - Hardware Conference 2013

What is DSP - Hardware Conference 2013

FPGAs allow massively

FPGAs allow massively parallel DSP processing Standard DSP processor – Sequential (generic DSP) Coefficients 864 clock cycles needed 1.2 GHz 864 clock cycles Data In X + Reg Data Out Single-MAC Unit = 1.38 MSPS Data In C0 FPGA - Fully Parallel Implementation (Virtex-6 6 FPGA) X Reg C1 C0 X 864 operations in 1 clock cycle Reg C2 600 MHz 1 clock cycle X + Reg C3 Data Out X = 600 MSPS Reg …C863 X BRINGING YOU THE NEXT LEVEL IN EMBEDDED DEVELOPMENT _ 11 Adder Tree to Adder Chain in in out out in out in 0 out BRINGING YOU THE NEXT LEVEL IN EMBEDDED DEVELOPMENT _ 12

Systolic FIR Filter Filter Specification: Sampling Frequency = 600 Mhz, Coefficients = 31 Input time delay series is created inside the DSP Slice for maximum performance irrespective of the number of coefficients x(n) 25 K0 K1 K29 K30 0 y(n) 48 DSP48 Slice DSP48 Slice DSP48 Slice DSP48 Slice Max Sample Rate = Clock Rate Dedicated cascade connections (PCOUT and PCIN) are exploited to achieve maximum performance BRINGING YOU THE NEXT LEVEL IN EMBEDDED DEVELOPMENT _ 13 Pre-adder Benefits with Symmetrical Filters When the coefficients are symmetrical, ‣ pre-adders either reduce the number of multiplications by 50% ‣ or double the sample rate Factorizing the taps replaces one multiplication by a pre-addition/-subtraction Symmetrical Filter Example k13 k17 Non symmetrical filter (k13?k17) : (tap13×k13) + (tap17×k17) 2 mults and one post-add Symmetrical filter (k13=k17) : (tap13+tap17) × k13 Direct benefit : saves 50% of the DSP slices 1 pre-add 1 mult BRINGING YOU THE NEXT LEVEL IN EMBEDDED DEVELOPMENT _ 14

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