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What is DSP - Hardware Conference 2013

What is DSP - Hardware Conference 2013

Symmetric Systolic FIR

Symmetric Systolic FIR Filter 12 Sample in Z -30 srl32 0 K0 K1 K14 K15 0 27 Sample out DSP48 Slice 1 DSP48 Slice 2 DSP48 Slice 15 DSP48 Slice 16 Max Sample Rate = Clock Rate = 600 MHz BRINGING YOU THE NEXT LEVEL IN EMBEDDED DEVELOPMENT _ 15 Flip-Flop Flop Control Guidelines ‣ Use active high control signals when possible ‣ Do not use asynchronous set / resets ‣ Only use set / reset when necessary ‣ Be careful with coding unnecessary clock enables ‣ Use synthesis constraints wisely BRINGING YOU THE NEXT LEVEL IN EMBEDDED DEVELOPMENT _ 16

Flip-Flop Flop Set and Reset Conditions ‣ When using any combination of asynchronous set or reset with synchronous set or reset ‣ Asynchronous set or reset has priority (furthermore, reset has highest priority) ‣ In above mode, the synchronous set, reset, or both are implemented in a LUT ‣ The priority of the synchronous set versus synchronous reset is defined by how the HDL is written BRINGING YOU THE NEXT LEVEL IN EMBEDDED DEVELOPMENT _ 17 What’s s Better than Synchronous Resets? Resets BRINGING YOU THE NEXT LEVEL IN EMBEDDED DEVELOPMENT _ 18

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