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JFET AND MOSFET - BITS Pilani

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<strong>JFET</strong> <strong>AND</strong> <strong>MOSFET</strong><br />

<strong>BITS</strong> <strong>Pilani</strong><br />

Dubai Campus<br />

Dr Jagadish Nayak


<strong>BITS</strong> <strong>Pilani</strong><br />

Dubai Campus<br />

Junction Field Effect Transistors &<br />

Metal Oxide Semiconductor Field<br />

Effect Transistors


<strong>JFET</strong><br />

Construction (n channel)<br />

Symbol<br />

D<br />

G<br />

S<br />

<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus


<strong>JFET</strong><br />

Construction (p channel)<br />

Symbol<br />

<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus


<strong>JFET</strong><br />

<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus


<strong>JFET</strong><br />

Circuit analysis<br />

<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus


<strong>JFET</strong><br />

When V DD = V GG =0, two junctions<br />

with associated depletion region<br />

is shown<br />

<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus


<strong>JFET</strong><br />

When the V DD =v DS is small (positive) number, a small positive<br />

drain current results. The potential at drain v D is approximately<br />

equal to source voltage v S (v S ≈ v D =0)<br />

However if V GG is increased, since v GS = -V GG , then pn<br />

junction will become more reverse biased and depletion<br />

region gets wider.<br />

Because v S (v S ≈ v D =0) , the depletion regions are<br />

symmetrical.<br />

When the VGG is sufficiently increased , the depletion region<br />

will be widened and channel will become narrower.<br />

The value of v GS = -V GG , which eliminates the channel is called<br />

as pinchoff voltage.<br />

<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus


<strong>JFET</strong><br />

As long as V DD = v DS = v D -v S remains small , the depletion<br />

region will be essentially symmetrical and i D will be<br />

proportional to v DS , i. e channel will behave as a linear<br />

resistor.<br />

However, if V DD =v DS =v D -v S gets larger, then i D gets larger<br />

and v D becomes greater than v S<br />

Since v GS =0 V<br />

v GD =v GS -v DS = 0-v DS =-v DS<br />

<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus


<strong>JFET</strong><br />

Since gate drain voltage<br />

is negative and gate<br />

source voltage is zero,<br />

portion of the pn junction<br />

between the gate and<br />

drain is more reverse<br />

biased than portion<br />

between gate and source.<br />

Due to this channel is<br />

narrower at the drain end<br />

than source end.<br />

<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus


<strong>JFET</strong><br />

As v DS increases, i D also<br />

increases , channel gets<br />

narrower at the drain end<br />

than source end. The<br />

channel resistance<br />

increases and its nature is<br />

non linear.<br />

If v DS is made large enough<br />

pinch off is reached as<br />

shown<br />

v GD =v GS -v DS =0-v DS =V p or<br />

v DS =-V p<br />

<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus


<strong>JFET</strong><br />

For v DS > -V p , channel is still pinched off (very narrow),<br />

then the drain current will remain constant for v DS ≥ -V p ,<br />

and drain current is said to saturate.<br />

The plot for i D vss v DS is shown<br />

For v GS =0. The value of constant<br />

saturation current is I DSS , it can<br />

range from tenths of mA to<br />

hundred of mA.<br />

pn junction will breakdown if large<br />

Reverse voltage is applied.<br />

<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus


<strong>JFET</strong><br />

Pinch off can be reached in two ways<br />

1. When v GS = 0 V, the channel is pinched off for v GD = -v DS =Vp<br />

or v DS = -Vp.<br />

2. When V GG > 0 or v GS < 0 , the channel is pinched off, when<br />

v GD =v GS -v DS = Vp or v DS = v GS - Vp<br />

Thus by decreasing vGS, the value of vDS required to<br />

pinch off the channel decreases.<br />

<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus


<strong>JFET</strong> (Drain characteristics)<br />

I DSS = 12mA and<br />

pinch off voltage is<br />

Vp= -3V.<br />

If v GS =0 V, channel<br />

pinchoff when v DS= -<br />

Vp=3V<br />

If v GS =-1V, channel<br />

pinchoff at<br />

v DS = v GS - Vp =<br />

-1+3=2V<br />

<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus


<strong>JFET</strong> (Drain characteristics)<br />

The dashed curve is corresponding to v DS = v GS - Vp<br />

To the right of this curve , (v DS > v GS - Vp ), The channel is<br />

pinched off and this region is called as pinch off region or<br />

saturation region. (active region).<br />

To the left of this curve, (v DS < v GS - Vp ), the channel is not<br />

pinched off and the region is called as ohmic region.<br />

When the gate is sufficiently reverse biased , channel will<br />

be totally eliminated for v GS < Vp, under this<br />

circumstances increasing v DS , will not be sufficient to<br />

produce a drain current. i D =0 and <strong>JFET</strong> is said to be in<br />

cutoff.<br />

<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus


<strong>JFET</strong> (Equations)<br />

When the <strong>JFET</strong> is in the ohmic region, drain current iD is<br />

given by<br />

i<br />

D<br />

I<br />

DSS<br />

2 1<br />

v<br />

V<br />

GS<br />

p<br />

v<br />

V<br />

DS<br />

p<br />

v<br />

V<br />

DS<br />

p<br />

2<br />

For a small value of vDS, we have –Vp >> vDS, so<br />

small , thus<br />

v<br />

V<br />

DS<br />

p<br />

2<br />

is<br />

v<br />

2I<br />

GS DS DSS<br />

iD<br />

I<br />

DSS<br />

2 1<br />

1<br />

Vp<br />

Vp<br />

Vp<br />

v<br />

v<br />

V<br />

GS<br />

p<br />

v<br />

DS<br />

<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus


<strong>JFET</strong> (Equations)<br />

From which we can write<br />

i<br />

v<br />

D<br />

DS<br />

2I<br />

V<br />

DSS<br />

p<br />

1<br />

v<br />

V<br />

GS<br />

p<br />

2I<br />

DSS<br />

( v<br />

GS<br />

2<br />

p<br />

V<br />

V<br />

p<br />

)<br />

Thus for a small v DS , channel behaves as a linear resistor<br />

r DS and is given by<br />

r<br />

DS<br />

v<br />

i<br />

DS<br />

D<br />

2I<br />

DSS<br />

V<br />

( v<br />

2<br />

p<br />

GS<br />

V<br />

p<br />

)<br />

When the <strong>JFET</strong> is in the active region , drain current is<br />

i<br />

D<br />

I<br />

DSS<br />

1<br />

v<br />

V<br />

GS<br />

p<br />

2<br />

<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus


<strong>MOSFET</strong><br />

<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus


<strong>MOSFET</strong><br />

The resistance between reverse biased gate and source<br />

is typically in megaohms.<br />

For <strong>MOSFET</strong>, because of the insulation between gate<br />

and the substrate , the resistance between the gate and<br />

source is extremely high (in 10 10 to 10 15 )<br />

If v GS is made negative, the positive charges are induced<br />

on the n channel, there by effectively narrowing it.<br />

For varying value of vDS , the behavior of the device is<br />

similar to the <strong>JFET</strong>.<br />

Since it operates in the depletion mode, it is called as<br />

depletion <strong>MOSFET</strong>.<br />

<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus


<strong>MOSFET</strong><br />

<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus


<strong>MOSFET</strong><br />

Given that I DSS =8mA and V p =-2V. Find<br />

v GS , i D , v DS .<br />

By inspecting the circuit , vGS=1V.<br />

Assume that <strong>MOSFET</strong> is in active<br />

region, then<br />

vGS<br />

iD I<br />

DSS<br />

1 18mA<br />

V<br />

P<br />

3<br />

v DS<br />

500 (18x10 ) 16 7V<br />

2<br />

Since v DS = 7 > v GS -V p = 1+2=3V,<br />

then the <strong>MOSFET</strong> is indeed in the<br />

active region<br />

<strong>BITS</strong> <strong>Pilani</strong>, Dubai Campus

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