Presentation Materials Including Discussion Notes - UCSD VLSI ...

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Presentation Materials Including Discussion Notes - UCSD VLSI ...

2 nd DAC EDA Roadmap Workshop

June 14, 2010, 9am – 3pm

Anaheim Convention Center, Room 213D

For latest version, contact J. Antonio Carballo (juananto@us.ibm.com) or Andrew Kahng (abk@cs.ucsd.edu)


Goals

• Goal of this workshop

–To further the dialogue between the various communities /

bodies involved in roadmapping design technology, and to bring

together key constituencies (designers, EDA companies,

researchers, and multiple world regions) with a view towards a

more explicit future interlock

• Uniqueness of this workshop

–The only forum for deep discussion around roadmap issues

related to the EDA industry. Leaders from semiconductor

companies, consortia, and academia jointly assess the need for

and state of roadmap efforts, to craft a blank-sheet view of

roadmap activities for the next 15 years

TODAY

Where/How should the EDA industry improve its roadmap(ping)

1


Our Agenda !

Session/title Speaker(s) Time

Introduction and Plenary J.A.Carballo (IBM), A.B. Kahng (UCSD) 9AM

Session I: Corporate Roadmap Views

IBM's EDA Roadmap View David Kung (IBM) 9:20

IDM View Shishpal Rawat (Intel) 9:40

EDA Standards @ Si2: 2010 view Sumit Dasgupta (Si2 Roadmap) 10:00

GF EDA Roadmap View Walter Ng (GlobalFoundries) 10:20

EDA 360 Andreas Kuehlmann (Cadence) 10:40

Maximizing performance per Watt Rob Knoth (Magma) 11:00

IP View Yervant Zorian (Virage Logic) 11:20

IDM / Fablite View Nagaraj NS (TI) 11:40

Panel Discussion and Working Lunch (sandwich orders in the morning) Noon

Session II: Consortia (and Corporate Stragglers) Views

EU CATRENE / ENIAC roadmap Ahmed Jerraya (CEA-LETI) 1:10

Japan's EDA Roadmap View STRJ (Kahng / Carballo rep) 1:30

ITRS's EDA Roadmap View Kahng / Carballo (UCSD / IBM) 1:50

IP View Dipesh Patel (ARM) 2:10

Panel Discussion and Next Steps Kahng / Carballo (UCSD / IBM) 2:30


Some Questions and Actions from 2009

QUESTIONS

1. What would make an EDA roadmap more useful

– To whom (R&D, marketing, standards bodies, consortia, ...)

2. Which EDA areas lack most in roadmap efforts

– Parallel EDA, SW EDA, analog EDA, ESL

3. Which EDA areas are behind what the roadmaps say

– Does this matter

ACTIONS

4. Need: Process to ensure tight contributors-users interlock

5. Need: Commitment to a yearly report of

i. how EDA roadmap is used

ii. by whom

iii. feedback for improving it next year

• Are existing efforts OK (point to them as “meta-roadmap”) or not

3 (new one needed)


Process for Today

1. Short (10-15 min) viewpoint talks in 20-min slots

– Leaving time for discussion

2. Different from last year: IP, IDM, foundry perspectives

3. Organizers will scribe discussion highlights and follow-up actions

4. Slides and discussion outcomes will be posted on the same website

i. who is responsible for {development, review, integration} of roadmap

ii. in what specific areas (applications, embedded software, AMS, …)

iii. on what timeline (when should we have follow-ups this year)

iv. for what consumers (ITRS Design/SysDrivers chapters, EDAC, …)

5. Misc: lunch signups, etc.

4


TECHNOLOGY GAPS IN EDA ROADMAP

1. End-product roadmaps (what is EDA enabling!) x

Semi companies compete on cost, TTM, quality

2. System-level - virtual platforms, executable specification

TI, Bosch

3. Design space exploration – pathfinding (incl. 3D), IP

selection, what-if analyses (incl. cost)*

4. SW synthesis and verification (concurrency)

5. Post-silicon: perf/power closure, diagnosis, debug * (Test)

6. EDA scaling (cf. evolving computing platforms

(manycore, accelerators, cloud) *

Simply follow Moore’s Law, handle technology

7. Power management (analysis, optimization, power-driven

design) *

Apple, Google, Nokia

8. 3D (end of CMOS, heterogeneity, cost, perf, power)

9. Variability (trends), resilience, BTWC design *

10.Analog / mixed-signal

11.Interoperability

5


NATURE OF EDA

1. Predictable (RAS), incremental design flows

(e.g., functional sim)

2. Wall time (tool, design process)

3. Hierarchy (passing design intent, integration)

4. IP encapsulation, migration, reuse

5. Extracting value from a mature technology node

6. Enabling user development

7. Usability

(product class-specific)

8. Industry efficiency

6


ROADMAP = CHALLENGES + SOLUTIONS + METRICS

1. Standards (e.g., OpenPDK, IP encapsulation)

2. *Move from hardware to system (hw, sw, fw) level*

= Expanding scope of EDA

3. Interoperability

4. *COST – of design, of product, of tool integration

Design for Cost (what-if from spec to arch …)

5. Industry efficiency

6. Usability (e.g., enabling user development)

Waves: long Tcl script foundation flows

7


NOTES

1. Other

i. Business justification for EDA development

ii. Technology vs. design entitlement gap

2. What is the crisis

i. According to what metric

3. Sharing of EDA R&D / product metrics

4. Verticalization of EDA

8


ATTENDEES

1. David Kung, IBM kung@us.ibm.com

2. Shishpal Rawat, Intel shishpal.s.rawat@intel.com

3. Nowjand Attaie, Intel nowjand.attaie@intel.com

4. Chin-Fu Chen, Qualcomm cfchen@qualcomm.com

5. Myungsoo Jang, Samsung msjang@samsung.com

6. Woosick Choi, Hynix woosick.choi@hynix.com

7. Walter Ng, GLOBALFOUNDRIES ngw@globalfoundries.com

8. Nagaraj NS, TI nsnr@ti.com

9. James You, Broadcom jyou@broadcom.com

10. Deepak Sherlekar, Virage Logic deepak.sherlekar@viragelogic.com

11. Yervant Zorian, Virage Logic zorian@viragelogic.com

12. Hisam El-Masry, CMC Microsystems elmasry@cmc.ca

13. Matthew Hogan, Mentor matthew_hogan@mentor.com

14. Roberto Suaya, Mentor roberto_suaya@mentor.com

15. Merlyn Brunken, Mentor merlyn_brunken@mentor.com

16. Jay Adams, Synopsys jka@synopsys.com

17. Narendra Shenoy, Synopsys nshenoy@synopsys.com

18. William Joyner, SRC william.joyner@src.org

19. Sumit Dasgupta, Si2 dasgupta@si2.org

20. Ahmed Jerraya, CEA-LETI ahmed.jerraya@cea.fr

21. W. Rhett Davis, NC State Univ. rhett_davis@ncsu.edu

22. Michael Kochte, Univ. Stuttgart kochte@iti.uni-stuttgart.de

23.

9

Alper Sen, Bogazici Univ. alper.sen@boun.edu.tr

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