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Predicting the Performance of Synchronous Discrete ... - IEEE Xplore

Predicting the Performance of Synchronous Discrete ... - IEEE Xplore

Predicting the Performance of Synchronous Discrete ... - IEEE

1130 IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL. 15, NO. 12, DECEMBER 2004 Predicting the Performance of Synchronous Discrete Event Simulation Jinsheng Xu, Member, IEEE, and Moon Jung Chung, Member, IEEE Abstract—In this paper, we develop a model to predict the performance of synchronous discrete event simulation. Our model considers the two most important factors for the performance of synchronous simulation: load balancing and communication. The effect of load balancing in a synchronous simulation is computed using probability distribution models. We derive a formula that computes the cost of synchronous simulation by combining a communication model called LogGP and computation granularity. Even though the formula is simple, it is effective in capturing the most important factors for the synchronous simulation. The formula helps us to predict the maximum speed up achievable by synchronous simulation. In order to examine the prediction model, we have simulated several large ISCAS logic circuits and a simple PCS network simulation on an SGI Origin 2000 and Terascale Computing System (TCS) at the Pittsburgh Supercomputing Center. The results of the experiment show that our performance model accurately predicts the performance of synchronous simulation. The performance model developed is used to analyze the effect of several factors that may improve the performance of synchronous simulation. The factors include problem size, load balancing, granularity, communication overhead, and partitioning. Index Terms—Parallel discrete event simulation, performance evaluation. æ 1 INTRODUCTION SYNCHRONOUS simulation is one of the simplest and easiest parallel simulation protocols. In synchronous simulation, events with the smallest timestamp are executed in a simulation cycle. After the event execution step, processors are synchronized, forcing processors to wait until all other processors finish their event execution. The cost of the longest executing processor is considered as the computation cost of each time step. Other processors that have a shorter execution time will have to wait for the longest executing processor before all of them can proceed to the next timestamp. After each time step, all the processors exchange messages. This parallel programming model can be categorized as a BSP programming model [32]. Except for additional communication cost, synchronous simulation has little overhead when compared to sequential simulation. Although conservative and optimistic simulations can exploit more parallelism, they have much more overhead than synchronous simulation, which can make the overall performance worse than synchronous simulation. Soule and Gupta evaluated the Chandy-Misra algorithm [7] for digital logic simulation. They found that the overhead of Chandy-Misra algorithm would overwhelm its advantage and the performance is about three times slower than traditional parallel event-driven algorithm [30]. Konas and Yew compared the performance of a synchronous simulation to the conservative and optimistic [20] algorithms in . J. Xu is with the Department of Computer Science, North Carolina A&T State University, 1601 E. Market St., Greensboro, NC 27411. E-mail: jxu@ncat.edu. . M.J. Chung is with the Department of Computer Science, Michigan State University, EB 3115, East Lansing, MI 48824. E-mail: chung@cse.ms.edu. Manuscript received 18 Apr. 2003; revised 24 Nov. 2003; accepted 2 June 2004. For information on obtaining reprints of this article, please send e-mail to: tpds@computer.org, and reference IEEECS Log Number TPDS-0060-0403. simulating a synchronous multiprocessor system [15]. Their results show that the synchronous method is considerably faster than both the asynchronous approaches, the main reason being that both the asynchronous simulation algorithms introduce significant overhead. The performance uncertainty is one main reason for less frequent use of parallel simulation techniques on circuit and network simulation. This motivates us to develop a model that predicts the performance of synchronous discrete event simulation. Agrawal and Chakradhar [1] considered only the load balancing factor of synchronous simulation. They proposed a statistical model for synchronous simulation. Given a system with uniform granularity of event execution and with random partitioning, an object is active with a probability of activity rate. The number of independent random variables is the same as the number of objects in the system. At each cycle, different processors have a different number of active objects, while the cost of the cycle is determined by the maximum order statistics of binomial random variables. They proposed a performance model based on the number of objects together with the activity rate. They compared the theoretical prediction with the benchmark for several circuits. However, they only analyzed the case of very high event execution granularity and left the case of interprocessor communication out as an open research topic. This model has limited application, especially for logical simulation and some network simulation where event execution has small granularity. Another limitation of the model is that it requires objects to have the same activity rate. This does not apply to network simulation where different types of objects have significantly different activity rate. For example, a router is much more active than a normal terminal. Quaglia et al. [27] presented an analytic model for the performance of optimistic simulation. Their model is used to evaluate if indeed an optimistic implementation can out perform the sequential algorithm. However, the communication cost is ignored in their model. Bagrodia and 1045-9219/04/$20.00 ß 2004 IEEE Published by the IEEE Computer Society

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