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Hercules<br />
ARM ® Cortex TM -R4 Safety Microcontrollers<br />
1
Make the world a safer place with Hercules TM<br />
MCUs<br />
<strong>Electronics</strong> are proliferating in safety-critical applications<br />
EN 50128<br />
(railway)<br />
DO-254<br />
DO-178B<br />
(aerospace)<br />
IEC<br />
60601<br />
(medical<br />
equipment)<br />
IEC<br />
61511<br />
(process<br />
industry)<br />
TM<br />
Hercules<br />
MCU<br />
IEC<br />
50156<br />
(furnaces)<br />
IEC 60880<br />
(nuclear<br />
power<br />
stations)<br />
IEC 62061<br />
ISO 13849<br />
(machinery)<br />
IEC 61508<br />
(safety)<br />
ISO 26262<br />
(automotive)<br />
Hercules MCUs<br />
provide<br />
developers of<br />
safety-critical<br />
applications:<br />
Protection against random and systematic failures<br />
Headroom for application differentiation<br />
Simplified development and system certification<br />
2
TI Hercules TM MCU Platform<br />
ARM ® Cortex Based Microcontrollers<br />
Hercules Platform<br />
RM4x<br />
TMS570<br />
TMS470M<br />
High Performance<br />
Industrial and Medical<br />
Safety MCUs<br />
• Industrial Applications<br />
• Medical Applications<br />
• -40 to 105°C Operation<br />
• ENET, USB, CAN & UART<br />
• Developed to Safety Standards<br />
• IEC 61508 SIL-3<br />
• Cortex-R – over 350 DMIPs<br />
High Performance<br />
Transportation and<br />
Safety MCUs<br />
• Transportation Applications<br />
• Automotive Q100 Qualification<br />
• -40 to 125°C Operation<br />
• FlexRay, ENET, CAN, LIN/UART<br />
• Developed to Safety Standards<br />
• ISO 26262 ASIL-D<br />
• IEC 61508 SIL-3<br />
• Cortex-R – over 280 DMIPs<br />
Value Line<br />
Transportation and<br />
Safety MCUs<br />
• Transportation Applications<br />
• Automotive Q100 Qualification<br />
• -40 to 125°C Operation<br />
• CAN, LIN/UART Connectivity<br />
• Supports Safety for<br />
• IEC 61508 Systems<br />
• Cortex-M – to 100 DMIPS<br />
3
Hercules Safety MCU Roadmap<br />
Industrial &<br />
Medical<br />
RM48L9x<br />
• 2*R4F LS<br />
• 3MB, 256kB<br />
• 220MHz<br />
Production 4Q 2012<br />
RM48L5x<br />
• 2MB, 192kB<br />
ETHERNET<br />
Samples 3Q 2012<br />
RM46x<br />
• 2*R4F LS<br />
• 1.25MB, 192kB<br />
• 220MHz<br />
RM42x<br />
• 2*R4LS<br />
• 384KB, 32KB<br />
• 100 MHz<br />
Samples 3Q 2012<br />
ETHERNET<br />
QEP<br />
QEP / PWM<br />
Safe<br />
Motor Control<br />
Industrial<br />
Automation<br />
Safe<br />
Connectivity<br />
Medical<br />
Automotive & Transportation<br />
TMS570LS202S<br />
• 2*R4F LS<br />
• 2MB, 160kB<br />
• 160MHz<br />
TMS570LS102S<br />
• 1MB, 160kB<br />
TMS470MF066S<br />
• ARM® Cortex-M3<br />
• 640kB, 48kB<br />
• 80MHz<br />
TMS470MF042S<br />
• 448kB, 24kB<br />
TMS470MF031S<br />
• 320kB, 16kB<br />
TMS570LS31x<br />
• 2*R4F LS<br />
• 3MB, 256kB<br />
• 180MHz<br />
Production 4Q 2012<br />
TMS570LS21x<br />
• 2MB, 192kB<br />
ETHERNET<br />
TMS570LS12x<br />
• 2*R4F LS<br />
• 1.25MB, 192kB<br />
• 180MHz<br />
Samples 4Q 2012<br />
TMS570LS11x<br />
• 1MB, 128kB<br />
TMS570LS04x<br />
• 2*R4 LS<br />
• 384KB, 32KB<br />
• 80MHz<br />
Samples 4Q 2012<br />
TMS570LS03x<br />
• 256KB, 24kB<br />
ETHERNET<br />
QEP / PWM<br />
QEP<br />
Stability<br />
Control<br />
Power<br />
Steering<br />
Vehicle<br />
Electrification<br />
ABS<br />
Power Steering<br />
Passive Safety<br />
CAN Communication<br />
Production<br />
Sampling<br />
Production/Sample Date<br />
Lockstep<br />
CPUs<br />
61508<br />
SIL3<br />
26262<br />
ASIL-D<br />
TI Confidential - NDA Restrictions
Hercules Cortex-R4F MCU safety features<br />
CPU Self Test<br />
Controller requires<br />
little S/W overhead<br />
ECC for flash / RAM /<br />
interconnect evaluated<br />
inside the Cortex R4F<br />
–Safe Island Hardware diagnostics (RED)<br />
–Blended HW diagnostics (BLUE)<br />
–Non Safety Critical Functions (BLACK)<br />
Logical / physical<br />
design optimized to<br />
reduce probability of<br />
common cause<br />
failure<br />
Dual Core Lockstep -<br />
Cycle by Cycle CPU<br />
Fail Safe Detection<br />
Parity on all<br />
Peripheral, DMA and<br />
Interrupt controller<br />
RAMS<br />
Parity or CRC in<br />
Serial and Network<br />
Communication<br />
Peripherals<br />
Lockstep<br />
CPUs<br />
ARM ®<br />
Cortex -<br />
R4F<br />
Fail Safe Detection<br />
OSC PLL<br />
POR<br />
CRC<br />
Enhanced System Bus and Vectored Interrupt Module<br />
Serial<br />
Interfaces<br />
Memory<br />
Flash<br />
w/ ECC<br />
RAM<br />
w/ ECC<br />
Flash<br />
EEPROM w/ ECC<br />
Network<br />
Interfaces<br />
Calibration<br />
JTAG Debug<br />
Embedded Trace<br />
DMA<br />
Dual<br />
ADC<br />
Cores<br />
Power, Clock, & Safety<br />
PBIST/LBIST<br />
ESM<br />
RTI/DWWD<br />
Memory Interface<br />
External Memory<br />
Dual<br />
High-end<br />
Timers<br />
GIO<br />
Memory BIST on all<br />
RAMS allows fast<br />
memory test at<br />
startup<br />
On-Chip Clock and<br />
Voltage Monitoring<br />
Error Signaling<br />
Module w/ External<br />
Error Pin<br />
IO Loop Back, ADC<br />
Self Test, …<br />
Dual ADC Cores with<br />
shared channels<br />
5
1oo1D Dual Core Safety Concept<br />
– Unique design to reduce common<br />
cause failures (βIC)<br />
– Second CPU mirrored and<br />
rotated<br />
– Minimum distance 100µm<br />
between CPUs<br />
– Cycle delayed lockstep<br />
– Guard ring per CPU<br />
– Duplicated clock tree per CPU<br />
Output + Control<br />
Cycle Delay<br />
ARM ®<br />
Cortex -R4F<br />
> 100um<br />
CCM<br />
Self<br />
Test<br />
Compare<br />
Error<br />
– CPU Compare Module (CCM)<br />
– Self-test capability<br />
– Self-test error injection/error<br />
forcing<br />
– Output error injection<br />
Input + Control<br />
Cycle Delay<br />
6
CPU Self Test Controller (STC/LBIST)<br />
Clock<br />
controller<br />
ROM<br />
ROM<br />
interface<br />
Clock cntrl<br />
FSM<br />
ARM ®<br />
Cortex -R4F<br />
Test<br />
controller<br />
PCR<br />
VBUSP<br />
interface<br />
STC<br />
STC BYPASS/<br />
ATE Interface<br />
REG Block<br />
&<br />
Compare<br />
Block<br />
DBIST<br />
CNTRL<br />
DBIST<br />
CNTRL<br />
ERR<br />
ESM<br />
• Provides High Diagnostic Coverage<br />
• Significantly Lowers S/W and Runtime Overhead<br />
• No SW BIST (Built In Self Test) Code overhead in Flash<br />
• Simple to configure and start BIST via register
Programmable Memory BIST (PBIST)<br />
– All on-chip RAMS<br />
can be tested<br />
Functional<br />
Read/Write<br />
Datapath<br />
– Simple register setup and<br />
configuration<br />
– Typically run at startup, but can<br />
be executed during the<br />
application<br />
VBUS I/f<br />
Tester I/f<br />
ROM I/f<br />
Cfg<br />
block<br />
Ext<br />
block<br />
ROM<br />
block<br />
PBIST<br />
Controller<br />
RAM<br />
Data<br />
path/<br />
Collars<br />
To / From<br />
Memories<br />
(RAM<br />
groups)<br />
– Multiple Memory Test<br />
Algorithms<br />
Data<br />
Logger<br />
– Detects multiple failure modes<br />
- Provides a mechanism to determine if runtime faults were caused by hard or<br />
soft error. This capability can be used to improve availability through inline<br />
recovery from soft error.
Flash / RAM ECC Protection<br />
Cortex-R4F<br />
64 Inst.<br />
8 Stage<br />
Pipeline<br />
64 Data<br />
32 Data Bits<br />
4 ECC Bits<br />
Flash<br />
8 ECC<br />
Error<br />
ECC Logic<br />
8 ECC<br />
RAM<br />
32 Data Bits<br />
4 ECC Bits<br />
• ECC evaluated in the Cortex R4F CPU<br />
– Single Bit Error Correction and Double Bit Error Detection (SECDED)<br />
– ECC evaluated in parallel to processing data/instructions<br />
– No latency or performance impact<br />
– Protects Busses from CPU to Flash and RAM
Safety Aspects of Network Interfaces<br />
– Networked peripherals (Ethernet, FlexRay, DCAN, and SCI/LIN) are<br />
considered grey-channel / black-channel communications<br />
– In such communications application level protocols (time redundancy, CRC in<br />
data packet, etc.) are necessary<br />
– When such assumption is made, the Dangerous Undetected Failure from the<br />
network is effectively not measurable (
Error Signaling Module (ESM)<br />
ESM<br />
Errors for Group 1<br />
INTEN<br />
INTLVL<br />
Low Level Interrupt<br />
Handling<br />
High Level Interrupt<br />
Handling<br />
To Interrupt<br />
Manager<br />
Errors for Group 2<br />
Errors for Group 3<br />
ERROR<br />
SIGNAL<br />
CONTROL<br />
LOW TIME<br />
COUNTER PRELOAD<br />
LOW TIME<br />
COUNTER<br />
nERROR pin
Clock Monitoring<br />
– External clock prescaler (ECLK)<br />
– Allows external monitoring of CPU clock frequency<br />
– Configurable pin (GIO or ECLK)<br />
– Oscillator monitor<br />
– Detects failure if oscillator frequency exceeds defined min/max thresholds<br />
– Selectable hardware response on oscillator fail<br />
– Reset device<br />
– Switch to internal ‘low power oscillator’ (LPO) clock source<br />
– FMPLL slip detector<br />
– Indicates PLL slip if phase lock is lost<br />
– Selectable hardware response on PLL slip<br />
– Reset device<br />
– Switch to internal ‘low power oscillator’ (LPO) clock source<br />
– Switch to external oscillator clock source<br />
LPO<br />
Input from<br />
Oscillator<br />
FMPLL<br />
CLK Signal to<br />
CLK Control Module<br />
Bypass on Slip<br />
Slip<br />
Detector<br />
BPOS<br />
BPOS<br />
Reset on Slip<br />
ROS<br />
To Device Reset<br />
PLLMUL<br />
12
Dual Clock Comparator (DCC)<br />
• The DCC module is used to measure the frequency of a clock signal<br />
using a second clock signal as a reference.<br />
– Allows application to ensure that a fixed frequency ratio is maintained<br />
between two clock signals<br />
– Supports the definition of a programmable tolerance window in terms of<br />
number of reference clock cycles<br />
– Supports continuous monitoring without requiring application intervention<br />
– Alternatively can be used in a single-sequence mode for spot measurements<br />
– Flexible clock source selection for Counter 0 and Counter 1 resulting in<br />
several specific use cases<br />
Clock 0 Sources<br />
•<br />
•<br />
•<br />
Clock 0<br />
Preload 0<br />
Counter 0<br />
0<br />
=<br />
Valid Preload 0<br />
Valid Counter 0<br />
0<br />
=<br />
Clock 0 Select<br />
Preload 1<br />
Clock<br />
Compare<br />
ERROR<br />
Clock 1 Sources<br />
•<br />
•<br />
•<br />
Clock 1<br />
Counter 1<br />
Clock 1 Select<br />
PLLMUL<br />
13
Digital Windowed Watch Dog (DWWD)<br />
– The DWWD module will reset the MCU or generate a non maskable<br />
interrupt to the CPU if the application fails to service the watchdog to<br />
within the appropriate time window.<br />
– Optional safety diagnostic that can detect a runaway CPU<br />
– Includes a 25-bit down counter<br />
– Alerts the Error Signaling Module when a CPU interrupt is generated<br />
– Supports multiple service windows: 100%, 50%, 25%, 12.5%, 3.125%<br />
– Servicing requires a specific two part key sequence<br />
– Once enabled can only be disabled by a system or power on reset<br />
Down<br />
Counter<br />
100%<br />
Window<br />
Window Open Window Open<br />
50%<br />
Window<br />
Window Open Window Open<br />
DWWD Preload<br />
Down Counter<br />
0<br />
=<br />
25%<br />
Window<br />
12.5%<br />
Window<br />
6.25%<br />
Window<br />
3.125%<br />
Window<br />
W Open<br />
Open<br />
O<br />
O<br />
W Open<br />
Open<br />
O<br />
O<br />
Digital<br />
Windowed<br />
Watch<br />
Dog<br />
RESET<br />
INTERRUPT<br />
ESM<br />
PLLMUL<br />
14
Memory Protection Unit (MPU)<br />
– A Dedicated Memory Protection Unit (MPU) is implemented for each bus master<br />
Lockstep<br />
CPUs<br />
ARM ®<br />
Cortex ARM -<br />
®<br />
R4F Cortex -<br />
R4F<br />
ARM 160MHz ®<br />
Cortex 160MHz -<br />
R4F<br />
Fail Safe<br />
Detection<br />
Memory<br />
Flash w/ ECC<br />
RAM w/ ECC<br />
Memory Protection<br />
Calibration<br />
JTAG Debug<br />
Embedded Trace<br />
DMA<br />
Power, Clock, & Safety<br />
OSC PLL<br />
PBIST<br />
LBIST<br />
Enhanced System Bus and Vectored Interrupt Management<br />
Serial I/F<br />
MibSPI<br />
128 Buffers; 4 CS<br />
MibSPI<br />
128 Buffers; 4 CS<br />
MibSPIP<br />
128 Buffers; 4 CS<br />
Network I/F<br />
FlexRay<br />
2 ch FlexRay<br />
Transfer Unit<br />
(FTU)<br />
8K Message RAM<br />
CAN1 (64mb)<br />
CAN2 (64mb)<br />
CAN3 (32mb)<br />
UART1 (LIN1)<br />
UART2 (LIN2)<br />
DMA<br />
ADC<br />
MibADC1<br />
64 Buffers<br />
12-bit, 16ch<br />
(8ch shared)<br />
MibADC2<br />
64 Buffers<br />
12-bit, 16ch<br />
(8ch shared)<br />
POR<br />
CRC<br />
RTI<br />
Memory Interface<br />
EMIF<br />
Timers / IO<br />
High End<br />
High Timer End<br />
(NHET) Timer<br />
Transfer 128 words, Unit<br />
(HTU) 32 ch<br />
GIOA/INTA (8)<br />
GIOB (8)<br />
• Bus masters include the CPU,<br />
DMA, HTU and the FTU<br />
• A memory region is defined which<br />
allows read and write access for<br />
the bus master<br />
• Access outside the defined region<br />
can be any of the mode<br />
• Read Only: Read access allowed for<br />
the memory accesses outside the<br />
region. Write accesses are blocked<br />
• No Access: Read and write access is<br />
blocked.<br />
• In the event of a memory<br />
protection violation the Error<br />
Signaling Module (ESM) is notified
Voltage Monitor<br />
– Supply Voltage Monitor (VMON)<br />
– Holds reset until core and I/O rails in expected range (removes power<br />
sequencing requirements)<br />
– Asserts reset if core or I/O supply exceeds defined min/max<br />
thresholds<br />
– Asserts reset when core supply is below specified min voltage and<br />
asynchronously sets all I/O pins to high impedance mode<br />
-<br />
+
– ADC calibration logic can improve<br />
Dual Analog to Digital Converters<br />
– Dual12-bit ADC Cores:<br />
– Core 1 supports 24 analog inputs &<br />
Core 2 supports 16 analog inputs<br />
– Up to 16 analog channels can be<br />
shared between the 2 cores for safety<br />
critical conversions/comparison<br />
(1oo2 safety redundancy)<br />
– Internal ADC reference voltages can<br />
be used to check converter<br />
functionality.<br />
– Self Test Mode enables in application<br />
detection of opens/shorts on ADC<br />
inputs<br />
AD1EVT<br />
AD1IN[7..0]<br />
AD1IN[23..8] /<br />
AD2IN[15..0]<br />
VccAD<br />
VssAD<br />
VrefHi<br />
VrefLo<br />
AD2EVT<br />
Self-Test & Calibration<br />
MibADC1<br />
MibADC2<br />
Self-Test & Calibration<br />
To Peripheral Bus To Peripheral Bus
Exida Has Certified TMS570LS20216S<br />
61508 SIL 3 Capable<br />
IEC<br />
• All Hercules TMS570 and RM<br />
products will be assessed by Exida<br />
and/or TÜV-SÜD<br />
• To get a Safety Certificate, Hercules<br />
MCUs are assessed for:<br />
– Development Process<br />
– Product Safety Architecture/Concept<br />
– Silicon<br />
• TI has chosen to work with TÜV-SÜD<br />
(DAkkS accredited) and Exida (ANSI<br />
accredited) for both IEC 61508:2010<br />
and ISO 26262:2011
Hercules Safety Documents<br />
Documents provided by TI some under NDA to assist in the<br />
safety certification process:<br />
– Hercules TMS570/RM Device Safety Manual (SM)<br />
• Details product safety architecture and recommended usage<br />
NDA<br />
NDA<br />
– Safety Analysis Report Summary (SAR1)<br />
• Summary of FIT rate and FMEDA at DEVICE level for IEC 61508<br />
and ISO 26262<br />
– Detailed Safety Analysis Report (SAR2)<br />
• Full details of all safety analysis executed down to MODULE level for<br />
IEC 61508 and ISO 26262<br />
NDA<br />
– Safety Case Report (SCR)<br />
• Summary of compliance to IEC 61508 and/or ISO 26262
Hercules TM<br />
Hercules MCUs<br />
provide<br />
developers of<br />
safety-critical<br />
applications:<br />
Safety MCUs Provides Developers<br />
Protection against random and systematic failures<br />
Headroom for application differentiation<br />
Simplified development and system certification<br />
Hardware Safety Architecture<br />
Application Headroom<br />
Safety Certification & Documentation<br />
• Lockstep CPUs<br />
• CPU & RAM Built-in Self Test<br />
• Flash & RAM ECC<br />
• Clock Monitoring<br />
• Voltage Monitoring<br />
Over 350 DMIPs of<br />
processing power<br />
20
High Performance Cortex-R4F floating-point CPU<br />
ARM ® v7R Cortex TM ISA<br />
fully backward Compatible<br />
to ARM7/9/11<br />
Up to 220 MHz CPU<br />
Clock Speed<br />
Fast MULT, DIV, and<br />
SQRT enables modelbased<br />
control; simplifies<br />
algorithm<br />
implementation<br />
Lockstep CPUs:<br />
Single core programming<br />
model – second core<br />
checks the first.<br />
ARM ®<br />
Cortex -R4F<br />
220 MHz<br />
Supports ARM, Thumb<br />
and Thumb-2 instructions<br />
Single / double<br />
precision IEEE 754<br />
floating-point<br />
Floating point and<br />
integer instructions<br />
operate in parallel<br />
12 region memory<br />
protection<br />
Broad ARM IDE/Compiler<br />
Support:<br />
CCS, KIEL, IAR, etc…<br />
• Over 350 DMIPS of performance<br />
• High performance floating point<br />
• ARM-based: broad industry adoption<br />
Superscalar, SIMD,<br />
8 stage pipeline delivers<br />
1.6 DMIPS/MHz<br />
Scalable ARM Based<br />
Solutions from TI:<br />
Stellaris, Concerto,<br />
Hercules & Sitara<br />
21
RM46x Block Diagram<br />
ARM ® Cortex-R4F Floating Point Microcontroller<br />
Performance / Memory<br />
• Up to 220 MHz ARM Cortex-R4F w/ Floating Point<br />
• Up to 1.25MB Flash and 192KB Data SRAM<br />
• Dedicated 64KB Data Flash (EEPROM Emulation)<br />
• 16 Channel DMA<br />
Features<br />
• Safety<br />
• Dual CPUs in Lockstep<br />
• CPU Logic Built in Self Test (LBIST)<br />
• Up to 12 CPU MPU regions<br />
• Flash & RAM w/ ECC (w/ bus protection)<br />
• Memory Built-in Self Test (PBIST)<br />
• Cyclic redundancy checker module (CRC)<br />
• Peripheral RAMs protected by Parity<br />
• Communication Networks<br />
• 10/100 Ethernet<br />
• USB Host and Device<br />
• 3 CAN Interfaces<br />
• 5 SPI (3 Multi-Buffered)<br />
• 2 UART, 1 I2C<br />
• Enhanced I/O Control<br />
2x High End Timer Coprocessor (N2HET)<br />
• Up to 40 pins plus 6 monitor channels<br />
• All pins can be used as Hi-Res PWM or Input Capture<br />
Motor Control Timers<br />
• 7x ePWM (14 ch), 6x eCAP, 2x eQEP<br />
2 x12-bit Multi-Buffered ADC<br />
• 24 total input channels (8 shared)<br />
• Calibration and Self Test<br />
Up to 101 GPIO pins (16 dedicated)<br />
Targeted Applications<br />
• General IEC61508 Safety Applications<br />
• Industrial, Medical, Energy<br />
ARM ®<br />
Cortex ARM -<br />
®<br />
R4F Cortex -<br />
160MHz<br />
R4F<br />
Up to 220MHz<br />
Fail Safe<br />
Detection<br />
Memory<br />
1.25MB Flash<br />
w/ ECC<br />
192KB RAM<br />
w/ ECC<br />
Calibration<br />
JTAG Debug<br />
DMA<br />
Power, Clock, & Safety<br />
OSC PLL<br />
PBIST<br />
LBIST<br />
Enhanced System Bus and Vectored Interrupt Module<br />
Serial I/F Network I/F ADC<br />
MibSPI1<br />
128 Buffers; 6 CS<br />
MibSPI3<br />
128 Buffers; 6 CS<br />
MibSPIP5<br />
128 Buffers; 6 CS<br />
SPI2 (2CS)<br />
SPI4 (1CS)<br />
64KB Data Flash<br />
EEPROM w/ ECC<br />
USB Full Speed<br />
Host & Device<br />
CAN1 (64mb)<br />
CAN2 (64mb)<br />
CAN3 (64mb)<br />
2x UART (LIN1)<br />
I2C<br />
10/100 EMAC*<br />
MibADC1<br />
64 Buffers<br />
12-bit, 24ch<br />
(16ch shared)<br />
MibADC2<br />
64 Buffers<br />
12-bit, 16ch<br />
(16ch shared)<br />
POR<br />
CRC<br />
RTI/DWWD<br />
Memory Interface<br />
SDRAM EMIF<br />
Timers / IO<br />
2x High End Timer<br />
(N2HET)<br />
160 words<br />
ePWM (14ch)<br />
eCAP (x6)<br />
eQEP (x2)<br />
GIOA/INT(16)<br />
Packages: LQFP: 144pin -20x20; nfBGA: 337 pin-16x16, 0.8mm;<br />
-40 to 105°C Temperature Range<br />
Note :Above reflects max configuration of each module – some functions are multiplexed.<br />
TI Confidential – NDA Restrictions
Hercules TM Development Kits<br />
Development Evaluation<br />
TMDXRM48USB – RM48 USB Stick Kit<br />
TMDX570LS31USB – TMS570 USB Stick Kit<br />
TMDX470MF066USB – TMS470M USB Stick Kit<br />
• USB Powered<br />
• On Board USB XDS100v2 JTAG Debug<br />
• On Board SCI to PC Serial Communication<br />
• Access to Select Signal Pin Test Points<br />
• LEDs, Temp Sensor & Light Sensor<br />
• Accelerometer (TMS570 & RM)<br />
• CAN transceiver<br />
TMDXRM48HDK, TMDXRM46HDK, TMDXRM42HDK – RM4 Kits<br />
TMDX570LS31HDK, TMDX570LS12HDK, TMDX570LS04HDK – TMS570 Kits<br />
TMDX470MF066HDK – TMS470M Development Kit<br />
– On Board USB XDS100v2 JTAG Debug<br />
– External high speed emulation via JTAG<br />
– TRACE pads for ETM/RTP/DMM<br />
– LEDs, Temp Sensor & Light Sensor<br />
$79<br />
$199<br />
– CAN Transceivers<br />
Motor Control<br />
– RJ45 10/100 Ethernet Interface (TMS570 & RM)<br />
DRV8301-RM48-KIT, DRV8301-RM46-KIT – RM4 Motor Kits<br />
DRV8301-TMS570LS31-KIT, – USB-A Host Interface DRV8301-TMS570LS12-KIT (RM)<br />
– TMS570 Motor Kits<br />
TMDXRM48CNCD, – USB-B TMDXRM46CNCD Device Interface (RM) – RM4 Control Cards<br />
TMDX570LS31CNCD, TMS570LS12CNDC – TMS570 Control Cards<br />
Hercules controlCARDs:<br />
• Isolated xds100v2 and external JTAG connector<br />
• RJ45 Ethernet connector<br />
DRV8301 EVM :<br />
• Teknic 6,000 rpm, 7.1 A motor with built in encoder<br />
• 1.7A Pre-driver ,1.5A buck converter & 60A+ FETs.<br />
$499<br />
23
Hercules TM<br />
Software Tools<br />
IDEs (compilers & debuggers)<br />
Program/debug code using these<br />
IDEs:<br />
• Code Composer Studio<br />
• IAR Workbench<br />
• KEIL µVision<br />
• Green Hills MULTI<br />
RTOS Support<br />
Real Time Operating System Support:<br />
• SAFERTOS: High Integrity Systems<br />
• µC/OS: Micrium<br />
• ThreadX: Express Logic<br />
• Sciopta RTOS<br />
• AUTOSAR: Vector Microsar and EB tresos<br />
GUI-based Code Generation Tools and Other SW Tools<br />
Safety MCU Demos<br />
• Safety Feature Highlight<br />
• Ambient Light & Temperature Demo<br />
• LED Light Show<br />
• Maze Game<br />
• Source Code Viewable via CCS<br />
PLL Calculators<br />
Easily configure the FMzPLL and FPLLs in<br />
the Hercules platform Phase Lock Loop<br />
modules.<br />
HET IDE<br />
• Graphical Programming Environment<br />
• Output Simulation Tool<br />
• Generates CCS-ready software modules<br />
• Includes functional examples from TI<br />
HALCoGen<br />
• User Input on High Abstraction Level<br />
• Graphical-based code generation<br />
• Easy configuration<br />
• Quick start for new projects<br />
• Supports CCS, IAR & KEIL IDEs<br />
now ECC ECC Generation Tool<br />
Command line program for generating<br />
Error Correction Code for Hercules<br />
devices. Can be used in conjunction with<br />
CCSv4<br />
now Flash Flash Programming Tool<br />
GUI and command line programmer for<br />
loading code into Hercules devices<br />
without an IDE.
Demo: PWM Generation using the N2HET
Overview<br />
– In this exercise we will:<br />
– Create a new HALCoGen Project<br />
– Configure HALCoGen to generate<br />
– A basic PWM with a period of 1 second and a duty cycle of 75%<br />
– A basic PWM with a period of 0.5 seconds and a duty cycle of 50%<br />
– Use the PWM to toggle the NHET1[0] and NHET1[17] LEDs on the board<br />
– Generate and Import code into Code Composer Studio<br />
– Build and Deploy our code to the microcontroller<br />
– Required Hardware:<br />
– Windows Based PC (WinXP, Vista, 7)<br />
– TMS570LS31HDK/USB or RM48HDK/USB
HALCoGen GUI Overview<br />
Menus and Icons<br />
Help<br />
Module Selection/Configuration<br />
Device<br />
Block<br />
Diagram<br />
Device/<br />
Output File<br />
Explorer<br />
Output/Status<br />
27
HALCoGen Help<br />
HALCoGen’s embedded help window provides full documentation of<br />
each communication drivers, implemented functions, file dependencies<br />
and examples.<br />
28
HALCoGen File Dependencies and Function Listing<br />
File<br />
Information<br />
Control<br />
File<br />
Explorer<br />
File<br />
Dependency<br />
Diagram<br />
Function<br />
Listing<br />
29
Set up a New HALCoGen Project<br />
• To launch HALCoGen go to:<br />
• → Programs → Texas Instruments → Hercules → HALCoGen<br />
• Create a new project:<br />
• File → New → Project<br />
1<br />
• For the TMS570 Kit:<br />
– Choose Family: TMDX570LS31x<br />
– Device:TMDX570LS31USB<br />
• For the RM48 Kit:<br />
– Choose Family: TMDXRM48<br />
– Device:TMDXRM48USB<br />
2<br />
3<br />
• Then define a name: ‘N2HET’<br />
• Location: “C:\myWorkspace”<br />
30
Driver Enable<br />
• In ‘Driver Enable’ tab enable the HET1 driver.<br />
1<br />
2<br />
3<br />
31
N2HET PWM Configuration<br />
• In ‘Driver Enable’ tab enable the NHET1 driver.<br />
• In ‘HET1’ ‘PWM 0-7’ tab:<br />
• Configure PWM 0 to 75% Duty Cycle, with a Period 1000000.00uS on Pin 0<br />
• Configure PWM 1 to 50% Duty Cycle, with a Period of 500000.00uS on Pin 17<br />
32
N2HET Output Configuration<br />
• In the ‘HET1’ ‘Pin 0-7’ tab:<br />
• Make sure that the output on Pin 0 is enabled<br />
• In the ‘HET1’ ‘Pin 16-23’ tab:<br />
• Make sure that the output on Pin 17 is enabled<br />
• Generate Code: File → Generate Code<br />
33
Setting up Code Composer Studio<br />
– Launch Code Composer Studio (CCS)<br />
– Start → Programs → Texas Instruments → Code Composer Studio v5<br />
→ Code Composer Studio v5<br />
– When it launches, CCS will ask you to select a workspace, we will chose<br />
“C:\myWorkspace”<br />
– Once CCS loads, go to<br />
File → New → CCS Project<br />
34
Setting up our Project<br />
– From the New Project window, expand the ‘Code Composer Studio’<br />
folder .<br />
– Select ‘CCS Project’<br />
• Click ‘Next’<br />
1<br />
2<br />
3<br />
35
Setting up our Project<br />
– Our project name needs to match the name of our HALCoGen Project,<br />
‘Exercise’<br />
– Make sure that your project<br />
‘Family’ is set to ARM<br />
• Next, set the Variant<br />
to “Cortex R”<br />
2<br />
1<br />
3<br />
• For the TMS570 kits:<br />
– Choose: TMS570LS3137<br />
• For the RM48 kits:<br />
– Choose : RM48L950<br />
4<br />
• Then set the ‘Connection’ to the<br />
Texas Instruments XDS100v2<br />
5<br />
• Then click ‘Finish’<br />
36
Setting up our Project<br />
• First delete expand the project and delete file ‘main.c’ from CCS “Project Explorer”<br />
Note: CCS will create a file named ‘main.c’ automatically when a new project is created. Since we are<br />
using code that HALCoGen created for us, we will not need this file.<br />
1<br />
2<br />
37
Setting up our Project<br />
• Next we need to add our ‘include’ directory to the project from the CCS “Project<br />
Explorer”<br />
• Right click on the<br />
‘Exercise’ project<br />
in the Project<br />
Explorer<br />
1<br />
• Then choose<br />
‘Properties’<br />
2<br />
38
Setting up our Project<br />
• Then in the<br />
‘Properties’ window<br />
expand the ‘Build -><br />
ARM Compiler’<br />
category and select<br />
‘Include Options’<br />
1<br />
2<br />
• Then select the ‘+’<br />
button to add the<br />
directory with our<br />
‘.h’ header files<br />
3<br />
4<br />
• In the ‘Add directory<br />
path’ window, click<br />
the ‘Workspace…’<br />
button<br />
• Finally, select the ‘include’<br />
folder that HALCoGen<br />
created for us that<br />
contains all our ‘.h’ header<br />
files<br />
39
Enter Code into the CCS Project<br />
• Expand the project and open the “sys_main.c” file from the CCS “Project Explorer”<br />
Note: Since the HALCoGen and CCS project have the same project name, all the startup and driver<br />
files generated by HALCoGen will be automatically included in the CCS project. Use the “sys_main.c”<br />
file for your main program code.<br />
40
Code Composer Studio<br />
– In the Code Composer Project and enter the following code:<br />
– Inside User Code 1, insert the code below.<br />
/* USER CODE BEGIN (1) */<br />
#include "het.h"<br />
/* USER CODE END */<br />
– Then in User /* Code USER 3, CODE insert the BEGIN code (3) below. */<br />
hetInit();<br />
while(1);<br />
/* USER CODE END */
Compiling the Project<br />
– The code is now complete and we are ready to build our project.<br />
– Go to Project → Build All<br />
42
Programming the Flash<br />
– We are now ready to program the flash.<br />
– Go to Run → Debug<br />
– A new window should appear as it programs the flash memory.<br />
– This may take a few moments.<br />
43
Testing our Program<br />
• Click the green arrow on the debug tab to run our program<br />
– Alternatively the program can be run without the debugger connected by<br />
• Clicking the red square on the debug tab to terminate the debugger’s connection<br />
• Hitting the reset button on the board and observe the behavior of the N2HET LEDs<br />
• Congratulations! You have completed the exercise.<br />
44
Additional Hercules Information<br />
Hercules Web Page: www.ti.com/hercules<br />
RM4 Web Page: www.ti.com/rm4<br />
TMS570 Web Page: www.ti.com/tms570<br />
TMS470M Web Page: www.ti.com/tms470m<br />
– Data Sheets<br />
– Technical Reference Manual<br />
– Application Notes<br />
– Software & Tools <strong>Download</strong>s and Updates<br />
– Order Evaluation and Development Kits<br />
Engineer 2 Engineer Support Forum:<br />
www.ti.com/hercules-support<br />
– News and Announcements<br />
– Useful Links<br />
– Ask Technical Questions<br />
– Search for Technical Content<br />
Hercules WIKIs:<br />
RM4 WIKI: www.ti.com/hercules-rm4-wiki<br />
TMS570 WIKI: www.ti.com/hercules-tms570-wiki<br />
TMS470M WIKI: www.ti.com/hercules-tms470m-wiki<br />
– How to guides<br />
– Intro Videos<br />
– General Information
More Hercules TM<br />
1 Day Training Class:<br />
Hercules 1 Day Safety Seminar<br />
• Introduction<br />
• What is Functional Safety<br />
• Safety Standards Overview<br />
• IEC 61508 Safety Standard<br />
• ISO 26262 Safety Standard<br />
• Random Fault Management<br />
• Safety System Architectures<br />
• Hercules Safety Concept<br />
Training<br />
• Lab 1: Hercules Safety MCU Demos<br />
• Hercules Architecture<br />
• Development Tools: HW kits, SW tools<br />
• Embedded Flash Memory tools<br />
• Real Time Interrupt (RTI)<br />
• Vectored Interrupt Manager (VIM)<br />
• Direct Memory Access (DMA)<br />
• General-purpose I/O (GIO) & NHET<br />
3 Day Training Class:<br />
Safety Critical Design and Programming with<br />
ARM ® Cortex TM -R4F based Hercules MCUs<br />
• Lab 2: Using NHET as GIO<br />
• Communication Interfaces: UART, LIN, CAN, FlexRay,<br />
Multi-Buffered Serial Peripheral Interface (MibSPI)<br />
• Lab 3: PC to SCI Communication<br />
• External Memory Interface (EMIF) / Parameter Overlay<br />
• Multi-buffered Analog-to-Digital Converter (MibADC)<br />
• Support Structure: Web, Forum, WIKI<br />
Who should attend:<br />
• Hardware and Software Developers<br />
• Project Managers<br />
• Safety Specialists<br />
• Anyone interested in Hercules MCUs and<br />
functional safety<br />
Day 1 Day 2 Day 3<br />
• Welcome and Intro<br />
• Hercules Product Overview / MCU<br />
Roadmap<br />
• Safety Standards and Hercules Safety<br />
Features<br />
• HALCoGen / Exercise<br />
• Code Composer Studio / Demonstration /<br />
Exercise<br />
• Compiler / Exercise<br />
• Flash Overview<br />
• Flash Tools: nowFlash TM , nowECC TM ,<br />
nowProfile TM<br />
• Summary / Questions<br />
• ARM ® Cortex -R4F CPU Architecture<br />
Overview<br />
• System Module Overview<br />
• Device setup/startup, Real Time Interrupt<br />
Module, Vectored Interrupt Manager<br />
• CRC Controller, CPU Compare Module,<br />
Error Signaling Module)<br />
• General Purpose I/Os / Supply<br />
• Direct Memory Access Controller (DMA)<br />
• Serial Communication Interface<br />
(SCI/UART/LIN)<br />
Please contact Anthony Vaughan (tvaughan@ti.com) for more information<br />
• Summary / Questions<br />
• Multi-Buffer Serial Peripheral Interface<br />
(SPI / MIBSPI-P)<br />
• DCAN<br />
• FlexRay / Transfer Unit<br />
• Multi-Buffer ADC (MIBADC)<br />
• External Memory Interface (EMIF) /<br />
Parameter Overlay Module (POM)<br />
• NHET (High End Timer) IDE<br />
• NHET<br />
• NHET Transfer Unit<br />
• Summary & Questions
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