34~chapter 03 lfsim.pdf

Chapter 3 Exercise Solutions
3.1 (Parallel Gate Evaluation)
The Z-to-u conversion, i.e., to convert a signal x = x 1
x 2
to x ˆ = x ˆ 1
x ˆ 2
according to the
following rule,
00 => 00 (0 => 0)
01 => 01 (u => u)
10 => 01 (Z => u)
11 => 11 (1 => 1)
can be realized by
ˆ x 1
= x 1
x 2
ˆ x 2
= x 1
+ x 2
Note that the Z-to-u conversion is necessary only if the gate input is driven by tri-state
gate.
(a) Apply the Z-to-u conversion,
ˆ A 1
= A 1
& A 2
ˆ A 2
= A 1
| A 2
ˆ B 1
= B 1
& B 2
ˆ B 2
= B 1
| B 2
&, |, and ~ denote the bitwise AND, OR, and NOT operations, respectively.
AND, OR, and NOT evaluation procedures are as follows.
C = AND(A,B):
C 1
= A ˆ
1
& B ˆ
1
C 2
= A ˆ
2
& B ˆ
2
C = OR(A,B):
C 1
= A ˆ
1
| B ˆ
1
C 2
= A ˆ
2
| B ˆ
2
C = NOT(A)
C 1
=~ B ˆ
2
C 2
=~ A ˆ
1
VLSI Test Principles and Architectures Ch. 3 – Logic & Fault Simulation – P. 1/15

(b) Two-to-one multiplexer.
Let A and B be the 0/1 inputs, E the selection input, and O the output.
⎧ A ˆ if E ˆ = 0
⎪
O = ⎨ B ˆ if E ˆ =1
⎪
⎩ u if E ˆ = u
The k-maps are as follows.
O ˆ
1
A ˆ
1
B 1
00 01 11 10
E ˆ ˆ
1
E 2
00 0 0 1 1
01 0 0 0 0
11 0 1 1 0
10 x x x x
O ˆ
2
A ˆ
2
B 2
00 01 11 10
E ˆ ˆ
1
E 2
00 0 0 1 1
01 1 1 1 1
11 0 1 1 0
10 x x x x
It can be derived that
O 1
= A ˆ
1
&( ~ E ˆ
2 )| B ˆ
1
& E ˆ
1
O 2
= ( A ˆ | E ˆ
2 2 )& B ˆ
2
| ~ ˆ
( ( E ) 1
XOR gate
C = XOR( A,B)
The k-maps for C 1
and C 2
are:
C 1
C ˆ
2
A ˆ
1
A 2
00 01 11 10
B ˆ ˆ
1
B 2
00 00 01 11 xx
01 01 01 01 xx
11 11 01 00 xx
10 xx xx xx xx
It can be derived that
C 1
= ( ~ A ˆ
2 )& B ˆ
1
| A ˆ
1
& ~ B ˆ
2
C 2
= A ˆ
2
&( ~ B ˆ
1 )+ ( ~ A ˆ
1 )& ˆ
( )
B 2
VLSI Test Principles and Architectures Ch. 3 – Logic & Fault Simulation – P. 2/15

(c) Tri-state buffer
Let A be the input, E the enabling signal, and O the output.
⎧ A ˆ if E ˆ =1
⎪
O = ⎨ Z if E ˆ = 0
⎪
⎩ u if E ˆ = u
The k-maps for O 1
and O 2
are:
O 1
O ˆ
2
A ˆ
1
A 2
00 01 11 10
E ˆ ˆ
1
E 2
00 10 10 10 xx
01 01 01 01 xx
11 00 01 11 xx
10 xx xx xx xx
It can be derived that
O 1
= ( ~ E ˆ
2 )| A ˆ ˆ
1
E 1
O 2
= ( ~ E ˆ
1 )& E ˆ
2
| A ˆ
2
& E ˆ
2
VLSI Test Principles and Architectures Ch. 3 – Logic & Fault Simulation – P. 3/15

3.2 (Timing Models)
(a) Nominal + Inertial Delays
(b) Rise/Fall Delays
VLSI Test Principles and Architectures Ch. 3 – Logic & Fault Simulation – P. 4/15

(c) Min-Max Delays
VLSI Test Principles and Architectures Ch. 3 – Logic & Fault Simulation – P. 5/15

3.3 (Compiled-Code Simulation)
(a) Levelization
(b) Pseudo code
while(true) do
read(A,B,C);
D = AND(A,B);
E = NOT(B);
F = OR(B,C);
H = AND(D,E);
H = AND(H,F);
H = NOT(H);
J = NOT(F);
L = AND(H,J);
L = NOT(L);
end
VLSI Test Principles and Architectures Ch. 3 – Logic & Fault Simulation – P. 6/15

3.4 (Event-Driven Simulation)
Time L E L A Scheduled Events
0 {(B,0)} {D,E,F} {(D,0,1),(E,1,0.6),(F,1,1)}
0.1 {(A,0)} {D} {(D,0,1.1)}
0.4 {(A,1)} {D} {(D,0,1.4)}
0.5 {(C,0)} {F} {(F,0,1.5)}
0.6 {(E,1)} {H} {(H,0,1.8)}
1 {(D,0),(F,1)} {H} {(H,1,2.2)}
1.1 {(D,0)}
1.4 {(D,0)}
1.5 {(F,0)} {H,J} {(H,1,2.7),(J,1,2.1)}
1.8 {(H,0)} {L} {(L,1,2.8)}
2.1 {(J,1)} {L} {(L,1,3.1)}
2.2 {(H,1)} {L} {(L,0,3.2)}
2.7 {(H,1)}
2.8 {(L,1)}
3.1 {(L,1)}
3.2 {(L,0)}
VLSI Test Principles and Architectures Ch. 3 – Logic & Fault Simulation – P. 7/15

3.5 (Hazard Detection)
To detect static and dynamic hazards, use 8-valued logic.
A = F
B = R
C = F
D = AND(A,B)
= AND(F,R)
= AND({1110,1100,1000},{0001,0011,0111})
= {0000,0010,0110,0100}
= 0*
E = NOT(B)
= NOT(R)
= F
F = OR(B,C)
= OR(R,F)
= OR({0001,0011,0111},{1110,1100,1000})
= {1111,1101,1001,1011}
= 1*
H = NAND(D,E,F)
= NAND(0*,F,1*)
= NAND({0000,0100,0110,0010},{1110,1100,1000},
{1111,1011,1001,1101})
= {1111,1011,1001,1101}
= 1*
J
= NOT(F)
= NOT(1*)
= 0*
L = NAND(H,J)
= NAND(1*,0*)
= 1*
A static 1-hazard may occur at output L.
VLSI Test Principles and Architectures Ch. 3 – Logic & Fault Simulation – P. 8/15

3.6 (Hazard Detection)
Use 8-valued logic.
pattern 1 (10) ==> pattern 2 (01)
a = F
b = R
c = OR(AND(a,b),NOT(b))
= OR(AND(F,R),NOT(R))
= OR(0*,F)
= OR({0000,0100,0110,0010},{1110,1100,1000})
= {1110,1100,1000,1010}
= F*
A dynamic 0-hazard may occur.
pattern 2 (01) ==> pattern 3 (11)
a = R
b = 1
c = OR(AND(a,b),NOT(b))
= OR(AND(R,1),NOT(1))
= OR(R,0)
= R
No static or dynamic hazard.
VLSI Test Principles and Architectures Ch. 3 – Logic & Fault Simulation – P. 9/15

3.7 (Parallel-Pattern Single-Fault Propagation)
PPSFP input internal output
fault P a b D E F c
P1 1 0 0 0 1 1
fault-free P2 0 1 1 0 0 0
P3 1 1 1 1 0 1
P1 1 0 0 0 1 1
α P2 0 1 0 0 0 0
P3 1 1 0 0 0 0
P1 1 0 0 0 1 1
β P2 0 1 1 0 1 1
P3 1 1 1 1 1 1
VLSI Test Principles and Architectures Ch. 3 – Logic & Fault Simulation – P. 10/15

3.8 (Parallel Fault Simulation)
PFS input internal output
Pattern fault a b D E F c
P1
P2
P3
fault-free 1 0 0 0 1 1
α 1 0 0 0 1 1
β 1 0 0 0 1 1
fault-free 0 1 1 0 0 0
α 0 1 0 0 0 0
β 0 1 1 0 1 1
fault-free 1 1 1 1 0 1
α 1 1 0 0 0 0
β 1 1 1 1 1 1
VLSI Test Principles and Architectures Ch. 3 – Logic & Fault Simulation – P. 11/15

3.9 (Deductive Fault Simulation)
The controlling value of a NOR gate is one, and the inversion value is also one. Let S be
the set of inputs that hold the controlling value, and I be the set of all inputs, i.e.,
I = {A, B, C}.
When all inputs hold the non-controlling value (ABC = 000), we have
L D
=
⎛
⎜
⎞
∪ L
⎝ j
⎟ ∪ D/ c ⊕ i
j ∈I ⎠
{ ( )}
= ( L A
∪ L B
∪ L C )∪{ D/0}
When at least one input holds the controlling value, we have
⎛ ⎛
L D
= ⎜
⎞ ⎛ ⎞ ⎞
⎜ ∩ L
⎝ j
⎟ −⎜
∪ L
j ∈S ⎠
j
⎟ ⎟ ∪
⎝ ⎝ j ∈( I −S
{ D/1}
) ⎠ ⎠
For example, if ABC = 110, L D will be
L D
= ( L A
∩ L B )− L C )∪{ D/1}
VLSI Test Principles and Architectures Ch. 3 – Logic & Fault Simulation – P. 12/15

3.10 (Deductive Fault Simulation)
For the purpose of demonstration, we do not perform fault collapsing here. The noncollapsed
fault list is {a/0, a/1, b/0, b/1, D/0, D/1, H/0, H/1, E/0, E/1, F/0, F/1, c/0, c/1}.
VLSI Test Principles and Architectures Ch. 3 – Logic & Fault Simulation – P. 13/15

3.11 (Concurrent Fault Simulation)
VLSI Test Principles and Architectures Ch. 3 – Logic & Fault Simulation – P. 14/15

3.12 (Critical Path Tracing)
VLSI Test Principles and Architectures Ch. 3 – Logic & Fault Simulation – P. 15/15