- Page 1 and 2: PIC18F97J60 Family Data Sheet 64/80
- Page 3 and 4: PIC18F97J60 FAMILY 64/80/100-Pin Hi
- Page 5 and 6: PIC18F97J60 FAMILY Pin Diagrams 64-
- Page 7 and 8: PIC18F97J60 FAMILY Pin Diagrams (Co
- Page 9 and 10: PIC18F97J60 FAMILY TO OUR VALUED CU
- Page 11: PIC18F97J60 FAMILY 1.0 DEVICE OVERV
- Page 15 and 16: PIC18F97J60 FAMILY FIGURE 1-1: PIC1
- Page 17 and 18: PIC18F97J60 FAMILY FIGURE 1-3: PIC1
- Page 19 and 20: PIC18F97J60 FAMILY TABLE 1-4: Pin N
- Page 21 and 22: PIC18F97J60 FAMILY TABLE 1-4: Pin N
- Page 23 and 24: PIC18F97J60 FAMILY TABLE 1-4: Pin N
- Page 25 and 26: PIC18F97J60 FAMILY TABLE 1-5: Pin N
- Page 27 and 28: PIC18F97J60 FAMILY TABLE 1-5: Pin N
- Page 29 and 30: PIC18F97J60 FAMILY TABLE 1-5: Pin N
- Page 31 and 32: PIC18F97J60 FAMILY TABLE 1-5: Pin N
- Page 33 and 34: PIC18F97J60 FAMILY TABLE 1-6: Pin N
- Page 35 and 36: PIC18F97J60 FAMILY TABLE 1-6: Pin N
- Page 37 and 38: PIC18F97J60 FAMILY TABLE 1-6: Pin N
- Page 39 and 40: PIC18F97J60 FAMILY TABLE 1-6: Pin N
- Page 41 and 42: PIC18F97J60 FAMILY TABLE 1-6: RJ0/A
- Page 43 and 44: PIC18F97J60 FAMILY 2.0 OSCILLATOR C
- Page 45 and 46: PIC18F97J60 FAMILY 2.5 Internal Osc
- Page 47 and 48: PIC18F97J60 FAMILY 2.7.1 OSCILLATOR
- Page 49 and 50: PIC18F97J60 FAMILY 3.0 POWER-MANAGE
- Page 51 and 52: PIC18F97J60 FAMILY FIGURE 3-1: TRAN
- Page 53 and 54: PIC18F97J60 FAMILY 3.3 Sleep Mode T
- Page 55 and 56: PIC18F97J60 FAMILY 3.4.3 RC_IDLE MO
- Page 57 and 58: PIC18F97J60 FAMILY 4.0 RESET The PI
- Page 59 and 60: PIC18F97J60 FAMILY 4.2 Master Clear
- Page 61 and 62: PIC18F97J60 FAMILY FIGURE 4-5: TIME
- Page 63 and 64:
PIC18F97J60 FAMILY TABLE 4-2: Regis
- Page 65 and 66:
PIC18F97J60 FAMILY TABLE 4-2: Regis
- Page 67 and 68:
PIC18F97J60 FAMILY TABLE 4-2: Regis
- Page 69 and 70:
PIC18F97J60 FAMILY TABLE 4-2: Regis
- Page 71 and 72:
PIC18F97J60 FAMILY 5.0 MEMORY ORGAN
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PIC18F97J60 FAMILY 5.1.3 PIC18F9XJ6
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PIC18F97J60 FAMILY 5.1.5 PROGRAM CO
- Page 77 and 78:
PIC18F97J60 FAMILY 5.1.6.4 Stack Fu
- Page 79 and 80:
PIC18F97J60 FAMILY 5.2.3 INSTRUCTIO
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PIC18F97J60 FAMILY FIGURE 5-7: DATA
- Page 83 and 84:
PIC18F97J60 FAMILY 5.3.4 SPECIAL FU
- Page 85 and 86:
PIC18F97J60 FAMILY TABLE 5-5: REGIS
- Page 87 and 88:
PIC18F97J60 FAMILY TABLE 5-5: REGIS
- Page 89 and 90:
PIC18F97J60 FAMILY TABLE 5-5: REGIS
- Page 91 and 92:
PIC18F97J60 FAMILY 5.3.6 STATUS REG
- Page 93 and 94:
PIC18F97J60 FAMILY 5.4.3.1 FSR Regi
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PIC18F97J60 FAMILY 5.6.1 INDEXED AD
- Page 97 and 98:
PIC18F97J60 FAMILY 5.6.3 MAPPING TH
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PIC18F97J60 FAMILY 6.0 FLASH PROGRA
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PIC18F97J60 FAMILY REGISTER 6-1: EE
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PIC18F97J60 FAMILY 6.3 Reading the
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PIC18F97J60 FAMILY 6.5 Writing to F
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PIC18F97J60 FAMILY 6.5.2 WRITE VERI
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PIC18F97J60 FAMILY 7.0 EXTERNAL MEM
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PIC18F97J60 FAMILY 7.2 Address and
- Page 113 and 114:
PIC18F97J60 FAMILY 7.6.1 16-BIT BYT
- Page 115 and 116:
PIC18F97J60 FAMILY 7.6.3 16-BIT BYT
- Page 117 and 118:
PIC18F97J60 FAMILY 7.7 8-Bit Data W
- Page 119 and 120:
PIC18F97J60 FAMILY 7.8 Operation in
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PIC18F97J60 FAMILY 8.0 8 x 8 HARDWA
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PIC18F97J60 FAMILY 9.0 INTERRUPTS M
- Page 125 and 126:
PIC18F97J60 FAMILY 9.1 INTCON Regis
- Page 127 and 128:
PIC18F97J60 FAMILY REGISTER 9-3: IN
- Page 129 and 130:
PIC18F97J60 FAMILY REGISTER 9-5: PI
- Page 131 and 132:
PIC18F97J60 FAMILY 9.3 PIE Register
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PIC18F97J60 FAMILY REGISTER 9-9: PI
- Page 135 and 136:
PIC18F97J60 FAMILY REGISTER 9-11: I
- Page 137 and 138:
PIC18F97J60 FAMILY 9.5 RCON Registe
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PIC18F97J60 FAMILY 10.0 I/O PORTS D
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PIC18F97J60 FAMILY TABLE 10-3: PORT
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PIC18F97J60 FAMILY TABLE 10-5: PORT
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PIC18F97J60 FAMILY 10.4 PORTC, TRIS
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PIC18F97J60 FAMILY TABLE 10-8: SUMM
- Page 149 and 150:
PIC18F97J60 FAMILY TABLE 10-9: PORT
- Page 151 and 152:
PIC18F97J60 FAMILY 10.6 PORTE, TRIS
- Page 153 and 154:
PIC18F97J60 FAMILY TABLE 10-11: POR
- Page 155 and 156:
PIC18F97J60 FAMILY TABLE 10-13: Pin
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PIC18F97J60 FAMILY TABLE 10-15: Pin
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PIC18F97J60 FAMILY 10.9 PORTH, LATH
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PIC18F97J60 FAMILY 10.10 PORTJ, TRI
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PIC18F97J60 FAMILY 10.11 Parallel S
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PIC18F97J60 FAMILY FIGURE 10-4: PAR
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PIC18F97J60 FAMILY 11.0 TIMER0 MODU
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PIC18F97J60 FAMILY 11.3 Prescaler A
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PIC18F97J60 FAMILY 12.0 TIMER1 MODU
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PIC18F97J60 FAMILY 12.2 Timer1 16-B
- Page 175 and 176:
PIC18F97J60 FAMILY The Real-Time Cl
- Page 177 and 178:
PIC18F97J60 FAMILY 13.0 TIMER2 MODU
- Page 179 and 180:
PIC18F97J60 FAMILY 14.0 TIMER3 MODU
- Page 181 and 182:
PIC18F97J60 FAMILY 14.2 Timer3 16-B
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PIC18F97J60 FAMILY 15.0 TIMER4 MODU
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PIC18F97J60 FAMILY 16.0 CAPTURE/COM
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PIC18F97J60 FAMILY 16.2 Capture Mod
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PIC18F97J60 FAMILY TABLE 16-2: REGI
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PIC18F97J60 FAMILY The CCPRxH regis
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PIC18F97J60 FAMILY 17.0 ENHANCED CA
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PIC18F97J60 FAMILY TABLE 17-1: PIN
- Page 197 and 198:
PIC18F97J60 FAMILY 17.4 Enhanced PW
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PIC18F97J60 FAMILY FIGURE 17-2: PWM
- Page 201 and 202:
PIC18F97J60 FAMILY 17.4.5 FULL-BRID
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PIC18F97J60 FAMILY FIGURE 17-8: SIG
- Page 205 and 206:
PIC18F97J60 FAMILY REGISTER 17-3: E
- Page 207 and 208:
PIC18F97J60 FAMILY 17.4.9 SETUP FOR
- Page 209 and 210:
PIC18F97J60 FAMILY 18.0 ETHERNET MO
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PIC18F97J60 FAMILY 18.1.4 MAGNETICS
- Page 213 and 214:
PIC18F97J60 FAMILY 18.2.1 ETHERNET
- Page 215 and 216:
PIC18F97J60 FAMILY 18.2.1.2 Receive
- Page 217 and 218:
PIC18F97J60 FAMILY 18.2.2 SFRs AND
- Page 219 and 220:
PIC18F97J60 FAMILY 18.2.4 MAC AND M
- Page 221 and 222:
PIC18F97J60 FAMILY REGISTER 18-6: M
- Page 223 and 224:
PIC18F97J60 FAMILY To read from a P
- Page 225 and 226:
PIC18F97J60 FAMILY REGISTER 18-9: P
- Page 227 and 228:
PIC18F97J60 FAMILY REGISTER 18-12:
- Page 229 and 230:
PIC18F97J60 FAMILY 18.3 Ethernet In
- Page 231 and 232:
PIC18F97J60 FAMILY REGISTER 18-15:
- Page 233 and 234:
PIC18F97J60 FAMILY 18.3.1.1 Receive
- Page 235 and 236:
PIC18F97J60 FAMILY 18.4 Module Init
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PIC18F97J60 FAMILY 18.5 Transmittin
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PIC18F97J60 FAMILY 18.5.2 TRANSMITT
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PIC18F97J60 FAMILY TABLE 18-4: TRAN
- Page 243 and 244:
PIC18F97J60 FAMILY TABLE 18-5: RECE
- Page 245 and 246:
PIC18F97J60 FAMILY TABLE 18-6: Regi
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PIC18F97J60 FAMILY 18.7 Flow Contro
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PIC18F97J60 FAMILY 18.8 Receive Fil
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PIC18F97J60 FAMILY FIGURE 18-12: RE
- Page 253 and 254:
PIC18F97J60 FAMILY 18.8.5 PATTERN M
- Page 255 and 256:
PIC18F97J60 FAMILY 18.9 Direct Memo
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PIC18F97J60 FAMILY 18.10 Module Res
- Page 259 and 260:
PIC18F97J60 FAMILY 19.0 MASTER SYNC
- Page 261 and 262:
PIC18F97J60 FAMILY REGISTER 19-2: S
- Page 263 and 264:
PIC18F97J60 FAMILY 19.3.3 ENABLING
- Page 265 and 266:
PIC18F97J60 FAMILY 19.3.6 SLAVE MOD
- Page 267 and 268:
PIC18F97J60 FAMILY 19.3.8 OPERATION
- Page 269 and 270:
PIC18F97J60 FAMILY 19.4 I 2 C Mode
- Page 271 and 272:
PIC18F97J60 FAMILY REGISTER 19-4: S
- Page 273 and 274:
PIC18F97J60 FAMILY REGISTER 19-6: S
- Page 275 and 276:
PIC18F97J60 FAMILY 19.4.3.2 Address
- Page 277 and 278:
PIC18F97J60 FAMILY FIGURE 19-8: I 2
- Page 279 and 280:
PIC18F97J60 FAMILY FIGURE 19-10: I
- Page 281 and 282:
PIC18F97J60 FAMILY FIGURE 19-12: I
- Page 283 and 284:
PIC18F97J60 FAMILY 19.4.4 CLOCK STR
- Page 285 and 286:
PIC18F97J60 FAMILY FIGURE 19-15: I
- Page 287 and 288:
PIC18F97J60 FAMILY 19.4.5 GENERAL C
- Page 289 and 290:
PIC18F97J60 FAMILY 19.4.6.1 I 2 C M
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PIC18F97J60 FAMILY 19.4.7.2 Clock A
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PIC18F97J60 FAMILY 19.4.9 I 2 C MAS
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PIC18F97J60 FAMILY FIGURE 19-23: I
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PIC18F97J60 FAMILY 19.4.12 ACKNOWLE
- Page 299 and 300:
PIC18F97J60 FAMILY 19.4.17.1 Bus Co
- Page 301 and 302:
PIC18F97J60 FAMILY 19.4.17.2 Bus Co
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PIC18F97J60 FAMILY TABLE 19-4: REGI
- Page 305 and 306:
PIC18F97J60 FAMILY 20.0 ENHANCED UN
- Page 307 and 308:
PIC18F97J60 FAMILY REGISTER 20-2: R
- Page 309 and 310:
PIC18F97J60 FAMILY 20.1 Baud Rate G
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PIC18F97J60 FAMILY TABLE 20-3: BAUD
- Page 313 and 314:
PIC18F97J60 FAMILY 20.1.3 AUTO-BAUD
- Page 315 and 316:
PIC18F97J60 FAMILY 20.2 EUSARTx Asy
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PIC18F97J60 FAMILY TABLE 20-5: REGI
- Page 319 and 320:
PIC18F97J60 FAMILY FIGURE 20-6: EUS
- Page 321 and 322:
PIC18F97J60 FAMILY FIGURE 20-8: AUT
- Page 323 and 324:
PIC18F97J60 FAMILY 20.3 EUSARTx Syn
- Page 325 and 326:
PIC18F97J60 FAMILY 20.3.2 EUSARTx S
- Page 327 and 328:
PIC18F97J60 FAMILY TABLE 20-9: REGI
- Page 329 and 330:
PIC18F97J60 FAMILY 21.0 10-BIT ANAL
- Page 331 and 332:
PIC18F97J60 FAMILY REGISTER 21-3: A
- Page 333 and 334:
PIC18F97J60 FAMILY After the A/D mo
- Page 335 and 336:
PIC18F97J60 FAMILY 21.2 Selecting a
- Page 337 and 338:
PIC18F97J60 FAMILY 21.7 A/D Convert
- Page 339 and 340:
PIC18F97J60 FAMILY 22.0 COMPARATOR
- Page 341 and 342:
PIC18F97J60 FAMILY 22.2 Comparator
- Page 343 and 344:
PIC18F97J60 FAMILY 22.9 Analog Inpu
- Page 345 and 346:
PIC18F97J60 FAMILY 23.0 COMPARATOR
- Page 347 and 348:
PIC18F97J60 FAMILY FIGURE 23-2: COM
- Page 349 and 350:
PIC18F97J60 FAMILY 24.0 SPECIAL FEA
- Page 351 and 352:
PIC18F97J60 FAMILY REGISTER 24-1: C
- Page 353 and 354:
PIC18F97J60 FAMILY REGISTER 24-4: C
- Page 355 and 356:
PIC18F97J60 FAMILY REGISTER 24-6: C
- Page 357 and 358:
PIC18F97J60 FAMILY 24.2 Watchdog Ti
- Page 359 and 360:
PIC18F97J60 FAMILY 24.4 Two-Speed S
- Page 361 and 362:
PIC18F97J60 FAMILY FIGURE 24-5: FSC
- Page 363 and 364:
PIC18F97J60 FAMILY 25.0 INSTRUCTION
- Page 365 and 366:
PIC18F97J60 FAMILY FIGURE 25-1: GEN
- Page 367 and 368:
PIC18F97J60 FAMILY TABLE 25-2: BIT-
- Page 369 and 370:
PIC18F97J60 FAMILY 25.1.1 STANDARD
- Page 371 and 372:
PIC18F97J60 FAMILY ANDWF AND W with
- Page 373 and 374:
PIC18F97J60 FAMILY BNC Branch if No
- Page 375 and 376:
PIC18F97J60 FAMILY BRA Unconditiona
- Page 377 and 378:
PIC18F97J60 FAMILY BTG Bit Toggle f
- Page 379 and 380:
PIC18F97J60 FAMILY CLRF Clear f CLR
- Page 381 and 382:
PIC18F97J60 FAMILY CPFSGT Compare f
- Page 383 and 384:
PIC18F97J60 FAMILY DECFSZ Decrement
- Page 385 and 386:
PIC18F97J60 FAMILY INCFSZ Increment
- Page 387 and 388:
PIC18F97J60 FAMILY LFSR Load FSR MO
- Page 389 and 390:
PIC18F97J60 FAMILY MOVLW Move Liter
- Page 391 and 392:
PIC18F97J60 FAMILY NEGF Negate f NO
- Page 393 and 394:
PIC18F97J60 FAMILY RCALL Relative C
- Page 395 and 396:
PIC18F97J60 FAMILY RETURN Return fr
- Page 397 and 398:
PIC18F97J60 FAMILY RRNCF Rotate Rig
- Page 399 and 400:
PIC18F97J60 FAMILY SUBLW Subtract W
- Page 401 and 402:
PIC18F97J60 FAMILY TBLRD Table Read
- Page 403 and 404:
PIC18F97J60 FAMILY TSTFSZ Test f, S
- Page 405 and 406:
PIC18F97J60 FAMILY 25.2 Extended In
- Page 407 and 408:
PIC18F97J60 FAMILY CALLW Subroutine
- Page 409 and 410:
PIC18F97J60 FAMILY SUBFSR Subtract
- Page 411 and 412:
PIC18F97J60 FAMILY ADDWF ADD W to I
- Page 413 and 414:
PIC18F97J60 FAMILY 26.0 DEVELOPMENT
- Page 415 and 416:
PIC18F97J60 FAMILY 26.7 MPLAB ICE 2
- Page 417 and 418:
PIC18F97J60 FAMILY 27.0 ELECTRICAL
- Page 419 and 420:
PIC18F97J60 FAMILY 27.1 DC Characte
- Page 421 and 422:
PIC18F97J60 FAMILY 27.2 DC Characte
- Page 423 and 424:
PIC18F97J60 FAMILY 27.2 DC Characte
- Page 425 and 426:
PIC18F97J60 FAMILY 27.2 DC Characte
- Page 427 and 428:
PIC18F97J60 FAMILY 27.3 DC Characte
- Page 429 and 430:
PIC18F97J60 FAMILY TABLE 27-1: MEMO
- Page 431 and 432:
PIC18F97J60 FAMILY 27.4 AC (Timing)
- Page 433 and 434:
PIC18F97J60 FAMILY 27.4.3 TIMING DI
- Page 435 and 436:
PIC18F97J60 FAMILY FIGURE 27-5: CLK
- Page 437 and 438:
PIC18F97J60 FAMILY FIGURE 27-7: PRO
- Page 439 and 440:
PIC18F97J60 FAMILY FIGURE 27-9: TIM
- Page 441 and 442:
PIC18F97J60 FAMILY FIGURE 27-11: EX
- Page 443 and 444:
PIC18F97J60 FAMILY FIGURE 27-13: EX
- Page 445 and 446:
PIC18F97J60 FAMILY FIGURE 27-15: I
- Page 447 and 448:
PIC18F97J60 FAMILY FIGURE 27-17: MA
- Page 449 and 450:
PIC18F97J60 FAMILY FIGURE 27-19: EU
- Page 451 and 452:
PIC18F97J60 FAMILY TABLE 27-27: A/D
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PIC18F97J60 FAMILY 28.0 PACKAGING I
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PIC18F97J60 FAMILY © 2008 Micr
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PIC18F97J60 FAMILY © 2008 Micr
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PIC18F97J60 FAMILY © 2008 Micr
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PIC18F97J60 FAMILY © 2008 Micr
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PIC18F97J60 FAMILY APPENDIX A: Revi
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PIC18F97J60 FAMILY INDEX A A/D ....
- Page 467 and 468:
PIC18F97J60 FAMILY Default System C
- Page 469 and 470:
PIC18F97J60 FAMILY Instruction Set
- Page 471 and 472:
PIC18F97J60 FAMILY RH2/A18 ........
- Page 473 and 474:
PIC18F97J60 FAMILY PIR3 (Peripheral
- Page 475 and 476:
PIC18F97J60 FAMILY Time-out Sequenc
- Page 477 and 478:
PIC18F97J60 FAMILY THE MICROCHIP WE
- Page 479 and 480:
PIC18F97J60 FAMILY PRODUCT IDENTIFI