(HEVC) Standard

2011 18th IEEE International Conference on Image Processing
However, due to the existence of the fractional parts of
intercept which are caused by the accumulation of the angle,
the location of the selected reference samples may arise on a
non-integer displacement. This means the displacements of
the five selected samples are discontinuous when predicting
a few rows of pixels in some modes. The discontinuation
phenomenon also explains why an extended array is
developed to refine the reference samples in such modes.
The refinement technique results in the waste of the
memory. In addition, processing latency is increased
because this method requires copying the selected samples
into extended array before prediction.
After summarizing the characteristics of these modes,
we found a simple rule to detect the discontinuation
situation: if the fractional parts of the intercept are nonzero,
and the upper-left corner sample A_L is used as the first
selected reference sample in predicting the first row of a
mode, the discontinuation phenomenon will occur in the rest
rows of the mode where the first selected reference sample
is not A_L. The rule can be implemented by a simple
detecting circuit with a comparator and a counter. After
detecting the rows in this mode, if it is the vertical
directional mode, the reference sample L1 is skipped to as
one of the selected reference samples in five. Likewise, if it
is the horizontal directional mode, the reference sample A1
is skipped.
Obviously, the flexible reference samples selection
technique does not need to project the samples from the side
reference to the main reference which will be used in the
linear interpolation filter. So, it can save memory resources.
In addition, the procedure of detecting the skipped samples
is completed with the procedure of the prediction. Thus, it
can reduce the processing latency compared with the
method copying samples into extended array before
prediction procedure.
4. IMPLEMENTATION RESULT
The proposed architecture is designed by Verilog HDL and
implemented using the TSMC 0.13μm CMOS technology.
Table 3 lists the specifications of VLSI implementation. In
this table, we can observe that the total gate count of the
proposed architecture is 9020. The design can work at the
highest frequency 150MHz.
Table 3. Specifications of VLSI implementation
Technology
TSMC 0.13μm CMOS
Logic Gate Count 9020
Max Operation Freq.
Processing Latency
Average Cycles to Generate a Pixel
150MHz
8 Clocks
1.5 Clocks
By using the novel register array with the correlation
parameters and the flexible reference samples selection
technique, we only need half of the memory resources than
that implemented by the software described. Furthermore, it
is unnecessary to waste time copying the selected samples
into the extended array. All of the predictions can be
finished in 24 clocks with 8 clocks processing latency. It
takes 1.5 clocks to generate a prediction pixel in average.
5. CONCLUSIONS
In this paper, we propose a high efficient uniform VLSI
architecture and a flexible reference samples selection
technique for 4×4 intra prediction in HM. This architecture
integrates the copying circuit and the interpolation circuit
into a uniform circuit to save the hardware resources. The
new samples selection technique can relieve the memory
pressure and reduce the processing latency considerably.
Implementation with TSMC 0.13μm CMOS technology
indicates that the proposed architecture can work at 150
MHz operation frequency and 9020 logic gates acquired.
This architecture can be extended to parts of the 8×8, 16×16,
32×32 and 64×64 intra prediction. So they can share same
logics to improve the utilization.
6. ACKNOWLEDGMENT
The authors are grateful to Ji Zheng Xu and You Zhou for
their valuable discussions.
This work was supported in part by the National Science
Foundation of China under Grants 60736043, 61033004,
61070138, and the Fundamental Research Funds for the
Central Universities of China under Grant K50510020032.
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