1 - Andrzej Materka
1 - Andrzej Materka
1 - Andrzej Materka
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POLITECHNIKA L6DZKA<br />
WYDZIAt ELEKTROTECHNIKI I ELEKTRONIKI<br />
<strong>Andrzej</strong> <strong>Materka</strong><br />
Analog Electronics<br />
Lecture notes<br />
L6dz,1998
QM- 0041 ml&oif<br />
Recenzent / Reviewer<br />
Prof, dr in. Jersgi Ludnski<br />
Sklad komputerowy, przygotowanie rysunkow i przelamanie tekstu /<br />
Computer text-editing, figure artworks, text formatting<br />
Andrgj <strong>Materka</strong><br />
Projekt graficzny okladki / Cover graphics design<br />
Wojtek <strong>Materka</strong><br />
© Copyright by Wydzial Elektrotechniki i Elektroniki Politechniki Lodzkiej<br />
ISBN 83-87202-06-1<br />
Na okladce: Seria dziewi^ciu analogowych ukladow scalonych, z ktorych kazdy pelni<br />
funkcje. sztucznej sieci neuronowej Kohonena. Uklady zaprojektowano w zespole<br />
naukowo-badawczym kierowanym przez Autora w Instytucie Elektroniki Politechniki<br />
Lodzkiej, we wspolpracy z prof. Alexisem De Vosem z Uniwersytetu w Gandawie.<br />
Zostaly one wyprodukowane przez fabryke. ukladow scalonych 'Alcatel' w Belgii. Uklad<br />
sieci Kohonena pozwala na praktyczna. realizacje. idei uczenia nienadzorowanego, m. in.<br />
do celow rozpoznawania obrazow.<br />
Front cover: A lot of 9 analog integrated circuits, each performing the function of<br />
Kohonen-type artificial neural network. The research team led by the Author in the<br />
Institute of Electronics, Technical University of Lodz - in cooperation with Professor<br />
Alexis De Vos of Gent University - has designed the circuits. The 'Alcatel' silicon<br />
foundry in Belgium fabricated the ICs. The Kohonen network implements the idea of<br />
unsupervised learning for pattern recognition - among many other applications.
Contents<br />
1 Introduction, 9<br />
1.1 Signals and Their Spectra, 9<br />
1.2 Analog and Digital Signals, 12<br />
1.3 Electronic-System Block Diagrams, 15<br />
1.4 Information-Processing Electronics Versus Power Electronics, 16<br />
1.5 Behavior of Circuit Components Versus Frequency, 16<br />
1.6 Summary, 17<br />
2 Amplifiers: Behavioral Description, 18<br />
2.1 Basic Concepts, 18<br />
2.2 Cascaded Amplifiers, 22<br />
2.3 Power Supplies and Efficiency, 23<br />
2.4 Decibel Notation, 25<br />
2.5 Frequency Response, 26<br />
2.6 The Miller Theorem, 34<br />
2.7 Linear Distortion, 37<br />
2.8 Pulse Response, 39<br />
2.9 Nonlinear Distortion, 44<br />
2.10 Summary, 46<br />
3 Diode Circuits, 48<br />
3.1 The Ideal Diode, 48<br />
3.2 Terminal Characteristics of Semiconductor Diodes, 52<br />
3.3 Analysis of Diode Circuits, 56<br />
3.4 The Diode Small-Signal Model at Low Frequencies, 61<br />
3.5 Rectifier Circuits, 66<br />
3.6 Zener-Diode Voltage Regulator Circuits, 70<br />
3.7 Wave-Shaping Circuits, 73<br />
3.b Switching and High-Frequency Behavior of thepn Junction, 76<br />
3.9 Special Diodes, 84<br />
3.10 Summary, 86<br />
4 Field-Effect Transistor Circuits, 88<br />
4.1 The »-channel Junction FET, 88<br />
4.2 Metal-Oxide-Semiconductor FETs, 91<br />
4.3 Load-Line Analysis of a Simple JFET Amplifier, 94<br />
4.4 The Self-Bias Circuit, 96<br />
4.5 The Fixed- Plus Self-Bias Circuit, 98<br />
4.6 The Small-Signal Equivalent Circuit, 100<br />
4.7 Basic Small-Signal FET Amplifier Circuits, 103<br />
4.8 The FET as a Voltage-Controlled Resistance, 113<br />
4.9 CMOS Analog Switch, 115<br />
4.10 CMOS Logic Circuits, 116<br />
4.11 FET Dynamic Circuit Model, 121<br />
4.12 Summary, 125<br />
-3-
5 Bipolar Transistor Circuits, 127<br />
5.1 Load-Line Analysis of a Common-Emitter Amplifier, 130<br />
5.2 The pnp Bipolar Junction Transistor, 133<br />
5.3 Secondary Effects, 135<br />
5.4 Large-Signal dc BJT Models, 139<br />
5.5 Large-Signal dc Analysis of BJT Circuits, 141<br />
5.6 Four-Resistor Bias Circuit, 145<br />
5.7 Small-Signal Equivalent Circuits, 149<br />
5.8 The Common-Emitter Amplifier, 150<br />
5.9 The Emitter Follower, 153<br />
5.10 Review of Small-Signal Equivalent Circuit Analysis, 156<br />
5.11 The Common-Emitter Hybrid-Parameter Small-Signal Model, 160<br />
5.12 The Hybrid-* Model, 161<br />
5.13 Bipolar Transistor Behavior at High Frequencies, 164<br />
5.14 Large-Signal Dynamic Model for die BJT, 173<br />
5.15 Switching Behavior of die BJT, 177<br />
5.16 Summary, 181<br />
6 Feedback Circuits, 183<br />
6.1 Effects on Sensitivity, Bandwidth and Distortion, 184<br />
6.2 Feedback Types, 194<br />
6.3 Effect of Feedback Types on Input and Output Impedance, 196<br />
6.4 Summary of the Effect of Various Feedback Types, 198<br />
6.5 Practical Feedback Networks, 199<br />
6.6 Stability of Feedback Amplifiers, 202<br />
6.7 Sinusoidal Oscillators, 205<br />
6.8 Summary, 221<br />
References, 223<br />
Review Questions, 224<br />
Problems, 230<br />
Appendix<br />
A. Nominal Values and the Color Code for Resistors, 256<br />
B. Introduction to PSpice, 258<br />
C. English-Polish Dictionary of Selected Terms, 266<br />
D. Manufacturers' Date Sheets for 2N2222A transistor, 272<br />
-4-
Przedmowa / Preface<br />
Niniejszy skrypt powstal w wyniku zebiania i uporzajikowania notatek z wykladow<br />
Analog Electronics oraz Electronic Devices and Systems, ktore mialem przyjemnosc<br />
prowadzic w Politechnice Lodzkiej dla kilku grup studenckich IFE (International Facility<br />
of Engineering) w latach 1995-1997. Opisuje. w nim zasady dzialania i wlasciwosci<br />
podstawowych ukiadow elektronicznych - analogowych.<br />
Zakres materialu opisanego w skrypcie w niewielkim jedynie stopniu obejmuje olbrzymia,<br />
rozmaitosc znanych ukiadow elektronicznych. Staralem si zawrzec w nim informacje<br />
podstawowe, zdefiniowac terminologie. i omowic elementarne obwody zawieraja.ce diody,<br />
tranzystory polowe, bipolarne a takze obwody ze sprzzeniem zwrotnym. Oprocz<br />
wiadomosci teoretycznych i przykladow symulacji komputerowych skrypt zawiera<br />
cwiczenia rachunkowe, ktore pozwalajq. na ilosciowe zilustrowanie wlasciwosci ukiadow,<br />
a w niektorych przypadkach lepsze zrozumieiiie zalozeri projektowych. Pytania<br />
powtorkowe zwracaj% uwage na zasadnicze elementy tresci merytorycznej<br />
poszczegolnych rozdzialow i moga. bye pomocne w porza_dkowaniu wiedzy przed<br />
egzaminem.<br />
Program studiow inzynierskich w IFE zawiera zmniejszona^ liczbe. godzin zajee z<br />
ukiadow elektronicznych w porownaniu ze studiami magisterskimi na Wydziale<br />
Elektrotechniki i Elektroniki PL. Dla lepszego wykorzystania przydzielonych limitow<br />
czasowych i zwikszenia skutecznosci przekazu wiedzy, wyklady swoje ilustrowaiem<br />
dose obficie przyktadami obhezen za pomoca. programu SPICE. W tym celu<br />
prowadzilem wyklady w laboratorium komputerowym, w ktorym kazdy ze studentow<br />
mogl samodzielnie realizowac symulacje omawianych ukiadow. Ta forma zajec<br />
dydaktycznych dowiodla swojej uzytecznosci i jest godna polecenia innym,<br />
zainteresowanym wykladowcom. Przyklady wybranych programow w jzyku SPICE<br />
zawarlem w skrypcie. Zachecam Czytelnikow do korzystania z tych przykladow, a takze<br />
do pisania wlasnych programow i wykonywania symulacji ukiadow. Symulacje takie nie<br />
moga. zastapic, bez wa_tpienia, doswiadczeri praktycznych i pomiarow rzeczywistego<br />
obwodu. Sa_ one jednak mniej kosztowne, trwaj% krocej, a w przypadku projektowania<br />
ukiadow scalonych sa. jedyna. forma, sprawdzania poprawnosci projektu przed faza.<br />
realizacji. Zainteresowanym mog udostpnic darmowa. edukacyjna_ wersje. programu<br />
PSpice (dwie dyskietM 3.25"). Przy tej okazji chcialbym podziekowac Wydawnictwu<br />
Prentice Hall, ktore przyslalo mi ten program wraz z ksia^zka. [12] do oceny, kiedy<br />
pracowalem jako wykladowca w Monash University w Australii.<br />
Z faktu, iz studenci IFE — sluchacze moich wykladow — z niecierpliwoscia. pytali o<br />
kolejne porcje notatek wnosz, ze napisanie skryptu bylo potrzebne. Wypelnia on<br />
okreslona. iuk w krajowym pismiennictwie akademickim, dotyczaca. zwlaszcza<br />
materialow optacowanych w jezykach obcych, co jest szczegolnie wazne w okresie<br />
otwierania si Polski na swiat Z drugiej strony, polskojzyczni studenci IFE powinm<br />
miec mozliwosc zapoznania si z rodzima. terminologie w dziedzinie ich studiow. Na ich<br />
potrzeby opracowalem slownik angielsko-polski terminow uzywanych w skrypcie,<br />
zawarty w Dodatku. Trzeba podkreslic, ze lektura niniejszego skryptu nie moze zastaj>ic<br />
prawdziwie poglbionych studiow przedmiotu. W tym celu odsylam Czytelnikow do<br />
-5-
dziel obszetniejszych, z ktotych kotzystalem przygotowujajc notatki do moich wykladow.<br />
List tych prac zawieta spis literatury.<br />
Na koniec chc zaznaczyc, ze optacowanie niniejsze nie mogloby powstac gdyby moja<br />
Zona i moj Syn nie zgodzili si na to, abym 30 weekendow toku 1997 spdzil z edytotem<br />
tekstu. Setdecznie Im za to dziekuj. Jestem towniez wdziczny Dziekanowi Wydzialu<br />
Elekttotechniki i Elekttoniki Politechniki Lodzkiej, Panu Ptofesotowi Doktotowi Janowi<br />
Leszczyriskiemu za ufundowanie honotatium, ktote pozwoli mi na modetnizacj mojego<br />
komputeta. Dziki temu zmniejsz troch dystans do czolowki tego fascynuja.cego i<br />
ptzeiazaja_cego wyscigu powszechniej komputetyzacji, u ktoiej podstaw znajduje si<br />
postp w dziedzinie elekttoniki. No doubts it is...<br />
Zycz Panstwu ptzyjemnej i owocnej lektuty -<br />
<strong>Andrzej</strong> <strong>Materka</strong>.<br />
Lodz, wlutym 1998.
Preface / Przedmowa<br />
This textbook is a systematized collection of the notes of lectures that I had a pleasure to<br />
deliver in 1995-1997 to a number of student groups at the International Faculty of<br />
Engineering (IFE), Technical University of Lodz. It describes the principle of operation<br />
and properties of basic analog electronic circuits.<br />
The material included in this textbook covers the huge variety of known electronic<br />
circuits to a very limited degree only. I have made efforts to introduce fundamental<br />
concepts, define terminology, and discuss elementary circuits that comprise diodes, fieldeffect<br />
and bipolar transistors, as well as circuits with feedback. Besides the theory and<br />
computer simulation examples, the lecture notes include problems and exercises for the<br />
student, which help quantitatively illustrate various circuit properties and provide better<br />
understanding of design specifications in some cases. Review questions'provided turn the<br />
reader's attention to essential elements of the theory presented in individual chapters;<br />
they can be helpful to sort things out before exams.<br />
The 4-year BEng study program at IFE allows less class time for Analog Electronics than<br />
the 5-year MSc studies at the TUL's Faculty of Electrical and Electronic Engineering do.<br />
To make better use of the student contact-hours allocated, I kept amply illustrating my<br />
lectures with computer simulation examples, using the SPICE program. To achieve that,<br />
a computer laboratory was chosen to be the place to give the lectures, where almost<br />
every listener had an access to a PC terminal to individually exercise the virtual<br />
experiments with the circuits under study. This form of carrying on the teaching has<br />
proven its usefulness and deserves recommendation to other interested lecturers. I<br />
integrated examples of the SPICE code with the text of the lecture notes. I encourage<br />
the readers to use these examples and to write their own programs for circuit simulation.<br />
Simulations can not, of course, replace practical experiments and measurements of<br />
physical circuits. They are, however, less expensive, last shorter, and in the case of<br />
integrated circuits are the only means of verifying the circuit correctness before its<br />
fabrication. The interested readers can copy a free educational version of the PSpice<br />
program (two 3.5 inches floppies) from my resources. On this occasion I wish to thank<br />
the Prentice Hall publishing house representative who sent me this program along with<br />
the book [12] for evaluation when I was with Monash University, Melbourne, Australia,<br />
working as a lecturer.<br />
From the fact that IFE students - the listeners to my lectures — kept impatiently asking<br />
me about consecutive printouts of the lecture notes I gather writing the textbook was<br />
needed. It fills up a gap in the country's academic literature that concerns especially<br />
foreign-language material that is particularly important in the period of Poland's opening<br />
to the outside world. On the other hand, those of students who are Polish native<br />
speakers should be given an opportunity to familiarize with their mother-tongue<br />
terminology in the field of their studies. I then elaborated a short English-Polish<br />
dictionary of selected terms utilized in the textbook, which is included in the Appendix.<br />
It should be emphasized that reading this textbook can not replace truly thorough studies<br />
of ^he subject. To do such studies, I recommend the readers to refer to more extensive<br />
-7-
ooks that I used to prepare the lecture notes. The list of these works is provided at the<br />
end of the text<br />
Finally, I wish to point out that this textbook would not appear if my wife and my son<br />
would not agree that I might spend 30 week-ends in 1997 with the text editor. I do<br />
sincerely thank them for this opportunity. I am also grateful to the Dean of the Faculty<br />
of Electrical and Electronic Engineering, Professor Jan Leszczynski, for founding a<br />
scholarship that will help upgrade my computer. Then I will be able to cut a litde bit die<br />
distance to the leaders of the fascinating and frightening race of widespread<br />
computerization that is actually based on the progress in electronics. Bez wa.tpienia tak<br />
jest...<br />
I wish you enjoyable and fruitful reading,<br />
Lodz, in February 1998.<br />
<strong>Andrzej</strong> <strong>Materka</strong>.
Analog Electronics /Introduction<br />
1. Introduction<br />
In these lecture notes we shall study electronic devices and their interconnections that form discrete<br />
or integrated circuits (ICs). These circuits are devised to perform a variety of functions within<br />
electronic systems' of interest The well-known examples of contemporary electronic systems are<br />
Walkman radio, TV set, PC computer, TV satellite receiver, computerized monitors for patients in<br />
intensive-care units, cellular phones, and the like. There exist also a variety of complex systems,<br />
which do not operate based mainly on electrons' movement but nevertheless would not function<br />
properly without an embedded electronic circuitry. These include aircraft, photocopying machines,<br />
weather satellites, etc. Electronic systems control fuel mixture and ignition timing to maximize<br />
performance and minimize undesirable emissions from automobile engines. It is in fact impossible<br />
to overestimate the role of electronics in the modem society. Perhaps there is no human activity<br />
area, ranging from daily life to space exploration, in which we don't utilize the electronic devices.<br />
The foundations of electronics were established by the observations of M. Faraday (1791-1867) and<br />
the discovery of electron by J. J. Thomson in 1897, but its development proceeded relatively slowly<br />
until the importance of radar became apparent at the beginning of World War II. During that<br />
period and extending until about 1955, the expanding field of electronics depended heavily on the<br />
principle of electron emission from the hot cathode of a vacuum tube. By modern standards,<br />
vacuum tube electronics was expensive, bulky, hot, unreliable and even dangerous because of the<br />
high voltages present in the tubes. With the discovery of the transistor by J. Bardeen, W. H. Brittain<br />
and W. B. Schockley in 1948, the stage was set for the solid-state electronics explosion of today.<br />
This technological explosion is often compared to the industrial revolution.<br />
Since the invention of transistor the technology has progressed from an individually prepared<br />
laboratory device (a tube) to millions of components (diodes, transistors) on a single silicon wafer<br />
only a millimeter a side. Coupled with this astounding miniaturization has been a corresponding<br />
decrease in the price per component For example, a current popular microcomputer chip,<br />
containing more than one million components, costs about the same as one of the electron tubes of<br />
earlier electronics. At the same time, with the increased internal complexity and overall functionality<br />
of solid- 1 tate chips, the number of external components is highly reduced as compared to vacuum<br />
tube electronic circuits. Also, the temperature of device operation is decreased. These two main<br />
factors lead to a much higher reliability of solid state electronic systems.<br />
1.1 Signals and Their Spectra<br />
The main function of most electronic circuits is either to process or to generate signals. Signals<br />
contain information about a variety of things in our physical world. For example, information about<br />
the weather is contained in signals that represent the air temperature, pressure, the wind speed, etc.<br />
The voice of a radio announcer reading the news into the microphone provides an acoustic signal<br />
that carries information about world affairs. To monitor and diagnose the status of the human<br />
body, biopotentials are measured on the surface of the skin to represent the activities of the heart<br />
(ECG - the electrocardiogram), the brain (EEG - electroencephalogram), the muscles (EMG -<br />
electromyogram) and others.<br />
Processing of signals is needed to extract information from them, for an observer (be it a human or<br />
a machine). Electronic circuits and systems most conveniently perform the signal processing. For<br />
this to be possible, the signals, which are not originally in the form of an electrical signal, must first<br />
-9-
Analog Electronics /Introduction<br />
be converted into a voltage or current Devices known as transducers accomplish this process. A<br />
variety of transducers exist, each suitable for one of the various forms of physical signals. For<br />
instance, a microphone is in effect a pressure transducer. It is not our purpose here to study<br />
transducers; rather, we shall assume that the signals of interest already exist in the electrical domain.<br />
For the purpose of our study the signals will be represented by one of the equivalent forms shown<br />
in Fig. 1.1. In Fig. 1.1(a) the signal is represented by a voltage source v//) having a source resistance<br />
R r In the alternate representation of Fig. 1.1(b), the signal is represented by a current source /,(/)<br />
having a source resistance R r Although the two representations are equivalent, the one shown in<br />
Fig. 1.1(a) (known as the Thevenin form) is preferred when R, is low. The representation of Fig.<br />
1.1(b) (known as the Norton form) is preferred when R s is high.<br />
From the discussion above it should be apparent that a signal is a time-varying quantity that can be<br />
represented by a graph such as those shown in Fig. 1.2. In fact, the information content is<br />
represented in changes in signal magnitude as time progresses. The overall level of the magnitude is<br />
one of the signal characteristic features. Table 1.1 gives examples of the range of magnitudes of<br />
different signals. In general, waveforms are difficult to characterize mathematically. In other words,<br />
it is difficult to describe succincdy an arbitrary looking waveform, such as one of those of Fig. 1.2.<br />
TABLE 1.1<br />
MAGNITUDE AND INTERNAL RESISTANCE OF SELECTED SIGNAL SOURCES<br />
SIGNAL SOURCE<br />
RANGE OF INTERNAL RESISTANCE<br />
MAGNITUDES<br />
ECG
Analog Electronics /Introduction<br />
The essential parts of the spectra of practical signals are usually confined to relatively shon<br />
segments of the frequency axis. For instance, die spectrum of audible sounds such as speech and<br />
music extends from about 20Hz to about 20kHz - a frequency range known as die audio band.<br />
This observation is very useful in the processing of such signals and important for electronic circuit<br />
designers. This is because the properties of signal processing circuits have to match the signal<br />
properties. For example, there is no point in amplifying the signal in the frequency range in which<br />
there is no signal component of significant energy. This would mean amplification of noise and<br />
interference, which corrupt the information. Sometimes the range of frequencies occupied by a<br />
signal can be changed. In radio communication, this is done so that different transmitter occupies<br />
-11-
Analog Electronics /Introduction<br />
different frequency ranges. Then a receiver can separate the desired signal from the others by the<br />
use of frequency-selective electrical circuits called filters.<br />
When we approach the design of an electronic circuit to process a signal, one of our first questions<br />
should be "What is the frequency range of the signal" For example, we will see that ICs known as<br />
operational amplifiers can be very useful but they are limited to fairly low frequencies, usually below<br />
1MHz. If we need an amplifier for Channel 10 television we can rule out the use of operational<br />
amplifiers. Table 1.2 provides examples of the frequency ranges of some signals of practical interest.<br />
We conclude this section by noting that a signal can be represented either by the manner its<br />
waveform varies with time or in terms of its frequency spectrum. The two alternative<br />
representations are known as the time-domain and the frequency-domain representations,<br />
respectively. The frequency representation of a signal v(t) will be denoted by the symbol V(o>).<br />
TABLE 1.2<br />
FREQUENCY RANGES OF SELECTED SIGNALS<br />
SIGNAL<br />
Electrocardiogram<br />
Audible sounds<br />
Video signals<br />
AM radio broadcasting<br />
TV broadcasting<br />
FM radio broadcasting<br />
GSM cellular phone<br />
Satellite TV broadcasting<br />
FREQUENCY RANGE<br />
0.05-100Hz<br />
20 Hz-20kHz<br />
0-6 MHz<br />
150- 285kHz (LW)<br />
525 - 1600kHz (MW)<br />
48.5 - 56.5MHz (channel 1 VHF)<br />
222 - 230MHz (channel 12 VHF)<br />
470 - 478 MHz (channel 21 UHF)<br />
790 - 798MHz (channel 61 UHF)<br />
66 - 73MHz, 87.5 - 108MHz<br />
890 - 915MHz, 935 - 960MHz<br />
11.7 - 12.5GHz<br />
1.2 Analog and Digital Signals<br />
The voltage waveforms depicted in Fig. 1.2 are analog signals. The name derives from the fact<br />
that such a signal is analogous to the physical signal that it represents. The analog signal is a<br />
continuous function of time. Its magnitude can take on any value. Electronic circuits that process<br />
such signals are known as analog circuits. A variety of analog circuits will be studied in this<br />
subject.<br />
An alternative form of signal representation is that of sequence of numbers, each number<br />
representing the signal magnitude at an instant of time. The resulting signal is called a discrete-time<br />
signal or, shortly, discrete signal The signal is converted from analog to discrete form in the<br />
process of sampling. This process is illustrated in Fig. 1.4. The time instants t v /„ /,... are marked<br />
along the time axis. The magnitude of the signal is measured (sampled) at each of these time<br />
instants.<br />
Yet another useful form of signal representation is that of digital signal. It is obtained from a<br />
discrete signal by encoding the magnitude of signal samples with the use of finite-word-length<br />
binary code. In the example shown in Fig. 1.4, each sample value is represented by a 3-bit code<br />
word, corresponding to the amplitude zone into which the sample falls. Each sample value is<br />
converted into a code word, which in turn can be represented by a digital two-level waveform as<br />
shown in the lower panel of the figure. The digital signal is thus a sequence of encoded numbers.<br />
-12-
Analog Electronics /Introduction<br />
The circuit for conversion of signals in this manner is called an analog-to-digital converter<br />
(ADC). Conversely, a digital-to-analog converter (DAQ converts digital signals back to analog<br />
form. Now if we represent the magnitude of each of the signal samples in Fig. 1.4 by a number<br />
having a finite number of digits, then the signal magnitude will no longer be continuous; rather, it is<br />
said to be quantized or digitized. The resulting digital signal then is simply a sequence of gn^n^iypH<br />
numbers that represents the magnitudes of the successive signal samples.<br />
An example of analog, discrete and digital signal for a real world ECG waveform is shown in Fig.<br />
1.5. Please note that the discrete signal of Fig. 1.5(b) is defined only at the sampling instants. It no<br />
longer is a continuous function of time. However, since the magnitude of each sample can take any<br />
value in a continuous range, a discrete signal is still an analog signal. Perfect (error-free)<br />
reconstruction of analog signal is possible given the discrete-time signal, provided it has been<br />
sampled at sufficiendy high rate. Obviously, there is no way to recover the original analog signal<br />
from the digital signal. We will discuss these issues in more detail below.<br />
1.5<br />
1<br />
0.5<br />
0<br />
vffltmV]<br />
*5,<br />
0 0.1 0.2 0.3 0.4<br />
tim*[s)<br />
0.5 0.6 0.7 0.8<br />
'l.5<br />
v(n) [mV]<br />
10 20 30 40 50 60 70 80<br />
sampling instance indax, n<br />
Figure 1.5 Sampling of continuous-time analog signal (upper panel) results in the discrete-time signal (lower<br />
panel). Quantization of the discrete signal produces the following sequence of numbers:<br />
{0,0,5,11,14,14,11,7,4,1,0,1,1,1,2,3,3,3,3^6^0,51,90,105,77,27,-12,-28,-24,-10,<br />
-2,1,1,1,0,0,0,0,0,0,1,2,3,4,5,7,8,10,11,12,12,14,18^2^6,31,36,41,46,51,55,56,57,57,<br />
56,54,49,43,36,29,23,17,12,8,5,2,1,0,0} which represents the digital signal.<br />
The rate at which a signal must be sampled depends on the frequency content of the signal If a<br />
signal contains no components with frequencies higher than fy, the signal can be exacuy<br />
-13-
Analog Electronics /Introduction<br />
reconstructed from its samples, provided that the sampling rate is selected to be more than twice f b .<br />
(This is known as Shannon-Kotelnikov theorem.) For example, audio signals have a highest<br />
frequency of less than 20kHz. Therefore, the minimum sampling rate that should be used for audio<br />
signals is 40 kHz. Practical considerations require selection of a sampling frequency somewhat<br />
higher than the theoretical minimum. For instance, audio compact-disc technology converts audio<br />
signals to digital form with a sampling rate of 44.1kHz. Naturally, it is desirable to use the lowest<br />
practical sampling rate to minimize the amount of data (in the form of code words) to be stored,<br />
transmitted or manipulated.<br />
The second consideration important in converting analog signals to digital form is the number of<br />
magnitude zones to be used. Exact signal amplitudes cannot be represented, because all amplitudes<br />
falling into a given zone have the same code word. Thus, when a DAC converts the code words to<br />
form the original analog waveform, it is only possible to reconstruct an approximation to the<br />
original signal - the reconstructed voltage is constant within each zone. This is illustrated in Fig. 1.6.<br />
Thus some quantization error exists between the original signals and the reconstruction. Using a<br />
large number of zones can reduce this error, which requires a longer code word for each sample<br />
The number N of amplitude zones is related to the number of bits k by<br />
N = 2* (1.1)<br />
Thus if we are using an 8-bit {k=S) ADC, there are N=f—256 amplitude zones. In compact-disc<br />
technology, 16-bit words are used to represent sample values. With this number of bits, it is rather<br />
difficult for a listener to detect the effects of quantization error on the reconstructed audio signal.<br />
Reconstruction<br />
CMfclMtftiS I .—Analog signal<br />
jj I \ 1^ I Quantisation<br />
" *^I/ / *" ~ error<br />
,p - f- - t- - i Y<br />
Figure 1.6 Quantization error occurs when analog signal is reconstructed from its digital form<br />
Electronic circuits that process digital signals are called digital circuits. The digital computer is a<br />
system constructed mostly of digital circuits. Digital processing of signals has become quite popular<br />
primarily because of the tremendous advances made in the design and fabrication of digital circuits.<br />
Digital processing of signals is economic and reliable. Furthermore it allows a wide variety of<br />
processing functions to be performed - functions that are either impossible or impractical to<br />
implement by analog means. Nevertheless, most of the signals in the physical wodd are analog<br />
Also, there remain many signal-processing tasks that are best performed by analog circuits. They<br />
refer especially to high-frequency signals, but apply even to digital circuits themselves, which in fact<br />
are analog dynamical systems that we interpret as digital ones. It follows that a good electronics<br />
engineer must be proficient in both forms of signal processing. Such is the philosophy adopted in<br />
the contemporary electronic engineering study programs.<br />
The advantages of digital electronics are either coming through the use of digital electronics or are<br />
related to limitations of analog electronics. They are listed below.<br />
(1) Advantages of digital signal processing that originate in the features of digital electronic systems<br />
• flexibility (digital circuits are programmable),<br />
• lower sensitivity to external (e.g. temperature) and internal (e.g. aging and drift) effects,<br />
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Analog Electronics /Introduction<br />
• accuracy can be controlled by selecting the word length to represent signal samples,<br />
• circuits are reproducible (no trimming or tuning during manufacture),<br />
• circuits are easier to manufacture in IC technology (no large Ls or Cs).<br />
(2) Advantages of digital signal processing related to limitations of analog electronics<br />
• "ideal memory" to store signals for an infinite time is possible with the digital techniques;<br />
thus very low frequency signals can be processed with no need for .large Ls and Cs,<br />
• linear phase filters - not available in analog electronics,<br />
• circuits for exact compensation of two effects,<br />
• adaptive systems,<br />
• precise signal transforms,<br />
• possibility of processing 2D signals (images).<br />
The main disadvantages of digital electronics are as follows:<br />
• more supply power required (passive digital circuits do not yet exist),<br />
• restricted to low-frequency applications,<br />
• when used in analog environment, often complex AD and DA converters are required<br />
• difficulties with AD and DA conversion of very weak and very strong signals;<br />
complicated analog pre- and post-amplifiers are required in such cases,<br />
• the same information (e.g. music signal) requires larger bandwidth as a digital signal than<br />
it does as the analog one.<br />
The analog circuits are<br />
• less accurate,<br />
• sensitive to noise,<br />
• advantageous for high-frequency, small- and large-signal applications.<br />
Modem and future systems contain both analog and digital circuits. We call them mixed-sigi* «J<br />
systems.<br />
1.3 Electronic System Block Diagrams<br />
Electronic systems are composed of subsystems or functional blocks. These functional blocks can<br />
be categorized as amplifiers, filters, signal sources, wave-shaping circuits, digital logic<br />
circuits, power supplies and converters. Briefly, we can say that amplifiers increase the power<br />
level of signals, filters separate desired signals from undesired signals and noise, signal sources<br />
generate waveforms such as sinusoids or square waves, wave-shaping circuits change one waveform<br />
into anomer (sinusoid to square wave, for example), power supplies provide necessary dc (direct<br />
current) power to the other functional blocks, and converters change signals from analog form to<br />
digital form, or vice versa. In section 1.6 we will consider the external characteristics of amplifiers in<br />
some detail.<br />
The block diagram of a typical AM radio is shown in Fig. 1.7, as an example of a simple electronic<br />
system. Notice that mere are three amplifiers and two filters. The local oscillator is an example of a<br />
signal source, and a peak detector is a special case of wave-shaping circuit The complete system<br />
description would include detailed specification of each block. For example, the gain, input<br />
impedance, output impedance, the bandwidth (range of frequencies where the gain does not drop<br />
below a specified value) of each amplifier would be given. (We define these terms later in uiis<br />
chapter.) Each functional block in turn consists of a circuit composed of resistors, capacitors,<br />
transistors, integrated circuits, inductive coils, and other devices.<br />
-15-
Analog Electronics /Introduction<br />
The main goal of this text is to introduce basic electronic circuits comprising diodes, bipolar<br />
transistors, field-effect transistors and opamps, in terms of their function and principle of operation.<br />
At present, due to the ever-increasing complexity of electronic circuits and systems, no circuit can<br />
be designed properly without the use of computers and adequate CAD software. We will then use<br />
one of the most popular programs for circuit simulation, called PSpice, to investigate the properties<br />
of the circuits under study. This approach, integrating the theory and simplified mathematical<br />
analysis with computer laboratory exercises will, we hope, prepare the readers for the circuit design<br />
methodologies they will "encounter as practicing engineers. A set of practical laboratory exercises is<br />
provided also to further strengthen the knowledge and to familiarize with measurement techniques<br />
typical for low-frequency analog electronics.<br />
1.4 Information-Processing Electronics versus Power Electronics<br />
Many electronic systems fall into one or more of the following categories: communication systems,<br />
medical electronics, instrumentation, control systems, and computer systems. A unifying aspect of<br />
these categories is that diey all involve collection and processing of information-bearing signals.<br />
Thus the primary concern of many electronic systems is to extract, store, transport or process<br />
information in a signal.<br />
Often, systems are also required to deliver substantial power to an output device. Certainly, this is<br />
true in an audio system for which power must be delivered to a speaker to produce the desired<br />
sound level A cardiac pacemaker uses information extracted from the electrical signals produced by<br />
the heart to determine when to apply a stimulus in the form of a minute pulse of electricity to<br />
ensure proper pumping action. Although the output power of a pacemaker is very small, it is<br />
necessary to consider the efficiency of its circuits to ensure long battery life.<br />
Many systems are concerned mainly with the power content of signals rather than information. For<br />
example, we might want to deliver ac (alternating current) electrical power, converted from dc<br />
supplied by batteries, to a computer even when the ac line power fails.<br />
1.5 Behavior of Circuit Components versus Frequency<br />
The way that a component behaves and the theoretical model we must use to represent it depend<br />
on the frequency of operation. For example, a simple 1000Q resistance can model the 1000Q-<br />
0.25W carbon-film resistor at frequencies of a few kilohertz, but at several hundred megahertz the<br />
more complex circuit model shown in Fig. 1.8 is needed for good accuracy. The small capacitance<br />
in parallel with the resistance has such a high impedance at low frequencies that it can be neglected.<br />
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Analog Electronics /Introduction<br />
However, it cannot be neglected at high frequencies. Similarly, the inductance has very low<br />
impedance and can be neglected at low frequencies. (The inductance is associated with the magnetic<br />
field surrounding the leads when current flows in the resistor. Thus the exact inductance value<br />
depends on die length of the wire leads used in making connection to the remainder of the circuit.)<br />
We see later that the circuit models used for transistors at high frequencies include capacitances that<br />
can be neglected at low frequencies.<br />
•A/W<br />
1000 ohm<br />
w<br />
nH<br />
Figure 1.8 Circuit model for a 1000ft 0.25W carbon-film resistor<br />
Even the construction methods for a circuit depend on its operating frequency range. Many circuits<br />
intended to operate at low frequencies, say below 100 kHz, can be constructed by plugging<br />
individual components into a prototype board and wiring them together without much regard to<br />
the length of connecting wires or the distance between them. On the other hand, circuits intended<br />
to operate at several hundred megahertz must be carefully constructed with regard to the layout and<br />
lead length.<br />
It is somewhat difficult to make a definite boundary between "low" frequencies for which stray<br />
inductance and capacitance are not troublesome and "high" frequencies, for which they must be<br />
considered. In a high-impedance circuit for which the components have impedance of several<br />
megaohms or more, stray capacitance will be significant at lower frequencies than for a lowerimpedance<br />
circuits with impedance less than 100Q. In general, however, we do not need to<br />
consider stray wiring effects below about 100kHz. Usually, we must take them into consideration<br />
above about 10MHz.<br />
1.6 Summary<br />
Main function of electronic circuits is to process or generate signals. Either the Thevenin form or<br />
the Norton form can represent an electrical signal source. The sine-wave signal is completely<br />
characterized by its peak value (or rms value which is the peak/ V2 ), its frequency, and its phase<br />
with respect to an arbitrary reference time. A signal can be represented either by its waveform<br />
versus time, or as a sum of sinusoids. The latter representation is known as the frequency spectrum<br />
of the signal. Analog signals have magnitudes that can assume any value. Electronic circuits that<br />
process analog signals are called analog circuits. Sampling the magnitude of an analog signal at<br />
discrete instants of time and representing each signal sample by a number, results in a digital signal.<br />
Digital signals are processed by digital circuits. Modem and future systems contain both analog and<br />
digital circuits. Systems are composed of subsystems or functional blocks. The functional blocks are<br />
signal sources, amplifiers, niters, wave-shaping circuits, digital logic circuits, power supplies and<br />
converters. Electronic systems fall into the category of either information-processing or powerprocessing<br />
electronics. Any electronic system is made up of components (resistors, capacitors,<br />
inductors, semiconductor devices, etc.). Electrical properties of components depend on the signal<br />
frequency.<br />
BIBLIOTEKA GtOWNA PL<br />
W36^ S<br />
I<br />
-17-
Analog Electronics /Amplifiers<br />
2 Amplifiers: Behavioral Description<br />
In this chapter we introduce most important functional blocks that are employed in almost every<br />
electronic system, namely signal amplifiers. We will define specifications and characteristics of<br />
amplifiers, which describe their behavior as seen by an external observer. In this system-like<br />
approach we will not discuss internal structure of amplifiers, leaving this topic for the later chapters.<br />
2.1 Basic Concepts<br />
Signal amplification is conceptually the simplest signal-processing task. The need for amplification<br />
arises because transducers provide signals that are said to be "weak", that is in the microvolt (uV)<br />
and millivolt (mV) range. An example is a signal from a microphone, which is of about lmV peak<br />
as one speaks to this transducer. Such a weak signal cannot produce any noticeable acoustic effect if<br />
used to drive a loudspeaker. Much stronger signal is needed for a loudspeaker in order to obtain a<br />
louder version of the sound entering the microphone. Thus the signal from the microphone is used<br />
as the input to an amplifier with a voltage gain of 10000 to produce an output signal which is a peak<br />
value of 10 V. This "strong" signal is applied to the loudspeaker which produces a loud replica of<br />
the microphone's input.<br />
The concept of signal amplification is illustrated in Fig. 2.1. The signal source produces a signal t\(t)<br />
that is applied to the input terminals of the amplifier, which generates an output signal<br />
v o (0 = 4,v,(0 (2-1)<br />
across the load resistance R L connected to the output terminals. The constant A^ is called the<br />
voltage gain of the amplifier. Often, the voltage gain is much larger than unity, but we will see later<br />
that useful amplification can take place even if the magnitude of A, is less than unity.<br />
Sometimes A^ is a negative number, so the output voltage is an inverted version of the input, and<br />
he amplifier is then called an inverting amplifier. On the other hand, if A^ is a positive number,<br />
we have a noninverting amplifier. These notions are illustrated in Fig. 2.2.<br />
Equation (2.1) is a linear relationship; hence the amplifier it describes is a linear amplifier. A linear<br />
amplifier does not introduce any distortions to sinusoidal amplified signals. The output signal is an<br />
exact replica of the input, except of course for having larger amplitude (and possibly a nonzero<br />
phase shift with respect to the input, which is discussed in Section 2.6). Linearity is the muchneeded<br />
feature of amplifiers so that the information contained in die signal is not changed and no<br />
new information is introduced. Any change in waveform is considered distortion and is obviously<br />
undesirable.<br />
-18-
Analog Electronics/Amplifiers<br />
Figure 2.2 Input signal to an amplifier (upper panel), output signal of a noninverting amplifier of gain A, =8,<br />
output signal of an inverting amplifier of gain A y =-8\<br />
The signal amplifier is a two-port network. This is clearly seen in Fig. 2.1 where the two input<br />
terminals are distinct to the two output terminals. A more common situation however is illustrated<br />
in Fig. 2.3 where a common terminal exists between the input and the output The common<br />
terminal is used as a reference point and is called the circuit ground.<br />
Figure 2.3 An amplifier with a common terminal (ground) between the input and the output ports.<br />
Voltage amplification can be modeled as a voltage controlled voltage source as illustrated in Fig. 2.4.<br />
Because real amplifiers draw some current from the signal source, a realistic model of an amplifier<br />
must include a resistance r\ across the input terminals. Furthermore, a resistance R^ must be<br />
included in series with the output terminals to account for the fact that the output voltage of an<br />
amplifier is reduced when load current flows.<br />
The input resistance R; of the amplifier is the equivalent resistance seen when looking into the<br />
input terminals. As we will find later, the input circuitry can sometimes include capadttve and<br />
inductive effects, and we would then refer to the input impedance. For example, the input<br />
amplifier of a typical oscilloscope has input impedance containing a 1-Mfi resistance in parallel with<br />
a 47-pF capadtance.<br />
Figure Z4 Model of an electronic amplifier<br />
The voltage-controlled voltage source in Fig. 2.4 models the amplification properties of the<br />
amplifier. Notice that the voltage produced by this source is the input voltage times a constant A°.<br />
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Analog Electronics /Amplifiers<br />
If the load is an open circuit, R^—°o, there is no drop across the output resistance R^ then v Q =<br />
A%v t . For this reason the constant A% is called the open-circuit voltage gain. To summarize, the<br />
voltage-amplifier model has three parameters: the input impedance, the output impedance and the<br />
open-circuit voltage gain.<br />
As shown in Fig. 2.4, the input current i t is the current delivered to the input terminals of the<br />
amplifier and the output current to is the current flowing through the load. The cuttent gain A i of<br />
the amplifier is the ratio of the output current to the input current<br />
For linear amplifiers, the input current can be expressed as the input voltage divided by the input<br />
resistance. For linear load, the output current is the output voltage divided by the load resistance.<br />
(Linear amplifiers will be investigated in this chapter unless stated otherwise.) Thus we can find the<br />
current gain in terms of the voltage gain and the resistance as<br />
in which<br />
A= - (2-4)<br />
is the voltage gain with the load resistance connected. Usually, A^ is smaller in magnitude than the<br />
open-circuit voltage gain A°, because of the voltage drop across the output resistance.<br />
The power delivered to the input terminals by the signal source is called the input power P^ and the<br />
power delivered to the load is the output power P Q . The power gain G of an amplifier is the ratio<br />
of the output power to the input power<br />
G = £ (2.5)<br />
Because we are assuming that the input impedance and the load are purely resistive, the average<br />
power at either set of terminals is simply the product of die root-mean-square (rms) current and the<br />
rms voltage. Thus we can write<br />
Notice that we have used uppercase symbols, such as V 0 and J 0 , for the rms values of the currents<br />
and voltages. We use lowercase symbols, such as v 0 and i^ for the instantaneous values. Of course,<br />
since we have assumed that the instantaneous output is a constant times the instantaneous input,<br />
the ratio of the rms voltages is the same as the ratio of the instantaneous voltages, and both are<br />
equal to the voltage gain of the amplifier.<br />
Exetcise 2.1 An amplifier has an input resistance l\ = 2000 Q, an output resistance of 25 Q, and<br />
an open-circuit voltage gain of 500. The source has an internal voltage of V s =20mV and a<br />
resistance R t =500Q. The load resistance is R L =750. Find the voltage gains A y = VJV\ and A^=-<br />
VJ V s , the current gain and the power gain. Ans. ^=375,^=300,^=10 4 , G=3.75-10 6 .<br />
Exetcise 2.2 Assume that we can change the load resistance in Exercise 2.1. What value of load<br />
resistance maximizes the power gain What is the power gain for this resistance Ans. R L =250,<br />
G=5-10 6 .<br />
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Analog Electronics /Amplifiers<br />
There exist other models of amplifiers, alternative to the voltage model. The input and output<br />
resistances are the same for all models. They differ by the type of controlled source at the output.<br />
Current amplifier model employs a current controlled current source, transconductance<br />
amplifier uses a voltage-controlled current source and the transresistance amplifier is the one<br />
with current-controlled voltage source at the output. The choice of the particular model is the<br />
matter of analytical convenience or feasibility of measurement of the model parameters. An<br />
amplifier can be modeled by any of the four models, provided that neither of the resistances (input<br />
or output) is zero or infinity. For example, if JRj^O, then t»,=0 and the voltage gain A^— v 0 /i\ is not<br />
defined.<br />
One can easily show that if the input impedance of an amplifier is much higher than the internal<br />
impedance of the source, the voltage produced across the input terminals is-nearly the same as the<br />
internal source voltage. On the other hand, if the input impedance is very low, the input current is<br />
neady equal to the short-circuit current of the source. From this point of view, voltage amplifiers<br />
should be designed to have large input impedance and current amplifiers should have very low<br />
input impedance. Taking the output impedance level into consideration, we can force a desired<br />
voltage waveform to appear across a variable load by designing the amplifier to have very low<br />
output impedance compared to the load impedance. An example is an audio amplifier with a<br />
variable number of loudspeakers connected to it On the other hand, we can force a given current<br />
waveform through a variable load by designing an amplifier to have very high output impedance<br />
compared to the load impedance. Here an example could be the amplifier in optical communication<br />
system where a light-emitting diode (LED). It is used to produce a light wave whose intensity is<br />
proportional to a message signal such as a voice waveform. Because LED has nonlinear relationship<br />
between voltage and current, light intensity "is not" proportional to the voltage across this device,<br />
whereas it is proportional to the current flowing through the diode. Thus LED should be driven<br />
from a current amplifier in this example.<br />
We see that certain applications call for amplifiers with very high or very low input impedance<br />
(compared to the source) and very high or very low output impedance (compared to the load). Such<br />
amplifiers are classified as follows.<br />
An ideal voltage amplifier (voltage-controlled voltage source) senses the open-circuit voltage of<br />
die source and produces and amplified voltage across the load - independent of the load impedance.<br />
Thus the ideal voltage amplifier has infinite input impedance and zero output impedance.<br />
Figure 26 An ideal current amplifier (CCCS)<br />
-21-
Analog Electronics /AmpMers<br />
An ideal current amplifier (current-controlled current source) senses the short-circuit current of<br />
the source and forces an amplified version of this current to flow through the load. Thus an ideal<br />
current amplifier has zero input impedance and infinite output impedance.<br />
O 4 O<br />
Figure 2.7 An ideal ttansconductanceamplifier (VCCS)<br />
An ideal transconductance amplifier (voltage-controlled current source) senses the open-circuit<br />
voltage and forces a current proportional to this voltage to flow through the load. Thus it has<br />
infinite input impedance and infinite output impedance.<br />
Figure 2.8 An ideal transresistance amplifier (CCVS)<br />
An ideal transresistance amplifier (current-controlled voltage source) senses the short-circuit<br />
current of the source and produces a voltage proportional to this current to appear across the load.<br />
Thus the ideal transresistance amplifier has a zero input impedance and zero output impedance.<br />
The amplifier models considered here are unilateral; that is signal flow is unidirectional, from input<br />
to output Most real amplifiers show some reverse transmission, which is usually undesirable but<br />
must nonetheless be modeled. We will return to this point later.<br />
Recall that we originally defined the gain of an amplifier to be the ratio of the output signal to the<br />
input signal (2.4). This is true for amplifiers that do not contain any energy-storing element.<br />
However, if any time delay or linear distortion occur, the ratio of output to input is a function of<br />
time rather than a constant Thus we should not try to find the gain of an amplifier by taking the<br />
ratio of the instantaneous output to input. Instead we recognize that gain is a function of frequency<br />
and take the ratio of phasors for a sinusoidal input signal to find the (complex) gain at each<br />
frequency<br />
2.2 Cascaded Amplifiers<br />
Amplifiers are built using active devices - most often transistors. We will see later that the gain<br />
obtainable from a single-transistor amplifier is limited. Thus there is often a need to combine a<br />
number of amplifiers in order to amplify a weak signal to the desired level. This can be achieved by<br />
connecting the output of one amplifier to the input of another, as shown in Fig. 2.9. This is called a<br />
cascade connection of-the amplifiers. The overall voltage gain of the cascade connection is given<br />
by<br />
A v = ^ (2.7)<br />
Multiplied and divided by f ol this becomes<br />
-22-
Analog Electronics /Amplifiers<br />
" v n v 0l<br />
However, referring to Fig. 2.5, we see that v^v oV<br />
Therefore we can write<br />
(2.8^<br />
'<br />
v ,i<br />
v ,2<br />
We note also ^3OSAA^X=V OX / » A is the gain of the first stage andy4 v2 =f o2 / tfo is the gain of the second<br />
stage, so we have<br />
A v =A vl A v2 (2.10)<br />
Thus the overall gain of cascaded voltage amplifiers is the product of the voltage gains of the<br />
individual stages. (Of course, it is necessary to include loading effects in computing the gain of each<br />
stage. Notice that the input resistance of the second stage loads the first stage.) Similar rules can be<br />
derived for the number of cascaded amplifiers bigger than two can.<br />
(2.9)<br />
Exercise 2 J Show that the overall current gain of a cascade connection of amplifiers is the product<br />
of the current gains of the individual stages and that the overall power gain is the product of<br />
individual power gains.<br />
2.3 Power Supplies and Efficiency<br />
For appropriate operation of the internal circuitry of an amplifier, power must be supplied to it<br />
from an external power supply. The power supply typically delivers current from several dc<br />
voltages, see an example in Fig. 2.10. The average power supplied to the amplifier by each voltage<br />
source is the product of the average current and voltage. The total power supplied is the sum of the<br />
powers delivered by each source. For example, the total average power supplied to the amplifier of<br />
Fig. 2.10 is<br />
*s - 'AA^A + *BB*B<br />
(2.11)<br />
We have seen in Exercise 2.1 that the power gain of an amplifier can be very large. Thus the output<br />
power delivered to the load is much greater than the power taken from the signal source. This<br />
additional power is taken from the power supply. For example, a stereo audio system converts part<br />
of the power taken from the power supply into signal power that is finally converted to sound by<br />
the loudspeakers. Part of the supplied power is also dissipated as heat in the internal circuits of the<br />
amplifier. This dissipation is an undesirable effect since the dissipated power is lost in most cases<br />
and makes the battery discharged too fast in case of mobile battery-powered devices. We usually try<br />
to minimize this effect when designing the internal circuitry of amplifiers.<br />
-23-
_ Analog Electronics /Amplifiers<br />
Figure 2.10 TTie power supply delivers power to the amplifier from<br />
several external constant voltage supplies.<br />
From energy conservatiqn law, the sum of the power entering the amplifier from the signal<br />
P { and the power from the power supply P s must be equal to the sum of the output power<br />
the power dissipated P d .<br />
p i+ p s = p 0 +p d (2.12)<br />
:>wer is negligible compared to the other terms in this<br />
percentage of the power supplied that is converted in<br />
P.<br />
n =<br />
P,+P s<br />
(2.13)<br />
The power and efficiency values given in Exercise 2.4 below are typical of one channel of a stereo<br />
amplifier under high output test conditions. Maximi2ing the efficiency is one of the important<br />
design goals for battery-operated devices such mobile phones, hearing aids, implantable heart<br />
pacemakers, etc., as well as for high-power equipment, such as motor drivers, power regulators,<br />
DC-DC converters, etc.<br />
Exercise 2.4 Find the input, output, supply and dissipated power in the amplifier shown in Fig. 2.6,<br />
assuming the following values of its parameters: v s = 1 mV^, J^ = 0, ^ = 100 kQ, A% = 10 4 , R^ =<br />
2Q,R L =8Q, Vj^ = 15 V, J A = 1 A, V m = 15 V, J B = 0.5 A. Calculate the efficiency of the<br />
amplifier. Am. P k = 10 pW, P 0 = 8 W, P s = 22.5 W, P d = 14.5 W, rj = 35.6%.<br />
Most amplifiers discussed in this lecture notes are small-signal circuits. The power involved is very<br />
small and the efficiency was not a concern. We do not consider power amplifiers, or output<br />
stages that are expected to provide large signal power requited by their loads. Examples of loads<br />
for power amplifiers are stereo and public address loudspeakers, deflection coils in video monitors,<br />
and servomotors in X-Y plotters. Powers supplies are also good examples of power circuits; their<br />
function is to provide the dc power required by digital and analog components of all lands.<br />
Several special concerns preoccupy the designer of an amplifier that must deliver a large amount of<br />
power to the load. One is the amplifier efficiency, as discussed above in this Section. Equation<br />
(2.13) shows that, for given output power, low efficiency directly means greater demand for<br />
supplied power. Furthermore, efficiency suggests a second issue - the ability of the circuit<br />
components to dissipate heat Any power that does not leave the circuit as the load power<br />
contributes to the heating of transistors and resistors. In power circuits special efforts should be<br />
-24-
Analog Electronics /Amplifiers<br />
made to ensure that components are not desttoyed by excessive heat. Finally, the large signal<br />
amplitudes necessary for large output signal power make nonlinear distortion (see Section 2.9) a<br />
matter of concern. Small signal models, based upon linearization of the device characteristic at some<br />
jj-point (Sections 3.4, 4.6, 5.7 and 5.11), no longer apply here. Large-signal dynamic models have to<br />
be used for circuit analysis and design, such as SPICE models discussed in Sections 3.8, 4.10 and<br />
5.14.<br />
Power amplifiers are classified according to the fraction of the time an output power transistor<br />
conducts the current during one signal cycle. Class A amplifiers have output transistors in which<br />
signal current is nonzero all the time. The FET amplifiers discussed in Sections 4.7 and 5.13 are all<br />
class A amplifiers. The dc current of a class A amplifier is the same, no matter the signal is zero or<br />
nonzero. For greater efficiency, class B amplifiers employ transistors that are active only half time -<br />
otherwise they are cut-off. At zero signal value, there is no dc current through- a class B output stage<br />
- and no power consumption. An example of PSpice simulation of a class B bipolar transistor<br />
amplifier is presented in Section 6.1.3. So-called crossover distortion appears in class B amplifiers<br />
(see Section 6.1.3), so for their reduction class AB amplifiers are designed. In class AB circuits,<br />
transistors conduct slightly more than half the signal cycle. Class AB circuits have efficiencies<br />
approximately the same as for class B circuits, but produce less distortion.<br />
Class C amplifiers deliver large amount of output power at high efficiency by employing an output<br />
transistor that conducts output current for only small fraction of a cycle. The resulting short,<br />
periodic pulses of output current excite a resonant circuit, which suppresses the distortion<br />
components that arise from the nonlinear operation of the transistor.<br />
Class D amplifiers produce binary output waveforms of very high power with efficiencies<br />
approaching 100% by using transistors as switches. In analog applications, the class D amplifier<br />
includes a modulator that first transfers information from waveform amplitude into a more suitable<br />
form as pulse width. A lossless filter than removes undesired high-frequency terms from the output.<br />
Applications of power amplifiers, especially class C and D circuits, are somewhat specialized.<br />
Therefore, they are not discussed further in this text<br />
2.4 Decibel Notation<br />
As we have noticed from the Exercises, the gain of an amplifier can take on values spanning a very<br />
large range of magnitudes. To facilitate visualization of these extreme values, amplifier gain is often<br />
expressed with a logarithmic measure. Specifically, the voltage gain A^ can be expressed in decibels<br />
(dB)as<br />
^=201og|^v|dB (2.14)<br />
and the current gain A, can be expressed as<br />
^=201ogM,|dB (2.15)<br />
Since power is related to voltage (or current) squared, the power gain G can be expressed in<br />
decibels as follows<br />
G^g^OlogG dB (216)<br />
A power gain of G=100 converts to 20dB, unky gain converts to OdB, and so on. The absolute<br />
values of the voltage and current gains are used because in the case of inverting amplifiers A^oxA^<br />
can be negative values. A negative gain A v means that there is a 180°-phase difference between die<br />
input and output signals; it does not imply mat the amplifier attemiates the signal On the other<br />
-25-
AmJofElectronica/AinptiSen<br />
hand, an amplifier whose voltage gain is -20 dB is, in fact attenuating the input signal by a factor of<br />
10 (that is ^=0.1).<br />
Recall that the overall gain for cascaded amplifiers is the product of the power gains of the<br />
individual amplifiers. Wbeti fa gm an e>pnssedmdecfals, the gons of cascaded stagum<br />
the properties of the logarithm function. To illustrate this point we have<br />
G = G X G 2 (2.17)<br />
When expressed in decibels, this becomes<br />
G* = lOlogG - lOlogCG.Gj) = lOlogCG,)* 101og(G 2 ) dB (2.18)<br />
Note, referring back to (2.6), that power gain in decibels is equal to voltage gain in decibels only<br />
when RL=R}.<br />
Electronics engineers often use decibel notation for voltages, currents, powers, or other quantities.<br />
To do so, a reference level must be stated or implied The quantity to be expressed in decibels is<br />
divided by the reference value and the ratio is converted to decibels by taking 20 times me<br />
logarithm of the ratio for voltages or currents. Ten times the logarithm of the ratio is taken for<br />
powers. Some commonly used reference levels are 1 volt (dBV), 1 mW (dBm), and 1 watt (dBW).<br />
For example, 40 dBV is a designation of 100 V, -10 dBm is for 0.1 mW, -40 dBW is also 0.1 mW,<br />
and so on.<br />
2.5 Frequency Response<br />
From Chapter 1.1 we know that the input signal to an amplifier can always be expressed as the sum<br />
of sinusoidal signals. So far we have considered the gain parameter to be a constant However, since<br />
physical amplifiers contain capatiuve and inductive elements, the gain is a function of frequency.<br />
Furthermore, the amplifier affects the amplitude as well as the phase of the input signal<br />
It follows then that an important characterization of an amplifier is in terms of its response to input<br />
sinusoids of different frequencies. Such characterization of amplifier performance is known as the<br />
amplifier frequency response.<br />
26
Analog Ehcttoaka/AmpWka<br />
Figure 212 Measuring the frequencyresponse of a Knear amplifier (a), phase characteristic of a two-transistor<br />
small-signal amplifier (b) whose amplitude characteristic is shown in Fig. 2.7<br />
Figure 2.12a shows a linear voltage amplifier fed at its input with a sine-wave signal of amplitude V {<br />
and frequency CD. As the figure indicates, the signal measured at the amplifier output is also<br />
sinusoidal with exactly me same frequency 0). This is always true for linear circuits. However, the<br />
output sinusoid will have in general different amplitude and a different phase relative to the input.<br />
The ratio of the amplitude of me output sinusoid (VJ to the amplitude of the input sinusoid (V$ is<br />
the amplifier gain or transmission at the test frequency 0). Hie angle
Analog Electronics /Amplifiers<br />
as the midband region. This is typical for wideband amplifiers. Wideband amplifiers are used for<br />
signals that occupy a wide range of frequencies, such as audio signals or video signals (see Table<br />
1.1). In some cases, the frequency response of an amplifier is deliberately limited to a small<br />
bandwidth compared to the center midband frequency. Such an amplifier is called a nattowband<br />
or banpass amplifier. Bandpass amplifiers are frequency selective circuits used in radio receivers to<br />
amplify the signal from one transmitter and reject the signals from other transmitters in adjacent<br />
frequency ranges.<br />
Figure 2.13 Gain versus frequency for wideband amplifiers: ac-coupled amplifier (a) and<br />
dc-coupled amplifier (b)<br />
Usually we specify the approximate useful frequency range of an amplifier by giving the frequencies<br />
at which the voltage (or current where appropriate) gain magnitude is l/\2 times the midband gain<br />
magnitude. These are known as half-power frequencies (cut-off frequencies) because the output<br />
power level is half the value for the midband region if the constant-amplitude, variable-frequency<br />
sinewave test input is used. Expressing the factor 1 /"V2 in decibels results in -3.01 dB. Thus at the<br />
half-power frequencies, the voltage or current gain is approximately 3dB lower than the midband<br />
gain. The bandwidth B of an amplifier is the distance between the half-power frequencies, {f H -f{).<br />
This is illustrated in Fig. 2.13.<br />
In the cases illustrated by Fig. 2.13(a), the gain drops to zero at dc (zero frequency). Such amplifiers<br />
are called ac-coupled, because only ac signals are amplified. These amplifiers are often constructed<br />
by cascading a number of amplifiers that are connected together by coupling capacitors, so that<br />
dc voltages of signal source, and individual amplifier stages are separated from each other. This is<br />
illustrated in Fig. 2.14 where; caparitive coupling prevents a dc input component from affecting the<br />
first stage, dc voltages in the first stage from reaching the signal source and the second stage, and dc<br />
voltages in the second stage from reaching the first stage and the load. Sometimes magnetic<br />
transformers are used for coupling, which also leads to an ac-coupled amplifier with a zero gain at<br />
dc.<br />
-28-
Analog Electronics /Amplifiers<br />
Other amplifiers have constant gain all the way down to the dc, as shown in Fig. 2.13(b). They are<br />
said to be dc-coupled or direct coupled. Amplifiers that are realized as integrated circuits are<br />
often dc coupled because the capacitors or transformers needed for ac coupling cannot be<br />
fabricated in integrated form.<br />
Electrocardiograph amplifiers are deliberately ac-coupled because a dc voltage of nearly a volt often<br />
occurs in the input due to contact potentials developed on the electrodes placed on the skin. The ac<br />
signal generated by the heart is on the order of lmV, and therefore the gain of the amplifier is high -<br />
typically 1000 or more. A lV-dc input would cause the amplifier to produce an output of 1000V. It<br />
would be difficult and undesirable to design an amplifier capable of such large outputs. Therefore, it<br />
is necessary to ac-couple the input circuit of an electrocardiograph to prevent the dc component<br />
from overloading the amplifier.<br />
Amplifiers for video signals need to be dc coupled because video signals have frequency<br />
components from dc to about 6MHz, see Table 1.1. Dark pictures result in a different dc<br />
component than bright on the average pictures. It is necessary to dc-couple a video amplifier in<br />
order to preserve dc component and to obtain proper brightness of the image.<br />
As indicated in Fig. 2.13, the gain of an amplifier always drops off at high frequencies. This is<br />
caused either by small capacitance in parallel with the input or output terminals or by small<br />
inductances in series with the signal path in the amplifier circuitry. This is illustrated in Fig. 2.10.<br />
Recall that impedance of a capacitor is inversely proportional to frequency, resulting in effective<br />
short circuit at sufficiendy high frequencies. The impedance of an inductor is proportional to<br />
frequency, so it becomes an open circuit at very high frequencies.<br />
Figure 2.15 Capacitance in parallel with the signal path and inductance in series with the signal path reduce<br />
gain in the high-frequency region<br />
Some of these small capacitances occur because of stray wiring capacitance between signal-carrying<br />
conductors and ground. Other capacitances are integral parts of active devices (transistors)<br />
necessary for amplification. Small inductances result from the magnetic fields surrounding the<br />
conductors in the circuit For example, a critically placed piece of wire 1-cm long can have enough<br />
inductance to limit severely the frequency response of an amplifier intended to operate at several<br />
GHz.<br />
2y
Analog Electronic* /AupttiBen<br />
Fot frequencies up to several MH2, the circuit and device capacitances ate the main source of<br />
frequency response roll-off, either at low or high frequencies. To illustrate their impact on<br />
frequency response we will consider an amplifier that can be represented by a real transconductance<br />
amplifier model (Figure 2.16). Such a model is an ideal transconductance amplifier as shown in<br />
Figure 2.7, augmented with input nonzero resistance r, and output finite resistance r* It is an<br />
adequate low-frequency representative of amplifying devices, such as field-effect and bipolar<br />
transistors. For the field-effect transistor, the input resistance r t is infinite whereas for the bipolar<br />
transistor a base resistance is added in series with the input terminal as will be discussed in Chapters<br />
4 and 5, respectively.<br />
Figure 2.16 Low frequencynon-ideal transconductance amplifier model<br />
The input to the amplifier is voltage source it with internal resistance R». Resistance RL represents<br />
the load They are shown in Fig. 2.17. The symbol ^n used in Figs 2.16 and 2.17 to denote the shortcircuit<br />
transconductance coefficient is equivalent to A& in Fig. 2.7. To illustrate the effect of the<br />
source resistance on the frequency response, we will use a voltage gain definition slightly different<br />
to that given by Equation (2.1), namely<br />
4. = 7T (2- 21 )<br />
Figure 217 Transconductance amplifier<br />
There is no capacitive or inductive element in the schematic diagram of Fig. 2.17. Therefore, the<br />
bandwidth of this circuit is infinite. Indeed, the output voltage<br />
r 0 R<br />
V L<br />
0 =-ZmVi<br />
r 0 +R]L<br />
does not depend on frequency. The voltage gain of the amplifier in Figure 2.17 can be expressed as<br />
r 0Ri<br />
Ays ~ ~8lH "" Ay, (2.23)<br />
r >so<br />
0 +R L r { +R s<br />
The coefficient Ano in Equation (2.23) is a constant as plotted in Figure 2.18(a) wherein = 50 mS,<br />
R, = 600 Q, r, = 5 kO, r 0 = 100 kQ, and RL = 5.6kft were assumed. The phase characteristic in<br />
Figure 2.18(b) is also constant and equal to 180 degrees that means the amplifier under<br />
consideration is an inverting one. Of course, the circuit discussed is an idealized model of real-world<br />
amplifiers. Nevertheless, for medium frequency range it is an adequate model of transistor<br />
amplifiers.<br />
Low frequency effects. To illustrate the effect of coupling capacitances on the frequency response<br />
of amplifiers we consider the circuit of Figure 2.19. It contains a coupling capacitor C, in series with<br />
the input resistance r f The output voltage is described by Equation (2.22) and the input voltage can<br />
be expressed as<br />
-30-
Analog Ekctroak* /AnpUtten<br />
Vi=V t<br />
R s +r t +<br />
1<br />
Jar t C s<br />
= V,<br />
(2.24)<br />
l+JG>(R s +r t y: s<br />
JG>(R s +ri)C s<br />
* rt,+r, 1+ ./*L<br />
R s +r i l+ja>T L<br />
Figure 219 Ac-coupled ttansconductanceamplifier<br />
where<br />
U=(*S+ri)C s (2.25)<br />
is the low-frequency time constant of the amplifier. Combining Equations (2.22) and (2.26), one<br />
obtains the effective voltage gain of the amplifier in Fig. 2.19<br />
Ays ~ 8n<br />
n JQ>r L r 0 R L<br />
R s +r i l + ja>T L r 0 +R l<br />
(2.26)<br />
~~Ayso<br />
1+JOTL<br />
Equation (226) indicates that in this case the voltage gain is a single-pole function of frequency.<br />
The voltage gain magnitude<br />
Vl+(a>rJ 2 (2.27)<br />
-31-
Analog Electronics /Amplifiers<br />
tends to zero for frequencies approaching zero. Thus an ac-coupled amplifier does not provide a dc<br />
gain. This is shown in Figure 2.20a where C s = \ \x¥ was assumed with the other circuit parameters<br />
taking the same values as for Figure 2.18.<br />
The gain increases with frequency. For high frequencies, the gain magnitude is equal to A yM . Then<br />
one can say the ac-coupled amplifier acts as a highpass filter. At the lower cut-off frequency, jL, the<br />
It is easy to show that for a single-pole transfer function of the type given by Equation (2.26), the<br />
lower cut-off frequency is inversely proportional to the low-frequency time constant<br />
h=^— (2-28)<br />
Using Equation (2.26) one can find expression that describes the phase characteristic of the<br />
amplifier in Figure 2.19<br />
ZA\, S =270° -tg-\coT L )<br />
(2.29)<br />
.-li<br />
=-90 -tg- J (a>r L )<br />
The phase characteristic (2.29) of the ac-coupled amplifier, computed using PSpice program is<br />
plotted in Figure 2.20b.<br />
High frequency effects. Capacitances in parallel with the signal path (as well as capacitances<br />
connected between the output and input terminals of inverting amplifiers that will be discussed later<br />
on) make the amplifier gain decreasing with frequency. To illustrate this effect, capacitance C 0 is<br />
connected in parallel to the load resistance of the amplifier, as shown in Figure 2.21. The output<br />
voltage is now given as<br />
gain magnitude is equal to A\, so I-J2 . The same results (except for different expression to describe<br />
the low-frequency time constant) would be obtained if a coupling capacitor is connected in series<br />
with the load resistance RL-<br />
-32-
Analog Electronics /AmpliBets<br />
v Q = -g m Vi<br />
jcoC 0<br />
R 0 +—t—<br />
JoCo<br />
Ro<br />
= -g m Vi<br />
\+jaC 0 R 0<br />
(2.30)<br />
= n R ~Sm's 0<br />
ri+Rs \+jaC 0 R 0<br />
-_«T V 1-<br />
R o<br />
where<br />
T H ~<br />
R o C o<br />
is the high frequency time constant of the amplifier and<br />
_ r Q R L<br />
Rn =<br />
r 0 + R L<br />
(2.31)<br />
(2.32)<br />
Figure 2.21 A transconductance amplifier with parallel capacitance at the output<br />
Substituting Equation (2.23) into (2.31), dividing both sides by V s and making use of the definition<br />
(2.21), one obtains the voltage gain<br />
4,=-,<br />
K ° (2-33)<br />
that is a single-pole function of frequency. Its magnitude<br />
I4«(
Antdog Electronics /Amplifiers<br />
The phase characteristic (2.36) of the amplifier in Figure 2.21 with parallel capacitance C = 10 pF,<br />
computed using the PSpice program, is plotted in Figure 2.22b.<br />
2.6 The Miller Theorem<br />
It is often the case in transistor circuits that a capacitor is connected between the output and input<br />
ports of the amplifier. Such a capacitor may represent a base-collector junction capacitance of a<br />
bipolar device or drain-gate capacitance of FET or MOSFET field-effect devices. As an example, a<br />
simplified equivalent circuit of such an amplifier is shown in Figure 2.23, where g„ = 50 mS, R, =<br />
600 CI, r,, = 5 kQ, r 0 = 100 \£i, R^ = 5.6kQ and C F = 10 pF are assumed.<br />
Figure 2.23 A transconductance amplifier with a feedback capacitor<br />
The capacitive element connected between the input and output terminals causes difficulties in<br />
analysis since its presence leads to higher-order nodal equations. The difficulties can be overcome<br />
by applying Miller theorem to the circuit This theorem is a basis to one of approximate methods of<br />
transistor amplifier analysis. To derive it, we will consider a general amplifier with feedback<br />
impedance as shown in Figure 2.24a.<br />
y,*<br />
O"o<br />
v, o 1<br />
-OVo<br />
\ ><br />
(a)<br />
(b)<br />
Figure 2.24 Original amplifier with feedback impedance (a), equivalent amplifier with feedback element split<br />
into two parts (b)<br />
-34-
Analog Electronics /Amplifiers<br />
For the original circuit we have<br />
j _VJ-VQ JTi-AVi =Vj>1. If Z is resistive, the impedances Zml and Zm2 are also resistive, with Zmi being much<br />
smaller than Z and Zm2 being approximately equal to Z. If Z is a capacitive element, Z=l/')(oC, the<br />
impedances Zmi and Zm2 are also capacitive<br />
C ml =C(l-A) (2.43)<br />
C m2 =C l -^j (2.44)<br />
i<br />
Figure 2.25 Circuit equivalent to the amplifier of Fig. 2.23<br />
Figure 2.25 shows the equivalent circuit for the amplifier of Figure 2.23. The approximate values of<br />
die Miller capacitances are<br />
C ml =C F (l-A vo ) (2.45)<br />
C m2 =C F 1 -^- (2-46)<br />
-A vo<br />
where Am = Vo/V{. Now one can derive die formula for the voltage gain of die amplifier. The<br />
output voltage is given by<br />
-35-
Analog Electronics /AmpliGcra<br />
"o ~ Sm"i, .<br />
l + JG>T 2<br />
where Ro is defined by Equation (2.32) and the output circuit time constant is described :das<br />
T 2 = R 0 C„2<br />
(2.48)<br />
In turn, for the input voltage we have<br />
1<br />
(2.49)<br />
where<br />
l ~ R \ C m\<br />
and<br />
V/<br />
*1 = *s+n<br />
(2.47)<br />
(2.50)<br />
(2.51)<br />
Combining Equations (2.47), (2.49) and (2.23), one obtains the voltage gain<br />
A =_, __J L_<br />
l + JCDTi l + JG)T 2<br />
(2.52)<br />
which is a two-pole transfer function. The time constants are related to the angular firequendes<br />
CO X = — (2.53)<br />
fi> 2 =— (2.54)<br />
*2<br />
called break firequendes, since for CO exceeding a value of any of these firequendes the slope of the<br />
amplifier amplitude characteristic increases by 20 dB/decade. Using (2.53) and (2.54) one can<br />
rewrite Equation (2.52) as follows<br />
Ay S — ~A VS0<br />
CO<br />
•I'<br />
1 + 7— ll + y<br />
CO<br />
One can perform the multiplication in the denominator of (2.55) to obtain<br />
A>5 = ~A\s VSO /<br />
1 1<br />
+<br />
CO<br />
0>1 Q} 2 ) G>\1 *>2) (2.58)<br />
1<br />
s-A VSO<br />
l+y—<br />
o °>\
Analog Electronics /AmpliGers<br />
relates the approximate higher cut-off frequency fflb = (o H to the break frequencies CO, and 0)2. By<br />
using Equations (2.53) and (2.54) one obtains<br />
a> 0 s —— = - (2.60)<br />
r, + r 2 T 0<br />
It should be noted that Equation (2.60) underestimates the actual value of the higher cut-off<br />
frequency, which is the effect of dropping the right-side term in the denominator of Equation<br />
(2.56). The actual value of 0) H is higher than Oh and lower than minimum of CO, and co r It is then<br />
reasonable to write<br />
o) 0 H i,0)2} (261)<br />
The latter formula can be easily extended to three- and more-pole amplifiers.<br />
Using the numerical values assumed above for the elements of our circuit, we have A. = 265.2, C,<br />
= 2662 pF, C 2 = 10.04 pF, R, s 536 Q and R, = 5.3 kQ. They give z, = 1.426 us, r 2 = 52.83 ns, T 0 =<br />
1.479 us, which are respectively equivalent to co, = 701.36 krad/s, Q) 2 S 18.93 Mrad/s, and flfc =<br />
676.3 krad/s. Knowing that^ =
Analog Electronics /Amplifiers<br />
Zero phase characteristic of an amplifier results in an output waveform that is identical to the input<br />
(up to the scale factor). On the other hand, if the phase shift between the output and input signals<br />
of an amplifier is proportional to frequency, the output signal is a time-shifted version of the input,<br />
but their shapes are the same, so we do not say any distortions take place.<br />
Figure 2.26 Linear amplitude distortion: input signal (upper panel), output signal (lower panel).<br />
If the phase shift of an amplifier is not proportional to frequency, phase distortion occurs. As an<br />
example suppose the signal (2.63) is applied to uie inputs of three amplifiers A, B, C, which have a<br />
constant gain magnitude of 10. The amplifiers have different phase characteristics, as specified in<br />
Table 2.1<br />
TABLE 2.1 TRANSFER FUNCTION OF EXAMPLE AMPLIFIERS<br />
Amplifier GainatlkHz Gain at 3kHz<br />
A 10Z0° 10Z0°<br />
B 10Z-45 0 10Z-135 0<br />
C 10Z-45 0 10Z-45 0<br />
Apparently, amplifier A has a zero-phase response. The phase response of amplifier B is<br />
proportional to frequency with a proportionality constant of-45 degrees per kilohertz, and amplifier<br />
C has the phase response which is not proportional to frequency (or more precisely, it is nonzero<br />
constant, so the proportionality factor is zero). The plots of the output signals of the amplifiers are<br />
shown in Fig. 2.27. It is clear that the amplifier A does not change the shape of the signal.<br />
(However, it cannot be realized physically, as there is no delay between the input and the output -<br />
compare with Fig. 2.26.) Amplifier B also does not introduce any signal distortion, as the shapes of<br />
the input and output are the same. (Note the time delay between the signals.) Amplifier C that does<br />
not have its phase proportional to frequency produces severe distortion of the signal.<br />
We conclude that to avoid linear signal distortions, an amplifier should have constant gain<br />
magnitude and a phase response that is linear versus frequency for the range of frequencies<br />
contained in the input signal. For an audio amplifier it is required to have a constant gain for the<br />
frequency range from 20Hz to about 20kHz. However, since it turns out that the ear is not sensitive<br />
to phase distortion (at least for monophonic signals), we would not require the phase signals of an<br />
audio amplifier to be strictly proportional to frequency. Since the shape of the waveform ultimately<br />
determines the brightness of various points of an image, either amplitude or phase distortions of<br />
television signals would severely affect the image quality. Therefore we require the gain magnitude<br />
of a video amplifier to be constant and the phase response to be proportional to frequency in die<br />
whole range from dc to 6MHz.<br />
-38-
Analog Electronics /Amplifiers<br />
2.8 Pulse Response<br />
Often one needs to amplify a pulse signal such as the waveform v(l) shown in Fig. 2.28a. Pulses<br />
contain components that are spread over a wide range of frequencies; therefore amplification of<br />
pulses calls for a wideband amplifier. A typical amplifier output pulse is shown in Fig. 2.28a,<br />
denoted by v(7). The output waveform differs from the input in several important respects: the<br />
pulse is delayed, it displays overshoot and ringing, the leading and trailing edges are gradual rather<br />
than abrupt, and if the amplifier is ac-coupled, the top of the output pulse is tilted.<br />
The gradual rise of the leading edge of the amplifier response is quantified by giving the rise time /„<br />
which is the time interval between the point t 10 at which the amplifier achieves 10% of the eventual<br />
output amplitude K-and the point /j^ at which the output is 90% of the steady-state value. This is<br />
illustrated in Fig. 2.29.<br />
-39-
Analog Electronics/Amplifiers<br />
ho ho '<br />
Figure 2.29 Rising edge of a typical ac-coupied broadband amplifier output pulse<br />
(Note: no tilt is shown. When it is present, some judgement is necessary<br />
to estimate the finalamplitude Vj).<br />
The rounding of the leading edge can be attributed to the roll-off of gain in the high-frequency<br />
region. A rule-of-thumb relationship between the half-power bandwidth B and the rise time t r of a<br />
wideband amplifier is<br />
t r s ~Y (2-64)<br />
This relationship is not exact,for all types of amplifiers; it is accurate for firs' order (single pole)<br />
circuits. Analogously, the fall time U can be defined for the trailing edge of amplifier's pulse<br />
response. Equation (2.64) approximates the value of tr as well, at least for linear wideband<br />
amplifiers.<br />
Another aspect of the output pulse shown in Fig. 2.28 is overshoot and ringing, which are also<br />
related to the way the gain behaves in the high-frequency region. An amplifier that displays<br />
pronounced overshoot and ringing usually has a peak in its amplitude characteristic, as shown in<br />
Fig. 2.28b. The frequency of maximum gain approximately matches the ringing frequency. Because<br />
both rise time and overshoot are related to the high-frequency response, there is usually some tradeoff<br />
between these specifications. In a particular design, component values that reduce rise time<br />
often lead to more overshoot and tinging. Pulse amplifiers designed for fast rise time typically<br />
display about 10% overshoot because a higher amount of overshoot and associated ringing are<br />
usually undesirable.<br />
Figure 2.30 Pulse response that does not display ringing (a) and corresponding amplitude characteristic (b) of<br />
an amplifier<br />
Example 2.1 A television picture (25 pictures per second, 625 lines per picture) is produced by a<br />
TV camera that is able to reproduce about 765 distinguishable image elements within a 52^s active<br />
-40-
Analog Electtoaica/AxapHSets<br />
interval during each picture line. Estimate the bandwidth required for the video amplifier embedded<br />
within this camera.<br />
Solution. We estimate the bandwidth by the use of equation (2.22). Each picture element occupies<br />
die interval of 52)ls/765=68ns. Assume 80% of this interval is allowed to be the rise time: t r<br />
=54.4ns. Thus we obtain<br />
n 0.35 , A<br />
5 = -—— = 6.4 MHz<br />
54.4/w<br />
This is very close to die actual video bandwidth used in Europe.<br />
(2.65)<br />
Figure 2.31 Pulse responses (a) and amplitude characteristics (b) of ac-coupled amplifiers.<br />
(Tis the input pulse duration and r represents the shortest time constant of the coupling circuit)<br />
v(2): T« T, v(3): T=T, v(4): T» T.<br />
The tilt at the top of the output pulse, shown in Fig. 2.31a occurs if the amplifier is ac-coupled and<br />
originates from charging of coupling capacitors during the pulse. (After all, if the pulse lasted<br />
indefinitely, it would be the same as a new dc level at the input Since ac-coupled amplifiers do not<br />
pass me dc signal, output voltage would eventually return to zero.) Tilt (sag) is specified as a<br />
percentage of the initial pulse amplitude<br />
AF % = —-100% (2.66)<br />
where AV and V are defined in Fig. 2.32. As the duration of the input pulse increases (or die<br />
amplifier lower cut-off frequency is raised by changing the coupling circuits to have shorter time<br />
constants), output waveforms of consistently increased tilt result as shown in Fig. 2.31b.<br />
For small amount of tilt, the following approximate formula relates the percentage tilt to the lower<br />
cut-off (half-power) frequency^<br />
AV % =200^7 (2.67)<br />
where Tis the duration of the pulse.<br />
-41-
Analog Electronics /AmpliSera<br />
Figure 232 Pulse response that displays tilt<br />
Example 2.2 A cathode ray oscilloscope (CRO) is used to measure the pulse response of me<br />
amplifier shown in Figure 2.21. The equivalent impedance of the oscilloscope, including the cable<br />
connected between amplifies output and oscilloscope's input, is represented by a 1-MQ resistance<br />
in parallel with a 100-pF capacitance. This is illustrated in Figure 2.33. Find the output pulse rise<br />
time, as obtained from the measurement Compare with the value obtained for the circuit of Figure<br />
2.21.<br />
Figure 233 A transconductance amplifier with parallel capacitance and<br />
Oscilloscope + cable equivalent connected at the output<br />
Solution. We will use Equation (2.56). For the amplifier under consideration, the bandwidth equals<br />
to the higher cut-off frequency. To find the higher cut-off frequency for the circuits in Figure 2.21<br />
and 2.33, one can use Equation (2.35) with appropriate values for the equivalent resistance and<br />
capacitance to calculate the time constant In the case of Figure 2.21, we have<br />
— = —+ — (2.68)<br />
R o<br />
r o &L<br />
which for RL = 5.6 kQ and r 0 = 100 kfi gives Ro = 5.303 kfl. The equivalent capacitance is equal to<br />
Co = 10 pF. The time constant is the product RoG>, which is tti = 53.03 ns. This corresponds to the<br />
upper cut-off frequency of/k = 3 MHz and the rise time of £ = 0.12 ^ls. In the case of Figure 2.33,<br />
we have<br />
1 1 1 1<br />
• = — + • + -<br />
(2.69)<br />
Ro<br />
r o<br />
R L<br />
R CRO<br />
which for the assumed values gives Ro = 5.275 kQ. The equivalent capacitance is equal to (G> +<br />
CCRO) = HO pF. The time constant is the product RO(G)+CCRO), which is m = 580.2 ns. This<br />
corresponds to the upper cut-off frequency offii = 274 kHz and the rise time of U = 1.28 |J.s.<br />
One can see from the results of Example 2.2 that a substantial reduction of the apparent cut-off<br />
frequency can be experienced when measuring it by the oscilloscope, direcdy connecting die<br />
oscilloscope input to the amplifier output by a coaxial cable. Lower value of the cut-off frequency<br />
means that such an oscilloscope measurement setup introduces errors to the rise time and cannot<br />
be used to evaluate amplifier pulse response. The rise and fall times will apparency be much longer<br />
-42-
Analog Electronics /Amplifiers<br />
than their true values. To get rid of this undesired effect a device known as probe is used. The<br />
oscilloscope probe is an RC voltage attenuator as shown in Figure 2.34, where V^i denotes the<br />
voltage at die amplifier output and V2 is the voltage at the oscilloscope input Typically, a probe<br />
introduces 10 times attenuation of the input signal. If the probe capacitance Cp is properly adjusted,<br />
the attenuation is constant over a very wide frequency range. Such a probe is said to be<br />
compensated. For a compensated ptobe with 10-times attenuation, the input capacitance is 10<br />
times lower than the oscilloscope + cable capacitance. Thus the apparent reduction in the higher<br />
cut-off frequency is not as severe as it is with the CRO directly connected to the amplifier.<br />
Figure 234 Schematic diagram of the oscilloscope probe<br />
Example 2.3 Find the values of Rp and Cp of the oscilloscope probe in Figure 2.34 such that the<br />
attenuation V2/V\ is equal to 10 for all frequencies. Assume RCRO = 1 Mft and CCRO =100 pF.<br />
Solution. One can easily verify that the transfer function of the probe is described by<br />
A v =^ = P ^ n ( 2 - 70 )<br />
V l Rr, +R l + J*> R CRO C CRO ^<br />
P<br />
^R°<br />
1 + jaRpCp<br />
It will be a constant equal to<br />
Aw = *CRO (2J1)<br />
RCRO +<br />
R p<br />
for all frequencies if the following condition is satisfied<br />
RpCp = RcRO C CRO ( 2 - 72 )<br />
Putting Avo = 0.1 in Equation (2.71) one obtains.Kp = 9 MQ, which substituted into condition<br />
(2.72) gives Cp = 11.1 pF. It is suggested to the reader to find out that the input capacitance of the<br />
probe + oscilloscope arrangement is, under these circumstances, equal to Cm = 10 pF, whereas the<br />
parallel resistance Rin that loads the amplifier output is Rin = 10 MQ.<br />
Example 2.4 Find the upper cut-off frequency of the amplifier in Figure 2.33, as measured using a<br />
10-times attenuating compensated probe.<br />
Solution. We replace the oscilloscope equivalent RCROCCRO in Figure 2.33 by a parallel connection<br />
of Rin and Cm that represent the probe of Figure 2.34. Thus the equivalent output resistance of the<br />
amplifier is now equal to<br />
1 1 1 1<br />
— = — + — + — (2.73)<br />
R r 0 o<br />
R L Rin<br />
which for the assumed values gives Ro = 5.300 kfl. The equivalent capacitance is equal to (Co +<br />
Cm)= 20 pF. The time constant is the product Ro(G+Cm), which is m = 106 ns. This corresponds<br />
to the upper cut-off frequency of jk = 1.5 MHz and the rise time of £ = 0.23 ^s. The latter value is<br />
much closer to the true value of 0.12 |is than the rise time of 1.28 |4.s, as measured straight by the<br />
oscilloscope with no probe. This illustrates the advantage of using die probe for wideband amplifier<br />
characterization.<br />
-43-
Analog Electronics /Amplifiers<br />
2.9 Nonlinear Distortion<br />
Consider again an ideal resistive amplifier. Define its transfer characteristic as a ratio of the<br />
instantaneous output to instantaneous input For an ideal amplifier, the transfer characteristic can be<br />
plotted as a straight line on the output-input plane. For real amplifiers, diis characteristic remains<br />
linear over only a limited range of input and output voltages. For an amplifier operated from two<br />
power supplies the output voltage cannot exceed a specified positive limit and cannot decrease<br />
below a specified negative limit. Thus the output becomes saturated for large positive and large<br />
negative inputs. The resulting transfer characteristic is shown in Fig. 2.35, with the positive and the<br />
negative saturation levels denoted as L + and L_, respectively. Each of the two saturation limits is<br />
usually within 1 or 2 volts of the corresponding power supply. The output signal becomes distorted<br />
when me input exceeds the respective values 2, + / A y and L_ I A y . Obviously, in order to avoid<br />
distorting the output signal waveform, the input signal swing should be kept within the linear range<br />
of operation<br />
L_/A,Zv,ZLJA, (2.74)<br />
Fig. 2.35 shows the input waveforms (1) and (2) and the corresponding output waveforms. We note<br />
that the peaks of the larger waveform have been dipped off because of the saturation effect In<br />
some applications, like audio signal amplification, clipping is perceived as a rather severe distortion.<br />
Even small departures from linearity can be considered to be very serious in such cases. Assume the<br />
output-input relationship of a nonlinear amplifier can be written as<br />
v o (0 = M-(') + ^2[v,(')] 2 +4J[V,(01 3 +••• (2.75)<br />
where A u A& A 3 and so on are constants selected so diat the equation (2.75) matches the curvature<br />
of the nonlinear transfer characteristic. Obviously, for a linear amplifier, A 2 -A 3 =...= 0. Consider<br />
the case for which the input signal is a sinusoid given by<br />
v / (0 = ^ocos(fl> o r) (2.76)<br />
Now, we find an expression for the corresponding output signal. Substituting equation (2.76) into<br />
(2.75), applying trigonometric identities for [cos(flJ^]*, collecting terms and defining V 0 to be the<br />
sum of all of the constant terms, V, to be the sum of the terms with frequency 0)^, and so on, we<br />
find that<br />
v 0 (0 = V 0 Q + V ol cos(
Analog Electronics /Amplifiers<br />
The desired output is the V Q \ cos(co 0 t) term, which we call the fundamental component. The<br />
KJQ term represents a shift in the dc level (which does not appear at the load if it is ac-coupled). In<br />
addition, terms at multiples of the input frequency have resulted from the second and higher order<br />
nonlinear terms of the transfer characteristic (2.75). These terms are called harmonic distortion.<br />
The 2co 0 term is called second harmonic, the 3co 0 term is die third harmonic, and so on.<br />
Harmonic distortion is objectionable in a wideband amplifier because the harmonic can fall in die<br />
frequency range of the desired signal In an audio amplifier, harmonic distortion degrades die<br />
aesthetic qualities of the sound produced by the loudspeakers.<br />
The second harmonic distortion factor D 2 is defined as die ratio of the amplitude of the second<br />
harmonic to the amplitude of the fundamental.<br />
£) 2 =^2 (2.78)<br />
V ° l<br />
Similarly the third-order harmonic distortion factor, and so on, are defined as<br />
B-J-03 D 4 3 4 - (2.79)<br />
3<br />
v 0 { v ol<br />
The total harmonic distortion (THD) denoted by D is defined as<br />
D = VA 2 +^2+A 2 +- ( Z8 °)<br />
We can often find THD expressed as a percentage. A well-designed audio amplifier might have a<br />
THD specification of 0.01% (i.e. D- 0.0001) at rated output power.<br />
Notice diat THD specification of an amplifier depends of die amplitude of the output signal<br />
because the degree of nonlinearity of the transfer characteristic is amplitude-dependent. Certainly,<br />
any amplifier clips me output signal if the input becomes large enough. When clipping occurs, THD<br />
becomes large.<br />
Harmonic distortion is usually not a problem for bandpass amplifiers if the bandwidth is narrow<br />
enough so mat harmonics fall outside the frequency range of the desired signal. However, amplifier<br />
nonlinearity causes another type of distortion that can be very troublesome even for narrowband<br />
amplifiers. This is intermodulation and crossmodulation distortion that appear when die<br />
amplifier is excited by a sum of two or more sinusoidal components of close frequencies. Some of<br />
die intermodulation components generated due to amplifier nonlinearity fall into the original<br />
frequency band. The crossmodulation, which is the transfer of the amplitude of one input signal to<br />
a term wim a frequency of anodier input signal, is a very serious problem for radio receivers. These<br />
topics, however, fall outside the scope of this texdbook.<br />
Exercise 2.5 For the bipolar transistor amplifier shown below, write the PSpice code, run .AC<br />
analysis and plot amplitude and phase characteristics in the frequency range from 1Hz to 10MHz,<br />
100 points per decade. Identify the midband frequency range of this amplifier and find its halfpower<br />
bandwidth. Calculate its voltage, current and power gains at 1kHz. Explain me role of die<br />
capacitors C : and C 0 in the circuit<br />
-45-
Analog Electronics /Amplifiers<br />
I l><br />
R S CS | jg~""<br />
"••IT<br />
cc<br />
s<br />
Exercise 2.5- bipolar transistor common-amitter amplifier<br />
Vs 1 0 ac InV<br />
Rs 1 2 Ik<br />
Cs 2 3 luF<br />
RBI 7 3 330k<br />
RB2 3 0 100k<br />
Ql 5 3 4 Q2N2222A<br />
.LIB EVAL.LIB<br />
RE 4 0 10k<br />
CE<br />
RC<br />
Co<br />
RL<br />
4<br />
7<br />
5<br />
6<br />
470uF<br />
12k<br />
luF<br />
10k<br />
VCC 7 0 10V<br />
.ac dec 100 1Hz 10MEGHZ<br />
.end<br />
Exercise 2.6 For the bipolar transistor amplifier of Exercise 2.5, modify the PSpice code to run the<br />
transient and Fourier analyses for the time interval of 5ms, assuming that the input signal is a<br />
sinusoidal waveform of frequency 1 kHz and amplitude 1 mV. Repeat the simulation 10 times, each<br />
time for a different value of the input signal amplitude, covering the range from 2 mV to 20 mV.<br />
For each value of V s :<br />
(a) plot the waveforms of v(6) and -A*ik on a common diagram and compare their shapes,<br />
(b) find the corresponding value of THD, as recorded in the output file.<br />
(c) make the plot of the total harmonic distortion of the output signal as a function of input signal<br />
amplitude.<br />
2.10 Summary<br />
Linear amplifiers obey the- superposition principle. Their transfer characteristic, output voltage<br />
versus the input voltage, is a straight line with a slope equal to the voltage gain. Linear amplification<br />
can be obtained from a device having a nonlinear transfer characteristic by employing dc biasing<br />
and keeping the input signal amplitude small Depending on the signal to be amplified (voltage or<br />
current) and on the desired form of output signal (voltage or current), there are 4 basic amplifier<br />
types: voltage, current, transresistance and transconductance amplifiers. Amplifiers can be cascaded<br />
to increase the gain available, provided loading effects are taken into account Amplifiers increase<br />
-46-
Analog Electronics /Amplifiers<br />
the signal power and thus require dc power supplies for their operation, to convert the dc current<br />
energy from the power supply into the ac current energy of the signal amplified. Sinusoidal signals<br />
are invariant to linear operators; they are used to measure the frequency response of linear<br />
amplifiers. Amplifiers are classified according to the shape of their amplitude characteristic as<br />
lowpass, bandpass or highpass. The banpass amplifiers can be narrowband or wideband. Accoupled<br />
amplifiers are used to filter out dc component of the input signal and to break the dc<br />
current path between the signal source and the amplifier input, as well as between the amplifier<br />
output and the load. Ac-coupled amplifiers can never be classified as lowpass; they are either<br />
highpass or, more realistically, bandpass. In every physical amplifier there are always stray wiring or<br />
component capacitances in parallel with the signal path present At high frequencies they act as lowimpedance<br />
shunting elements that reduce the amplifier gain. Thus every physical amplifier has a<br />
limited bandwidth. The amplifier gain remains almost constant over the midfrequency band. It falls<br />
off at high frequencies where stray capacitances of components and devices no longer have high<br />
reactance. For ac amplifiers the gain falls off at low frequencies as well, because the coupling<br />
capacitors no longer have very low reactance. The amplifier bandwidth is the frequency range over<br />
which the gain remains within 3dB of the value at midband. The limits of the bandwidth are the<br />
frequencies^, and^. (For dc amplifier only^fr is meaningful). Variations of the amplitude and phase<br />
characteristics of an amplifier with frequency may cause distortion to the signal shape. Amplifiers<br />
do not distort signals if their gain is constant and phase is proportional to frequency for the range of<br />
frequencies contained in the input signal. If the frequency response of an amplifier is inadequate for<br />
a particular signal, there will be linear distortion — either amplitude distortion or phase distortion, or<br />
both. The shape of the unit step and pulse responses of the amplifier is related to its transfer<br />
function. Large bandwidth amplifiers produce pulses with a short rise time. Small values of the<br />
lower cutoff frequency give low percentage tilt. If the input signal amplitude is not sufficiently small,<br />
nonlinear distortion occurs due to inherent nonlinearities of amplifying devices. Nonlinear<br />
amplifiers do not obey the superposition principle. For sinusoidal input, sine waves of frequencies<br />
different to the input signal frequency appear in the output signal spectrum. Their amplitudes<br />
relative to the amplitude of the input sine-wave signal are the measure of nonlinear distortion<br />
introduced by an amplifier.<br />
-47-
Analog Electronics /Diodes<br />
3. Diode Circuits<br />
The simplest and most fundamental element of semiconductor circuits is the diode. Just like a<br />
resistor, it has two terminals; but unlike the resistor, it is a nonlinear element This chapter is<br />
concerned with the study of basic circuits that contain diodes. In order to understand the essence<br />
of diode function, we begin with a fictitious element, the ideal diode. We then introduce the real<br />
semiconductor junction diode, explain its terminal i-v characteristic and provide techniques for<br />
the analysis of diode circuits. The latter task involves the important subject of diode modeling,<br />
both for large-signal and small-signal applications.<br />
Of the many applications of diodes, their use in the design of rectifiers (which convert ac to dc) is<br />
the most common. Therefore, we shall study rectifier circuit in some detail and briefly look at a<br />
number of other diode applications.<br />
The semiconductor diode is a two-terminal device that incorporates a pn junction. The pn<br />
junction is the basis of many other solid-state devices, including the bipolar junction transistor.<br />
Thus an understanding of the/>» junction is essential to the study the material of this chapter.<br />
3.1 The Ideal Diode<br />
The ideal diode is a two-terminal device having the circuit symbol of Fig. 3.1(a) and the i-v<br />
characteristic shown in Fig. 3.1(b). One of its terminals is called the anode and the other is the<br />
cathode. The voltage v across the diode is referenced positive at the anode and negative at the<br />
cathode. The current is referenced positive when it flows from the anode to the cathode. The<br />
terminal characteristic of the ideal diode can be interpreted as follows: If a negative voltage is<br />
applied to the diode, no current flows and the diode behaves as an open circuit [Fig. 3.1(c)].<br />
Diodes operated in this mode are said to be reverse biased, or operated in the reverse direction.<br />
An ideal diode has a zero current when operated in the reverse direction and is said to be cut-off.<br />
(c)<br />
(d)<br />
Figure 3.1 The ideal diode: circuit symbol (a), i-v characteristic (b), equivalent circuit in the reverse<br />
direction (c), equivalent circuit in the forward direction (d).<br />
On the other hand, if a positive current is applied to the ideal diode, zero voltage-drop appears<br />
across the diode. In other words, the ideal diode behaves as a short circuit when biased in the<br />
forward direction [Fig. 3.1(d)]. It passes any current with zero voltage-drop. A forward-biased<br />
diode is called to be turned on or simply on.<br />
-48-
Analog Electronics /Diodes<br />
It is evident from Fig. 3.1(b) that the i-v characteristic is far away from a linear relationship. It<br />
contains two straight-line segments at 90 degrees one to another; thus it is highly nonlinear,<br />
although one may say it is piecewise linear. Other variations of piecewise-linear diode<br />
descriptions will be considered later in this chapter.<br />
'D<br />
V D 'D .. _ n l D =0<br />
v D =0<br />
VD<br />
(d)<br />
Figure 3.2 Rectifier circuit (a): equivalent circuit for v s >0 (b), equivalent circuit for v^0 (c),<br />
input waveform (d, upper panel),output waveform (d, lower panel).<br />
The fundamental application of the diode, one that makes use of its severely nonlinear i-v curve,<br />
is the rectifier circuit shown in Fig. 3.2a. The circuit consists of a series connection of a diode D<br />
and a resistor R. Let the input voltage be the sinusoid shown in Fig. 3.2d, and assume the diode<br />
to be ideal. During the positive half-cycles of the input sinusoid, the positive v s will cause current<br />
to flow through the diode in its forward direction. It follows that the voltage drop across the<br />
ideal diode will be zero. Thus the circuit will have the equivalent shown in Fig. 3.2(b), and the<br />
output )ltage v Q will be equal to the input voltage r s . On the other hand, during the negative<br />
half-cyciits of p f , the diode will not conduct. Thus the circuit will have the equivalent shown in<br />
Fig. 3.2c, and the output voltage will be zero. Note that while v s alternates in polarity and has a<br />
zero average value, v 0 is unidirectional and has a finite average value, or a non-zero dc<br />
component. Thus the circuit from Fig. 3.2a rectifiers the signal and hence is called a rectifier. It<br />
can be used to generate dc from ac. We will study more complex rectifier circuits later in this<br />
chapter.<br />
Exercise 3.1.For the circuit in Fig. 3.2a, sketch the transfer characteristic v Q versus v s .<br />
Exercise 3.2 For the circuit in Fig. 3.2a, sketch the waveform of the voltage across the diode.<br />
12V<br />
-49-
Analog Electronics /Diodes<br />
Example 3.1 Fig. 3.3 shows a circuit for charging a 12-V battery. If v s is a sinusoid with 24-V<br />
peak amplitude, find the fraction of each cycle during which the (ideal) diode is on. Also find the<br />
peak value of the diode current and the maximum voltage that appears across die diode and,<br />
finally, find the average current that charges the battery.<br />
Solution The diode conducts when s exceeds 12V, as shown in Fig. 3.3(b). The conduction<br />
angle is 20, where 6 is given by 24cos(6[)=12. Thus #=60° and the conduction angle is 120°, or<br />
one-third of a cycle. The peak value of the diode current occurs when the input voltage is<br />
maximum, and is given by 7 d =(24-12)/10 = 1.2A. The maximum reverse voltage across the diode<br />
occurs when v s is at negative peak and is equal to 24V+12V = 36V. The average current which<br />
1 *<br />
charges the battery is given as 1^ = —— J I d cos(g)d£ = 0.33 A, where £ is the integration<br />
variable.<br />
In<br />
1 IT *<br />
+5V<br />
00 (b)<br />
Figure 3.4 Diode logic gates: (a) OR gate; (b) AND gate<br />
Diodes together with resistors can be used to implement digital logic functions. Fig. 3.4 shows<br />
two diode logic gates. To see how these circuits function, consider a positive logic system in<br />
which voltage values close to 0 correspond to logic 0 (or low state) and voltage voltages close to<br />
+5V correspond to logic 1 (or high state). The circuit in Fig. 3.4a has three inputs, v A , v B , and v c .<br />
It is easy to see that diodes connected to +5V will conduct, thus clamping the output voltage v Y<br />
to a value equal to +5V. This positive output voltage will keep the diodes whose anodes are low<br />
(at zero voltage) cut off. Thus the output will be high if one or more inputs are high. The circuit<br />
in Fig. 3.4a therefore implements the logic OR function, which in Boolean notation is expressed<br />
as<br />
Y=A+B+C<br />
-50-
Analog Electronics<br />
/Diodes<br />
Similarly, the reader is encouraged to show that the circuit in Fig. 3.4b implements the logic<br />
AND function, that is<br />
Y = ABC.<br />
In analysis of circuits containing ideal diodes we may not know in advance which diodes are on<br />
and which are off. Thus we are forced to make a considered guess. Then we analyze the circuit to<br />
find the currents in the diodes assumed to be on and the voltage across the diodes assumed to be<br />
off. If the current i D through the diodes assumed to be on is positive and the voltage v D across the<br />
diodes assumed to be off is negative, our assumptions are correct and we have solved the circuit.<br />
Otherwise, me must make another assumption about the diodes and try again. After a little<br />
practice, our first guess is usually correct, at least for simple circuits.<br />
+I0V<br />
+I0V<br />
r-10V<br />
00 (b)<br />
Figure 3.5 Circuits for Example 3.2<br />
Example 3.2 Assuming the diodes to be ideal, find values of J and Kin the circuits of Fig. 3.5.<br />
Solution In these circuits it might not be obvious at first sight whether none, one or both diodes<br />
are conducting. In such a case we make a plausible assumption, proceed with the analysis and<br />
then check whether we end up with a consistent solution.<br />
For the circuit in Fig. 3.5a, we shall assume that both diodes are conducting. It follows that V B =0<br />
and V=0. The current through D2 can now be determined from<br />
I D2 = (10V-0V)/10k = 1mA.<br />
Writing the first Kirchhoff s law equation for node 8 we obtain<br />
1+lmA^ (0-(-l 0V))/5k = 2mA.<br />
Thus I=2mA-lmA = 1mA is larger then zero and thus diode Dl is conducting as originally<br />
assumed, and the final result is J=lmA, K=0.<br />
For the circuit in Fig. 3.5b, if we assume that both diodes are conducting, then V B =0 and V=0.<br />
The current through D2 is obtained from<br />
I D2 = (10V - 0V)/5k = 2mA<br />
The node equation at B is<br />
I+2mA = (OV - (-10V))/10k<br />
which yields I—1mA. The current is negative, so this result is not consistent with the assumption<br />
that diode Dl is on. We start again, assuming that Dl is off and D2 is on. The current through<br />
diode D2 is given by<br />
I D2 = (10V-(-10V))/(10k+5k)=1.33mA<br />
and the voltage at node B is<br />
V B = -10V +10k*1.33mA = 3.3V.<br />
Thus the voltage across Dl is negative (the anode is at 2ero and the cathode is at +3.3V), which<br />
means diode Dl is off as assumed, and the final result is 7=0 and K=3.3V.<br />
Exercise 3.3 Find the current I and voltage V for the circuits shown in Fig.3.6.<br />
Ans. (a) 2mA, 0V, (b) 0mA, 5V, (c) 0mA, -5V, (d) 2mA, 0V, (e) 3mA, 3V, (f) 4mA, IV.<br />
-51-
Analog Electronics /Diodes<br />
(e) (0<br />
Figure 3.6 Circuits for Exercise 3.3<br />
Exercise 3.4 Find the state of the ideal diodes in the circuits of Fig. 3.7<br />
lkQ<br />
4kO<br />
|6kfi<br />
5mA<br />
1 ©<br />
T3V<br />
10V<br />
Figure 3.7 Circuits for Exercise 3.4<br />
Exercise 3.5 Fig. 3.8 shows a circuit for an ac voltmeter. It utilizes a moving-coil meter that<br />
gives a full-scale reading when the average current flowing through it is 1mA. Hie moving-coil<br />
meter has a 50 Q resistance. Find the value R that results in the meter indicating full-scale reading<br />
when the input sine-wave voltage r s is 20V peak-to-peak. Ans. R=3.133 kfi.<br />
Moving-coil<br />
'oJ meter<br />
Figure 3.8 Circuit for Exercise 3.5<br />
3.2 Terminal Characteristics of Semiconductor Diodes<br />
In this section we study the characteristics of real diodes - specifically semiconductor junction<br />
diodes made of silicon. Fig. 3.9 shows an example of the i-v characteristic of a silicon junction<br />
diode. As indicated, the characteristic curve consists of three distinct regions:<br />
1. The forward-bias region determined by v>0.<br />
o—W-<br />
-52-
Analog Electronics / Diodes<br />
2. The reverse-bias region, determined by v
Analog Electronics /Diodes<br />
v = nV T \n{—) (3.4)<br />
The exponential relationship of the current / to the voltage v holds over many decades of current<br />
(a span of as many as seven decades - that is a factor of 1CK 7 - can be found). This is quite a<br />
remarkable property of junction diodes (and bipolar transistors as well), one that has been<br />
exploited in many interesting applications. The diode i-v characteristic is then most conveniently<br />
plotted on a semilog paper. One can show that using the vertical, linear axis for v and the<br />
horizontal, log axis for i, one obtains from (3.3) a straight line with a slope of 2.3«K T per decade<br />
of current.<br />
Since both I s and V T in (3.3) are functions of temperature, the forward i-v characteristic varies<br />
with temperature as illustrated in Fig. 3.10. At a constant diode current, the voltage drop across<br />
the silicon diode decreases by approximately 2mV for every kelvin increase in temperature. This<br />
property has been exploited in the design of electronic thermometers.<br />
A glance at the i-v characteristic in the forward region (Fig. 3.9) reveals that the current / is<br />
negligibly small for v smaller than about 0.5V. This value is usually referred to as the knee<br />
voltage. It should be emphasized, however, that this apparent threshold in the diode<br />
characteristic is simply a consequence of the exponential relationship. Another consequence of<br />
this relationship is the rapid increase of /'. Thus for a "fully conducting" diode; the voltage drop<br />
across it lies in a narrow range, approximately from 0.6 to 0.8V for silicon diodes. This gives rise<br />
to a simple model of a diode where it is assumed that a conducting diode is replaced by a 0.7-V<br />
battery. This constant-voltage-drop model is discussed later on in this chapter. Diodes with<br />
different ratings (i.e. different areas and different 1$) will exhibit the 0.7-V drop at different<br />
currents. For instance, a low-power switching diode may be considered to have 0.7V drop at<br />
/'=lmA, while a higher power diode may have a 0.7V drop at /-1A.<br />
-54-
Analog Electronics /Diodes<br />
The reverse-bias region. The reverse-bias region is entered when the diode voltage v is made<br />
negative. Equation (3.1) predicts that if v is negative and its absolute value is a few times larger<br />
than V T (25mV), the exponential term becomes negligibly small compared to unity and the diode<br />
current becomes<br />
i=-Is (3.5)<br />
that is, the current in the reverse direction is constant and equal to I s -.'m magnitude. This is the<br />
reason behind the term saturation current: the current saturates when-1 v\>Vj, v
Analog Electronics /Diodes<br />
The second mechanism causing breakdown is called the Zener effect. It occurs in abrupt<br />
junctions having high doping levels. For such junctions, the depletion region is very narrow<br />
because die charge density of ionized dopant atoms is high and a large amount of charge can be<br />
stored in a very thin layer. As reverse bias is applied, the field in the depletion region increases in<br />
intensity. When the field strength is of the order of 1 V divided by the crystal lattice spacing, it is<br />
possible for covalent bonds to be broken by the field. In other words, the forces are so strong<br />
that electrons are pulled loose from their bonds.<br />
The energy gap between the top of the valence band and the bottom of the conduction band<br />
becomes slightly smaller with increased temperature. Hence the force required to break the<br />
covalent bonds is slighdy smaller at higher temperatures. As a result, if the Zener effect is<br />
responsible for breakdown, the breakdown voltage tends to become smaller with increased<br />
temperature. This is opposite to the case for avalanche breakdown.<br />
As a rule, the Zener effect is responsible if the breakdown voltage magnitude is less man 6 V, and<br />
the avalanche effect is responsible if the breakdown voltage is greater than 6 V. For diodes<br />
having breakdown voltages of approximately 6 V, a mixture of both mechanisms can occur. It is<br />
possible to obtain diodes having breakdown voltages of about 6 V with very small temperature<br />
coefficients, because the temperature effects of the two breakdown types offset one another.<br />
Dynamic impedance also tends to be a function of breakdown voltage, reaching a minimum for<br />
breakdown voltages of about 6 V. Thus, as circuit designers, we tend to select 6-V diodes.<br />
As can be seen from Fig. 3.9, in the breakdown region the reverse current increases rapidly, and<br />
the associated increase in the voltage drop is very small. Diode breakdown is normally not<br />
destructive, provided that the power dissipated in the diode is limited by external circuitry to a<br />
"safe" level. This safe value is normally specified on the device data sheets. It therefore is<br />
necessary to limit the reverse current in the breakdown region such that the product of the dc<br />
current and the dc voltage is lower than the permissible power dissipation.<br />
The fact that the diode i-v characteristic in breakdown is almost a vertical line enables it to be<br />
used in voltage regulation (stabilization). This subject will be studied in Section 3.6.<br />
3.3 Analysis of Diode Circuits<br />
In this section, we shall study methods for the analysis of diode circuits. We shall concentrate on<br />
circuits in which the diodes are operating in the forward-bias region. Operation in the breakdown<br />
region is considered in Section 3.5.<br />
Consider the circuit shown in Fig. 3.11 consisting of a dc source V DDJ a resistor R and a diode.<br />
We wish to analyze this circuit to determine the diode current I D and the diode voltage V D .<br />
R ID<br />
Figure 3.11 A simple diode circuit<br />
-56-
Analog Electronics /Diodes<br />
The diode is obviously biased in the forward direction. Assuming that V DD is greater than 0.1V or<br />
so, the diode current will be much greater than I s and we can represent the diode i-v characteristic<br />
by the exponential relationship<br />
/ D = / S exp(-^-) (3.6)<br />
The other equation that governs the circuit operation is obtained by writing a Kirchhoff loop<br />
equation, resulting in<br />
I D =(V DD -V D )/R (3.7)<br />
Assuming that the diode parameters I s and n are known, Eqs. (3.6) and (3.7) are two equations in<br />
the two unknown quantities I D and Vp. Two alternative ways for obtaining the solution are<br />
graphical analysis and iterative analysis.<br />
Graphical analysis. Graphical analysis is performed by plotting the relationship (3.6) and (3.7)<br />
on the i-v plane. The solution can then be obtained as the coordinates of the point of intersection<br />
of the two graphs. A sketch of the graphical construction is shown in Fig. 3.11; the curve<br />
represents the exponential diode equation (3.6) and the straight line represents (3.7). Such a<br />
straight line is known as the load line, a name that will become more meaningful in later<br />
chapters. The load line intersects the diode curve at point Q, which represents the operating<br />
point of the circuit. Its coordinates give the values of I D and V D .<br />
Graphical analysis aids in the visualization of circuit operation. However, the effort involved in<br />
performing such an analysis, particularly for complex circuits, is too great to be justified in<br />
practice.<br />
V DD /R<br />
0-point<br />
o v D v DD<br />
Figure 3.12 Graphical analysis of the circuit in Fig. 3.11<br />
Iterative analysis. Equations (3.6) and (3.7) can be solved using a simple iterative procedure, as<br />
the one illustrated in the following example.<br />
Example 3.3 Determine the current I D and the diode voltage V D for the circuit in Fig. 3.11 with<br />
K DD =5V and R=lk. Assume that^lO 10 , «=1.7.<br />
Solution Taking a look at Figure 3.11 one may arrive at conclusion that the diode is biased into<br />
the forward direction. Thus Equation (3.6) describes the diode current Taking a natural<br />
logarithm of both sides of (3.6) one obtains<br />
V D =»V T ki(I D /Q.<br />
Now, substituting (3.7) for I D in the above formula gives<br />
V D =»V T ]n((V DD -V D )/(RI s ))<br />
The last equation can be rewritten for iterative calculations, such that the diode voltage in<br />
iteration (k+1) is related to its value in the previous iteration (k) as follows<br />
V D W = »V T ]n((V DD -V D
Analog Electronics<br />
/Diodes<br />
Assume the initial guess tor the diode voltage is V D<br />
—0.5V. Its values and the corresponding<br />
values of the current in successive iterations are<br />
k vj> J «<br />
0 0.5V 0.013mA<br />
1 0.748942V 4.500mA<br />
2 0.746524V 4.251mA<br />
3 0.746524V 4.251mA<br />
4 ...<br />
Thus the third iteration yields J D =4.251mA and K D =0.74624V. Since these values are not much<br />
different from the values obtained after the second iteration, no further iterations are necessary.<br />
Figure 3.13 The effect of diode series resistance<br />
The iterative analysis procedure utilized in the example above is simple and yields accurate results<br />
after two or three iterations. Nevertheless, there are situations in which the effort and time<br />
required to perform the iterative calculations are still greater than can be justified. Specifically,<br />
when one is doing a pencil-and-paper design of a relatively complex circuit, rapid circuit analysis<br />
is a necessity. Through quick analysis, the designer is able to evaluate various possibilities before<br />
deciding on a suitable circuit. To speed up the analysis process, one must be content with less<br />
precise results. This, however, is seldom a problem, as the more accurate analysis can be<br />
postponed until a final or almost final design is obtained. Accurate analysis of the final or almost<br />
final design can be performed with the aid of a computer-analysis program such as SPICE. The<br />
results of such an analysis can then be used to further refine or "fine-tune" the design.<br />
Diode models. At high current levels, the ohmic resistance of the semiconductor forming the<br />
junction becomes significant. Addition of a series resistance R t to the diode modeled by the<br />
Shockley equation (3.1) can account for this. The modified version of (3.4) becomes<br />
-58-
Analog Electronics /Diodes<br />
v-«F I .In(7-) + « J<br />
(3.8)<br />
Typical low-current diodes have Revalues ranging from 10 to 100Q. The resistance R, decreases<br />
with the diode cross-sectional area. Thus for high-current diodes it is of the order of 0.1Q. The<br />
effect of die diode series resistance on the i-v characteristic is illustrated in Fig. 3.13. For a fixed<br />
value of current, the voltage drop across the diode external terminals increases with the series<br />
resistance value.<br />
Slope=l/r£)<br />
(c)<br />
Figure 3.14 Approximating the diode forward characteristic with two straight lines (a), (b);<br />
equivalent circuit representation of the piecewise-linear model (c).<br />
Although the exponential i-v characteristic plus a series resistance is an accurate model in the<br />
forward region, its nonlinear nature complicates the analysis of diode circuits. The analysis can be<br />
greatly simplified if we can find piecewise-linear relationship to describe the diode terminal<br />
characteristics. An attempt in this direction is illustrated in Fig. 3.14, where the exponential curve<br />
is approximated by two straight-line segments, line A with zero slope and line B with a slope of<br />
//r D . It can be seen that for this particular diode, over the current range from 0 to 10mA the<br />
voltages predicted by the straight-line model differ from those predicted by the exponential<br />
model by less than 50 mV. Of course, the choice of two lines is not unique; one can obtain a<br />
closer approximation by restricting the current range over which the approximation is required.<br />
The straight-lines (or piecewise-linear) model of Fig. 3.14 can be described by<br />
»D = °><br />
V D ^ VDo<br />
h =<br />
Do<br />
v D >V Do (3.9)<br />
where V D , is the intercept of line B on the voltage axis and r D is the inverse of the slope of line B.<br />
For the particular example shown, V D , = 0.65 V and r D = 20 Q.<br />
-59-
Analog Electronics /Diodes<br />
The equivalent circuit shown in Fig. 3.14c can represent the piecewise-linear model described by<br />
(3.8). Note that an ideal diode is included in this model to constrain i D to flow in the forward<br />
direction only. This model is also known as the "battery-plus-resistance" model.<br />
Example 3.4 Repeat the problem in Example 3.3 utilizing the piecewise-linear model whose<br />
parameters are V Dt — 0.65 V, r D = 20 Q.<br />
Solution Replacing the diode in Fig. 3.11 with the equivalent circuit model of Fig. 3.14c results in<br />
the circuit in Fig. 3.15, from which we can write the current I D<br />
ID = {VDD - VJ/(R + r D ) =4.26mA<br />
The diode voltage can now be computed<br />
VD = VD. + roI D = 0.7353V<br />
Note that the values obtained using the simplified model are not very much different from the<br />
accurate values obtained in Example 3.3.<br />
Figure 3.15 The circuit of Fig. 3.11 with the diode replaced by its<br />
piecewise-linear model of Fig. 3.14c.<br />
An even simpler model of the diode forward characteristic can be obtained if we use a vertical<br />
straight line to approximate the fast-rising part of the exponential curve, as shown in Fig. 3.16a.<br />
The resulting model simply says that a forward-conducting diode exhibits a constant voltage drop<br />
V D . The value of V D for silicon diodes is usually taken to be 0.7V. The equivalent circuit shown<br />
in Fig. 3.16c can represent the constant-voltage-drop model. This model is the one most<br />
frequently employed in initial phases of analysis and design. Finally, note that if we employ the<br />
constant-voltage-drop model to solve the problem in Examples 3.3 and 3.4 we obtain<br />
IQ = (V DD -V D )IRI D = 4.3 mA which is not too differ^ it from the values obtained with the<br />
more elaborate models.<br />
V, D<br />
(b)<br />
-60-
Analog Electronics /Diodes<br />
Ideal<br />
V D<br />
(c)<br />
Figure 3.16 Development of the constant-voltage-drop model of the diode forward characteristic with<br />
two straight lines (a), (b); equivalent circuit representation of the model (c).<br />
In applications that involve voltages much greater than the diode voltage drop (0.6 - 0.8V), we<br />
may neglect the diode voltage drop altogether while calculating the diode current The result is<br />
die ideal diode model, which we studied in Section 3.1.<br />
The question of which diode model to use in a particular application is one a circuit designer<br />
faces repeatedly, not just with diodes but with every circuit element. One's ability to select<br />
appropriate device models improves widi practice and experience.<br />
3.4 The Diode Small-Signal Model at Low Frequencies<br />
We will encounter many examples of electronic circuits in which dc supply voltages are used to<br />
bias a nonlinear device at an operating point and a small ac signal is injected into the circuit. We<br />
often split analysis of such circuits into two parts. First, we analyze the dc circuit to find the<br />
operating point. In this analysis of bias conditions, we must deal with die nonlinear aspects of the<br />
device. In the second part of the analysis, we consider the small ac signal. Since virtually any<br />
nonlinear characteristic is approximately linear (straight) if we consider a sufficiendy small<br />
portion, we can find a linear small-signal equivalent circuit for the nonlinear device to use in<br />
die ac analysis.<br />
The small-signal linear equivalent circuit is an important analysis approach that applies to many<br />
types of electronic circuits. In diis section we demonstrate the principles with a simple diode<br />
circuit. In the next chapter we use similar techniques for transistor amplifier circuits.<br />
Now we will show that in the case of a diode, the small-signal equivalent circuit consists of a<br />
resistance. Consider a conceptual circuit in Fig. 3.17a and the corresponding graphical<br />
representation in Fig. 3.17b. A dc voltage Kp, represented by a battery, is applied to the diode;<br />
and a time-varying signal iy(/), assumed (arbitrarily) to have a triangular waveform, is added to<br />
(superimposed on) the dc voltage V D . In the absence of the signal ty(/) die diode voltage is equal<br />
to Vp, and correspondingly the diode will conduct the current I D given by the Shockley equation<br />
(3.1), which for V D »V T , (i.e. for sufficiently large forward current) simplifies to<br />
/ D = / S exp(-^T) (3-10)<br />
When die signal ta(/) is applied, the total instantaneous diode voltage v D (t) will be given by<br />
v D (t) = V D +v d (t) (3.11)<br />
Correspondingly, the total instantaneous diode current i D (t) will be<br />
K ' +V < ( 'fl (3,2,<br />
which can be rewritten<br />
-61-
Analog Electronics /Diodes<br />
Figure 3.17 Development of a diode small-signal model<br />
Using (3.10) we obtain<br />
/ D (0 = / D exp(^J<br />
(3.14)<br />
Now if the magnitude of the signal vt(t) is kept sufficiently small such that<br />
v,(0<br />
« 1<br />
(3.15)<br />
nV T<br />
then we may expand the exponential of (3.14) into the Taylor series and truncate the series after<br />
the first two terms to obtain approximate expression<br />
V ' ( '^ (3.16)<br />
i D (0 = I D ! + • nVT J<br />
This is the small-signal approximation. It is valid for signals whose amplitudes are smaller than<br />
about lOmV.<br />
From (3.16) we have<br />
i D (0 = I D +^-v d (t) (3.17)<br />
Thus superimposed on the dc current I D we have a signal component directly proportional to the<br />
signal voltage m(/). That is<br />
where<br />
Analog Electronics / Diodes<br />
r
Analog Electronics /Diodes<br />
Notice that the ac signal to be attenuated is connected to the circuit by a coupling capacitor.<br />
The output voltage is connected to the load R^ by a second coupling capacitor. However, the<br />
coupling capacitors are open circuits for dc. Thus die j2-point of die diode is unaffected by the<br />
signal source or the load. Furthermore, the coupling capacitors prevent (sometimes-undesirable)<br />
dc currents from flowing in the source or the load.<br />
Figure 3.19 Variable attenuator using a diode as a controlled resistance<br />
Because of the coupling capacitors, we only need to consider V c , R^ and the diode to perform<br />
the dc analysis to find the =
Analog Electronics / Diodes<br />
Figure 3.21 Small signal equivalent circuit for Figure 3.19<br />
Exercise 3.6 Suppose that the circuit of Fig. 3.19 has R = 100 Q, R^ - 2 kQ, and R L = 2 kQ.<br />
The diode has n - land is at a temperature of 300K. For purposes of j2-point analysis assume a<br />
constant diode voltage of 0.6 V. Find the j2-point value of the diode current and A vs for (a) V c -<br />
1.6 V and (b) V c = 10.6 V. Ans. (a) 1 D = 0.5 mA,A v = 0.331, (b) 7 D = 5*1^,^ = 0.0492.<br />
An application for voltage-controlled attenuator occurs in tape recorders, as an example. A<br />
problem frequently encountered in recording a conversation is that some persons speak quietly,<br />
whereas others speak loudly. Furthermore, some may be far from the microphone, whereas<br />
others are close. If an amplifier with fixed gain is used between the microphone and the tape<br />
head, either the weak signals are small compared the noise level or the strong signals drive the<br />
recording nonlinear so that severe distortion occurs.<br />
Figure 3.22 The voltage-controlled attenuator is useful in maintaining a<br />
suitable signal amplitude at the recording head<br />
A solution is to use a voltage-controlled attenuator placed between the microphone and a highgain<br />
amplifier in a system like that shown in Fig. 3.22. When the signal being recorded is weak,<br />
the control voltage is small and very little attenuation occurs. On the other hand, when the signal<br />
is stron^, the control voltage is large, so the signal is attenuated, preventing distortion. Rectifying<br />
the output of the amplifier generates the control voltage. The rectified signal is filtered by a longtime-constant<br />
RC filter so that the attenuation responds to the long-term average signal<br />
amplitude rather than adjusting too rapidly. With proper design, this system can provide an<br />
acceptable signal at the recording heads for a wide range of input signal amplitudes. Eventually,<br />
we will discuss all of the circuits required in this system.<br />
-65-
Analog Electronics /Diode Circuits<br />
3.5 Rectifier Circuits<br />
Now that we have introduced the diode and some methods for analysis of diode circuits, we<br />
consider some practical circuits. First, we consider several types of rectifiers that convert ac<br />
power into dc power. These rectifiers form the basis for electronic power supplies and batterycharging<br />
circuits. Other applications for rectifiers are in signal processing, such as demodulation<br />
of a radio signal, or measuring the average amplitude of a signal from a microphone, as<br />
considered in the previous section. Another application is precision conversion of an ac signal to<br />
the dc in an electronic voltmeter.<br />
Half-wave rectifier circuits. A half-wave rectifier with a sinusoidal source and resistive load is<br />
shown in Fig. 3.23a. (The same circuit has already been analyzed in Section 3.1, for the ideal<br />
diode case.). When the source voltage is positive, the diode is in the forward-bias region. If an<br />
ideal diode is assumed, the source voltage appears across the load. For a typical real diode, the<br />
output voltage is less than the source voltage by an amount equal to the drop across the diode,<br />
which is about 0.7V for silicon diodes at "room temperature". This can be seen in Fig. 3.23b.<br />
(a)<br />
(b)<br />
Figure 3.23 Half-wave rectifier with resistive load (a); input and load voltages versus time (b)<br />
If the source voltage is negative, the diode is reverse b;.. :d and no current flows through the<br />
load. Even for typical real diodes only a very small reverse current flows. Thus only the positive<br />
half-cycles of the source voltage appear across the load. One can use a half-wave rectifier to<br />
charge a battery, as shown in Fig. 3.3a. Current flows in that circuit whenever the instantaneous<br />
ac source voltage is higher than the battery voltage. As shown in the figure, it is often necessary<br />
to add resistance in series with the diode to limit the magnitude of the current. When the ac<br />
source voltage is less than'the battery voltage, the current is zero. Thus the current flows only in<br />
die direction that charges the battery.<br />
Half-wave rectifier with smoothing capacitor. Often, we want to convert an ac voltage into a<br />
nearly constant dc voltage to be used as a power supply for our designs. One approach to<br />
smoothing the rectifier output is to place a large capacitor across the output terminals of the<br />
rectifier. The circuit and waveforms of current and voltage are shown in Fig. 3.24. When die ac<br />
source reaches a positive peak, the capacitor is charged to the peak voltage (assuming an ideal<br />
diode). Then when the voltage drops below the voltage stored on the capacitor, the diode is<br />
reverse biased and no current flows through the diode. The capacitor continues to supply current<br />
to the load, slowly discharging until the next positive peak of the ac input. As shown in the<br />
figure, current flows through the diode in pulses that recharge the capacitor.<br />
-66-
Analog Electronics /Diode Circuits<br />
« (b)<br />
Figure 3.24 Half-wave rectifier with smoothing capacitor (a); voltage and current waveforms (b)<br />
Because of the charge and discharge cycle, the load voltage contains a small ac component called<br />
ripple. Usually, it is desirable to minimize ripple, so we choose the largest capacitance value that<br />
is practical. In this case, the capacitor discharges for nearly the entire cycle, and the charge<br />
removed from the capacitor during one discharge cycle is<br />
QsJJ (3.26)<br />
where I L is the average load current and T is the period of the ac voltage. Since the charge<br />
removed from the capacitor is the product of the change in voltage and the capacitance, we can<br />
also write<br />
Q=V r C (3.27)<br />
where V r is the peak-to-peak ripple voltage and C is the capacitance. Equating the right-hand<br />
sides of (3.27) and (3.26) allows one to solve for C<br />
/ T<br />
c=-£- (3.28)<br />
In practice, Equation (3.28) is approximate because the load current varies in time and because<br />
the cap; itor does not discharge for a complete cycle. However, it gives a good-starting value for<br />
the capacitance required in the design of power-supply circuits. We will return to the subject of<br />
power-supply design after we have introduced transistor circuits and operational amplifier<br />
feedback circuits.<br />
The average voltage supplied to the load if a smoothing capacitor is used is approximately<br />
midway between the minimum and maximum voltages. Thus, referring to Fig. 3.24, the average<br />
load voltage is<br />
V.<br />
v L =v m -v D - (3.29)<br />
An important aspect of rectifier circuits is the peak inverse voltage (PIV) across the diodes. Of<br />
course, the breakdown specification of the diodes should be greater in magnitude than PIV. For<br />
example, in the half-wave circuit with a resistive load, shown in Fig. 3.23, the PIV is V m .<br />
Addition of a smoothing capacitor in parallel with the load increases the PIV to (approximately)<br />
2V m . Referring to Fig. 3.24, for the negative peak of the ac input, we see that the reverse bias of<br />
the diode is the sum of the source voltage and the voltage stored on the capacitor.<br />
Full-wave rectifier circuits. Several full-wave rectifiers are in common use. One approach<br />
uses a center-tapped transformer and two diodes as shown in Fig. 3.25a. This circuit consists of<br />
-67-
Analog Electronics/Diode Circuits<br />
two half-wave rectifiers widi out-of-phase source voltages and a common load. The diodes<br />
conduct on alternate half-cycles.<br />
Figure 3.25 Center-tapped-transformer full-wave rectifier<br />
Besides providing the out-of-phase ac voltages, the transformer also allows adjustment of V m by<br />
selection of turns ratio. This is an important function because the ac voltage available is often not<br />
suitable for direct rectification - usually either higher or lower dc voltage is required.<br />
A second type of full-wave rectifier uses the diode bridge shown in Fig. 3.26a. When the ac<br />
voltage is positive at the top of the secondary winding, current flows through diode A, then<br />
through the load and returns through diode B as shown in the figure. For the opposite polarity,<br />
i.e. during the alternate half-cycle, current flows through diodes C and D. Notice that in either<br />
case the current flows in the same direction through the load. For real diodes, the peak voltage<br />
across the load is lower in the case of the diode bridge rectifier circuit compared to the centertapped<br />
transformer rectifier circuit. This is because two diodes are connected in series with the<br />
load in the diode bridge circuit and, consequently, twice the voltage drop across a forward-biased<br />
diode is subtracted from the ac source voltage to obtain the load voltage. A single voltage drop<br />
across the diode is subtracted in the case of the circuit in Fig. 3.25a. This property is illustrated in<br />
Fig. 3.26b and Fig. 3.25b.<br />
If one side of die load is connected to die ground as shown in Fig. 3.26a, neither of the ac source<br />
terminals of the diode bridge can be connected to the ground. The transformer with floating<br />
secondary winding helps to realize this condition. (If both the ac source and the load had a<br />
common ground connection and no transformer was used, part of die circuit would be shorted.)<br />
If one wishes to smooth the voltage across the load, a capacitor can be placed in parallel with the<br />
load similar to the half-wave circuit discussed earlier. In the full-wave circuits, the capacitor<br />
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Analog Electronics /Diode Circuits<br />
discharges for only a half-cycle before being recharged. Thus the capacitance required<br />
maintaining a given level of ripple is only half as much in the full-wave circuit as for the halfwave<br />
circuit. Therefore, Equation (3.28) can be modified to obtain<br />
C = - L -<br />
IV.<br />
for the full-wave rectifier with a capacitor filter.<br />
(3.30)<br />
-5.9U +<br />
*•<br />
n UUMIU)<br />
•. UC2)<br />
(b)<br />
Fig. 3.26 Diode-bridge full-wave rectifier<br />
Power supply circuit. A diode rectifier forms an essential building block of the dc power<br />
supplies required to feed electronic equipment. A block diagram of such a power supply is shown<br />
in Fig. 3.27. As indicated, the power supply is fed from the 220-V (tms) 50-Hz ac line, and it<br />
delivers a dc voltage V L (usually in the range of 5 to 20V) to an electronic circuit represented by<br />
the load block. The dc voltage V L is required to be as constant as possible in spite of variations<br />
in the ac line voltage and in the current drawn by the load. Normally, the ripple at the output of a<br />
rectifier circuit, with a smoothing capacitor of practical value, are to big and do not fulfill the<br />
requirements of most electronic equipment Further means are necessary to stabilize (regulate)<br />
the voltage across the load.<br />
-69-
Analog Electronics /Diode Circuits<br />
The first block in the power supply is the power supply. It consists of two separate coils wound<br />
around an iron core that magnetically couples the two windings. The primary winding, having<br />
N 7 turns, is connected to the 220-V ac supply. The secondary winding, having N 2 turns, is<br />
connected to the rectifier circuit We denote the turns ratio by n=N 1 /N 2 . Thus an ac voltage v s of<br />
220/ ft V(rms) develops between the two terminals of the secondary winding. By selecting the<br />
appropriate turns ratio n for the transformer, the designer can step the line voltage down to the<br />
value required to yield the particular dc voltage output of the supply. For instance, a secondary<br />
voltage of 8-V rms is usually required for a dc output of 5V. This can be achieved with the<br />
«=28:1 turns ratio.<br />
It should be noted that to simplify the discussion, zero-resistance transformer windings ate<br />
assumed for the rectifier circuits analyzed in this Section. Thus the results obtained are<br />
approximate only; however, they can still be sufficiently accurate for low-power applications.<br />
In addition to providing the appropriate sinusoidal amplitude for the dc power supply, the power<br />
transformer provides electrical isolation between the electronic equipment and die power line<br />
circuit. The isolation minimizes die risk of electric shock to the equipment user.<br />
The diode rectifier converts the input sinusoid v s to a unipolar output that can have a pulsating<br />
waveform indicated in Fig. 3.27. Although this waveform has a nonzero average, or a dc<br />
component, its pulsating nature makes it unsuitable as a dc source of electronic equipment, hence<br />
die need for a filter that suppresses high-frequency components of the rectifier's signal In its<br />
simplest form, the filter is a smoothing capacitor, as discussed above. The filter block in Fig. 3.27<br />
significantly reduces the variations of the rectifier output.<br />
The filtered rectifier output, though much more constant than without the filter, still contains a<br />
time-dependent component, known as ripple. To reduce the ripple and to stabilize the magnitude<br />
of the dc output voltage of the supply against variations caused by changes of in load current, a<br />
voltage regulator is employed. Such a regulator can be implemented using a Zener diode, which<br />
will be discussed, in the following section. Alternatively, an integrated circuit (IC) regulator can<br />
be used.<br />
Exercise 3.7 A power-supply circuit is needed to deliver 0.1 A and 15V (average) to the load. The<br />
ac source available is 220V rms with a frequency of 50Hz. Assume that the full-wave circuit of.<br />
Fig. 3.26 is to be used with a smoothing capacitor in parallel with the load. The peak-to-peak<br />
ripple voltage is to be 0.4V. Allow 0.7V for forward diode drop. Find the turns ratio n needed<br />
and the approximate value of die smoothing capacitor. Verify your results using SPICE. Ans.<br />
»=18.74, C=2500nF.<br />
Exercise 3.8 Repeat Exercise 3.7 using the circuit of Fig. 3.25 with a smoothing capacitor in<br />
parallel with the load resistance. (Define the turns ratio as the ratio of primary turns to the<br />
secondary, turns between the center tap and one end.) Verify your results using SPICE. Ans.<br />
»=19.58, C=2500nF.<br />
3.6 Zenor-Diode Voltage Regulator Circuits<br />
The circuit shown in Fig. 3.28 is used to provide a nearly constant output voltage from a variable<br />
source. (For its proper operation, it is necessary for the minimum value of the variable source<br />
voltage to be somewhat larger than the desired output voltage.) A Zener diode having a<br />
breakdown voltage equal to the desired output voltage is used. The resistor R limits die diode<br />
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Analog Electronics /Diode Circuits<br />
current to a safe value so that the Zener diode does not overheat Moreover, as will be shown<br />
later, the larger the value of R, the lower the output voltage variation for a given diode.<br />
'o<br />
Figure 3.28 A simple regulator circuit that provides a nearly constant<br />
output voltage from a variable input voltage<br />
Assuming that the characteristic of the diode is available, one can use a load-line construction<br />
(see Section 3.2) to analyze the operation of the circuit. As before, we use Kirchhoff s voltage law<br />
to write an equation relating v D to ijy. In this circuit, the diode operates in the breakdown region<br />
with negative values of v D and /p. For the circuit of Fig. 3.28, one obtains<br />
V ss + Ri D +v D =0 (3.31)<br />
This is the equation'of a straight line, so location of any two points is sufficient to construct the<br />
load line. Inspection of (3.31) shows that the slope of the load line is -1/R. Thus a change of the<br />
input voltage changes the position but not the slope of the load line. The intersection of the load<br />
line with the diode characteristic yields the operating point.<br />
Example 3.5 The voltage regulator circuit of Fig. 3.28 has R = 1 kfl and uses the Zener diode<br />
having the characteristic shown in Fig. 3.29. Find the output voltage for V ss — 15 V. Repeat for<br />
^=20V.<br />
Solution The load lines for both values of V ss are shown in Fig. 3.29: The output voltages are<br />
determined from the operating points where the load lines intersect the diode characteristic. The<br />
output voltages are found to be «y=10.0V for V SS =\5V and t^lO.SV for V SS =20V. Thus a 5 V<br />
change in the input voltage results in only a 0.5-V change in the regulated output voltage.<br />
irfmA)<br />
vjbOO<br />
Figure 3.29 Graphical analysis of the circuit of Fig. 3.28<br />
Actual Zener diodes are capable of much better performance than the one illustrated by Example<br />
3.5. The slope of the Zener diode characteristic has been accentuated in Fig. 3.29 for clarity.<br />
Actual Zener diodes have a more vertical slope in breakdown.<br />
The circuit of Fig. 3.28 is known as a shunt regulator because the Zener diode is connected in<br />
parallel (shunt with the load. The circuit is fed with a voltage that, as indicated in Fig. 3.27, is not<br />
very constant; it includes a large tipple component from a rectifier circuit. The load can be a<br />
simple resistor or a complex electronic circuit.
Analog Electronics / Diode Circuits<br />
The function of the regulator is to provide an output voltage v L that is as constant as possible in<br />
spite of the ripples in V ss and the variation in the load current I L . Two parameters can be used<br />
to measure how well the regulator is performing its function: the line regulation and the load<br />
regulation. The line regulation is defined as the change in V L corresponding to 1-V change in<br />
V ss<br />
Line regulation = AV,<br />
(3.32)<br />
AK<br />
ss<br />
and is usually expressed in mV/V. The load regulation is defined as the change in<br />
corresponding to a small change in I L<br />
Load regulation = —— (3.33)<br />
V L<br />
Variable<br />
supply<br />
V L =-v D<br />
0 (b)<br />
Figure 3.30 Piecewise linear model (a) for the Zener diode, valid for VD
Analog Electronics / Diode Circuits<br />
3.7 Wave-Shaping Circuits<br />
A wide variety of wave-shaping circuits find application in electronic systems. One of them is<br />
in function generators used to generate electrical test signals for laboratory work. In a function<br />
generator, a switching oscillator is used typically to generate a square wave. This square wave is<br />
then passed through a circuit that integrates it, resulting in a triangular waveform. Then the<br />
trianguk: waveform is passed through a carefully designed wave-shaping circuit to produce<br />
sinusoidal waveform. All three waveforms are available to the user. We will consider the design<br />
of such a function generator later. Numerous examples of wave-shaping circuits can be found in<br />
transmitters and receivers for television, as another example. In this section we discuss a few<br />
examples of wave-shaping circuits that can be constructed using diodes.<br />
Clipper Circuits. Diodes can be used to form clipper circuits in which a portion of input<br />
signals waveform is "clipped" off. For example, the circuit of Fig. 3.32a clips off any part of die<br />
input waveform above 6V and below -9V. (We are assuming ideal diodes.) If the input voltage is<br />
between -9V and 6V, both diodes are off and no current flows through them. Then there is no<br />
voltage drop across R and the output voltage v 0 is equal to the input voltage v s . On the other<br />
hand, if v s is larger than 6V, diode A. is on and the output voltage is 6V because the diode<br />
connects the 6-V battery to the output terminal. Similarly, if v s is lower than -9V, diode B is on<br />
and the output voltage is -9V. The output voltage resulting from 15V-peak triangular input is<br />
shown in Fig. 3.32b. The transfer characteristic of the circuit is shown in Fig. 3.32c.<br />
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Analog Electronics /Diode Circuits<br />
Figure 3.32 Clipper circuit (a), its input and output waveforms (b) and<br />
transfer characteristic (c)<br />
The resistor R is selected large enough so that the forward diode current is within reasonable<br />
bounds (usually, a few milliamperes) but small enough so that the reverse diode current results in<br />
a negligible voltage drop. Often, we find that a wide range of resistance values provide<br />
satisfactory performance in a given circuit.<br />
In Fig. 3.32 we have assumed ideal diodes. If low-current silicon diodes are used, we expect a<br />
forward drop of about 0.6V, so we should reduce the battery voltage to compensate.<br />
Furthermore, batteries are not desirable for use in circuits if they can be avoided, because may<br />
need periodic replacement. Thus a better design uses Zener diodes instead of batteries. Practical<br />
circuits equivalent to Fig. 3.32a are shown in Fig. 3.33. 'Tie Zener diodes are labeled with their<br />
breakdown voltage. The circuits shown in Fig. 3.33 have learly the same performance as the<br />
circuits of Fig. 3.32.<br />
/f=2kii<br />
/f=2kn<br />
v o (0<br />
. 00 (b)<br />
Figure 3.33 Circuit of Fig. 3.32a with batteries replaced by Zener diodes and<br />
allowance made for a 0.6 forward diode drop (a); simpler circuit (b)<br />
Exercise 3.9 Sketch the transfer characteristic for the circuits of Fig. 3.34a and 3.34b. Allow for<br />
a 0.6V forward drop for die diodes. Sketch the output voltage if *> s (/)=15sin(ey/).<br />
-74-
Analog Electronics /Diode Circuits<br />
(a)<br />
Figure 3.34 Clipper circuits for Exercise 3.9<br />
(b)<br />
Clamp Circuits. Another diode wave-shaping circuit is the clamp circuit that is used to add a<br />
dc component to an ac-input waveform, so that the positive (or negative) peaks are forced to<br />
take a specified value. In other words, the peaks of the waveform are. "clamped" to a specified<br />
voltage value. A simple clamp circuit example is shown in Fig. 3.35. In this circuit, the positive<br />
peaks of die input are clamped to -5V. As an application example, clamp circuits are used to<br />
restore die dc component (black picture level) of video signals transmitted through ac-coupled<br />
channels.<br />
In the circuit of Fig. 3.35 the capacitor is a large value, so it discharges only very slowly and we<br />
can consider the voltage across the capacitor to be constant. Because the capacitance is large, die<br />
capacitor has very small impedance for the ac-input signal. Thus the output voltage of the circuit<br />
is given by<br />
v o (0 = v 5 (0-^c (3-35)<br />
If die positive swing of the input signal attempts to force the output voltage to become more<br />
positive than -5V, the diode conducts, charging die capacitor and thus increasing the value of V c .<br />
Thus the capacitor is charged to a value that adjusts the maximum positive value of the output<br />
voltage to -5V. A large resistor R is provided so that the capacitor can slowly discharge. This is<br />
necessary so that the circuit can adjust if the input waveform changes to smaller peak amplitude.<br />
Of course, one can change the voltage to which the circuit clamps by changing the battery<br />
voltage in Fig. 3.35. Reversing the direction of the diode causes the negative peak to be clamped<br />
instead of the positive peak. Switched, or pulse operating clamp circuits are actually used in the<br />
video e upment.<br />
v„(V)<br />
Figure 3.35 Example clamp circuit (a); output waveform for<br />
triangular, 0 dc, 10-V peak-to-peak input (b)<br />
Selection of R and C values for clamp circuits is a compromise. On one hand, we want die<br />
capacitor to have very small impedance compared to the resistor for the ac signal. This is<br />
necessary because we want the ac part of the output waveform to be identical to the input. On<br />
the other hand, if we make the RC time constant too long, the circuit takes a long time to adjust<br />
to changes in input amplitude. For now we can choose R to be a fairly large resistor, say about<br />
100 kQ, so diat the peak diode currents are not required to be large (more than a few<br />
milliamperes). Then we pick C so that the RC time constant is large compared to the period of<br />
die ac input signal, say by an order of magnitude. (In the case of video signal, the discharge<br />
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Antdog Electronics / Diode Circuits<br />
period is equal to 64 |is, which is the duration of a single picture line.) This gives a clamp circuit<br />
with approximately the desired clamping action. Then we can simulate the circuit and adjust<br />
values until the performance is satisfactory. Finally, we can construct the circuit to measure its<br />
performance.<br />
3.8 Switching and High-Frequency Behavior of the pn Junction<br />
We have seen that the pn junction conducts little current when reverse biased and easily conducts<br />
a lot of current when forward biased. In many applications, such as high-speed logic circuits and<br />
high-frequency rectifiers, diodes that can switch rapidly between the conducting and<br />
nonconducting states are extremely desirable. Unfortunately, thepn junction displays two charge<br />
storage mechanisms that introduce delays and slow down the switching. Both of these<br />
mechanisms can be modeled as nonlinear capacitances.<br />
Due to the presence of the charge-storage effects, one has to distinguish between static and<br />
dynamic properties of any electronic device, using the diode as the simple example. The diode's<br />
familiar i-v characteristic is a static characteristic. For a one-port the word "static" implies that<br />
operation is described by an algebraic equation, i D —fiv^j, that relates corresponding dc voltage and<br />
current values, this is Equation (3.1) in the case of ideal pn junction. A device's static<br />
characteristic also relates time-varying voltages and currents, but only if the time variations are<br />
not "too fast". Electronic devices always contain internal capacitances that modify device<br />
behavior for fast signals. Therefore, these devices are described by differential equations, which<br />
reduce to algebraic equations for sufficiently slow signals. Thus "static" means that the device<br />
variables are changing at such low rates that their time derivatives in the differential equation are<br />
small enough to ignore. At high frequencies, derivatives of the circuit variables cannot be<br />
neglected and the device capacitances significantly affect the circuit performance. Before we<br />
consider charge storage in pn junctions, we briefly review conventional linear capacitors.<br />
A capacitor is constructed by separating two conducting plates by an insulator as shown in Figure<br />
3.36a. If voltage is applied to the capacitor terminals, charge flows in and collects on one plate.<br />
Meanwhile, current flows out of the other terminal and a charge of opposite polarity collects on<br />
the other plate. Positive charge accumulates on the plate to which the positive voltage is applied.<br />
This is illustrated in Figure 3.36b.<br />
Q<br />
Conducting<br />
plates<br />
Insulating<br />
dielectric ++++++++++++<br />
Figure 3.36 Parallel-plate capacitor (a), applying voltage to a capacitor causes a charge +J2 to accumulate<br />
on one plate and -Q to accumulate on the other plate (b)<br />
The magnitude of the net charge Q on one plate is proportional to the applied voltage V. Thus<br />
we have<br />
Q=CV (3.36)<br />
For a parallel-plate capacitor such as that shown in Figure 3.36, the capacitance is given by<br />
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Analog Electronics / Diode Circuits<br />
-f<br />
(3.37)<br />
where A is the area of one plate, d is the distance between the plates, and e is the dielectric<br />
constant of the material between the plates. Often, the dielectric constant is expressed as<br />
e = e r e 0 (3.38)<br />
where e r is the relative dielectric constant and Eo = 8.85xl0" 12 F/m'is the dielectric constant for<br />
vacuum. [Actually, (3.37) is an approximation valid for d much smaller than both the length and<br />
the width of the plates.] Notice that the capacitance of the parallel-plate capacitor is proportional<br />
to the area of the plates and inversely proportional to the distance between the plates.<br />
Depletion Capacitance. Now consider ike. pn junction under reverse bias. As the magnitude of<br />
the voltage applied to the junction is increased, the field in the depletion region becomes<br />
stronger, and the majority carriers are pulled back farther from the junction. This is illustrated in<br />
Figure 3.37.<br />
The charge in the depletion region is similar to the charge stored on parallel-plate capacitor.<br />
Unlike the parallel-plate capacitor, a larger distance separates each additional increment of charge<br />
stored in the depletion region. Thus the reverse-biased junction behaves as a capacitor, but its<br />
equivalent plates move apart with the voltage, so the capacitance is not constant. The stored<br />
charge is not proportional to the applied voltage. This capacitance is called the depletion<br />
capacitance. Because the relationship between the stored charge and the applied voltage is not<br />
linear, we say that the depletion capacitance is nonlinear.<br />
C j = dv D<br />
(3.39)<br />
in which dQ is the differential of the charge stored in one side of the depletion region, and dv D is<br />
the increment in the voltage which caused the charge increment. C\ is the capacitance of the<br />
diode for a small ac signal superimposed on a dc operating point.<br />
It can be shown that the incremental depletion capacitance is given by<br />
BIBLIOTEKA GLOWNA PL<br />
QWb^ 5<br />
-77
Analog Electronics / Diode Circuits<br />
C J=-<br />
1-<br />
V J0]<br />
~\m<br />
(3.40)<br />
in which Cjo is the incremental depletion capacitance for zero bias, v D is the voltage across the<br />
diode (which is negative for reverse bias), V® is the built-in barrier potential (typically about 1 V),<br />
and m is called the grading coefficient. For a linearly graded junction m — 1 /3, and for an abrupt<br />
junction m— 1/2.<br />
The zero-bias depletion capacitance Cjo is approximately proportional to the area of the junction.<br />
Thus it is larger for high-power rectifiers, which must be physically large to accommodate high<br />
power dissipation. The value of Cjo also depends on doping levels. In highly doped junctions, a<br />
large amount of charge can be stored close to the junction - similar to the parallel-plate capacitor<br />
with small plate separation. Thus we find high values of CJO for highly doped junctions and low<br />
values for lighdy doped junctions.<br />
A reverse-biased diode can be used in circuits as a variable, voltage-controlled capacitor. A<br />
control signal reverse biases the diode, and as the control signal changes, the capacitance of the<br />
diode varies accordingly. -Diodes designed to have smoothly varying capacitance over a wide<br />
range of control voltage are called variable-capacitance diodes or varicaps. They can be used<br />
in. an JLC resonant circuit to vary the resonant frequency. Variable capacitance diodes can be used<br />
to design bandpass filters for which a control filter vary the center frequency, e.g. to tune in to an<br />
AM radio station. Varicaps are also useful in the design of voltage-controlled oscillators in which<br />
the frequency of oscillation depends on the diode capacitance. An application of this is the<br />
automatic frequency control (AFC) circuit of an FM radio. Manufacturers offer diodes intended<br />
for these applications having zero-bias capacitance Cp ranging from 10 to 1000 pF.<br />
For the MV2201 variable-capacitance diode (Motorola), approximate values of the parameters of<br />
formula (3.40) are CJO = 15 pF, m = 0.43, and KJO = 0.75 V. A plot of the depletion capacitance<br />
versus bias voltage using these parameters is shown in Figure 3.38.<br />
Figure 3.38 Depletion capacitance versus bias voltage for the MV2201 varicap diode<br />
Diffusion capacitance. Another basic charge-storage mechanism occurs when thepn junction is<br />
forward biased. For simplicity, we consider an abrupt junction with much heavier doping on the<br />
p-side than on the »-side (Le. N A »N^). Sometimes this is called a/> + » junction, where "plus"<br />
refers to heavy doping of the />-material. For such a diode under forward bias, die current<br />
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Analog Electronics /Diode Circuits<br />
crossing the junction is due mainly to holes crossing from the/>-side to die /x-side. The current of<br />
electrons that are injected from the /r-side to the/>-side can be neglected.<br />
P<br />
P<br />
n-type<br />
n-type<br />
Stored<br />
charge<br />
Stored<br />
charge<br />
(a)/ D =J,<br />
(b)/ D =^>I,<br />
Figure 3.39 Hole concentration versus distance for two values of forward current<br />
Consider the hole concentration of the forward-biased p*n junction shown in Figure 3.39. The<br />
charge associated with the' holes that have crossed the junction is stored charge and is<br />
represented by the areas indicated in the figure. The charge is stored because a finite time passes<br />
before an average hole disappears due to electron-hole recombination. This time is called<br />
minority carriers lifetime. As the forward current is increased, more holes cross the junction and<br />
the stored charge increases. Because this charge is associated with bain that ice diffusing across<br />
the junction, we call the effect diffusion capacitance.<br />
It can be shown that the incremental diffusion capacitance is given approximately by<br />
in which T T is a parameter known as the transit time of the minority carriers. For the p + n<br />
junction, x T — Z" p is the lifetime of the holes on the »-side of the junction. On the other hand, f *. r<br />
the n + p junction, we have T T = r n , which is the lifetime of the free electrons on the/>-side. For \<br />
junction with comparable doping levels, r T is the weighted average of both lifetimes. Finally, I 0 s<br />
the j2-point diode current, and V T is the thermal voltage.<br />
9.2V It<br />
JT) c 40*B-9»IMlote><br />
Figure 3.40 Diffusion capacitance versus voltage for the 1N4148 diode<br />
Notice that the diffusion capacitance is proportional to the diode current. Thus the diffusion<br />
capacitance, like the current, increases rapidly when the voltage V D exceeds approximately 0.6 V<br />
for silicon devices at room temperature. A plot of the diffusion capacitance- of the 1N4148<br />
switching diode is shown in Figure 3.40. Under forward bias conditions, the diffusion capacitance<br />
is much larger than the depletion capacitance. (For the 1N4148 device, the depletion-capacitance<br />
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Analog Electronics /Diode Circuits<br />
parameter Cjo is approximately equal to 2 pF.) However, diffusion capacitance is negligible for<br />
reverse bias.<br />
Small-signal diode model at high frequencies. A small-signal equivalent circuit for the pnjunction<br />
diode is shown in Figure 3.41. The resistance R* represents the ohmic resistance of die<br />
material on both sides of the junction; r& is the dynamic resistance of die pn junction that is<br />
discussed in Section 3.4. Its value is given by Equation (3.20), which is repeated here for<br />
convenience<br />
nV T<br />
r *=-T (3-42)<br />
1 D<br />
Cj is the depletion capacitance and Cdif is the diffusion capacitance.<br />
All die equivalent circuit parameters except R» depend on the bias point Under reverse-bias<br />
conditions, Cdif is zero, and ra is an open circuit. Hence die equivalent circuit simplifies as shown<br />
in Figure 3.41b.<br />
This equivalent circuit is vahd for the ptt junction over a wide range of frequencies, provided that<br />
small-signal conditions apply. At very high frequencies, lead inductances and stray capacitances of<br />
the diode physical structure are added to provide adequate accuracy.<br />
Diodes are most often used with large signals, and their nonlinear behavior must be taken into<br />
account. Computer modeling does this most easily. We illustrate this widi a few examples.<br />
(a) Forward bias<br />
Figure 3.41 Small signal linear circuits for the/>«-junction diode at high frequencies<br />
Large-Signal Diode Switching. Consider the circuit shown in Figure 3.42. The waveform of<br />
die source voltage t>s is shown in Figure 3.43a. Until / = 10 ns, v, is +50 V and the diode is<br />
forward biased. At / = 10 ns, the source voltage jumps rapidly to -50 V, reverse biasing the diode.<br />
rj] tf=5kO ryj<br />
Figure 3.42 Circuit illustrating switching behavior of a/>«-junction diode<br />
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Analog Electronics /Diode<br />
Circuits<br />
-81-
Analog Electronics /Diode Circuits<br />
(d) Voltage across the diode (expanded scale)<br />
Figure 3.43 Waveforms for the circuit of Figure 3.42<br />
The resulting diode current is shown in Fig. 3.43b. As one might expect, the diode current is<br />
approximately (50 V)/(5 \£l) = +10 mA until / = 10 ns. Then the source voltage jumps to -50 V.<br />
Instead of dropping immediately to zero the diode current reverses to I R = -10 mA. At<br />
approximately / = 18.3 ns, -the current begins to fall in magnitude and approaches zero at / = 25<br />
ns. In the interval immediately after the source reverses polarity, the diode continues to act as it<br />
were forward biased. This is called the storage interval ft, as labeled in Figure 3.43.<br />
We can explain the behavior of the diode as follows. (To simplify the discussion, we assume a<br />
diode that is heavily doped on the/>-side compared to the «-side.) When forward bias is applied,<br />
holes flow across the junction into the »-side. The holes are minority carries there that diffuse<br />
into the «-side and eventually recombine with free electrons. When tfe reverses polarity, the holes<br />
stored in the »-side can again cross the junction back to the />-side. Until the supply of excess<br />
holes on the «-side is exhausted, current can easily flow in the reverse direction. This explains the<br />
storage interval of the diode current waveform.<br />
It can be shown that the storage interval for a/>»-junction diode is given by<br />
*,Z (3.43)<br />
B(l + B)<br />
in which T T is the transit time for the minority carriers and B= \I R /I F \ • I F is the forward current<br />
before switching and J R is the reverse current during the storage interval. The storage time<br />
becomes shorter at larger ratios B.<br />
After the excess holes have all recrossed the junction (or recombined with free electrons), the<br />
depletion capacitance of the diode is charged through the resistor. Thus, after the storage<br />
interval, we see an approximate exponential transient for the current in Figure 3.43b. (Since the<br />
depletion capacitance is nonlinear, the transient is not precisely exponential, as would be the<br />
transient in a linear RC circuit.) The interval for this transient, called transition time, is denoted<br />
by ft. By definition, the end of the transition interval occurs when the reverse diode current has<br />
reached a specific value, typically I R /10.<br />
The total time interval for the diode to become an approximate open circuit, called the reverse<br />
recovery time, is denoted by ftr. It is the sum of the storage time and the transition time.<br />
'«•='*+'/ (3-44)<br />
The transition time ft depends on the circuit resistance. Even though the depletion capacitance is<br />
nonlinear, the transition time is proportional to the circuit resistance.<br />
-82-
Analog Electronics /Diode Circuits<br />
The diode voltage is shown in Figure 3.43c. To be able to see the details of the diode voltage<br />
during forward bias, an expanded-scale waveform is also plotted in Figure 3.43d. Notice that the<br />
diode voltage remains positive during the storage time, showing that the diode continues to act as<br />
if it were forward biased, even though the current is in the reverse direction. The terminal voltage<br />
of the diode does fall somewhat when the current reverses, because the voltage drop across the<br />
ohmic resistance R, of the diode reverses polarity. Prior to / = 10 ns, the terminal voltage is the<br />
sum of the junction voltage and the ohmic drop. On the other hand, between / = 10 ns and t -<br />
18.3 ns the terminal voltage is the junction voltage minus the ohmic drop.<br />
Exercise 3.10 Consider the parallel-plate capacitor shown in Figure 3.36. The plates have<br />
dimensions of 20 |wm x 30 \ltn. (These dimensions are typical of the area of an integrated-circuit<br />
/>»-junction diode.) The relative dielectric constant of the material is ft = 11.9. (This is the value<br />
for silicon.) The capacitance is 1 pF, which is a typical zero-bias depletion capacitance for a lowpower<br />
diode. Find the distance between the plates. (The answer is the approximate zero-bias<br />
thickness of the depletion region.) Ans. d= 6.32x10 -8 m.<br />
Exercise 3.11 A certain abrupt-junction diode has a zero-bias depletion capacitance of 5 pF and<br />
a built-in barrier potential of 0.8 V. Compute the depletion capacitance for a reverse-bias voltage<br />
of (a) 5 V, (b) 50 V. Ans. 1.86 pF, 0.627 pF.<br />
Exercise 3.12 A certain diode has a transit time of 10 ns. Find values for the small-signal<br />
resistance and diffusion capacitance at I D = 5 mA. Assume the emission coefficient n-\ and a<br />
temperature of 300 K. Ans. r& - 5.2 Q., Cm = 1920 pF.<br />
Exercise 3.13 Consider the circuit of 3.42 with R changed to 50 kfi and with the source<br />
waveform of Figure 3.43a. (a) Think about the circuit and sketch the current versus time. Make<br />
use of results shown in Figure 3.43, use (3.43) to estimate / r Like the time constant of an RC<br />
circuit, /, is approximately proportional to R. (b) Write a PSpice program to obtain the plot of the<br />
diode current. Compare the results. Ans. The current waveforms are similar to Figure 3.43b with<br />
I F = 1 mA and I R = -1 mA, 4 = 8ns and A = 50 ns.<br />
Exercit : 3.14 Consider the circuit of 3.42 with the input voltage "being equal to -50 V in die<br />
time interval from 0 to 10 ns, then jumping up to reach 50 V at 10.01 ns, staying at 50V until 30<br />
ns and returning to -50 V at 30.01 ns. Write a PSpice program to obtain the plot of the diode<br />
current. Explain.<br />
TABLE 3.1 SPICE PARAMETERS FOR INJUNCTION DIODES<br />
Text<br />
notation<br />
SPICE<br />
notation<br />
Default<br />
value<br />
I IS 1.0E-14A<br />
n N 1<br />
V, BV oo V<br />
h IBV 1.0E-3A<br />
R, RS 0Q<br />
c* CJO OFyfV<br />
m M 0.5<br />
y t V] 1.0 V<br />
b r r TT 0s<br />
-83-
Analog Electronics / Diode Circuits<br />
SPICE ParatL. jis for Diodes. Figure 3.41a is the SPICE equivalent circuit for th&pn junction<br />
diode. Table 3.1 lists nine parameters required to model the static and dynamic behavior of the<br />
diode. The first four, describe the static properties of the diode, as expressed by the Schockley<br />
equation (IS, N) and the following equation that approximates the breakdown component of the<br />
diode current<br />
i D = -I z exp - V Z+v D<br />
(3.45)<br />
in terms of parameters (VB and IBV), where VB = V z is the breakdown voltage and IBV = I z is<br />
die current that flows through the diode at v D = V z . The remaining five parameters (RS, CJO, M,<br />
YJ, TT) describe the dynamic properties of the diode, following Equation (3.40) for depletion<br />
capacitance and (3.41) for diffusion capacitance. The default values of the two key dynamic<br />
parameters, CJO and TT, are both zero. This means that tbcdefault diode model in SPICE is a static<br />
model. To simulate dynamic effects, these default values must be overridden by nonzero values in<br />
.MODEL statement. An example diode model for the 1N4148 low-power general-purpose diode<br />
can be specified as follows:<br />
.model D1N4148 D(I»-0.1p Rs=16 CJO=*2p Tt=12n Bv«100 Ibv=0.1p)<br />
3.9 Special Diodes<br />
3.9.1 Schottky diodes<br />
The junction between certain metals (e.g. aluminum) and lightly doped n-type material forms a<br />
Schottky diode. A typical structure is shown in Figure 3.44. (On the other hand, a metallic<br />
contact with heavily doped »-type material results in an ohmic contact.)<br />
The detailed theory of the Schottky diode is somewhat different from that of the pn junction.<br />
However, the form of the results is the same - the current in the Schottky diode is given by the<br />
Shockley equation. The saturation current 7, is much higher for Schottky diodes than for pn<br />
junctions of the same size. A typical value for a Schottky diode is 7 S = 10" 10 A, whereas for a<br />
typical IC pn junction it is 7 S = 10" 16 A. Because of the larper value of 7 S , the forward voltage of<br />
the Schottky diode is significandy smaller (about 0.4 V compared to 0.7 V for a silicon pn<br />
junction diode).<br />
Schottky j— Ohmic<br />
contact -v / contact<br />
Figure 4.44 Schottky diode<br />
Another important difference is that the Schottky diode does not display charge storage when<br />
being switched from forward conduction to reverse-bias conditions. This is because for forward<br />
bias electrons rather than holes are injected from metal anode into the n material. Thus majority<br />
carriers (i.e. electrons) carry the current, and storage of minority carriers does not occur. Hence<br />
switching tends to be faster for the Schottky diode. This fact can be used to advantage in die<br />
design of fast logic gates. An example of a bipolar transistor inverter with a Schottky diode is<br />
discussed in Chapter 6.<br />
-84-
Analog Electronics/Diode Circuits<br />
3.9.2 Light-Emitting Diodes and Photodiodes<br />
Light emitting diodes (LEDs) are junctions constructed of special semiconductor materials<br />
(compounds) such as gallium arsenide-phosphide. In these devices,' the injected minority carriers<br />
that result from forward biasing give up energy in the form of radiated light when they<br />
recombine. Wavelength ranging from ultraviolet through the visible and into die infrared bands is<br />
obtainable by use of different semiconductors and doping impurities. LEDs are widely used as<br />
display devices, for transferring information into optical fibers, and for optical isolation as<br />
discussed shortly<br />
[••<br />
'D<br />
+<br />
0.7V<br />
V D<br />
Figure 3.45 Volt-ampere curves of photodiode/solar cell<br />
A photodiode is a junction in which photons of energy in incident light break covalent bonds,<br />
adding the drift of these new carriers to the existing reverse saturation current. Figure 3.45 shows<br />
die volt-ampere curve of such a diode as a function of increasing incident light intensity. In tiie<br />
third and fourth quadrants the device functions as a (dependent) current source controlled by<br />
light. I s is the amount of current that can flows through the diode in dark, at a given temperature<br />
Operation in the third quadrant represents passive conversion of light intensity information in<br />
electrical information. This is the photodiode functioning as an optical to electrical transduce-<br />
Applications include light meters and communication systems that receive information coded in<br />
the form of light. The obvious circuit model is a light-intensity-controlled current source.<br />
Diodes designed for fourth quadrant operation are called photovoltaic cells or solar cells.<br />
Points on the curves in the fourth quadrant correspond to voltage and currents of opposite sign,<br />
implying an active device that delivers power to an external circuit. The curves emphasize that the<br />
solar cell is an active device for voltages not exceeding 0.7 V. Series connection of many solar<br />
cells produce large dc voltages. Parallel connection of solar cells of large area generates high<br />
output currents. Thus series-parallel interconnections can convert relatively large amounts of<br />
solar power into electrical power at convenient voltage levels. Solar cell efficiency (electrical<br />
output power divided by solar input power) is typically of the order of 10 -15 %.<br />
Figure 3.46a shows how the light-emitting diode and the photodiode are combined in a useful<br />
device called an optical isolator. The signal th(t) is transferred to the load by means of light, with<br />
no physical connection whatsoever between the input and output circuits. The optical isolator is<br />
useful in many applications, including computer interfaces for biomedical instrumentation. In<br />
these applications, we want to transmit information while protecting a human subject and<br />
delicate equipment from dangers imposed by high voltages in the input circuit Figure 3.46b<br />
illustrates the principle. Notice that the hazard voltage that exists in the circuit on the left is not<br />
transferred to the load circuit on the right. Transformers also give isolation; however, die optical<br />
isolator operates at frequencies down to dc and is smaller, lighter and less expensive.<br />
-85-
Analog Electronics / Diode Circuits<br />
3.9 Summary<br />
The semiconductor diode is basically a pn junction. Such a junction is formed in a single<br />
semiconductor material crystal, most often silicon crystal. In the forward direction, the ideal<br />
diode conducts any current forced by the external circuit while displaying a zero voltage drop.<br />
The ideal diode does not conduct in the reverse direction; any applied voltage appears as reverse<br />
bias across the diode. The unidirectional current flow property makes the diode useful in the<br />
design of rectifier circuits. The diode i-v characteristic is described by Schockley equation; the<br />
forward conduction of practical silicon diodes is accurately described by the relationship i =<br />
7sexp[f/(«l/ T )]. A silicon diode conducts a negligible current until the forward voltage is at least<br />
0.5 V. Then the current increases rapidly, with the voltage drop increasing by 60 or 120 mV<br />
(depending on the value of ») for every decade of current change. In the reverse direction, a<br />
silicon diode conducts a current of the order of 1 nA. This current is much greater than 7s and<br />
increases with the magnitude of reverse voltage. The diode i-v characteristic and parameters<br />
depend on temperature. Diodes designed to operate in the breakdown region are called Zener<br />
diodes. They are employed in the design of voltage regulators whose function is to provide a<br />
constant dc voltage tfiat varies litde with variation in power supply voltage and/or load current.<br />
A hierarchy of diode models exists, with the selection of an appropriate model dictated by the<br />
application. Analysis of diode circuits depends on viewing the diode as a 3-state device that, at a<br />
particular time operates in its ON, OFF or breakdown state. For each state, we replace the diode<br />
by a simple equivalent that approximates the diode's i-v characteristic and we then solve the<br />
resulting linear circuit to check our state assumptions. In many applications, a conducting diode<br />
is modeled as having a constant voltage drop, usually about 0.7 V. A diode biased to operate at a<br />
dc current I D has a small-signal resistance ra = nV T /I D . With the diode modeling and analysis<br />
techniques, we can describe many useful circuits such as half- and full-wave rectifiers, limiters,<br />
clamping circuits, voltage doublers and voltage regulators. These perform a variety of useful<br />
functions such as turning ac into dc, shifting waveform levels, modifying the shapes of time-<br />
-86-
Analog Electronics /Diode Circuits<br />
varying waveforms, and producing dc that is relatively independent of changes in loading and<br />
source voltage. There are two sources of parasitic capacitance within the pn junction: depletion<br />
capacitance, associated with the layers of bound ions in the depletion region, and diffusion<br />
capacitance, associated with storing excess minority charge carriers just outside the depletion<br />
region. When signals change slowly in diode circuits, these capacitances are insignificant, and the<br />
diode satisfies its static equation (i.e. Schockley equation). For rapid.transitions or fast signals,<br />
however, a more appropriate diode description is needed, which is a differential equation that is<br />
nonlinear when posed in terms of diode current or voltage. Because of diode capacitances, delays<br />
occur in diode switching, and waveform processing predicted upon static diode theory<br />
deteriorates at high frequencies. SPICE models for diodes were introduced. By understanding<br />
how SPICE parameters relate to the diode parameters we use in circuit analysis, we can use<br />
simulation to study with increased accuracy and precision both static and dynamic operation of<br />
diodes. With SPICE we can formulate more realistic circuit descriptions, relying on computation<br />
to verify and reinforce our understanding of diode circuits. Accuracy of computer simulation,<br />
such as obtained from SPICE, is limited by the approximations we made when building models<br />
for real-world, physical devices. A Schottky diode is based on metal-semiconductor junction. It<br />
features fast switching and lower voltage drop when forward biased as compared to pn junction<br />
diode. Light-emitting diode, the photodiode and optical isolator are examples of optoelectronic<br />
devices useful in telecommunications and instrumentation technology.<br />
Notes<br />
-87-
Analog Electronics / FET Circuits<br />
4 Field-Effect Transistor Circuits<br />
Now we turn our attention to devices that can amplify an input signal. In this chapter we<br />
consider the field-effect transistor (FET). In the first few sections of this chapter we describe<br />
the external characteristics of several types of FETs. Then we consider some simple but<br />
important circuits that use FETs, useful in amplifiers and logic circuits.<br />
4.1 The n-Channel Junction FET<br />
The simplified physical structure of an ^-channel junction field-effect transistor (FET) is<br />
shown in Fig. 4.1a, and the circuit symbol is shown in Fig. 4.1b. The device consists of a channel<br />
of »-type semiconductor with ohmic (nonrectifying) contacts at each end. These contacts are<br />
called the drain and the source. Alongside the channel, there are regions of ^-type<br />
semiconductor electrically connected to each other and to the gate terminal.<br />
(a)<br />
Figure 4.1 Simplified physical structure (a) of an ^-channel FET; its circuit symbol (b)<br />
The /w»-junction between the gate and the channel is a rectifying contact similar to />»-junction<br />
diodes discussed in Chapter 3. In almost all applications, this junction is reverse biased, so<br />
virtually no current flows in the gate terminal. Hence the gate is negative with respect to the<br />
channel in normal operation of an »-channel FET. (Recall that the/>-side is negative with respect<br />
to »-side for reverse bias of a/>»-junction.)<br />
Applying reverse bias voltage between gate and channel causes the depletion layer of the gatechannel<br />
junction to become wider. The greater the reverse bias, the wider this nonconductive<br />
layer becomes. Eventually, for VQS
Analog Electronics / FET Circuits<br />
'D<br />
Figure 4.2 Circuit for discussion of drain characteristics of the ^-channel FET<br />
Suppose that v GS is zero. Then, as v DS increases, i D increases as shown in Fig. 4.3. The channel is<br />
a bar of conductive material with ohmic contacts at the ends - exactiy the type of construction<br />
used for ordinary resistors. Therefore, it is not surprising the i D is proportional to v DSi for small<br />
values of t> DS .<br />
VG5=0<br />
Figure 4.3 Drain current versus drain-to-source voltage for<br />
zero gate-to-source voltage<br />
However, for larger values of v DS , drain current increases more and more slowly. This is because<br />
the end of the channel closest to the drain is reverse biased by the (v DS + \ v GS \) = v DS voltage. As<br />
v DS increases, the depletion layer becomes wider, causing the channel to have higher resistance.<br />
After the pinch-off voltage is reached, the drain current becomes nearly constant for additional<br />
Cutoff v cs
Analog Electronics / FET Circuits<br />
value is under the control of v GS . If v GS is less than the pinch-off voltage, v GS V P (4-4)<br />
In the linear region, the drain current is given by<br />
i D =K[2(v as -V J .)v DS -vl s ] (4.5)<br />
The constant K has units of current per volt 2 . Study of this equation for a fixed value of v GS<br />
shows that it describes a parabola passing through the origin of the ip-Vps plane. Furthermore,<br />
the maximum of the parabola is on the boundary between the linear and saturation regions.<br />
Saturation region. An ^-channel FET is in the saturation region if<br />
v G5 > V, (4.6)<br />
and if<br />
V GD=( V GS- V DS)< V P (4.7)<br />
In the saturation region, the drain current is given by<br />
i D =K(v GS -V p f (4.8)<br />
A plot of Equation (4.8) is shown in Fig. 4.5. This plot represents the so-called transfer<br />
characteristic of the FET in saturation.<br />
The drain current in the saturation region for v GS =0 is denoted as I DSS and is usually specified on<br />
manufacturers' data sheets. Substituting v GS =0 into (4.8) we find that<br />
Ioss=KV^ (4.9)<br />
Solving for K, we have<br />
* = 7T (4-10)<br />
If values are given for I DSS and Vp, the static characteristics of the JFET can be plotted. Typical<br />
values for a small-signal »-channel JFET are: I DSS =5-rl0mA and K P =-3V.<br />
-90-
Analog Electronics/FET Circuits<br />
IDSS<br />
+ *GS<br />
Figure 4.5 Plot of fa versus VDS in the saturation region of the FET<br />
Breakdown. As we mentioned earlier, there are several effects not modeled by the device<br />
equations we have given. An example of one of these effects occurs if the reverse bias between<br />
gate and channel becomes too large - then the junction experiences breakdown and the drain<br />
current increases very rapidly. Usually, the greatest reverse bias is at the "drain end of the channel,<br />
so breakdown occurs when V^Q exceeds the breakdown voltage V B in magnitude. Because v DG =<br />
V DS ' V GS> breakdown takes place at smaller values of v DS as P GS takes values closer to pinch-off.<br />
This is illustrated in Fig. 4.6. We seldom operate FETs in breakdown; however, breakdown<br />
voltage value V B should be taken into design consideration to avoid the device entering into this<br />
operation region.<br />
4.2 Me il-Oxide-Semiconductor FETs<br />
Another important class of devices is the metal-oxide-semiconductor field-effect transistor<br />
(MOSFET). There are two types, known as depletion MOSFETs and enhancement<br />
MOSFETs. Each of them can be realized as an w-channel or a/(-channel device. Basically, all of<br />
these FETs have very similar characteristics. Once you master one type, such as the »-channel<br />
JFET, it is much easier to assimilate the relatively minor differences between them. Circuit<br />
symbols for the »-channel and for the />-channel MOSFET devices are shown in Fig. 4.7. The<br />
circuit symbols for/>-channel are the same as the circuit symbols for n-channel devices except for<br />
the directions of die arrowheads. The MOSFET terminal labeled as B denotes the substrate or<br />
the body contact.<br />
Drain current versus v GS in the saturation region for »-channel devices is shown in Fig. 4.8. The<br />
depletion MOSFET has output characteristics nearly identical to those of die JFET. The main<br />
difference between die »-channel JFET and the »-channel MOSFET is in the fact diat the<br />
MOSFET can be operated with positive values of v Gs . (This is usually not done with the JFET<br />
because it would result in forward bias of the gate-to-channel junction and the corresponding<br />
-91-
Analog Electronics/FET Circuits<br />
increase of gate current.) The equations we have given in Section 4.1 for the ^-channel JFET also<br />
apply for the //-channel depletion MOSFET.<br />
Source<br />
<br />
(h)<br />
Figure 4.7 //-channel FETs circuit symbols (a, b, c),/(-channel FETs circuit symbols (d, e, f),<br />
simplified physical structure of the //-channel enhancement MOSFET (g)<br />
and the //-channel depletion MOSFET (h)<br />
No current flows in the //-channel enhancement MOSFET for v GS less than a certain positive<br />
value known as the threshold voltage which is denoted by V A . The equations we have given in<br />
Section 4.1 for the //-channel JFET also apply for the //-channel enhancement MOSFET if the<br />
(positive) threshold voltage Vth replaces the (negative) pinch-off voltage Vp. In particular, the<br />
enhancement MOSFET is cutoff for v GS < V&.<br />
The characteristics of the /(-channel FETs are the same as for the respective »-channel devices<br />
except that voltage polarities and current directions are inverted. If we continue to reference the<br />
drain current into the drain, the algebraic signs of the currents and voltages must be inverted for<br />
/(-channel devices. As a consequence, for the /(-channel devices the drain current is negative and<br />
the pinch-off voltage V p is positive for the JFET and for the depletion MOSFET. The threshold<br />
voltage Vfo for the/(-channel enhancement MOSFET takes on negative values.<br />
Figure 4.8 Transfer characteristics for FETs:<br />
(a) //-channel JFET and depletion MOSFET, (b) //-channel enhancement MOSFET,<br />
(c) /(-channel JFET and depletion MOSFET, (d)/(-channel enhancement MOSFET.<br />
-92-
Analog Electronics / FET Circuits<br />
Gate protection. Because of their construction, MOSFETs have extremely high input<br />
impedance between gate and channel - in excess of 1000MQ. This high impedance is due to a<br />
thin insulating (silicon dioxide) layer placed between gate and channel. In handling these devices,<br />
it is easy to develop sialic electric voltages greater than the breakdown voltage of the gate<br />
insulation. Breakdown of the insulating layer is destructive, usually resulting in a short circuit<br />
between gate and chat<br />
To alleviate this problem, the gate terminals are usually protected by back-to-back Zener diodes<br />
as shown in Fig. 4.9. If the device is exposed to a static electric charge, one of the Zener diodes<br />
breaks down (depending on die voltage polarity, the other diode is on), providing a<br />
nondestructive discharge path. Usually, die diodes are fabricated on die same chip of<br />
semiconductor as the FET.<br />
Variation in FET parameters with temperature. It is well known mat the semiconductor<br />
material mobility decreases with temperature. Because of more frequent collisions of charge<br />
carriers with the rapidly moving lattice ions. It turns out that the constant K in (4.5) and (4.8),<br />
which are valid for both JFETs and MOSFETs (with V p = Kth where appropriate), is<br />
proportional to the carrier mobility. Consequendy, their transfer characteristics change as in Fig.<br />
4.9b and 4.9c. It follows that the output characteristics for both devices crowd more closely as in<br />
Fig. 4.9d, juat opposite of bipolar transistor characteristics that are considered in Chapter 5.<br />
The threshold and pinch-off voltages decrease by about 2 mV/°C with increases in temperature,<br />
causing the curves in Fig. 4.9b and 4.9c to shift to the left with temperature increases as they<br />
droop downward.<br />
-93-
Analog Electronics / FET Circuits<br />
4.3 Load-Line Analysis of a Simple JFET Amplifier<br />
In this section we analyze the JFET amplifier circuit shown in Fig 4.10 by use of the graphical<br />
load-line approach. The batteries bias the JFET at a suitable operating point so that amplification<br />
of the input signal v s {f) can take place. We will see that the input voltage v s (t) causes v GS to vary<br />
with time, which in turn causes t D to vary. The changing voltage drop across R D causes an<br />
amplified version of the signal to appear at the drain terminal.<br />
Figure 4.10 Simple JFET amplifier circuit<br />
Applying Kirchhoff s voltage law to the input loop, we obtain the following expression:<br />
VGS(0 = V,(0-K GC (4.11)<br />
As an example, we assume that the input signal is a 1-V peak 1-kHz sinusoid and that V GG is IV.<br />
Thus we have<br />
v C5 (/) = sin(2000^) -1 (4.12)<br />
Writing a voltage equation around the drain circuit, we obtain<br />
V DD = R D i D {t) + v DS {t) (4.13)<br />
For our example, we assume that R D =l]sQ and V DD =20V, so Equation (4.13) becomes<br />
20 = * D (/) + v DS (0 (4.14)<br />
where we have assumed that i D (t) is in milliamperes. A plot of this equation on the drain<br />
characteristic of the transistor is a straight line called the load line. To establish the load line, we<br />
first locate two points on it. Assuming zero drain current, i D — 0, in (4.14) we find that v DS —2QW.<br />
These values plot as the lower right-hand end of the load line shown in Fig. 4.11. For a second<br />
point, we assume that v DS = 0, which yields / D =20mA when substituted into (4.14). This pair of<br />
values (y DS — 0 and i D = 20 mA) plots as the upper left-hand end of the load line.<br />
If v s {t) = 0, Equation (4.11) yields v GS = -VQQ — -1 V. Therefore, the intersection of the curve for<br />
P GS = -1- V with the load line is the quiescent operating point. The quiescent values are 7p = 9 mA<br />
andK D =llV.<br />
The maximum and minimum values of the gate-to-source voltage are J^cj-max = 0 V and V i GSnan<br />
= -2V [see Equation (4.12) and Figure 4.12]. The intersections of the corresponding curves with<br />
the load line are labeled as points A and 23, respectively, in Fig. 4.11. At point A, we find that<br />
^nrmin= 4 V and 1 ^ = 16 mA. At point B, we find that V DSm2x = 16 V and 1 ^ = 4 mA.<br />
94-
Analog Electronics / FET Circuits<br />
The plots of v s (t) and v DS (t) versus time are shown in Fig. 4.12. Notice that the peak-to-peak<br />
swing of the drain-to-source voltage is 12V, whereas the peak-to-peak swing of the input signal is<br />
2V. Furthermore, the ac voltage at the drain is inverted compared to the signal at the gate.<br />
Therefore, this is an inverting amplifier. Apparently, one can calculate the circuit gain as equal to<br />
A^ = -12/2 = -6, where the minus sign is due to the inversion.<br />
Figure 4.11 Drain characteristic and load line for the FET amplifier<br />
Notice, however, that the output waveform shown in Fig. 4.12 is not a symmetrical sinusoid Wte<br />
the input. For illustration, we see that starting from the j2-point at V D = 11 V, the output voltage<br />
swings down to Vi >m^a — 4 V for a change of 7 V. On the other hand, the output swings up to<br />
16V for a change of only 5V from the j2-point on the positive going half-cycle of the output We<br />
cannot properly define gain for the circuit because the ac output signal is not proportional to the<br />
ac input Apparendy the FET is a nonlinear device. Nevertheless, die output signal is larger th n<br />
die input signal even if it is distorted.<br />
The distortion is due to the fact that die characteristic curves for the FET are not uniformly<br />
spaced. Of course, if much smaller input signal were applied, we would obtain amplification<br />
without appreciable distortion.<br />
The rather modest gain (A^ = -6) that we see in this circuit is typical of RC-coupled FET<br />
amplifiers. In general, BJT amplifiers have much larger voltage gains. However, if we consider<br />
current gain, FET circuits have larger gains than most BJT circuits. For example, we have<br />
considered the input current for the circuit of Figure 4.10 to be zero. An infinite current gain<br />
would result if one attempts to calculate current gain as the ratio of the ac current in R D to tb-i<br />
input current. On die other hand, the current gain of a BJT ranges from about 10 to several<br />
hundred.<br />
The amplifier circuit we have analyzed in this section is fairly simple. Practical amplifier circuits<br />
are usually much more difficult to analyze by graphical mediods. Later in this chapter we develop<br />
a small-signal equivalent circuit for the FET, and then we can use mathematical circuit-analysis<br />
techniques instead of graphical analysis. Usually it is more useful for investigation of practical<br />
amplifier circuits. However, graphical analysis of simple circuits provides an excellent way to<br />
understand die basic concepts of amplifiers.<br />
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Analog Electronics / FET Circuits<br />
4.4 The Self-Bias Circuit<br />
Analysis of amplifiers is undertaken in two steps. First, we analyze the dc circuit to determine the<br />
j2-point In this analysis, the nonlinear device equations and/or curves are used. Then, after the<br />
bias is found, we use a linear, small-signal equivalent circuits to find the input resistance, voltage<br />
gain, and so on. In this section and die next, we consider analysis and design of dc bias circuits<br />
for FETs.<br />
The two-battery bias circuit used in the amplifier of Fig. 4.10 is not practical. Usually one battery<br />
is available only. Even more significant problem is that FET parameters vary considerably from<br />
device to device. For a given type of JFET, I DSS may vary by a ratio of 5:1. Furthermore, the<br />
pinch-off voltage is different from device to device.<br />
Plots of i D versus v GS are shown in Fig. 4.13 for extreme FETs, all of which have die same<br />
manufacturer's type number. The range of variation shown is typical. Notice that if V GS were the<br />
same for all devices, a considerable variation in I D would occur. Some devices would be biased at<br />
one end of the load line and others at the opposite end. On the other hand, to obtain the<br />
maximum symmetrical swing of the output voltage without severe distortion, we require the<br />
operating point to be near the middle of the load line for all devices. Thus a fixed-bias circuit<br />
that maintains the same value of V GS independent of the device parameters is not suitable for<br />
mass production.<br />
Figure 13 Transfer characteristics of extreme devices for JFETs having the<br />
same type number. Bias with fixed VGS results in a large variation of h.<br />
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Analog Electronics / FET Circuits<br />
A more practical circuit, known as the self-bias circuit, is shown in Fig. 4.14. The resistor R s is<br />
essential to the operation of this bias circuit. The resistor R^ is usually a large value (several<br />
megaohms) that maintains the dc voltage at the gate close to the ground and still provides high<br />
input impedance at the gate. Since only a small current (InA or less) flows in the gate, the dc<br />
voltage drop across RQ is negligible. In applications where input signal is not applied to gate, RQ<br />
can be replaced by a short circuit. The drain resistance R D is required to be present if we want an<br />
amplified signal to appear at the drain. However, in some circuits, the output is taken from the<br />
source terminal, and then we would replace R D by a short circuit.<br />
DD<br />
Figure 4.14 Self-bias circuit used for JFETs and depletion MOSFETs<br />
The drain current flows out through the source and through the source resistor R s , creating a<br />
voltage drop. Writing a voltage equation around the gate-source loop of Fig. 4.14 and neglecting<br />
the drop across RQ we have<br />
v G s=-Rsh (4-15)<br />
A plot of this equation is called the bias line and is shown in Fig. 4.15, which also shows i D<br />
versus v GS for extreme devices of a given type. The operating point is at the intersection of the<br />
bias line and the device transfer curve. Notice that V GS is smaller in magnitude for the lowcurrent<br />
device than for the high-current device. Thus the self-bias circuit adjusts V GS to<br />
compensate for changes in the device, thereby reducing variations in I D compared to a fixed-bias<br />
circuit.<br />
Bias line<br />
VQS=-RS'D<br />
Figure 4.15 Graphical analysis of the self-bias. The device-to-device variation of drain current is<br />
much less than for the fixed-bias circuit.<br />
The device curves shown in Fig. 4.15 are valid only if device operates in the saturation region.<br />
Usually, in FET amplifier circuits, operation in the saturation region is desired. However, we<br />
should check to make sure that V DS is large enough for operation in the saturation region before<br />
accepting results based on this analysis.<br />
VGS<br />
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Analog Electronics / FET Circuits<br />
Exercise 4.1 Design a self-bias circuit for an »-channel FET having I DSS =4toA and V P =-2V.<br />
The circuit is to have R D =2.2kQ, V DD =20V, and Ij^ltnA. Use standard 10%-tolerance resistor<br />
values. Ans. Ry=270Q.<br />
Exercise 4.2 Analyze the self-bias circuit designed in Exercise 4.1. Repeat the analysis for a highcurrent<br />
device having 7 Dxr =8mA and V P =-4V. Ans. VQ^-OSGV, J D =2.07mA, V DS =U.9V;<br />
V GS =-l.l2V,I D =4.UmA, V DS =9.11V.<br />
4.5 The Fixed- plus Self-Bias Circuit<br />
The self-bias circuit gives fair performance in maintaining a fixed I D from device to device, but<br />
sometimes better performance is needed. The fixed- plus self-bias circuit shown in Fig. 4.16<br />
provides a solution.<br />
For purposes of analysis, we replace the gate bias circuit with its Thevenin equivalent, as shown<br />
in Fig. 4.16b. The Thevenin voltage is<br />
VQ<br />
r .=V n<br />
X<br />
DD R,+R,<br />
(4.16)<br />
and the Thevenin resistance RQ is the parallel combination of R f and R 2 . Writing a voltage<br />
equation around the gate loop of Fig. 4.16b, we obtain<br />
V G = v GS + R s i D (4.17)<br />
Notice &at we have assumed that the voltage drop across R^ is zero. Now, if we assume that the<br />
transistor is in the saturation, we have<br />
i D =K(v GS -V P f (4.18)<br />
Simultaneous solution of (4.17) and (4.18) yields the operating point (provided that it falls in the<br />
saturation region). Then we can find v DS by writing a voltage equation around the drain loop<br />
v DS =r D0 -(tf 0 + * s )/, (4.19)<br />
(a)<br />
(b)<br />
Figure 4.16 Fixed- plus self-bias circuit. Original circuit (a),<br />
Gate t>ias circuit replaced by its Thevenin equivalent (b).<br />
Figure 4.17 shows the graphical solution of Equations (4.17) and (4.18). Notice that higher values<br />
of V G result in smaller variation in I D for extreme devices because die bias line becomes closer to<br />
horizontal. (Also notice that V G =0 corresponds to the self-bias circuit.) However we must not<br />
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Analog Electronics / FET Circuits<br />
choose V G too high because this raises the voltage drop across R s and sufficient voltage must be<br />
allocated for v DS and R D .<br />
Exercise 4.3 Design for V^SV a fixed- plus self-bias circuit for the JFET of Exercise 4.1<br />
having I DSS =4mA and V P =-ZV. The circuit is to have R p =2.2kQ, V DD =20V, and I^lmA. Use<br />
standard 10%-tolerance resistor values. Ans. Rj=2.7kfi.<br />
Exercise 4.4 Analyze the self-bias circuit designed in Exercise 4.3. Repeat the analysis for a highcurrent<br />
device having I DSS =SmA and V P =-4V. Ans. F GJ -=-0.564V, 7 D =2.06mA, V DS =9.9V;<br />
V GS =-\.76V,I D =2.50mA, V DS =7.73V.<br />
Figure 4.17 Graphical solution for the fixed- plus self-bias circuit.<br />
Note that ID is nearly independent of the device if VG yz large.<br />
Another advantage of the fixed- plus self-bias circuit is that it also works for enhancement<br />
MOSFETs. On the other hand, the self-bias circuit is not suitable for enhancement MOSFETs<br />
because the gate must be more positive than the source (assuming »-channel devices), which is<br />
not possible in the self-bias circuit.<br />
Example 4.1 Design a bias circuit for an «-channel enhancement MOSFET having K /4 =4V and<br />
K=10- 3 A/V 2 . The power supply voltage is V DD =\5V. A jg-point of ,K DJ -=5V and / p =5mA is<br />
desired. The circuit is to be used in an amplifier with the ac output taken from the drain terminal.<br />
Solution. Since an enhancement device is specified, we must use the fixed- plus self-bias circuit<br />
because the self-bias circuit would give a zero drain current regardless of the resistor value<br />
selected. The circuit is shown below. Values must be selected for R,, R^, R D and R s .<br />
Figure 4.18 Circuit of Example 4.1<br />
Since the supply voltage is 15V and a bias value V DS =5V is specified, a total of 10V remains to<br />
be divided between R D and R s . The drain current flows through both resistors, so we have<br />
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Analog Electronics / FET Circuits<br />
R S +R D = {yoD ~^DSr ID = 2^ • Equation (4.17) shows that larger voltages across R s result<br />
in higher values for V G . As we have seen, large values of V G lead to good bias stability. Thus we<br />
are led to allocate a large portion of the available voltage to the drop across R s . In the extreme<br />
case, this would produce R D =0 and Ry=2k£2. However, since an ac output signal is to be<br />
developed at the drain, R D =0 is not acceptable. Thus we select R D =Rj-=lkfi. (This choice is<br />
somewhat arbitrary - perhaps in a complete amplifier design, the ac performance required would<br />
dictate particular choice.)<br />
Assuming the MOSFET is operating in the saturation region, we have<br />
Io = K{Vcs-V lh ) 2<br />
Substituting values and solving, we find that V GS = 6.24V. Thus the gate voltage is given by<br />
V G =V GS + R s I D =n.2V<br />
Now we must find values for R, and R^, so that the 15-V supply voltage divides with 11.2V<br />
across R^ and 15-11.2=3.8V across R ; . If we make somewhat arbitrary choice that<br />
R,+R 2 =1.5MQ, then R,=380kQ and R 2 =\A2MQ provide the desired voltage division.<br />
Therefore we choose the closest standard values, namely R,=390kfi and R 2 =1.1MQ<br />
Exercise 4.5 (a) Analyze jhe circuit designed in Example 4.1 to find of V DS and I D . The answer<br />
should verify that the operating point achieved is close to the design objectives, (b) Repeat the<br />
analysis for an «-channel enhancement MOSFET having V tb =5V and K=2taA/V z . Ans.<br />
7 D =4.87mA, K DJ =5.27V; J D =4.56mA, V DS =5.STV.<br />
Exercise 4.6 A certain «-channel enhancement MOSFET has V lt =2V and K=2mA/V 2<br />
The bias<br />
circuit (as shown in Fig. 4.18) has V DD =20V, R 7 =R 2 =1MQ, R D =lkO and Rj-=2.2kQ. Find V DS<br />
and I D . Ans. J D =3.07mA, V DS =\0.2V.<br />
Exercise 4.7 Find the largest value of R D that can be used in the circuit of Exercise 4.6 if the<br />
MOSFET is to remain in saturation. Assume that R , R 2 , and R s remain fixed. Ans.<br />
R Dmax =3.91kQ.<br />
4.6 The Small-Signal Equivalent Circuit<br />
In the preceding two sections, we considered dc bias circuits for FET amplifiers. Now we<br />
consider the relationships, between the signal currents and voltages for small changes from Q-<br />
point. As usual, we denote total quantities by lowercase letters with uppercase subscripts such as<br />
/ D (/) and v G5 (t). The dc j2~point values are denoted by uppercase letters with uppercase subscripts,<br />
such as J D and V GS . The signals are denoted by lowercase letters with lowercase subscripts such as<br />
*d(/) and %i(^. The total current or voltage is the sum of the j2-point value and the signal. Thus we<br />
can write<br />
i D (0 = I D +iAO (4-20)<br />
and<br />
v GS (0 = f GS +v ff (0 (4-21)<br />
In the following we assume that the FETs are biased in the saturation region, which is usually die<br />
case for amplifier circuits. Equation (4.8), repeated here for convenience, gives the total drain<br />
current in terms of the total gate-to-source voltage.<br />
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Analog Electronics / FET Circuits<br />
i D =K(v GS -V P f (4.8)<br />
Substituting (4.21) and (4.20) into (4.8), we obtain<br />
I D +i d (0 = tfycs + v^ -V P ] 2 (4.22)<br />
The right-hand side of (4.22) can be expanded to obtain<br />
I D + /,(/) = K(V GS -V P f +2K(V GS -V P ) Vgs + Kv 2 m (4.23)<br />
However, the j2-point values are also related by (4.8), so we have<br />
Io=K{V GS -V P ) 2 (4.24)<br />
Therefore the first term on either side of Equation (4.23) can be cancelled. Furthermore, we are<br />
interested in small-signal conditions for which the last term on the right-hand side is negligible<br />
and can be dropped [i.e. we assume that |f G j(^| is much smaller than | Vcr^pW- With these<br />
changes, Equation (4.23) becomes<br />
(t) = 2K(v GS -V P )v gs (4.25)<br />
We define the transconductance of the FET as<br />
g„=2K(V GS -V P ) (4.26)<br />
Then Equation (4.25) can be written as<br />
'„(') = S.v,(0 ( 4 - 27 ><br />
The gate current of the FET is negligible, so we have<br />
/ f (0 = 0 (4.28)<br />
The small-signal equivalent circuit shown in Fig. 4.19 can represent equations (4.27) and (4.28).<br />
Thus die FET is modeled by a voltage-controlled current source connected between the drain<br />
and source terminals. The model has an open circuit between gate and source.<br />
Figure 4.19 Small-signal equivalent circuit for FETs<br />
Solving Equation (4.24) for the quantity (V GS - V P ) and substituting into Equation (4.26), we<br />
obtain<br />
g m = 24H~ D (4.29)<br />
Then if we use Equation (4.10) to substitute for K, we have<br />
which is often a convenient formula for computing the transconductance of a JFET or depletion<br />
MOSFET at a given j2-point. Of course, I DSS does not apply for enhancement MOSFETs, and<br />
Equation (4.29) applies for them.<br />
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Analog Electronics / FET Circuits<br />
Figure 4.20 Small signal equivalent circuit that accounts for the dependence of ID on ws<br />
Furthermore, the first-order equations we have given for the FET do not include a term to<br />
account for the small effect of (&. on the drain current Previously, we assumed that the drain<br />
characteristics are horizontal in the saturation region, but this is not exact — the drain<br />
characteristics slope slightly upward with increasing Pd>. If we wish to account for the effect of &<br />
in the small-signal equivalent circuit, a resistance r& called the drain resistance is added between<br />
the drain and source as shown in Fig. 4.20. Equation (4.27) becomes<br />
U = Sm v ** + r ds<br />
(4.31)<br />
Figure 4.21 Determination of ra from the FET drain characteristics using (4.33)<br />
The definition of the reciprocal of n (which actually is the drain conductance gd=l/rd) is the<br />
partial derivative of drain current with respect to %., evaluated at j^-point:<br />
1 Si n<br />
(4.32)<br />
Sv DS<br />
-t*a<br />
Q-foial<br />
which can be approximated as<br />
1 A/ " (4-33)<br />
- uo<br />
where AI D is an increment of drain current centered at the j2-point. Similarly, Avds, is an<br />
increment of drain current centered at the jg-point. Equation (4.33) is useful to evaluate the drain<br />
resistance from the output characteristic of the FET plotted for a constant v GS =V Gs . This is<br />
illustrated in Fig. 4.21.<br />
Similarly, an alternative definition of the transconductance ^ is the partial derivative of I D with<br />
respect to v GS , evaluated at j2-point:<br />
on<br />
Sv, GS Q-poinl<br />
which can be approximated as<br />
(4.34)<br />
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Analog Electronics / FET Circuits<br />
bm —<br />
ML<br />
Av<br />
GS<br />
(4.35)<br />
where At^ is an increment of drain current centered at die jg-point. Equation (4.35) is useful to<br />
evaluate die transconductance from die FET output characteristics plotted for two different<br />
values of gate-to-source voltage. This idea is illustrated in Fig. 4.22.<br />
Figure 4.22 Determination of g^ from die FET drain characteristics using (4.35)<br />
The device equations and the equivalent circuit that we have derived from them describe only the<br />
static behavior of die device. For rapidly changing currents and voltages, the additional<br />
capacitances are required for an accurate model. A small-signal FET model suitable to represent<br />
die JFET behavior for high-frequency operation is shown in Fig. 4.23.<br />
Thr^e capacitances are added to the circuit of Fig. 4.20 to obtain the circuit of Fig. 4.23. The<br />
gate-source and gate-drain capacitances, Cgs and Cgd, respectively, represent die junction<br />
capacitance of die gate-to-channel junction. These capacitances are nonlinear — they depend<br />
respectively on gate-drain and drain-source dc voltages, Cgs = J{V G s) an d Qd = J^YGD)- Th e<br />
function J{.) has die form of Equation (3.40) with v D = V GS for Cgs and v D = V DS for Cgd. The<br />
capacitance Cds. is mainly the stray capacitance between the drain and source terminals, so it is a<br />
linear (constant) capacitance to a first approximation.<br />
It should be noted diat small-signal high-frequency model for a MOSFET device is a little more<br />
complicated than the circuit of Fig. 4.23. Namely it comprises diree other capacitances,<br />
connected between the gate, source and drain terminals and die bulk terminal, respectively. These<br />
capacitances are nonlinear (junction) capacitances, unlike die Cgs and Cgd capacitances diat are<br />
stray capacitances for the MOSFET. Such a model will be discussed in Section 4.11 for die<br />
purpose of SPICE simulation of MOSFET circuit behavior. For approximate, simplified analysis<br />
die circuit shown in Fig. 4.23 can be used for both JFET and MOSFET devices.<br />
+ V DS<br />
Figure 4.23 Small-signal high-frequency JFET equivalent circuit<br />
The small-signal JFET equivalent circuits shown in Fig. 4.20 and 4.23 will be used in die next<br />
section to analyze properties of basic types of FET amplifiers at low and high frequencies.<br />
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Analog Electronics / FET Circuits<br />
4.7 Basic Small-Signal FET Amplifier Circuits<br />
The circuit diagram of a common-source amplifier is shown in Fig. 4.24. The ac signal to be<br />
amplified is supplied by %(/). The coupling capacitors C 1 and C 2 as well as the bypass capacitor C s<br />
axe. intended to have very small impedance for the ac signal. In this section we then carry out a<br />
midband analysis of the amplifier, in which we assume that these capacitors are short circuits for<br />
the signal. Later when we consider the frequency response of amplifiers, we include the<br />
capacitors. The resistors R^, R s , and R D form a self-bias network, and their values are selected to<br />
obtain a suitable j2-point. The amplified output signal appears as the voltage drop across the load<br />
resistor R L .<br />
The small-signal equivalent circuit for the amplifier is shown in Fig. 4.25. The input coupling<br />
capacitor has been replaced by a short circuit. The FET has been replaced by its small-signal<br />
equivalent, which is shown in Fig. 4.20. Because the bypass capacitor C s is assumed to be a short<br />
circuit, the source terminal of the FET is connected direcdy to ground - which is why the circuit<br />
is called the common-source amplifier (the source is common to die input and the output). The dc<br />
supply voltage source is considered to be a short circuit for the ac signal. Consequendy, the<br />
resistor R D appears connected from drain to ground.<br />
Figure 4.24 Common-source amplifier<br />
Next we consider the voltage gain of the amplifier. Refer to the small-signal equivalent circuit<br />
and notice that the resistances r d , R D , and R L are in parallel. We denote the equivalent resistance<br />
by<br />
R = - (4.36)<br />
Figure 4.25 Small signal equivalent circuit for the common-source amplifier<br />
The output voltage is the product of the current from the controlled source and the equivalent<br />
resistance.<br />
v 0 = -ig.vJR' L ( 4 ' 3 )<br />
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Analog Electronics /FET Circuits<br />
The minus sign is necessary because of the reference directions selected (i.e. the current g [a v s<br />
flows out of the positive end of the positive end of the voltage reference for pj.<br />
The input voltage and the gate-to-source voltage are equal to each other<br />
Now if we divide Equation (4.37) by (4.38), we find the voltage gain, which is given by<br />
A v =^ = -g m R 1 (4.39)<br />
The minus sign in the expression for the voltage gain shows that the common-source amplifier is<br />
inverting.<br />
The input resistance of the common-source amplifier is given by<br />
R, = — = Rr<br />
(4.40)<br />
h<br />
This impedance forms part of the bias network, but its value is not critical. Practical values<br />
change from 0 to perhaps 10 MQ in discrete component circuits. Thus we have a great deal of<br />
freedom in design of the input resistance of a common-source amplifier. This is not true for BJT<br />
amplifier circuits. One should note, however, that the effective voltage gain<br />
defined as the ratio of the output voltage to the signal source voltage depends on the resistance<br />
jR^. Namely, one can easily demonstrate that<br />
Rr.<br />
K = -g«<br />
R + R, R Rr<br />
L=A V<br />
(4.42)<br />
R + Rr<br />
It follows from Equation (4.42) that with the decreasing gate resistance, the effective voltage gain<br />
decreases, approaching zero when r^—>0. Therefore, high-intemal-resistance sources require<br />
larger values of RQ to maintain large values of the effective voltage gain.<br />
Figure 4.26 Circuit used to find output resistance Ro<br />
To find the output resistance of an amplifier, we disconnect the load, replace the signal source by<br />
its internal resistance, and then find the resistance looking into the output terminals. The<br />
equivalent circuit with these changes is shown in Fig. 4.26.<br />
Because there is no source connected to the input side of the circuit, we conclude that fgs=0.<br />
Therefore, the controlled current source produces 2ero current and appears as an open circuit.<br />
Consequendy, the output resistance is the parallel combination of R D and ra.<br />
R ° = VR D + l/r d ( 4 - 43 )<br />
Exercise 4.8 Find the voltage gain, input resistance and output resistance for the circuit of Fig.<br />
4.24. Also find «(/) and v Q (t). Assume %(/) = 0.1sin(20007t/) V, R = 100 kQ, J^ = 1 MQ, R D = 2.7<br />
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Analog Electronics / FET Circuits<br />
kQ, RL= 10 \sQ, r d = oo, I DSS = 8 mA, V P = -2 V and I D = 2 mA. Ans. A„= -8.5, ft = 1 MQ, Ro =<br />
2.7 kQ.<br />
Exercise 4.9 Find the voltage gain of the amplifier of Exercise 4.8 if an open circuit replaces R^.<br />
Ans. A,,= -10.8.<br />
Exercise 4.10 Find the value of Rs of Exercise 4.8. Ans. R s = 500 Q.<br />
Exercise 4.11 Consider the circuit of Fig. 4.24 with the bypass capacitor replaced by an open<br />
circuit. Draw the small-signal equivalent circuit. Then assuming that ra is an open circuit for<br />
simplicity, derive an expression for the voltage gain in terms of gm and the resistors. Ans.<br />
Exercise 4.12 Evaluate the gain expression found in Exercise 4.11 using the values given in<br />
Exercise 4.8 and the value of Rs found in Exercise 4.10. Compare the results with the voltage<br />
gain found in Exercise 4.8. Ans. A v = -2.84.<br />
Another amplifier circuit known as source follower is shown in Fig. 4.27. The ac signal to be<br />
amplified is supplied by the %(/) signal source and R is the internal resistance of the signal source.<br />
The coupling capacitors C 1 cause the ac input to appear at the gate of the FET. The capacitor C 2<br />
connects the load to the source terminal of the FET. (In the midband analysis of the amplifier, in<br />
which we assume that the coupling capacitors behave as short circuits.) Later when we consider<br />
the frequency response of amplifiers, we include the capacitors. The resistor R s provides a path<br />
for the dc current flowing out of the source terminal of the FET.<br />
Figure 4.27 Source follower<br />
The resistor R^ provides a path for the gate leakage current. One reason for using a source follower is to<br />
obtain high input impedance, and we would pick a large value for R^. The largest resistors available<br />
are on the order of 10 Mfi. Even with such large values, the dc voltage drop caused by leakage<br />
current is usually negligible, so we can consider the bias value of the gate-to-source voltage to be<br />
zero. As a result, the bias value of the drain current is I D = I DSS . Since I DSS demonstrates<br />
considerable device-to-device variation, the bias current of this circuit is not well controlled.<br />
(This situation could be corrected by returning R^ to ground, forming the self-bias circuit<br />
discussed in Section 4.4, but this causes a significant reduction of the input resistance.) Even<br />
though the circuit of Fig. 4.27 has poor bias stability, it achieves extremely high input resistance,<br />
so it is sometimes useful.<br />
The small-signal equivalent circuit is shown in Fig. 4.28. The coupling capacitors have been<br />
replaced by short circuits, and the FET has been replaced by its small-signal equivalent. Notice<br />
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* * = •<br />
(4.44)<br />
Analog Electronics / FET Circuits<br />
that die drain terminal is connected to direcdy to ground because the dc supply becomes a short<br />
in the small-signal equivalent. Therefore, the source follower is also called the common-drain<br />
amplifier. The FET equivalent circuit is drawn in different configuration than shown in Fig. 4.25,<br />
but it is the same electrically.<br />
Drawing the small-signal equivalent for an amplifier circuit is an important skill for electronics<br />
engineers. Test yourself to see if you can obtain the small-signal circuit starting from Fig. 4.27.<br />
Figure 4.28 Small-signal equivalent for the source follower<br />
Now we derive an expression for the voltage gain of the source follower. Notice mat r d , R s and<br />
R L are in parallel. We denote the parallel combination by<br />
1<br />
l/r d +l/R D +UR L<br />
The input current must flow through Rg. Therefore, the current flowing through R L is<br />
''y+SmV-Tkus<br />
v„ = K{L + g^v) (4-45)<br />
We can write the following voltage expression:<br />
V- = V v gS<br />
+<br />
'<br />
V<br />
y l<br />
v 0<br />
Finally,» otice that the voltage across Rg is v^, so we have<br />
v„, = RQif<br />
(4.46)<br />
(4.47)<br />
Equations (4.45), (4.46) and (4.47) form the set needed to solve for the voltage gain. First we use<br />
Equation (4.47) to substitute into Equation (4.45), resulting in<br />
Now if we substitute Equation (4.47) and (4.48) into (4.46), we obtain<br />
v i =R G ii + RL{ii+g m RG i t)<br />
Finally, if we divide Equation (4.48) by (4.49), we find the voltage gain<br />
A = V Q-<br />
R L(l + gm*G)<br />
(4.48)<br />
(4.49)<br />
(4.50)<br />
A few simple checks can be performed on this expression. First, voltage gain is dimensionless.<br />
Checking we see that the expression given on the right-hand side is indeed dimensionless. (Recall<br />
diat the units of g^ are Siemens, i.e. mA/V.) Another simple check is to notice that if ^=0, the<br />
controlled source in Fig. 4.28 becomes an open circuit. Then the equivalent circuit becomes a<br />
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Analog Electronics / FET Circuits<br />
resistive voltage divider. Substituting g^ = 0 into the voltage-gain expression results in the<br />
voltage-division ratio of the resistive circuit. Checks such as this are useful for detecting errors in<br />
writing equations or in the algebra.<br />
Notice that the voltage gain given in Equation (4.50) is positive and is less than unity. However,<br />
in most circuits, it is only slightly less than unity. It follows then, that the output voltage follows<br />
the input voltage that justifies the name source follower for the circuit in Fig. 4.27. To summarize, the<br />
source follower is a noninverting amplifier with a voltage gain slightly lower than unity.<br />
The input resistance can be found from Equation (4.49) by dividing both sides by r,<br />
R i = Vj - = R G^R L {\ + g m R G )<br />
(4.51)<br />
We see that the input resistance can be very large compared to R^.<br />
To find the output resistance, we remove the load resistance, replace the signal source with its<br />
internal resistance, and look into the output terminals. It is helpful to attach a test source v x to the<br />
output terminals as shown in Fig. 4.28. Then the output resistance is found as<br />
R - ^<br />
R "~i<br />
(4.52)<br />
where I x is the current supplied by the test source as shown in the figure. It can be shown that<br />
the output resistance is given by<br />
R„ = ; \ —ir~ (4-53)<br />
— — 1 . + .&A<br />
R + +<br />
s r d R G +R R + R G<br />
This can be quite low, and another reason for using a source follower is to obtain low output impedance.<br />
Figure 4.29 Equivalent circuit used to find die output resistance of<br />
the source follower.<br />
Exercise 4.13 Find the voltage gain, input resistance, output resistance, current gain and power<br />
gain of the source follower shown in Fig. 4.27 if R = 100 kQ, B^ = 10 MQ, R s = 1 kQ, R L = 2.2<br />
kQ. The FET has ra = oo, I DSS =16 mA, V P = -2 V; assume it operates in saturation. Ans. A v =<br />
0.917, ft = 120 MQ, R„= 59.4 Q,A,= 5-10 4 , G = 4.49-101<br />
From the results of Exercise 4.13 we see that even though the voltage gain of the source follower<br />
is less than unity, the output power is much greater than the input power because of the very<br />
high input resistance.<br />
Exercise 4.14 Derive expressions for the voltage gain, input resistance and output resistance of<br />
the source follower shown in Fig. 4.30. Calculate their respective numerical values if R = 100 kQ,<br />
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Analog Electronics / FET Circuits<br />
R G = 10MQ,Rj= 1 kQ.R^ 2.2 kO. The FET has r d =co,I D ss =<br />
operates in saturation.<br />
8 mA, V p = -2 V; assume it<br />
Exetcise 4.15 Derive expressions for the voltage gain, input resistance and output resistance of<br />
the common-gate amplifier shown in Fig. 4.31. Calculate their respective numerical values if R =<br />
100 kQ, Rc= 10 MQ, K s = 1 kfi, Ro= 2.7 kQ, R L = 10 kO. The FET has r d = oo, I DSS = 8 mA, V P<br />
= -2 V; assume it operates in saturation.<br />
TABLE 4.1 PROPERTIES OF BASIC FET AMPLIFIERS<br />
Circuit<br />
configuration<br />
Amplifier<br />
type<br />
Voltage gain<br />
at midband<br />
Input<br />
resistance<br />
Output<br />
resistance Bandwidth<br />
Common<br />
source Inverting -x-R',. Large Medium Medium<br />
Common<br />
drain Noninverting si<br />
Large/,<br />
very large Small Very wide<br />
Common<br />
gate Noninverting<br />
A*«.<br />
Small Medium Wide<br />
Looking at the results obtained from Exercises 4.8, 4.14 and 4.15, one can compare the<br />
properties of the basic FET amplifier configurations. They are summarized in Table 4.1. Please<br />
note that although the common-source and common-gate amplifiers have the same magnitude of<br />
voltage gain, the common-source circuit is an inverting amplifier, unlike the common-gate<br />
configuration. The common-gate one offers larger bandwidth, as will be discussed next in dais<br />
section.<br />
Example 4.1 Find the higher cutoff frequency of the common-source amplifier of Fig. 4.24.<br />
Assume R = 1 kQ, Rc = 10 MQ, R s = 1 kft, R D = 5.6 kfi, R^= 10 kft, r d = oo, I DSS = 16 mA, and<br />
V P = -2 V, Qs = 10 pF, Cgd = 3 pF, Gh = 2 pF.<br />
Solution. To find the circuit small-signal transconductance, one has to determine the j2-point of<br />
the FET by using the techniques of Section 4.4. In the case of the circuit shown in Fig. 4.24, the<br />
gate-to source voltage equals to HGS = -1.407 V. This corresponds to ^ = 2.372 mS. The<br />
equivalent circuit of the amplifier, valid for high frequencies is shown in Fig. 4.32. To build this<br />
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Analog Electronics / FET Circuits<br />
circuit, its model of Fig. 4.23 replaced the FET in Fig. 4.24, and the coupling and bypass<br />
capacitances were replaced by respective short circuits.<br />
Figure 4.32 Small signal high-frequency equivalent circuit for the common-source amplifier<br />
The capacitance Cgd in Fig. 4.32 is connected between the input and the output of the amplifying<br />
device and thus makes the derivations difficult. To simplify the analysis we will use the Miller<br />
theorem of Section 2.6. First, the midband voltage gain should be evaluated between the<br />
terminals to which the feedback capacitance is connected. We will use the circuit of Fig. 4.33 to<br />
find this gain, as<br />
V<br />
A = -- = -g m RL<br />
gs<br />
Since R' L = R D \ \ R L = 3.59 kQ, we find A = -8.52. According to Miller theorem, the capacitance<br />
Cgd may be split into two parts<br />
C m] =C gd (\-A)= 28.55 pF,<br />
\-A<br />
'ml = c gd -A<br />
= 3.35 pF.<br />
These capacitances are connected, respectively, from the gate to source, and drain to source<br />
terminals, as shown in Fig. 4.34. The resistance RQ has been neglected as being much larger than<br />
the signal-source resistance R and the reactance of capacitances (Cgs + C m i) at high frequencies.<br />
Figure 4.34 Simplified equivalent circuit for die common-source amplifier<br />
To find the higher cut-off frequency, one has to evaluate the effective gain of the amplifier<br />
-no-
Analog Electronics / FET Circuits<br />
The output voltage can be described as<br />
^o ~<br />
Sm'gs<br />
l + 7«*/.(C A +C m2 )<br />
(4.54)<br />
R'L<br />
= ~ Sm" gs<br />
1 + JQ)/0)2<br />
where Q) 2 =1/R^C^ +C m2 ) = 1/(3.59 kQ x 5.35 pF) s 1/18.94 ns = 52.8 Mrd/s. The gatesource<br />
voltage is equal to<br />
1<br />
V =V<br />
Y<br />
* gs l + jcoR(C gs +C ml )<br />
=v<br />
1<br />
1 + jco/coi<br />
(4.55)<br />
where
Analog Electronics /FET Circuits<br />
The PSpice simulation run for the circuit of Fig. 4.35a produced^ 2 27.7 MHz. The higher cutoff<br />
frequency of the common-drain amplifier is then much larger than the value of 3.0 MHz<br />
obtained for the common-source amplifier. *<br />
(a)<br />
common-gate amplifier<br />
V 1 0 ac lmV<br />
R 1 2 Ik<br />
Rs 2 0 Ik<br />
Cgs 2 0 lOpF<br />
Cds 2 3 2pF<br />
Cdg 3 0 3pF<br />
gm 3 2 0 2 2.372m<br />
Rd 3 0 5.6k<br />
RL 3 0 10k<br />
.ac dec 100 10Hz lOOMEGHz<br />
.end<br />
Figure 4.36 Small-signal high-frequency equivalent for the common-drain amplifier<br />
Example 4.3 Use PSpice to find the higher cut-off frequency of the common-gate amplifier<br />
shown in Fig. 4.31. Assume R = 1 kQ, R s = 1 kQ, R D ~ 5.6 kQ, R L = 10 kQ. The FET has r d =<br />
oo, I DSS =16 mA, Kp = -2 V, Cgs = 10 pF, Cgd = 3 pF, C
Analog Electronics / FET Circuits<br />
Exercise 4.16. Consider the amplifier shown in Figure 4.37. Both FETs have V& = 3 V, K = 0.6<br />
mA/V 2 , n = oo, Cgs = 10 pF, C g d = 3 pF, Qs = 2 pF, and operate in saturation. Assume R = 1<br />
k£2, R D = 5.6 k£2, R L = 10 kfi. Find device Q-points and transconductance. Draw the small-signal<br />
equivalent circuit valid for medium and high frequencies (replace the capacitances by short<br />
circuits). Run .ac PSpice analysis to find the amplitude characteristic of the amplifier. Determine<br />
the effective gain and bandwidth of the whole cascode as well as gain and bandwidth of its<br />
individual stages.<br />
24V<br />
Figure 4.37 2-MOSFET cascode amplifier<br />
In the next few sections, we turn our attention to other applications for the FET, such as voltagecontrolled<br />
resistance and CMOS logic circuits.<br />
4.8 The FET as a Voltage-Controlled Resistance<br />
Besides its use as an amplifier or as a switch (see Section 4.9), the FET is useful as a voltagecontrolled<br />
resistance. In this application, the bias point is chosen at the origin of the output<br />
(drain) characteristics as illustrated in Fig. 4.38.<br />
10<br />
VDSOO<br />
Figure 4.38 When used as a voltage-controlled resistance, the FET is biased at the origin<br />
If the gate-to source voltage is greater than the pinch-off voltage, the device operates in the linear<br />
(triode) region, and the drain current is given by Equation (4.5), which we repeated here for<br />
convenience<br />
i D =K[2(v GS -V P )v DS -v 2 DS]<br />
The transconductance of the device can be found by application of Equation (4.34), which is<br />
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Analog Electronics / FET Circuits<br />
di r<br />
dv GS<br />
Q-pmnt<br />
Applying this equation to (4.5) we have<br />
°« "»\Q-poml<br />
(4.57)<br />
But the jg-point is v DS = V DS =Q, so we have^n=0. Another way to obtain this result is to recall that<br />
gm is a measure of vertical spacing of the drain characteristics. However, as shown in Fig. 4.38, all<br />
the characteristic curves pass through the origin, and the spacing is zero for that point.<br />
Figure 4.39 Small-signal equivalent circuit for a FET operated at VDS = 0<br />
Because gm = 0, the controlled current source of the small-signal equivalent circuit for the FET<br />
biased as shown in Fig. 4.38 becomes an open circuit. Thus as shown in Fig. 4.39, die smallsignal<br />
equivalent circuit simply becomes a resistor ra connected between the drain and source<br />
terminals. This resistance can be found by application of Equation (4.32), which is repeated here,<br />
for convenience<br />
1 di r<br />
8v DS Q—poinl<br />
Applying this equation to (4.5), we obtain<br />
a<br />
Evaluating for v DS =0 and rearranging, we find that<br />
1<br />
2K(V GS -V P )<br />
(4.58)<br />
(4.59)<br />
which is valid provided that V cs is above pinch-off. Of co. rse, if is less than Vp, die FET is in<br />
cutoff and ra=oo.<br />
Figure 4.40 Voltage-controlled FET attenuator<br />
Thus we see tiiat if the FET is biased at the origin of the drain characteristics, it behaves as a resistor connect<br />
from drain to source, the value of which is controlled by the gate-to-source voltage. This conclusion can also b<br />
made by inspection of Fig. 4.38, where die curves are approximately straight lines intersecting die<br />
origin, and their slopes depend on v GS .<br />
One application of the FET as a variable resistance is in die voltage-controlled attenuator circuit<br />
drawn in Fig. 4.40. The resistor R and die resistance r
Analog Electronics / FET Circuits.<br />
v o= v s<br />
d<br />
R + r d<br />
(4.60)<br />
The control voltage is applied to the gate of the FET. If the control voltage is less than the<br />
pinch-off voltage, ra = oo and no attenuation occurs. However, as the control voltage is raised<br />
above pinch-off, rd becomes smaller and the attenuation becomes greater.<br />
The circuit of Fig. 4.40 is an alternative solution to the semiconductor diode voltage-controlled<br />
attenuator circuit discussed in Section 3.4. The FET-based attenuator is often used to stabilize<br />
die amplitude of RC sine-wave oscillators.<br />
Exercise 4.15 Suppose that R = 10 kQ in the voltage-controlled attenuator in Fig. 4.40 and a<br />
FET having I DSS = 16 mA, V P = -4 V is used. Compute values of ra and A v = *b/i% for a number<br />
of values of v GS = -V c — 0, -1, -2, -3 and -4V. Compare the results with those obtained in Exercise<br />
3.6. ADS. r d = 125 fi, 167 Q, 250 Q, 500 Q and oo ; A v =0.0123, 0.0164, 0.0243, 0.0476 and 1.0,<br />
respectively.<br />
4.9 The CMOS Analog Switch<br />
The CMOS analog switch also known as a transmission gate is shown in Fig. 4.41. We will<br />
see that it acts as a switch that either connects points A and B through a low resistance or<br />
disconnects mem, depending on the digital control signal V c .<br />
We assume that the logic levels for V e are +V DD (high) or -V DD (low). Note mat the control<br />
signal is connected directly to the gate of the NMOS and to the input of the logic inverter. The<br />
inverter output is connected to the gate of the PMOS. The input signal v s to be connected to the<br />
load R L can be either analog or digital and is assumed to range between -V DD and +V DD . The<br />
NMOS substrate is connected to the negative supply. We assume the FETs are identical except<br />
for polarity. The threshold voltage for the NMOS is V^ = V^ and for the PMOS is V^ = -<br />
V A . Furthermore, we assume that K A is less than V D p.<br />
Figure 4.41 CMOS analog switch<br />
If V c = -V DD , both FETs are cut off (provided that v s is within -K DD and + V DI j). Thus for V c<br />
low, an open circuit appears between A and B.<br />
Now consider V c = +K DD . To start, we assume that the input voltage v s is positive, so current<br />
flows from left to right through the FETs. With P S = 0 both the NMOS and PMOS are<br />
conducting. Then as v % increases, current flows through the FETs, raising the output voltage.<br />
-115-
Analog Electronics /FET Circuits<br />
Usually, the resistance of the FETs is low enough so that v Q is approximately equal to v r (The<br />
FETs operate in the triode region.) Notice that the gate-to-source voltage of the NMOS is<br />
V G SN=V C -V 0 (4.61)<br />
However, since we are assuming that V c = V DD , we have<br />
V GSN= V DD-V 0 (4.62)<br />
When the output voltage exceeds V DD -V A , the NMOS becomes cut off, but the PMOS is<br />
heavily conducting. Thus point A is connected to point B by a low-resistance path for all values<br />
of v % between zero and Vjrj D .<br />
Similar reasoning, with source and drain terminals interchanged, applies for negative values of the<br />
input voltage. Thus for V c high, point A is connected to point B regardless of the polarity of v s .<br />
For v 0 between -V DD +V A and V DD -V A , both FETs are on. Outside this range, only one of the<br />
FETs is on.<br />
The resistance of a FET is nonlinear. However, for an analog signal, it is undesirable for die<br />
resistance between points A and B to be nonlinear because this leads to distortion of the output<br />
voltage. Fortunately, it can be shown that the nonlinearities of the PMOS and NMOS cancel in<br />
the range of voltages for which both transistors are on. This is an advantage of the CMOS switch<br />
as compared to circuits having only a single transistor. For an analog input signal taking both<br />
positive and negative values, we should choose positive and negative logic level so that both<br />
transistors are on for the range of input voltages expected.<br />
Exercise 4.16 Suppose that the analog switch of Fig. 4.41 uses enhancement MOSFETs having<br />
\V A \ =1V and IK^lmA/V 2 . Also, V DD =SV and R L is large enough so that v Q is<br />
approximately equal to v s . The control signal is V c = V DDt so die gate is in the on state. Find the<br />
small-signal resistance r d of the NMOS for v s =0, 1, 2, 3, 4, and 5V. Repeat for the PMOS. Find<br />
the effective incremental resistance of each device between points A and B for each input<br />
voltage. (Hint. v DS =0, so Equation (4.56) can be used with appropriate changes in notation.)<br />
4.10 CMOS Logic Circuits<br />
In this section we briefly discuss an important logic family that uses complementary metaloxide-semiconductor<br />
(CMOS) FETs. The term complementary implies that both /(-channel and p-<br />
channel devices are employed.<br />
NMOS inverter with resistive pull-up. Before considering CMOS circuits, we discuss die<br />
simpler inverter circuit shown in Fig. 4.42. The transistor is an »-channel enhancement device<br />
(NMOS) having a threshold voltage V^. The load capacitance represents the input capacitance<br />
of driven circuits (such as gates, inverters).<br />
-116-
Analog Electronics / FET Circuits<br />
The drain characteristics of the NMOS transistor are shown in Fig. 4.43. The input voltage V m is<br />
applied to the gate, so we have v GS = V^. For the moment, we assume that the load capacitance is<br />
an open circuit. Using the values R D =10kQ and V DD =10V we construct the load line shown in<br />
Fig. 4.43.<br />
Notice that if the input voltage is less than the threshold voltage of the transistor (assumed to be<br />
K th =3V in this example), the transistor is cut off. Then the circuit operates at point A, and the<br />
output voltage is K 0 = V DD .<br />
As the input voltage is raised above threshold, the point of operation moves up the load line.<br />
When f^n= V DD , the circuit operates at point B, and the output voltage is low. Thus the circuit<br />
operates as a logic inverter (low input corresponds to high output and vice vend).<br />
Fig. 4.44a shows the transfer characteristic of the MOS inverter with resistive load. Points A and<br />
B are marked, as discussed above. With logic one at the input (v GS = 10 V), the output voltage is<br />
equal to 0.61 V and is considered output logic zero for this inverter circuit At the same time, the<br />
drain current is equal to 0.94 mA. Thus the inverter circuit considered draws a power from a<br />
power supply when its input is logic one. Part of this power is dissipated in die drain resistor [P R<br />
= (10V-0.61V)x0.94mA = 8.8mW] and the rest is dissipated inside the MOS transistor structure<br />
(P T = 0.61Vx0.94mA = 0.6mW). This causes the power loss that shortens the battery life in<br />
portable equipment and leads to heating of the circuit.<br />
-117-
Analog Electronics / FET Circuits<br />
In selecting the value of the pull-up resistor Rp, we encounter conflicting objectives. On die one<br />
hand, we want to make die resistor large because this leads to a small current the transistor is on.<br />
This, in turn, means a smaller demand on the power supply and less heating of die circuit On die<br />
other hand, we want to make R D small, so that when the FET switches off, the load capacitance<br />
is quickly charged. (Usually it is important for logic transitions to take place quickly.)<br />
The CMOS inverter. A solution to diis conflict is to use an enhancement ^-channel MOS<br />
(PMOS) transistor in place of die pull-up resistor as shown in Fig. 4.45. (An additional benefit is<br />
diat die PMOS takes much less chip area dian a resistor and dierefore is advantageous for IC<br />
implementation.)<br />
v DD =\0\<br />
11<br />
In the following discussion we assume diat except for the differences in voltage polarity and<br />
current direction, die NMOS and PMOS have identical characteristics. The direshold of die<br />
NMOS is Vfa n = Vfa which is a positive value, and the threshold voltage for the PMOS is V^ =<br />
-Vfa. Also we assume, as is often the case, that the supply voltage V DD is greater that twice die<br />
direshold voltage magnitude. (In the illustrations, we assume that K th =2V and V DD =\OV.)<br />
Notice in Fig. 4.45 that the source terminal of the PMOS is connected to V DD and that the drain<br />
is connected to the inverter output The gate-to-source voltage of the PMOS is given by<br />
v GS P=^-r DD (4-63)<br />
When V m = V DLh die gate-to-source voltage of the PMOS is zero, so it is cut off. Then it acts as<br />
a very high value of R^, and virtually no current flows from the supply. On the other hand, when<br />
V m = 0, we have P GSP = -V DD , and the PMOS can deliver a large drain current to charge the load<br />
capacitance. Since the NMOS is cut off for UQ^ = V^ = 0, no current flows after die<br />
capacitance is charged.<br />
An important advantage of CMOS logic is that, except during logic transitions, either the NMOS<br />
or the PMOS is cut off, and no current flows. Thus the static power consumption (i.e. the<br />
power consumption of a logic circuit when the logic states are not changing) is virtually zero.<br />
For this reason, CMOS is an attractive choice for battery-operated circuits such as portable<br />
computers.<br />
Now we consider load-line constructions for the CMOS inverter. Recall that in the case of a<br />
resistive load, the load line is straight - the volt-ampere characteristic of a resistor. However, for a<br />
PMOS pull-up transistor, the load line is not straight; instead, it is a characteristic curve of the<br />
PMOS. Furthermore, the resistor results in a fixed load line, but the line (actually, it is a curve)<br />
for the PMOS pull-up changes as V m changes. The load lines are shown for several values of V in<br />
on the characteristics of the NMOS in Fig. 4.46.<br />
-118-
Analog Electronics/FET Circuits<br />
Figure 4.46 Load-line analysis of CMOS inverter.<br />
For the NMOS V^ - 2V and for the PMOS K,hp=-2V.<br />
For V m - 0, die PMOS is highly conductive, but the NMOS if cut off, and the point of<br />
operation is at A. Point B illustrates the operating point for a value of V m greater than the<br />
threshold voltage of the NMOS but less than V DD /2. At point B the NMOS is in saturation and<br />
the PMOS in the triode region.<br />
When V m = V DD /2 = 5V, the load line and the NMOS characteristic intersect not at a single<br />
point but along a line from C to D in Fig. 4.46. Thus as V m increases through V DD /2, the<br />
operating point switches abrupdy from C to D.<br />
Point E illustrates an operating point for a value of V m between V DD /2 and V DD -V A . At point E<br />
die PMOS is in saturation, whereas the NMOS is in the linear region. For V m = K OD , the PMOS<br />
is cut off, and operating point is F.<br />
-119-
Analog Electronics / FET Circuits<br />
K A . The transfer characteristic falls abruptly for V m = V DD /2. The CMOS inverter closely<br />
approximates the ideal transfer characteristic for a logic inverter.<br />
The current flowing from the supply through the transistors of the CMOS inverter, assuming an<br />
ideal open-circuit load is shown in Fig. 4.47b. Notice that if V m = 0 or V m = V DD> then the<br />
current is zero. Maximum current flow occurs for V m = V DD /2. The maximum current value<br />
depends on the supply voltage and on the value of transistors' K.<br />
The CMOS NOR and NAND gates. The circuit diagram of a two-input CMOS NOR gate is<br />
shown in Fig. 4.48a. The source and drain terminals of the FETs are not labeled in the figure.<br />
The devices are physically symmetrical, so either end can be considered to be the source, with the<br />
other becoming the drain. Usually, we consider the source of the PMOS devices to be the<br />
terminal that current enters (i.e., the top en of this circuit). Similarly, we consider the sovirces of<br />
the NMOS devices to be the end that current leaves (Le., the bottom terminals of this circuit).<br />
Designation of source and drain is convenient in analysis of the circuit; however, the physical<br />
construction of a device is the same regardless of which end is the source or drain.<br />
Now we consider the operation of the circuit shown in Fig. 4.48a. If both inputs A and B are<br />
low, the PMOS transistors' M 1 and M 2 are conductive, and both the NMOS transistors M 3 and<br />
M 4 are off. Consequently, the output is high. If either A or B or both are high, one or both of the<br />
PMOS devices are cut off. Furthermore, at least one of the NMOS devices is conductive.<br />
Consequendy, the output is low. Consequendy, this circuit performs the NOR logic function. A<br />
two-input CMOS NAND gate is shown in Fig. 4.48b.<br />
A/ "H MM<br />
Mj<br />
(») (b)<br />
Figure 4.48 CMOS two-input logic gates: (a) NOR gate, (b) NAND gate<br />
Exercise 4.16 For the circuit of 4.48b, prepare a table showing all possible combinations of<br />
inputs (each input can be" high or low), the corresponding state of each transistor, and the<br />
corresponding output. Indicate the state of each transistor either as on for operation in the triode<br />
or saturation region or as o^for operation in cutoff.<br />
Exercise 4.17 Draw the circuit diagram of a three-input CMOS NOR gate.<br />
Exercise 4.18 Prepare a table showing the regions of operation (saturation, triode or cutoff) of<br />
the PMOS and the NMOS for each labeled point on the inverter transfer characteristic shown in<br />
Fig. 4.47.<br />
Exercise 4.19 A CMOS inverter is constructed with symmetrical devices having V^ = 3V and<br />
Vfo. = -3V. Sketch the transfer characteristic to scale if V DD = 15V.<br />
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Analog Electronics/FET Circuits<br />
Exercise 4.20 If the devices have \K\ =lmA/V 2 , find the supply current through the inverter of<br />
Exercise 4.20 if V m = V DD /2. Assume an open-circuit load. Ans. 20.25mA.<br />
4.11 FET Dynamic Circuit Models<br />
Figure 4.49 shows a circuit model for an ^-channel JFET and the corresponding SPICE<br />
parameters. Current source i D describes the static characteristic of the device. In pinch-off, the<br />
drain current of an ^-channel JFET is given by<br />
i D = K(v GS - Vpfil + Xvos) (4.64)<br />
in which K is a proportionality factor that depends on a particular device, V p is the pinch-off<br />
voltage, and the parameter X accounts for the slope of the output characteristic curves in<br />
saturation. In die preceding sections of this chapter we have assumed X = 0 to simplify<br />
discussion. The nonzero value of X leads to a nonzero value of the small-signal output<br />
conductance r
Analog Electronics /FET Circuits<br />
(Additional depletion capacitances C„ and C BD connect source and drain to the substrate in IC<br />
structures.) Ohmic resistances RQ and Ry complete the model. Below there are two examples of<br />
PSpice device statement for JFETs:<br />
Jl Dnode Gnoda Snoda JModName<br />
.MODEL JModNana NJF(VTO>-4 BETA=lE-3)<br />
Jl Dnode Gnoda Snode J2N3819<br />
.LIB EVAL.LIB<br />
Text<br />
notation<br />
TABLE 4.2 SPICE PARAMETERS FOR N-CHANNEL JFKD<br />
SPICE Parameter name Typical Default<br />
notation<br />
value value<br />
v P<br />
VTO Pinch-off voltage -3V -2V<br />
K BETA Transconductance<br />
coefficient<br />
600E-6A/V 2<br />
100E-6 A/V2<br />
X LAMBDA Channel-length<br />
2E-3 V 1 0<br />
modulation coefficient<br />
I IS Saturation current 2E-12 A 1.0E-14A<br />
n N Emission coefficient 1 1<br />
R D<br />
RD Ohmic drain resistance \Cl 0<br />
R s RS Ohmic source resistance 0.1 Q 0<br />
^GDO<br />
CGD Gate-drain depletion<br />
3pF 0<br />
capacitance (zero bias)<br />
^GSO<br />
CGS Gate-source depletion 3.3 pF 0<br />
capacitance (zero bias)<br />
m M Junction grading factor 0.333 0.5<br />
fo PB Built-in barrier potential IV 0.5 V<br />
"Typical values of the parameters are shown for a discrete general-purpose device<br />
An enhancement MOSFET structure is presented in Fig. 4.50. Notice that the length JL and<br />
width W of the channel are labeled on die figure. In the saturation region, the drain current is<br />
given by<br />
i D = j K(v GS - V th ) 2 {\ + Xv DS ) (4.69)<br />
(Previously, we assumed for simplicity that W/L. = 1 and X = 0.) Notice that the current depends<br />
on the width-to-length ratio of the channel. The device designer can vary this ratio to obtain<br />
devices best suited for various functions in a circuit It turns out that the small-signal<br />
transconductance depends on the W/L, ratio as follows<br />
8m = 2^KI D^(\ + XV DS ) (4.70)<br />
whereas the formula (4.65) is valid for MOS as weU. Keep in mind that the equation for ^n and gd<br />
are valid only for operation in the saturation region.<br />
Of course, it is desirable to construct devices with small dimensions so that a large number of<br />
mem fit in a .given chip area. Another advantage of smaller devices is that the device capacitances<br />
are smaller. Provided that the width-to-length ratio is maintained, the current available to charge<br />
and discharge these capacitances is independent of device size. Thus digital circuits constructed<br />
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Analog Electronics / FET Circuits<br />
with smaller MOS transistors can switch faster. Both the speed and complexity of digital MOS<br />
circuits can increase as the device dimensions become smaller.<br />
Figure 4.50 ^-Channel enhancement MOSFET structure with channel length L and channel width W<br />
SPICE uses Equation (4.69) to relate the current to the voltages, except that ohmic resistances<br />
are added in series with the source and the drain. This is shown in Fig. 4. In the MOSFET of Fig.<br />
4.51 there are depletion capacitances C BS and C BD between the substrate and reverse-biased n-<br />
type wells. To describe these capacitances, SPICE uses zero bias capacitances CBS and CBD,<br />
grading coefficient MJ and bulk junction potential PB. The SPICE model also includes the<br />
exponential volt-ampere behavior of the body-drain and body-source junctions. These junctions,<br />
characterized by the reverse saturation current IS, must be kept reverse biased in the simulation (as in the<br />
physical device) by connecting the substrate to the most negative point in the circuit.<br />
Figure 4.51 »-channel MOSFET dynamic circuit model<br />
Fig. 4.51 also suggests capacitance, C GB , between gate and substrate, with the oxide for its<br />
dielectric. It turns out that in places where the gate slighdy overlaps the drain and source<br />
materials there are additional capacitances C G5 and C GD . SPICE computes values for C GS , C GD , and<br />
C GB when we specify the value of oxide thickness, TOX, on the .MODEL line and when W and<br />
L are specified on the element lines of the transistors. TOX = 0.1U, W = 1U, and L = 1U suffice<br />
as rough estimates when actual values are unknown. Resistors R s and R D represent the voltage<br />
drops by current flowing to the external contacts D' and S'. SPICE includes temperature variation in<br />
threshold voltage and pn junction parameters; however, variations in mobility with temperature<br />
are absent in basic versions of SPICE.<br />
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Analog Electronics / FET Circuits<br />
Text<br />
notation<br />
SPICE<br />
notation<br />
TABLE 4.3 SPICE PARAMETERS FOR MOSFETs*)<br />
Parameter name<br />
Typical<br />
Value,<br />
NMOS<br />
Typical<br />
Value, PMOS<br />
Kh VTO Threshold voltage IV -IV<br />
2|K| KP Transconductance<br />
30E-6 A /V 2 12E-6 A/V 2<br />
coefficient<br />
X LAMBDA Channel-length<br />
modulation coefficient<br />
1E-2 V- 1 1E-2 V 1<br />
Ro RD Ohmic drain resistance 10 Q ion<br />
R s<br />
RS Ohmic source resistance 10 Q ion<br />
"Typical values are given for devices having W/L, = 1.<br />
Table 4.3 lists SPICE model parameters for static operation. The capacitances C cs , C CD , and C CB<br />
have been described in the text above. Relationships of the type (4.67) and (4.68) describe the<br />
capacitances Cf B and C DB . Notice that the SPICE transconductance coefficient is<br />
KP = 2|K|<br />
Much work has been expended to obtain SPICE models based on device dimensions and process<br />
parameters. Three of the resulting models are incorporated into PSpice. A particular model can<br />
be selected in the .MODEL statement by the LEVEL=1, 2, or 3 parameter. The default is<br />
LEVEL =1. Detailed discussion of these models is beyond the scope of these lecture notes. The<br />
device statement for MOSFETs takes the form<br />
Mdevice Dnode Gnode Snoda Bnoda MNama L»VALUE W-VALUE<br />
.MODEL MNama NMOS(VTO=l KP=30U LAMBDft-0.01 RD=10 RS-10)<br />
Notice that the first character of a MOS device must be M.<br />
Example 4.4 Write a PSpice code to plot the output characteristics for an NMOS having the<br />
model parameters given in Table 4.3. The device dimensions are JL = 20 um and W — 50 urn.<br />
Assume that the substrate is connected to the source. Allow the drain-to-source voltage to range<br />
from 0 to 20 V in 0.1-V steps and gate-to-source voltage to range from 0 to 10 V in 1-V steps.<br />
Solution. The program listing is<br />
NMOS characteristics example<br />
Ml 2 1 0 0 NAME L=20u W*50u<br />
.MODEL NAME NMOS (VTO=l KP=30u LAMBDA»0.01 RD=10 RS=10)<br />
VGS 1 0 dc 5V '<br />
VDS 2 0 dc 10V<br />
.DC VDS 0 20 0.1 VGS 0 10 1<br />
.END<br />
The reader is suggested to reconstruct the schematic diagram of the simulated circuit from the<br />
code.<br />
After running the program and starting PROBE, we request a plot of ID(M1). The resulting plot<br />
of the output characteristics is shown in Fig. 4.52.<br />
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Analog Electronics /FET Circuits<br />
n IBtmi<br />
Figure 4.52 Output characteristics for Example 4.4<br />
4.12 Summary<br />
Field-effect transistors are 3-state devices that serve as dependent sources in analog applications<br />
and as controlled switches in digital circuits. In one kind of FET, the control gate is insulated<br />
from the conducting channel; another FET class has a gate that is in physical contact with the<br />
channel by electrically separated by a reverse biased or Schottky junction. All ^-channel FETs<br />
share the same state definitions, equations, and circuit models, except for minor notational<br />
differences. Mathematically, the transfer characteristics of all «-channel FETs are the right-hand<br />
branches of parabolas; they differ only in the algebraic sign of the threshold or pinch-off voltage.<br />
Equations for /(-channel FETs are identical to those of //-channel devices; however, output<br />
characteristics plot in the second quadrant instead of the first. The circuit models differ only in<br />
the reference directions of the drain currents. The transfer characteristics are of all />-channel<br />
devices are left branches of parabolas; individual differences are only in the algebraic sign of the<br />
threshold or pinch-off voltage. In analysis of FET circuits we encounter two general classes of<br />
problems: finding ^-points when transistor states are known and finding j2-points when the<br />
states are unknown. The tools and procedures for solving these problems are load lines,<br />
equivalent circuits and guessing and verifying states. The infinite input resistance of the FET<br />
tends to simplify circuit analysis; however, FET circuits usually require us to solve a quadratic<br />
equation and select the solution that has physical meaning. The FET can operate as a voltagecontrolled<br />
linear resistor. The most significant second-order effects in FET are breakdown<br />
associated with reverse-biased junction that places an upper limit on the useful active region,<br />
channel length modulation that causes a nonzero positive slope of output characteristics in the<br />
saturation state, and the decrease of the threshold voltage and channel resistance with<br />
temperature. Internal parasitic capacitances limit the FETs ability to operate at high frequencies.<br />
Some are depletion capacitances associated with reverse-biased junctions; others are linear<br />
capacitances associated with insulated gates. Because the minority charge carriers do not take<br />
significant part in the current conduction in FETs, these devices lack large diffusion capacitances<br />
associated with stored minority charge carriers. SPICE models can simulate the nonlinearities of<br />
the static transistor models, and also include most second-order effects of FETs. Because of high<br />
input impedance and output characteristic that resemble resistor volt-ampere curves in both first<br />
and second quadrants, FETs make excellent switches. Bidirectional transmission gates<br />
constructed from FETs are widely used in both digital and linear applications. For small signals, a<br />
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Analog Electronics / FET Circuits<br />
FET biased in die saturation region functions as a voltage-controlled current source with a<br />
transconductance ^n = 2K(K cr Vth) and the output resistance r 0 = 1/(AJ D ). The common-source<br />
configuration provides a high voltage gain and a very high input impedance, but a limited highfrequency<br />
response. A much wider bandwidth is achieved in the common-gate configuration but<br />
its input impedance is low. The source follower (common-drain amplifier) provides a voltage gain<br />
less than unity but features a low output resistance. Integrated-circuit MOS amplifiers utilize<br />
MOS transistors as amplifying and as load devices. In CMOS technology, both n- and/(-channel<br />
enhancement MOSFETs are used, thus providing the circuit designer with considerable<br />
flexibility. The most important things to remember about FETs are their output and transfer<br />
characteristics, the state definitions, the procedure to find their jg-point given bias circuit, and the<br />
load line concepts, including load lines for CMOS inverter sketched in Fig. 4.46.<br />
Notes:<br />
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Analog Electronics/BJT Circuits<br />
5 Bipolar Transistor Circuits<br />
Bipolar junction transistors (BJTs) are constructed as layers of semiconductor materials (most<br />
often silicon) doped with suitable impurities, producing either »-type or/Mype layer. A simplified<br />
physical structure of an integrated circuit npn transistor is shown in Fig; 5.1a. The actual transistor<br />
action takes place along die A-A' line shown in Fig. 5a. The idealized structure of the bipolar<br />
transistor, corresponding to its cross-section along the A-A 1 line is presented in Fig. 5b, where a<br />
layer of p-type material is placed between two layers of the »-type material. This structure can be<br />
seen as two pn junctions made close together in a single crystal of semiconductor. The current in<br />
one junction affects the current in the other junction.<br />
The layers of the bipolar transistor are called the emitter, the base, and the collector, as shown<br />
in Fig. 5.1b. The circuit symbol of an npn transistor is shown in Fig.5c, including reference<br />
directions for the terminal currents and voltages.<br />
Recall that a pn junction is forward biased with applying positive polarity to the p-side. On the<br />
other hand, reverse bias occurs if the positive polarity is applied to the /|-side.<br />
In normal operation of a BJT as an amplifier, the base-collector junction is reverse-biased and the<br />
base-emitter junction is forward biased. In the following discussion we assume that the junctions<br />
are biased in this fashion unless stated otherwise.<br />
The Shockley equation gives die emitter current i E in terms of the base-to-emitter voltage v BE :<br />
'£ = J ES exp^-l (5.1)<br />
This is exacdy the same equation as for the current in a junction diode given in Equation (3.1),<br />
except for changes in notation. The emission coefficient n is made equal to unity since this is the<br />
appropriate value for most junction transistors. Typical values for the saturation current 1^ range<br />
from 10 12 A to 10" 16 A, depending on the size of the device. Recall that at a temperature of 300K,<br />
the thermal voltage V T is approximately 26mV.<br />
Of course, Kirchhoff s current law requires that the current flowing out of die BJT is equal to the<br />
sum of the currents flowing into it. Thus, referring to Fig. 5.1c, we have<br />
i£ =i C +i B (5.2)<br />
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Analog Electronics /BJT Circuits<br />
This equation is true regardless of the bias conditions of the transistor junctions.<br />
We define the parameter a for the transistor as the ratio of the collector current to the emitter<br />
current.<br />
'C<br />
a = l<br />
(5.3)<br />
E<br />
Values of a range from 0.9 to 0.999, with 0.99 being very typical. Equation (5.3) indicates that<br />
the emitter current is partly supplied through the base terminal and partly through the collector<br />
terminal. However, since a is nearly unity, the collector supplies most of the emitter current.<br />
Substituting Equation (5.1) into (5.3) and rearranging, we have<br />
r V BE<br />
i c = cdgs exp(——)-l (5.4)<br />
For v BE greater than a few tens of a volt, the exponential term in the bracket is much larger than<br />
unity. Then the 1 inside the bracket can be dropped. Also, we define the scale current as<br />
I s =a*ES " (5-5)<br />
and Equation (5.4) becornes (for the normal bias conditions)<br />
V T<br />
(5.6)<br />
Solving Equation (5.3) for i 0 substituting into Equation (5.2), and solving for the base current,<br />
we obtain<br />
i B =(\-a)i E (5.7)<br />
Since a is slighdy less than unity, then only a very small fraction of the emitter current is supplied<br />
by the base. Using Equation (5.1) to substitute for i E , we obtain<br />
i B =(l-a)/ £S exp(^)-l (5.8)<br />
We define the parameter fi as the ratio of the collector current to the base current. Taking the<br />
ratio of Equations (5.4) and (5.8) results in<br />
a<br />
o 'C<br />
(5.9)<br />
P<br />
i B l-«<br />
Values for/ range from about 10 to 1000, and a very common value is /£=100. We can write<br />
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Analog Electronics /BJT Circuits<br />
i c =Pi B (5.10)<br />
Note that since / is usually large compared to unity, the collector current is an amplified version of the<br />
base current. Current flow in an npn BJT is illustrated in Fig. 5.2.<br />
As in the case of the FET, the bipolar transistor is a three-terminal device. There are then three<br />
basic circuit configurations that employ the BJT as an amplifier, i.e. a circuit that has one input<br />
and one output. In each of these configurations, one of the transistor terminals is common to the<br />
input and to the output. The common-emitter configuration for an npn BJT is shown in Fig. 5.3.<br />
The battery connected between the base and the emitter supplies a positive voltage v BE that<br />
forward biases the base-emitter junction. The V& battery produces a positive voltage at the<br />
collector with respect to the emitter. Notice that the voltage across the base-collector junction is<br />
given by<br />
VBC= V BE~ V CE ( 511 )<br />
Thus if VCE is greater than v BE , the base-collector voltage v BC is negative, which is reverse bias.<br />
< *'c<br />
Figure 5.3 Common-emitter circuit configuration for the npn BJT<br />
The common-emitter characteristics of the transistor are plots of the currents i B and i c versus the<br />
voltage v BE and v^. Representative characteristics for a low-power silicon device are shown in<br />
Fig. 5.4.<br />
The common-emitter input characteristic shown in Fig. 5.4a is a plot of i B versus v BE , which<br />
are related by Equation (5.8). Notice that the input characteristic takes the same form as the<br />
forward characteristic of a junction diode. Thus, for appreciable current to flow, the base-toemitter<br />
voltage must be approximately 0.6V. Just as for a junction diode, the base-to-emitter<br />
voltage, for a given current, decreases with temperature by about 2mV/K.<br />
The common-emitter output characteristic shown in Fig. 5.4b is a plot of i c versus v^ for<br />
constant values of i B . The transistor illustrated has /£=100. As long as the collector-base junction<br />
is reverse-biased (ffc^O, or equivalently v C E >t, BE)> we have<br />
; C =/B B =IOOZ B<br />
As VCE becomes less than v BE , the base-collector junction becomes forward-biased, and eventually<br />
the collector current falls as shown at the left-hand edge of the output characteristics.<br />
Refer to Fig. 5.4a and notice that a very small change in the base-to-emitter voltage v BE can result<br />
in an appreciable change in the base current i B , partially if the base-emitter junction is forward<br />
biased, so some current (say, 40|iA) is flowing before the change in v BE is made. Provided that v^<br />
is more than a few tens of a volt, this change in base current causes a much larger change in the<br />
collector current i 0 because i^fii^ In suitable circuits, the change in collector current is<br />
converted into a much larger voltage change than the initial change in v BE . Thus the BJT can<br />
amplify a signal applied to the base-emitter junction.<br />
-129-
Analog Electronics /BJT Circuits<br />
5.1 Load-Line Analysis of a Common-Emitter Amplifier<br />
A simple amplifier circuit is shown in Fig. 5.5. The power-supply voltages V BB and V cc bias the<br />
device at an operating point for which amplification of die input signal ik(t) is possible. We will<br />
show that the amplified version of the input signal appears between the collector and die ground.<br />
~ Figure 5.5 Common-emitter amplifier<br />
The load-line technique will be used to analyze die circuit Applying the Kirchhoff s voltage law<br />
to die base loop, we obtain<br />
V B B + V,(/) = RbhiO + VBEiO (5-12)<br />
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Analog Electronics/BJT Circuits<br />
Figure 5.6 Load-line analysis of the amplifier of Fig. 5.5:<br />
(a) input (load line shifts downwards for a smaller value of«%), (b) output.<br />
A plot of Equation (5.12) is shown in Fig. 5.6a as the load line on the input characteristic of the<br />
transistr -. To establish the load line, we must locate two points. If we assume that i B =0, then<br />
Equatio (5.12) yields v BE =V BB +t>s- This establishes the point where trie load line intersects the<br />
voltage axis. Similarly, assuming that v BE =Q results in i B = (f flB +«fc)/.Rb, which establishes the<br />
load-line intercept on the current axis. The load line is shown in Fig. 5.6a.<br />
Equation (5.12) represents the constraints placed on the values of i B and v BE by the external<br />
circuit. In addition, i B and v BE must fall on the device characteristic. The values that satisfy both<br />
constraints are the values at the intersection of the load line and the device characteristic.<br />
The slope of the load line is -1/Kb. Thus the load line shifts position but maintains a constant<br />
direction ast% changes in value. For example, the lower load line in Fig. 5.6a is for a smaller value<br />
of t>s than that for the upper load line.<br />
The quiescent operating point or Q-point corresponds to %(/)=0. Thus as the ac input signal t%(/)<br />
changes in value with time, the instantaneous operating point swings above and below the Q-<br />
point value. Values of i B can be found from the intersection of the load line with the input<br />
characteristic for each value of t%.<br />
-131-
Analog Electronics /BJT Circuits<br />
After the input circuit has been analyzed to find values of i B , a load-line analysis of the output<br />
circuit is possible. Referring to Fig. 5.5, we can write a voltage equation for the collector loop,<br />
through V cc , R& and the transistor from collector to emitter. Thus we have<br />
YcC = R cic +v CE (513)<br />
This is plotted on the output characteristic of the transistor in Fig. 5.6b.<br />
Now, with the values of i B that we have already found by analysis of the input circuit, we can<br />
locate the intersection of the corresponding output curve with the load line to find values of i c<br />
and «>££. Thus ast% swings through a range of values, i B changes, and the instantaneous operating<br />
point swings up and down the load line on the output characteristic. Usually, the ac component<br />
of V& is much larger than the input voltage; hence the amplification takes place.<br />
Examination of Fig. 5.6a shows that as v&{t) swings positive, the value of i B increases (i.e. the<br />
intersection of the load line with the input characteristic moves upward). This in turn causes the<br />
instantaneous operating point to move upward on the output load line, and v^ decreases in<br />
value. Thus a swing in the positive direction for ik results in a (much larger) swing in the negative<br />
direction for v^. Therefore, as well as being amplified, the signal is inverted. In other words, the<br />
common-emitter amplifier is an inverting amplifier.<br />
>«T : r :.—.,—-^<br />
Figure 5.7 Output of the amplifier of Exercise 5.1 for s (/)=1.2sin(2000iu)<br />
demonstrating gross distortion<br />
Exercise 5.1 Assume that the circuit of Fig. 5.5 has V cc = 10 V, V BB = 1.6 V, R b = 40l£i<br />
R,. = 2 ls£l. The input signal is a 0.4-V peak 1-kHz sinusoid given by t> s (f) = 0.4sin(200(br/). Use<br />
PSpice to plot the device-characteristics assuming fi p = 100 and J s = le-14 A. Using the load-line<br />
technique find the maximum, minimum and Q-point values for v CE . Use PSpice to plot the<br />
waveforms of vjt) and v^t). Ans. p Canki s 3 V, V^ = 5 V, VCmaai s 7 V.<br />
It is not apparent in the waveforms that you have plotted in Exercise 5.1, but the output signal is<br />
not a precise sine wave like the input The amplifier is slightly nonlinear because of the curvature<br />
of the characteristics of the transistor. Therefore, as well as being amplified and inverted, the<br />
signal is distorted. Of course, distortion is not usually desirable. Fig. 5.7 shows the output of the<br />
amplifier of Fig. 5.5 and Exercise 5.1 if the input signal is increased in amplitude to 1.2 V peak.<br />
The distortion is obvious.<br />
and<br />
Notice that the positive peak of v^ has been clipped at K CC =10V. This occurs when i B and i c<br />
have been reduced to zero by the negative peaks of the input signal, and the instantaneous<br />
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Analog Electronics /BJT Circuits<br />
operating point moves down to the voltage-axis intercept of the output load line. When this<br />
happens, we say that the transistor has been driven into cut-off.<br />
The negative-going peak of the output waveform in Fig. 5.7 is dipped at v^ = 0.2 V. This occurs<br />
because i B becomes large enough so that operation is driven into the region at the upper end of<br />
the output load line, where the characteristic curves are crowded-together. We call this the<br />
saturation region.<br />
Reasonably linear (undistorted) amplification occurs only if the signal swing remains in the active<br />
region between saturation and cutoff on the load line. An output load line is shown in Fig. 5.8,<br />
including labels for the cutoff, saturation and active regions.<br />
J IC(Q1)<br />
W2<br />
Figure 5.8 Amplification occurs in the active region. Clipping occurs when the instantaneous operating<br />
point enters saturation or cutoff. In saturation, VCE = 0.2V.<br />
Exercise 5.2 Repeat Exercise 5.1 if Vs{t) = 0.8sin(2(XXbt^. Ans. Pamm = 1 V, V^ = 5 V,<br />
Vcsrv^S.SV.<br />
Exercise 5.3 Repeat Exercise 5.1 if tk(t) = 0.8sin(2000it/) and V BB = 1.2 V. Ans. ^c^un S3V, V^<br />
s 7 V, Pep* s 9.8 V.<br />
5.2 The pnp Bipolar Junction Transistor<br />
So far we have considered the npn BJT, but an equally useful device is the pnp bipolar junction<br />
transistor, in which the base is a layer of »-type material between />-type emitter and collector<br />
layers. For proper operation of an amplifier, the polarities of the dc voltages applied to the pnp<br />
device must be opposite to those of the npn device. Furthermore, current flows in the opposite<br />
direction. Aside from the differences in voltage polarity and current direction, the two types of<br />
devices are nearly identical<br />
A diagram of the structure of zpnp BJT and its circuit symbol are shown in Fig. 5.9. Notice that<br />
the arrow on the emitter of the pnp transistor points into the device, which is the normal<br />
direction of the emitter current For the pnp transistor we can write the following equations,<br />
which are exactly the same as for the npn transistor.<br />
'C = ctiE (5.14)<br />
i B =(\-a)i E (5.15)<br />
ic=fiB (5.16)<br />
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Analog Electronics /BJT Circuits<br />
and<br />
i£ =i C +i B ( 517 )<br />
Equations (5.14) through (5.16) are valid only if the base-emitter junction is forward biased (v BE<br />
negative for i-pnp) and the base-collector junction is reverse biased (y^ positive for a. pup). As for<br />
the npn transistor, typical values are a £ 0.99 and fi= 100.<br />
and<br />
These equations are identical to Equations (5.1) and (5.8) for the npn transistor except that - v#£<br />
has been substituted for v BE (because v BE takes negative values for ihepnp device). As for the npn<br />
device, typical values for 1^ range from 10" 12 to 10" ,6 A, and at 300K we have V-f226tiN.<br />
The common-emitter characteristics ofapnp transistor are exacuy the same as for the npn except<br />
that the values on the voltage axes are negative. A typical set of characteristics is shown in Fig.<br />
5.10.<br />
134
Analog Electronics /BJT Circuits<br />
z.« i<br />
! ItVB)<br />
(b)<br />
Figure 5.10 Common-emitter characteristics for zpttp BJT: (a) input, (b) output<br />
Exercise 5.4 Find the values of alpha and beta for the transistor having the characteristics shown<br />
in Fig. 5.10. Ans. a = 0.98, fi - 50.<br />
Exercise 5.5 Use load-line analysis to find the minimum, maximum and Q-point values of i B and<br />
VCE for the amplifier circuit shown in Fig. 5.11. Use the characteristics shown in Fig. 5.10. Does<br />
this pnp BJT common-emitter amplifier invert the signal Ans. igg^ = 5 |xA, I B = 25 |iA, tg^x =<br />
48 uA, VOa^ £ -8.3 V, KCES -5.3 V, Pcimax s -1.8 V.<br />
1<br />
-12M<br />
i c<br />
Rc=3kCl<br />
5.3 Secondary Effects<br />
Collector breakdown. The description we have given so far is only a first-order model of the<br />
BJT. Real transistors exhibit many secondary effects that can be important in circuit design. For<br />
example, the common-emitter output characteristics of a real transistor are shown in Fig. 5.12.<br />
Notice that the collector current increases very rapidly as the collector-emitter voltage v^<br />
approaches 30V in this case. This is due to the reverse-bias breakdown of the collector-base<br />
junction. Usually, we try to avoid having BJTs enter the collector-breakdown region because high<br />
currents and voltages can result in high power dissipation that leads to overheating and<br />
destruction of the device. Collector breakdown voltages range up to several hundred volts,<br />
depending on the device type.<br />
Base width modulation. Another difference between the first-order BJT model and real<br />
transistors is that even before collector breakdown is reached, the collector current increases with<br />
collector-to-emitter voltage. For example, notice the positive slope of the curves in the active<br />
region of Fig. 5.12a. The slope is more pronounced at higher currents. This effect is attributed to<br />
die base width modulation effect known from the physics of the BJT operation.<br />
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Analog Electronics /BJT Circuits<br />
The shading of Fig. 5.12c and 5.12d suggests how the two depletion regions extend into the/>type<br />
base region during forward active operation. The base-emitter depletion region is narrow,<br />
the reverse-biased base-collector junction has a wider depletion region. For increased v^, the<br />
depletion region of the base-collector junction extends still further into the base, which reduces<br />
the width of the base region. Thus carriers injected from the emitter spend shorter time for die<br />
transit through the base and therefore a lower number of them recombine in the base region.<br />
This brings a closer to one. Since / is a sensitive function of a, the separation of the commonemitter<br />
output characteristics increases noticeably with f^, as illustrated in Fig. 5.12a and 5.12b.<br />
For a constant base current, the collector current increases with v^. This is known as the Early<br />
effect. (The change in common-base output characteristics whose spacing is determined by a, is<br />
hardly noticeable because the percent change in a is small.)<br />
If straight lines extend the collector characteristics in the active region, they (approximately) meet<br />
at a point on the negative v^ axis as shown in Fig. 5.12b. The magnitude of the voltage at the<br />
intersection is called the Early voltage, denoted by V A .<br />
4 «+— '<br />
c mm<br />
si><br />
m<br />
(c)<br />
(d)<br />
Figure 5.12 Common-emitter output characteristic that shows collector breakdown (a);<br />
extensions of die active-region collector characteristics intersect at -VA (b),<br />
base width modulation (c) and (d)<br />
Variation of fi with Q-point. In the first order model of the BJT, the collector characteristic<br />
curves are uniformly distributed in the active region. Real transistors tend to have characteristics<br />
that are crowded closer together at very low and very high currents.<br />
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Analog Electronics /BJT Circuits<br />
At low values of I c , recombination of charge carriers within the depletion region of base-emitter<br />
junction becomes significant. These phenomena manifest themselves by the emission coefficient<br />
n in the Shockley equation for base current having a value close to n = 2 which decreases to n = 1<br />
for medium collector currents (e.g. for /^lmA in Fig.5.13a) whereas the emission coefficient for<br />
the collector current stays constant, n — 1. Thus for low currents, the ratio of base current to<br />
collector current is lower than for medium currents.<br />
At high values of 7 C , the unspoken assumption that the carriers injected into the base and emitter<br />
are not disturbing the original concentration of carriers is no longer valid. These high-injectiondensity<br />
effects, sometimes referred to as "current crowding", cause reduction of p. For large<br />
collector currents, e.g. /^lOmA in Fig. 5.13b, high current density in the base region causes a<br />
significant increase of the minority carrier concentration in the base which, in turn, produces a<br />
masking effect to the built-in nonuniform impurity concentration in -the base. In particular, the<br />
built-in electric field in the base is reduced by the injected charge and carrier transport efficiency<br />
is reduced. This reduces the value of the current gain.<br />
Earlier we defined fi = I C /I B , but since the curves are not uniformly spaced, the value of f) is not<br />
constant for all points in the active region of real transistors. The variation of fi with collector<br />
current is illustrated in Fig. 5.13a for a typical BJT, showing the current gain decrease both at low<br />
and high currents. However, since the curves are generally broad and flat at moderate values of<br />
I a we usually assume that ft is independent of operating point as a first approximation.<br />
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Analog Electronics /BJT Circuits<br />
(c)<br />
(d)<br />
Figure 5.13 Typical variation of ^with collector current (a),<br />
input characteristics of a real transistor (b);<br />
output characteristic at temperature Tt (c), T > T/ (d)<br />
Parameter variation with temperature. Input and output characteristics of the BJT change<br />
with temperature, as do the BJT parameters. The common-emitter input characteristic translates<br />
to the left with increased temperature, in a similar way to the diode forward characteristic shown<br />
in Fig. 3.10. The base current is described by Equation (5.8). As in the diode, V r = kT/q in the<br />
exponent dominates the temperature dependence and causes the voltage V BE to decrease by 2<br />
mV for every degree Kelvin increase in temperature (at constant base current).<br />
The output characteristics increase in separation and translate upward with increasing<br />
temperature as shown in Fig. 5.13c and 5.13d. This reflects the increase of j3 with temperature.<br />
Minority carrier lifetime increases with temperature, increasing the carrier transport efficiency<br />
through the base region and bringing a closer to one. According to Equation (5.9), / is a<br />
sensitive function of a, the result is a large increase in /, as temperature increases. An empirical<br />
relationship that predicts variations in /is<br />
flCn = fiCrJ^\ (5.20)<br />
where T and T R are temperatures in degrees Kelvin and B is a constant called the temperature<br />
exponent. For a class of silicon bipolar transistors one may select B - 1.7, which makes (5.20)<br />
predict that J3 approximately doubles from 27°C to 175°C.<br />
To explain the upward translation, we need to notice that equation (5.10) is an approximation.<br />
Namely, for higher accuracy it should have two terms as follows<br />
where I^g is a small dc saturation current that doubles for every 5K increase in temperature.<br />
From the three temperature-sensitive parameters, V BE actually proves to be the most<br />
troublesome in practical circuits. Even at elevated temperatures, J^ is usually too small to play a<br />
major role in silicon transistors. Also, it is relatively easy to design circuits that work well for any<br />
high value of fi. Many IC designs use the V BE drops of matched transistors to cancel each other<br />
over wide temperature ranges.<br />
Variation of/ from unit to unit. If we test many units of a transistor of a given manufacturer's<br />
type number, we generally "find that J3 displays considerable variation in the value from unit to<br />
unit. Typically, the ratio of the highest and lowest values of beta is 3:1. Furthermore, the value of<br />
beta-varies significantly with temperature for a given transistor. Therefore, m must design cinuits<br />
that junction properly for transistors having a wide range of beta values.<br />
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Analog Electronics /BJT Circuits<br />
Dependence of input characteristics on VCE. The input characteristics of a real transistor are<br />
shown in Fig. 5.13b. Notice that the input charactetistics ate not a single curve, as in the firstorder<br />
model, but instead consist of a family of curves. The effect of base-width modulation with<br />
the varying v K voltage is mainly responsible for this property. However, assuming that v^ is<br />
larger than a few tenths of a volt (i.e. the BJT is biased in the active region), the input<br />
characteristic curves are very close together.<br />
Charge storage effects. The characteristic curves show only die static operation of the device.<br />
For rapidly changing signals, charge storage effects occur, and the instantaneous operation of the<br />
BJT is not adequately described by the characteristic curves. These effects are important in the<br />
design of high-frequency amplifiers and high-speed logic circuits. We consider these aspects later<br />
in this chapter.<br />
Even though real BJTs display many secondary effects that can be important in the design of<br />
critical circuits, the first-order model is sufficient for many designs. Even in critical circuits,<br />
designs often begins with die simple model. In die next few sections, we show some useful<br />
circuits man be analyzed and designed by use of first-order models.<br />
5.4 Large-Signal dc BJT Models<br />
In the analysis or design of BJT amplifier circuits, we often consider the dc operating point<br />
separately from the analysis of the (small) signals. This was illustrated for diode circuits and FET<br />
circuits in previous sections. Usually, we consider the dc operating point first. Then we turn our<br />
attention to the signal to be amplified. In this section, we present models for large-signal dc<br />
analysis of BJT circuits. Then, in die next section, we show how to use these models to design<br />
and analyze bias circuits for BJT amplifiers. Later we consider small-signal models used to<br />
analyze the circuit for the signal being amplified.<br />
It is customary to use uppercase symbols with uppercase subscripts to represent large-signal dc<br />
currents and voltages in transistor circuits. Thus I c and V^ represent the dc collector current and<br />
collector-to-emitter voltage, respectively. Similar notation is used for the other currents and<br />
voltage.<br />
As we have seen, BJTs can operate in the active region, in saturation, or in cutoff. In the active<br />
region, the base-emitter junction is forward-biased and the base-collector junction is reversebiased.<br />
(Actually, the active region includes the forward bias of the collector junction by a few<br />
tenths of a volt.)<br />
C<br />
C<br />
n _ Q<br />
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Analog Electronics /BJT Circuits<br />
Figure 5.14 BJT large-signal models (Note: Values shown are appropriate for<br />
typical small-signal silicon devices at a temperature of 300K.)<br />
Active-region model. Circuit models for BJTs in the active region are shown in Fig. 5.14a. A<br />
current-controlled current source models the dependence of the collector current on the base<br />
current. The constraints given in the figure for I B and K^ must be satisfied to ensure validity of<br />
the active-region model.<br />
0.2V VC£(V) 0.5V vae(V)<br />
(*) (b)<br />
Figure 5.15 Regions of operation on the characteristics of an npn BJT:<br />
(a) output, (b) input characteristic.<br />
Let us relate the active-region model to the device characteristics. Fig. 5.15 shows the<br />
characteristic curves of an npn transistor. The base current I B is positive and p BH =0.7V for<br />
forward bias of the base-to-emitter junction as shown in Fig. 5.15b. Also notice in Fig. 5.15a that<br />
VCE must be greater than about 0.2V to ensure that operation is in the active region (i.e. above<br />
the knees of the characteristic curves).<br />
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Analog Electronics /BJT Circuits<br />
Similarly, for the pnp BJT we must have J B >0 and V CE I(>0.<br />
Cut-off region. In cutoff, both regions are reverse biased, and no current flows in the device.<br />
Thus the model consists of open circuits among all three terminals as shown in Fig. 5.14c.<br />
(Actually, if small forward-bias voltages up to 0.5V are applied, the .currents are non-zero but<br />
often negligible, and we still use the cutoff model.) The constraints on the voltages for the BJT to<br />
be in the cutoff region are shown in the figure.<br />
Inverted mode. When the collector-base junction is reverse-biased and the base-emitter junction<br />
is forward biased, we say that the transistor is operating in the forward or normal mode.<br />
Sometimes, we encounter situations for which the base-collector junction is forward biased and<br />
the base-emitter junction is reverse-biased. This is the opposite of the normal situation, and we<br />
say that the transistor is operating in the inverted mode. Operation in the inverted mode is the<br />
same as in the normal mode, but with the collector and emitter interchanged. Most devices are<br />
not symmetrical, so alpha and beta take different, much lower, values for the inverted mode that<br />
for the normal mode. For now, we concentrate our attention on operation in saturation, cutoff or<br />
the normal active mode regions.<br />
Exercise 5.6 A given npn transistor has /£=100. Determine the region of operation if (a)<br />
7 B =50uA and J^mA, (b) I B =50uA and V CE =5V i (c) V BE =-2V and V CE =-1 V.<br />
Exercise 5.7 A certain/>/#> transistor has /=100. Determine the region of operation if (a) V BE —-<br />
0.2V and K CT =5V, (b) 7 B =50uA and I c =2mA, (c) F CE =5V and 7 B =50uA.<br />
5.5 Large-Signal dc Analysis of BJT Circuits<br />
In this section, we will use the large-signal BJT models presented in Section 5.4 to analyze<br />
circuits.<br />
(a) (b) (c) (d)<br />
Figure 5.16 Bias circuits for Examples 5.1 and 5.2: actual circuit (a),<br />
equivalent circuits assuming operation in cutoff (b),<br />
in saturation (c), in the active region (d)<br />
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Analog Electronics /BJT Circuits<br />
In the dc analysis of BJT circuits, we first assume that the operation of the transistor is in a<br />
particular region (i.e. active, cutoff, or saturation). Then we use the appropriate model for the<br />
device and solve the circuit Next, we check to see if the solution satisfies the constraints for the<br />
region assumed. If so, the analysis is complete. If not, we assume operation in a different region<br />
and repeat until a valid solution is found. (This is very similar to the analysis of diode circuits<br />
using ideal-diode model or a piecewise-linear model.)<br />
This approach is particularly useful in the analysis and design of bias circuits for BJT amplifiers.<br />
The objective of the bias circuit is to place the operating point in the active region so that signal<br />
can be amplified. Because transistors show considerable variation of parameters, such as (3, from<br />
unit to unit and with temperature, it is important for the bias point to be independent of these<br />
variations.<br />
The next several examples illustrate the technique and provide some observations that are useful<br />
in bias-circuit design.<br />
Example 5.1 The dc bias circuit shown in Fig. 5.16a has R B =200kQ, Rc=lkQ, and K CC =15V.<br />
The transistor has /£=100. Solve for I c and VCE-<br />
Solution We will eventually see that the transistor is in the active region, but we start by<br />
assuming that the transistor is cut off (to illustrate how to test the initial guess of operating<br />
region). Since we assume operation in cutoff, the model for the transistor is shown in Fig. 5.14c,<br />
and the equivalent circuit is shown in Fig. 5.16b. We reason that 7 fl =0 and there is no voltage<br />
drop across R B . Hence we conclude that V B£ =15V. However, in cutoff, we must have K fl£ 0 is met, but /3I B >I C is not met.<br />
Therefore, we conclude that the transistor is not in saturation.<br />
Finally, if we assume that the transistor operates in the active region, we use the BJT model of<br />
Fig. 5.14a, and the equivalent circuit is shown in Fig. 5.16d. Solving, we find that<br />
4=(* / ar0.7)/R B =71.5uA<br />
where we have assumed a forward bias of 0.7V for the base-emitter junction. (Some authors<br />
assume 0.6V for low-power silicon devices. Others assume 0.7V.) In reality, the value depends on<br />
the particular transistor and the current level. Usually, the difference is not significant.) Now we<br />
have<br />
lc=Ph = 7.15nA<br />
Finally, V CE =V CC -R < I C = 7.85V<br />
The requirements for the active region are K CE >0.2V and 7 B >0, which are met. Thus the<br />
transistor operates in the active region.<br />
Exercise 5.8 Repeat Example 5.1 with /£=300. Ans. 7 c =14.8mA, K CE =0.2V (saturation).<br />
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Analog Electronics /BJT Circuits<br />
^15V<br />
v CT (V)<br />
(b) P = 300<br />
Figure 5.17 Load lines for Example 5.1 and Exercise 5.8<br />
It is instructive to consider the load-line constructions shown in Fig. 5.17 for the last two<br />
examples. For /£=100, the operating point is approximately in the center of the load line. On the<br />
other hand, for /=300, the operating point has moved up into saturation.<br />
To use this circuit as an amplifier, we would want a Q-point in the active region where changes
Analog Electronics/BJT<br />
Circuits<br />
Exercise 5.11 Solve the circuit shown in Fig. 5.18 to find I c and V^ if (a) >0^5O, (b) /£=150.<br />
Ans. (a) 7c=:0.965mA, ^=-10.35^ (b) 7 c =1.98mA, V a =-0JZV (transistor in saturation).<br />
lOkfl<br />
Figure 5.18 Circuit for Exercise 5.11<br />
In the next example we consider a circuit that achieves an emitter current that is relatively<br />
independent of /3.<br />
W<br />
(b)<br />
Figure 5.19 Circuit of Example 5.2 (a) and its equivalent circuit (b) assuming<br />
operation in the active region.<br />
Example 5.2 Solve for 7 C and V^ in the circuit of Fig. 5.19a if V C( ~=\5V, V BB =5V, Rc=2kQ,<br />
and yS^lOO. Repeat for ^=300.<br />
Solution We assume that the transistor is in the active region and use the equivalent circuit<br />
shown in Fig. 5.19b. Wr»«ing a voltage equation through V BB , the base-emitter junction and R H)<br />
we have<br />
F flB =0.7 + 7 E R H<br />
This can be solved for the emitter current<br />
h= {V BB -0.1)/R E = 2.15mA<br />
Notice that the emitter current does not depend on the value of fi.<br />
Next we can compute the base and collector current using Equations (5.10) and (5.2)<br />
I E = I B +/3I B = (JS+1)I B<br />
Solving for the base current, we obtain<br />
7 B =/ E /09+l)<br />
Substituting values, we obtain the results given in Table 5.1. Notice that 7 B is lower for the higher<br />
P transistor, and I c is nearly constant.<br />
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Analog Electronics /BJT Circuits<br />
TABLE 5.1 RESULTS FOR EXAMPLE 5.2<br />
1 p JJO^A) J^mA) ^CE(V)<br />
I 100 21.3 2.13 6.44<br />
1 300 7.14 2.14 6.42<br />
Now we can write a voltage equation around the collector loop to find *VCE<br />
Vc^RcIc+Vcz+RzIz<br />
Substituting values found previously, we find that 1^=6.44V for /=100 and<br />
K CE =6.42Vfor^=300.<br />
The Q-point for the circuit of Fig. 5.19a is almost independent of p. However, die circuit is not<br />
usually practical for use in amplifier circuits. First, it requires two voltage sources, V BB and V co<br />
but often one source is readily available. Second, we may want to inject the signal into the base<br />
(through a coupling capacitor), but the base voltage is fixed with respect to ground by the V BB<br />
source. Because the V BB source is constant, it acts as a short-circuit to ground for ac signal<br />
currents (i.e. the V BB source does not allow an ac voltage to appear at the base.)<br />
5.6 Four-Resistor Bias Circuit<br />
A circuit that avoids the objections discussed at the end of the previous section is shown in Fig.<br />
5.20a. We call this the four-resistor BJT bias circuit. The resistors R, and R 2 for a voltage<br />
divider that is intended to provide a nearly constant voltage at the base of the transistor<br />
(independent of transistor p). As we saw in Example 5.2, constant base voltage results in nearly<br />
constant values of I c and K^. Because the base is not directly connected to the supply or ground<br />
in the four-resistor bias circuit, it is possible to couple an ac signal to the base through a coupling<br />
capacitor.<br />
The circuit can be analyzed as follows. First, the circuit is redrawn as shown in Fig. 5.20b. Two<br />
separate voltage supplies are shown as an aid in the analysis to follow, but otherwise the circuits<br />
in part (a) and (b) of the figure are identical Next, we find the Thevenin equivalent for the circuit<br />
to die le t of the dashed line in Fig. 5.20b. The Thevenin resistance R fl is the parallel combination<br />
of R, and R 2 given by<br />
R^1^T<br />
RIM<br />
2 < 5 - 2,)<br />
The Thevenin voltage is<br />
R 2<br />
Vn 'B = V, CC (5.22)<br />
The circuit with the Thevenin replacement is shown in Fig. 5.20c. Finally, its active-region largesignal<br />
model as shown in Fig. 5.20d replaces die transistor.<br />
Now we can write a voltage equation around the base loop of Fig. 5.20d, resulting in<br />
V B = R B I B + V BE + R E I E (5.23)<br />
Of course, for low-power silicon transistors at room temperature, we have K B£ s0.7V. Now we<br />
can substitute<br />
/ £ «=(l+0)/a<br />
and solve to find that<br />
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Analog Electronics /BJT Circuits<br />
VB-VBE<br />
(524)<br />
''-Ri+Q+fiR,<br />
Once I B is known, I E and I c can be easily found. Then we can write a voltage equation around the<br />
collector loop of Fig. 5.20d and solve for V^. This yields<br />
V C E = VCC ~ Wc ~ &Eh (5-25)<br />
« (b)<br />
r cc<br />
07V<br />
'|/ £ =(P+i)4<br />
(c)<br />
(d)<br />
Figure 5.20 Four-resistor bias circuit (a), equivalent circuit show lg separate voltage sources for base and<br />
collector circuits (b), circuit using Thevenin's equivalent for Vcc, R/ and R2 (c),<br />
equivalent to part (c) with active-region transistor model (d).<br />
Exercise 5.12 Find the values of I c and V^ in the circuit of Fig. 5.20a for (a) /fc=100 and (b)<br />
y9=300. Assume that Vg^O.TV and that the circuit elements take on the following values of<br />
R,=10kQ, R,=5kQ, R^lkQ, R E =lkfi, F CC =15V. Ans. (a) J c =4.12mA, V CE =6.12V, (b)<br />
7c=4.24mA, V CE =6.5\V.<br />
Exercise 5.13 Repeat Exercise 5.12 for R,=100kQ and R 2 =50kQ. Compute the ratio of I c for<br />
/=300 to I c for /fc=100 and compare to the ratio of the currents found in Exercise 5.12. Ans.<br />
The ratio of the collector currents is 1.21. On the other hand, in the previous exercise, the ratio<br />
of the collector currents is only 1.029. Larger values of Rl and R2 lead to larger changes in I c<br />
with changes in f3.<br />
We "often use the four-resistor circuit of Fig. 5.20a for biasing BJTs in discrete-component<br />
amplifiers. Now we consider the design of this type of bias circuit The principal problem of bias<br />
circuit design is to achieve nearly identical operating points for the BJTs even though P may vary by a factor of 3<br />
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Analog Electronics / BJT Circuits<br />
more units. Furthermore, some circuits are required to function over a wide range of temperature,<br />
which can cause significant variations in fi and V BE .<br />
Notice that I c and V^ are nearly independent of fi in the circuit of Fig. 5.20a and Exercise 5.12.<br />
This is achieved by selecting values for R, and R 2 that provide a nearly constant voltage to the<br />
base. As the values of R, and R 2 become larger, the Q-point exhibits larger changes with /.<br />
Comparing the results of Exercise 5.13 with those of Exercise 5.12 can see .this.<br />
For the voltage divider to provide a nearly constant base voltage for different values of base<br />
current, the resistors R, and R 2 should be small in value. However, this leads to large currents,<br />
possible overheating, and the need for a larger, more expensive power supply. Moreover, the ac<br />
impedance seen at the base decreases with the decrease of the values of the resistors R, and R 2 ,<br />
which is undesirable in some applications. Thus we also wish to make R, and R 2 as large in value<br />
as possible. As a general rule, a good compromise is to choose R 2 so that the current through it is 10 to 20 times<br />
the largest base current expected.<br />
Equation (5.24) shows that the base current is proportional to the difference between V B and<br />
V BE . Recall that V BE decreases in value by about 2mV/K as temperature increases. Furthermore,<br />
resistor tolerances cause V B to vary. If we design so that the difference between K B and V BE is<br />
very small, these variations could result in troublesome changes in the jg-point. Therefore, we should<br />
design so that V B is much larger than the changes expected in V BE due to temperature variation and the changes<br />
in V B due to resistor tolerances.<br />
Often, we choose V B to be one-third of the supply voltage, which is usually large enough to<br />
ensure a sufficiently stable jg-point. Usually, V B is much larger than V BE , so that the drop across<br />
R E is approximately equal to V B . A rule in common use is to design so that one-third of the<br />
supply voltage is dropped across R^ one-third across the transistor (P^g) and one-third across<br />
R E .<br />
Consideration of the frequency response, peak signal swing, available component values and<br />
various other matters place constraints on the j2-point and the selection of resistor values to be<br />
used in the bias circxiit. Thus the design of the bias circuit is intertwined with the ac performance<br />
of an i iplifier. We consider more aspects of bias design later in conjunction with amplifier<br />
performance.<br />
Figure 5.21 Circuit for Example 5.3<br />
Example 5.3 Suppose that considerations of the frequency response of an amplifier have<br />
dictated that the j2-point of the transistor should be at I c = 2mA and that R^ = 4.7kQ. The<br />
supply voltage is V cc = 25V. The transistor to be used has / ranging from 100 to 300. Design a<br />
four-resistor bias circuit for this amplifier. Use standard 5%-tolerance resistor values.<br />
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Analog Electronics /BJT Circuits<br />
Solution The diagram of the circuit to be designed is shown in Fig. 5.21. The drop across R^ is<br />
V c - I c Rc= 9.4V. This leaves 25 - 9.4 = 15.6V to be allocated between V^ and the drop across<br />
RE-<br />
Suppose that we choose V^ = 10V leaving 5.6V across Rg. Then, since I E = I a we have RE =<br />
V E /I B = 2.8kQ. However, the closest nominal value is R E = 2.7kQ, so that is our choice. (See<br />
Appendix A for nominal 5%-tolerance resistor values.)<br />
Next, we compute the base voltage V B = V BE + V E = 0.7 + 5.6 = 6.3V. The base current is I B =<br />
Z c /p. Since we want the maximum base current to be much less than I 2 (so that V B does not<br />
change excessively when I B changes due to variations in j$), we use the minimum p. Thus I Bmax . —<br />
J c /P = 20|oA. Then using the rule of thumb that I 2 should be 10 times the maximum base<br />
current, we have I 2 = 0.2mA. Now, R 2 = V B /I 2 = (6.3V)/(0.2mA) = 31.5kQ, so we choose R 2 =<br />
33kQ, which is a standard value.<br />
Next, we see that I, = I B + I 2 = 0.22mA and V, = V cc - V B = 18.7V. Finally, R, = V,/I, = 85kQ,<br />
so we choose a close nominal value of R, = 91kQ. (We could just as well have chosen R, =<br />
82k£l)<br />
Thus our design calls for R^ = 2.7kn, R, = 91kfi, R 2 = 33kQ and R^ = 4.7kQ. Of course, many<br />
other choices could have been made in the design, resulting in different but equally useful values.<br />
Usually, there are many rijjfrt answers to the design problems.<br />
Exercise 5.14 Analyze the circuit designed in Example 5.3 to find the jg-point values of I c and<br />
Vcg that actually result with the nominal resistor values for (a) p=100; (b) P=300. Ans. (a) I c =<br />
2.00mA, VCE = 10.1V; (b) I c = 2.13mA, V^ = 9.22V.<br />
Exercise 5.15 In the four-resistor bias network, does I c decrease, increase or stay the same for a<br />
(small) increase in the value of (a) R^, (bJRg, (c) R„ (d) R^, (e) P<br />
Exercise 5.16 In the four-resistor bias network, does K^ decrease, increase or stay the same for<br />
a (small) increase in the value of (a) R& (tyRg, (c) R„ (d) R^, (e) P<br />
Exercise 5.17 Find the maximum and minimum values of I c and V^ for the circuit designed in<br />
Example 5.3. {Hint: Consider the combination of P and values of resistors within ±5% of the<br />
nominal values.) Ans. Icmn. = 2.43mA, i^, = 1.77mA, VcEmax ~<br />
12.1^1^, = 6.76V.<br />
Exercise 5.18 Suppose that V cc = 20V, R^ = lkQ and a j2-point of I c = 5mA is desired. The<br />
transistor has P ranging from 50 to 150. Design a suitable bias circuit. Use standard 5%-tolerance<br />
resistor values.<br />
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Analog Electronics /BJT Circuits<br />
5.7 Small-Signal Equivalent Circuits<br />
Now we turn our attention to small-signal currents and voltages in circuits containing BJTs. First<br />
we establish the notation used in amplifier circuits. We denote total currents and voltages by<br />
lowercase symbols with uppercase subscripts. Thus i B (t) is the total base current as a function of<br />
time.<br />
The Q-point currents and voltages are denoted by uppercase symbols with uppercase subscripts.<br />
Thus I B is the dc base current if the input signal is set to zero.<br />
Finally we denote the' changes in currents and voltages from the Q-point (due to the input signal<br />
being amplified) by lowercase symbols with lowercase subscripts. Thus i t (/) denotes the signal<br />
component of the base current. Since the total base current is the sum of the Q-point value and<br />
die signal component we can write<br />
iB® = h + M (5-26)<br />
Similarly<br />
•taW^re + ^O) ,( 5 - 27 )<br />
The Q-point is established by the bias circuit as discussed in the previous section. Now we<br />
consider how the small signal components are related to each other in the BJT. The total base<br />
current is given in terms of the total base-to-emitter voltage by (5.8), repeated here for<br />
convenience<br />
i B = (1 - ayigs exp(^)-l (5.28)<br />
We are concerned with operation in the active region for which the 1 inside the bracket is<br />
negligible and can be dropped. Substituting (5.26) and (5.27) into the modified (5.28) one obtains<br />
h + ^O = (1" "VES e*P[ VBE t Vbeit) ) (5-29)<br />
V T<br />
This can be written as<br />
I B + i b (l) = (1 - aVus<br />
, ^
Analog Electronics /BJT Circuits<br />
At room temperature, K^=26mV. A typical value of f$ is 100 and a typical bias current for a<br />
small-signal amplifier is l c - 1mA. These values yield r n - 2600Q.<br />
It is easy to show that the signal component of the collector current is given as<br />
» C (0 = A,(0 ' (5.34)<br />
Equations (5.32) and (5.34) relate the small-signal currents and voltages in a BJT. They lead to a<br />
small-signal equivalent circuit of the BJT shown in Fig. 5.22a. This circuit is very useful in the<br />
analysis of the BJT amplifier circuits. It turns out that the pnp transistor has exactly the same<br />
equivalent circuit as the npn - even the reference directions for the signal currents and voltages<br />
are the same. The resistance r„ is given by (5.33) for both transistor types.<br />
An alternative small-signal equivalent circuit is shown in Fig. 5.22b. Instead of the currentcontrolled<br />
current source it uses a voltage-controlled current source to describe the signal<br />
component of the collector current<br />
»c(0 = ft»v te (0 (5.35)<br />
The coefficient g, is called the transconductance of the BJT, defined as<br />
d (<br />
8m<br />
(5.36)<br />
&>BE V T<br />
Q- point<br />
Which one of the circuits shown in Fig. 5.22 is used for circuit analysis is the matter of<br />
convenience.<br />
Figure 5.22 Small-signal equivalent circuit for the BJT<br />
5.8 The Common-Emitter Amplifier<br />
In a BJT amplifier circuit, the power supply biases the transistor at an operating point in the<br />
active region for which amplification can take place. For example, we can use the four-resistor<br />
bias circuit discussed in Section 5.6. Coupling capacitors are used to connect the load and the<br />
signal source without affecting the bias point.<br />
We can analyze amplifier circuits to find gain, input resistance and output resistance by use of the<br />
small-signal equivalent circuit. In this section, and the next we illustrate this procedure for two<br />
important amplifier circuits.<br />
Fig. 5.23a shows the circuit diagram of a common-emitter amplifier. The resistors R,, R 2 , R E<br />
and R^ form the four-resistor biasing network. The capacitor C, couples the signal source to the<br />
base of the transistor, and JC 2 couples the amplified signal at the collector to the load R L . The<br />
capacitor C E is called the bypass capacitor. It provides a low-impedance connection between<br />
the emitter and ground, for ac.<br />
The coupling and bypass capacitors are chosen large enough so that they have very low ac<br />
impedance at the signal frequencies. For simplicity, in our initial small-signal ac analysis, we treat<br />
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Analog Electronics /BJT Circuits<br />
the capacitors as short circuits. However, at sufficiendy low frequencies, the capacitors reduce<br />
the gain of the amplifier, because their impedance increases in magnitude with decreasing signal<br />
frequency.<br />
Vc<br />
V C<br />
(a) Actual circuit<br />
'*><br />
B<br />
(b) Small-signal ac equivalent circuit<br />
'b=0 B<br />
Source<br />
"turned off<br />
^MJ<br />
(c) Equivalent circuit to find Z 0<br />
Figure 5.23 Common-emitter amplifier<br />
Because the bypass capacitor grounds the emitter for ac signals, the emitter terminal is common<br />
to the input source and to the load. This is the origin of the name common-emitter-amplifier.<br />
The analysis we give here is valid for the midband region of frequency. In the low-frequency<br />
region, the effects of the coupling and bypass capacitors must be considered. In the highfrequency<br />
region, a more complex transistor model must be used that includes the frequene<br />
limitations of the transistor. We treat this high-frequency response later in this chapter.<br />
Before we analyze the amplifier, it is very helpful to draw its small-signal equivalent circuit. This<br />
is shown in Fig. 5.23b. The coupling capacitors have been replaced by short circuits and the<br />
transistor has been replaced by its small-signal equivalent.<br />
The dc power supply is replaced by a short circuit. This is appropriate because it has zero internal<br />
resistance, so no ac voltage can appear on it.<br />
Carefully compare the actual circuit of Fig. 5.23a with the small-signal ac equivalent shown in Fig.<br />
5.23b. Notice that the signal source is connected directly to the base terminal because C, has<br />
been treated as a short circuit. Similarly, the emitter is connected direcdy to the ground and the<br />
load is connected to the collector.<br />
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Analog Electronics / BJT Circuits<br />
Notice that the top terminal of R, connects to the supply in the original circuit, but R, is<br />
connected from base to ground in the equivalent circuit, because the power-supply voltage<br />
source is treated as a short circuit to ground for ac signals. Notice also that R, ends up in parallel<br />
with R^. Similarly, R^ and R L are in parallel. We find it convenient to define R B as the parallel<br />
combination of R, and R 2<br />
Similarly, R^' is a parallel combination of B^ and RL<br />
R'L = - ^ \ - (5-38)<br />
To find the voltage gain v 0 /v/ of the amplifier, first we note that the input voltage is equal to the<br />
voltage across r„, given by<br />
v, = v^ = r K i b (5.39)<br />
The output voltage is produced by the collector current flowing through Rj/<br />
v o =-R L 0i b (5.40)<br />
The minus sign is necessary because of the reference directions for the current and voltage - the<br />
current flows out the positive voltage reference. Dividing (5.40) by (5.39) gives the voltage gain<br />
V Rr<br />
A=-^ = -/*— (5-41)<br />
V- r<br />
v i<br />
'it<br />
Notice that the gain is negative showing that the common-emitter amplifier is inverting. The gain<br />
magnitude can be quite large - several hundred is not unusual.<br />
The expression for gain given in (5.41) is the gain with the load connected. We found the opencircuit<br />
voltage gain useful to characterize amplifiers in Chapter 2. With R L replaced by an open<br />
circuit, the voltage gain becomes<br />
A vo =-/3^ (5.42)<br />
Another important amplifier specification is the input impedance, which in this case can be<br />
obtained by inspection of the equivalent circuit. The input impedance is the impedance seen<br />
looking into the amplifier-input terminals. For the equivalent circuit of Fig. 5.23b, it is a parallel<br />
combination of R B and r n .<br />
Z,=^ = - ^ - (5.43)<br />
', Rli+ r x<br />
In this case the input impedance is a pure resistance. Therefore we can find the impedance by<br />
dividing the instantaneous voltage f, by the instantaneous current i f Of course, if there were<br />
capacitances or inductances in the equivalent circuit, it would be necessary to obtain the<br />
impedance as the ratio of the phasor voltage and the phasor current.<br />
The current gain Aj can be found by use of Equation (2.3). With some changes in notation, the<br />
equation is<br />
4-'-- = 4%- (5.44)<br />
• l i<br />
R L<br />
The power gain G of the amplifier is the product of the current gain and the voltage gain<br />
(assuming that the input and load impedance are pure resistive).<br />
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Analog Electronics /BJT Circuits<br />
G = AjA v (5.45)<br />
The output impedance is the impedance seen looking back from the load terminals with the<br />
source voltage v s set to zero. This situation is shown in Fig. 5.23c. With v s set to zero, there is no<br />
driving source for the base circuit, so i b is zero. Therefore, the controlled source P/ 4 produces<br />
zero current and appears as an open circuit. Thus the impedance seen from the output terminals<br />
is simply R c .<br />
Z 0 = Rc (5.46)<br />
Exercise 5.19 Find A v , A vo , Zn, A\, G, and Z 0 for the amplifier shown in Fig. 5.23a with Rs =<br />
500Q, Ri=10kQ, R 2 =5kQ, R E =lkO, Rc=lkQ, R L =2kft, (3=100, V BE =0.TV, V CC = 15V. If<br />
f,(/)=0.001sin(=-<br />
28.1, G=2980, Z 0 =lkQ, f o =-54.6sin((0t) mV.<br />
Exercise 5.20 Repeat Exercise 5.19 if P = 300. (Hint: do not forget that the Q-point changes<br />
slighdy when beta changes.) Ans. A v =-\09, v4 vo =-164, Z,= 1185Q, Ai=-64.5, G=7030, Z c =lkQ,<br />
v o =-16Jsin((0t) mV.<br />
5.9 The Emitter Follower<br />
The circuit diagram of another type of BJT amplifier called an emitter follower is shown in Fig.<br />
5.24a. The resistors R f , R 2 and R E form the biasing circuit. The collector resistance is not present<br />
in diis circuit. Thus we have a four-resistor biasing circuit with R(- = 0. The input signal is applied<br />
to this circuit through the coupling capacitor C,. The output signal is coupled from the emitter to<br />
the load by the coupling capacitor C 2 .<br />
Vc<br />
V C<br />
(b) Small-signal equivalent circuit<br />
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Analog Electronics / BJT Circuits<br />
(c) Equivalent circuit used to find output impedance Z„.<br />
Figure 5.24 Emitter follower<br />
The ac equivalent circuit is shown in Fig. 5.24b. As before, we replace the capacitors and power<br />
supply with short circuits. The transistor is replaced by its small-signal equivalent.<br />
Notice that as a result, the collector terminal is connected directly to ground in the equivalent<br />
circuit. The transistor equivalent circuit is oriented with the collector at the bottom in Fig. 5.24b,<br />
but it is electrically the same as the transistor equivalent circuit we have used before. Because the<br />
collector is connected direcdy to ground, this circuit is sometimes called a common-collector<br />
amplifier.<br />
The ability to-draw the small-signal equivalents for BJT circuits is an important skill for the<br />
electronic-circuit designer. Carefully compare the small-signal equivalent in Fig. 5.24b to the ori<br />
circuit. Better still; try to draw the small-signal equivalent circuit on your own starting from the<br />
original circuit.<br />
Notice that R, and R 2 are in parallel in the equivalent circuit. We denote the combination by R B .<br />
Also, R E and R L are in parallel and we denote the combination by R L '. In equation form we have<br />
RB ~RI + R,<br />
and<br />
A1A<br />
Rr = RrR E R L<br />
RE+RL<br />
(5.47)<br />
(5.48)<br />
Next we find the voltage gain of the emitter follower. The current flowing through R L ' is 4+Pv<br />
Thus the output voltage is given by<br />
v 0 =R L (\ + {3)i b (5.49)<br />
Writing the voltage equation from the input terminals through r„ and then through the load to<br />
ground, we have<br />
Vi=V b +R L (l + /B)t b (5.50)<br />
Division of (5.49) by (5.50) results in<br />
A- = (5.51)<br />
r K + R L {\ + P)<br />
The voltage gain of the emitter follower is less than unity because the denominator of the<br />
expression is larger than the numerator. However, the voltage gain is usually only slighdy less<br />
dian unity. An amplifier widi voltage gain less than unity can sometimes be useful because it can<br />
have a large current gain.<br />
Also, notice that the voltage gain is positive. In odier words, the emitter follower is noninverting.<br />
Thus if the input voltage changes, the output at the emitter changes by almost the same amount<br />
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Analog Electronics /BJT Circuits<br />
and in the same direction as the input The output voltage follows the input voltage. This is the<br />
reason for the name emitter follower.<br />
The input impedance Zi can be found as the parallel combination of Rg and the input impedance<br />
seen looking into the base of the transistor, which is indicated as Z« in Fig. 5.24b. Thus we can<br />
write<br />
_ RaZu<br />
The input impedance looking into the base can be found by dividing both sides of (5.50) by i b .<br />
Zit=T- = r x +BL L (\ + P) (5.53)<br />
l b<br />
The input impedance of the emitter follower is relatively high compared to other BJT amplifier<br />
configurations. However, if very high input impedance is needed, we often have to resort to<br />
more complex amplifiers using feedback. We consider this approach later. We have already seen<br />
that field-effect transistors are capable of providing much higher input impedance than BJTs.<br />
Once we have found the voltage gain and input impedance of the emitter follower, the current<br />
gain and power gain can be determined by use of (2.3) and (2.5).<br />
The output impedance of an amplifier is the Thevenin impedance seen from the output<br />
terminals. To find the output impedance of the emitter follower, we remove the load resistance,<br />
put the signal source to zero, and look back into the output terminals of the equivalent circuit.<br />
This is shown in Fig. 5.24c. We have attached a test source v x that delivers a current i x to the<br />
impedance we want to find. The output impedance is given by<br />
Zo=T (5-54)<br />
l x<br />
(here again, the impedance can be expressed as the ratio of instantaneous time-varying quantities<br />
because the circuit is purely resistive. Otherwise, we should use phasors.)<br />
To find this ratio, we write equations involving v x and i x . For example, summing current at the<br />
top of J cr, we have<br />
ib+flb+ix-jfe (5-55)<br />
We must eliminate i b from this equation before we can find the desired expression for the output<br />
impedance. We do not want any circuit variables such as i h in the result - only transistor<br />
parameters and resistor values. Thus we need to write another circuit equation.<br />
First, we denote the parallel combination of R„ R, and R 2 as<br />
i<br />
R*RR<br />
R s = „ ' „ (5.56)<br />
The additional equation needed can now be obtained by applying Kirchhoff s voltage law to the<br />
loop consisting of v^ r x and R/.<br />
v x +r„i b +R s i b =0 (5.57)<br />
If we solve Equation (5.57) for t h substitute into (5.55) and rearrange the result, we obtain the<br />
output impedance.<br />
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Analog Electronics /BJT Circuits<br />
v x 1<br />
Z o~ f ~ \+p 1 ( 5 - 58 )<br />
R E<br />
*s+*K<br />
This can be recognized as the parallel combination of R^ and the impedance<br />
z v x R s + r-<br />
«=tr^t<br />
(559><br />
It can be shown that Z ot is the impedance seen looking into the emitter of the transistor, as<br />
indicated in Fig. 5.24c. The output impedance of the emitter follower tends to be smaller than<br />
that of other BJT amplifier configurations.<br />
Exercise 5.21 Compute the voltage gain, input impedance, current gain, power gain and output<br />
impedance of the emitter-follower amplifier shown in Fig. 5.24a. Assume R, = lOkft, R, =<br />
lOOkO, R2=100kQ, R E =2kQ, Ri=lkQ, B=200, K BE =0.7V, V C c=20V. Verify the results using<br />
PSpice. Ans. ^4 V =0.991, Zj=36.5kn, Z 0 =46.6Q, ^4=36.2, G=35.8<br />
In general, the output impedance of the emitter follower is much lower and the input impedance<br />
is much higher than those, of other single-stage BJT amplifiers. Thus we can use an emitter<br />
follower if high input impedance and low output impedance is needed.<br />
Notice that even though the emitter follower gain is less than unity, the current gain is large.<br />
Thus die output power is larger than the input power and the circuit is effective as an amplifier.<br />
If the emitter follower is cascaded with common-emitter stages, amplifiers with many useful<br />
combinations of parameters are possible. Furthermore, there are several other useful amplifier<br />
configurations using the BJT. Later we study additional circuit configurations and consider the<br />
design of multistage amplifiers.<br />
Exercise 5.22. Repeat Exercise 5.21 widi P=300. Compare the results. Verify the results using<br />
PSpice. Ans.y4 v =0.991, Zi=40.1kQ, Zo=33.2Q, ^4=39.7, G=39.4.<br />
5.10 Review of Small-Signal Equivalent-Circuit Analysis<br />
Before we leave the important topic of small-signal equivalent-circuit analysis, we review die<br />
technique and provide a few useful observations.<br />
The first step in analysis is to draw die small-signal equivalent circuit by making the following<br />
changes to the original circuit:<br />
1) Replace the dc power-supply voltage sources by short circuits.<br />
2) Sometimes we may encounter dc current sources. Replace these by open circuits. This is<br />
appropriate because dc current sources force a constant current with no ac component to<br />
flow.<br />
3) If a midband analysis is desired, replace the coupling and bypass capacitors with short circuits.<br />
However, if we want to find expressions for gain or impedance as a function of frequency or<br />
perform a transient analysis, the capacitors should be included in the equivalent circuit (and<br />
we should use phasors to represent currents and voltages in the ac analysis).<br />
4) Sometimes we use inductors to provide a dc connection, but the inductance is picked large<br />
enough so that it has very high impedance for the ac signal. (Usually, this technique is practical<br />
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Analog Electronics /BJT Circuits<br />
only in circuits intended to operate at high frequencies.) Replace such inductors by open<br />
circuits in the small-signal equivalent<br />
5) Replace the transistor with its equivalent circuit If the circuit has several transistors, use<br />
subscripts to distinguish the currents and parameters of different transistors.<br />
It pays to be careful in drawing the equivalent circuit; analysis of an incorrect circuit is time and<br />
effort wasted. Double-check your circuit before writing equations.<br />
Once the small-signal equivalent circuit is finished, we turn our attention to finding expressions<br />
for the gains and impedance of interest First, identify the pertinent currents and voltages and<br />
label them on the equivalent circuit For example, in finding the voltage gain, the pertinent<br />
variables are the input voltage v t and the output voltage tt>. On the other hand, for the input<br />
impedance, we are concerned with v t and the current i f<br />
The output resistance is the Thevenin resistance of the amplifier. To find the output resistance,<br />
we remove the load, turn off independent signal sources and look back into the output terminals<br />
to find the resistance. Turning off the independent signal sources means replacing voltage<br />
sources with short circuits and current sources with open circuits. Dependent sources, such as<br />
me controlled current source of the transistor equivalent, are not turned off - the controlled<br />
source models the effect of the transistor.<br />
Often, it is convenient to attach a test voltage v x to the output terminals as we did in Fig. 5.24c to<br />
find the output resistance of the emitter follower. Then the output resistance is the ratio of v x and<br />
After drawing the small-signal equivalent circuit and identifying the pertinent current and voltage<br />
variables, we use circuit analysis to write equations. Then we use substitutions to eliminate the<br />
unwanted currents and voltages until we have an equation relating the two variables of interest<br />
Make sure that the equations are not dependent. Otherwise, substitution results in cancellation of<br />
all terms, so that you have 0=0 that indicates you must return to writing additional circuit<br />
equations.<br />
After we have found expressions for the gain or impedance, it is a good_idea to check to see that<br />
me units of the expression are correct Voltage or current gain should be. unitless. Input or output<br />
impedance should have units of ohm. In case the units do not check as expected, we should look<br />
for errors in writing the original equations or for algebraic errors.<br />
Small-signal equivalent circuit analysis is not as troublesome as it might seem from this<br />
discussion. We have tried to mention all of the common problems encountered with this<br />
technique so that you will not waste too much time if they come up. Many useful results can be<br />
obtained with ease by the use of small-signal equivalent circuit analysis.<br />
Possibly the thought process and viewpoints gained from the small-signal analysis technique are<br />
just as important as the expressions that we derive using them. After all, if we only wanted the<br />
formulas, we could resort to using a handbook. It is the understanding of the circuits obtained<br />
that makes the technique so important<br />
Example 5.4 A variation of the common-emitter amplifier is shown in Fig. 5.25a. Draw die<br />
small-signal equivalent circuit and derive an expression for the voltage gain.<br />
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Analog Electronics/BJT Circuits<br />
Figure J3.25 Variation of the common-emitter amplifier (a), and<br />
its small-signal equivalent circuit (b)<br />
Solution The small-signal equivalent circuit is shown in Fig. 5.25b. For convenience, we denote<br />
the parallel combination of R^ and R L by R L '. To find voltage gain, we must write equations<br />
involving t>, and v 0 . However, we find it necessary to involve 4, i y and L in the equations. We can<br />
write<br />
v,=W (5-60)<br />
because t> ; is the voltage across r n . Summing currents at the collector node we have<br />
i f =j3i b +i y (5.61)<br />
The output voltage is<br />
v 0 = R L i y (5.62)<br />
Summing voltages around the outside of the circuit yields the fourth equation<br />
Vi = R B i f +v 0 (5.63)<br />
Equations (5.60) through (5.63) are the set we use to find the voltage gain. Before doing algebra,<br />
we check to be sure that enough equations have been written. The variables i h i, and i must be<br />
eliminated. Since a final equation relating t> ( to v 0 must result, a total of four equations is needed,<br />
and that is exactly the number we have written.<br />
Next, we proceed to eliminate the unwanted variables. First, we can solve Equation (5.60) for i b<br />
and substitute into the other equations to obtain the set<br />
If = + h,<br />
' K<br />
V 0 = Rtfy<br />
Vi = R B if+ v o<br />
The first equation in the last set can be used to substitute for i fi resulting in the equation set<br />
v 0 = R L i y<br />
v t =Ri ^ + i 1 + v<br />
\ r * i-ly +V 0<br />
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Analog Electronics /BJT Circuits<br />
Then we solve the first equation in this set for i p substitute into the second equation and use<br />
algebra to form the ratio of v 0 and t>,<br />
v, r„(R L +R B )<br />
Next, we check to make it sure that our expression is unitless, as it should be for the voltage gain.<br />
The check is satisfied. (Recall that P is unidess and r K has the units of resistance.)<br />
Exercise 5.23 Derive the expressions for the input resistance and output resistance for the<br />
circuit of Fig. 5.25a.<br />
where R ot =<br />
R B R S + R B r n + R s r a<br />
(\ + P)R s +r„<br />
Exercise 5.24 The circuit shown in Fig. 5.26 is known as a common-base amplifier. Derive<br />
expressions for the voltage gain, input resistance and the output resistance in terms of P, r x and<br />
die resistor values.<br />
Ans. A y =p-}t)mV,yl^0.819, G=21.<br />
Exercise 5.26. Draw the small-signal equivalent circuits for the circuits shown in Fig. 5.27.<br />
vc<br />
vc<br />
(a) Common-emitter amplifier widi unbypassed emitter resistor<br />
R<br />
Ans. R i =<br />
B +RL<br />
RcRpt<br />
~r,<br />
r RQn+*B<br />
+(l + P)R L " *c + R ot<br />
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Analog Electronics /BJT Circuits<br />
5.11 The Common-Emitter Hybrid-Parameter Small-Signal Model<br />
Another small-signal model for the BJT is shown in Figure 5.28. It is based on a set of two-port<br />
circuit parameters, known as hybrid parameters.<br />
Figure 5.28 Common-emitter A-parameter small-signal equivalent circuit<br />
This equivalent circuit is completely general for small-signal conditions. Given the proper values<br />
of the four parameters, the ^-parameter model accounts for all the second-order effects in the<br />
device. (This is, however, a linear model that does not account for nonlinear effects.) If the<br />
parameters are allowed to be complex-valued functions of frequency, the model is valid for all<br />
frequencies! However, the model parameters are related to the internal device physics in complex<br />
ways, so their variation with frequency is not easy to understand. Consequendy, other models<br />
that are more easily related to the device physics are usually used for high-frequency analysis as<br />
will be seen in the following section.<br />
In tdrms of die ^-parameters, the small-signal currents and voltages are related by<br />
ne =h ie i b + Ke v ce ( 5 - 64 )<br />
i c = h fe i b+ h oe v ce ( 5 - 65 )<br />
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Analog Electronics / BJT Circuits<br />
Notice that h k has the units of resistance, b n and b^ are unitless, and h„ is a conductance.<br />
Starting from Equations (5.64) and (5.65), we can express each parameter as a partial derivative,<br />
evaluated at the operating point. For example, if we set i k — 0 in Equation (5.64) and solve for h^<br />
we have<br />
v be Avj £<br />
h ro =<br />
(5.66)<br />
v ce i b =0<br />
AV CE<br />
Thus we can find the value of h„ by making a small change in v with / fl held constant, and taking<br />
die ratio of the resulting change in P BE and p^. In other words, h„ is the partial derivative of v BE<br />
vidi respect to v^.<br />
Expressions for the other three ^-parameters similar to Equation (5.66) can be found. These<br />
expressions can be used to determine low-frequency values for the A-parameters for the static<br />
characteristics. (This is similar to the procedure we used to determine low-frequency values for<br />
the FET in the previous chapter.) It is important to understand that parameter values found from<br />
the static characteristics of a device are valid only for low-frequency operation. The<br />
characteristics do not account for capacitances.<br />
-OE<br />
Figure 5.29 The A-parameter equivalent circuit with h„ =0 and h K = 0.<br />
The parameter h n accounts for the effect of base-width modulation on the input characteristic of<br />
die device. Typically, its value is very small. Similarly, h x is a small conductance that accounts for<br />
die upward slope of the output characteristics, which is also caused by base-width modulation.<br />
As an approximation, we can set b n and h K to zero. (Since h K is a conductance, setting it to zero<br />
causes it to become an open circuit.) With these changes, the ^-parameter equivalent circuit<br />
reduces to the circuit shown in Figure 5.29. Except for different labeling of the parameters this is<br />
the same as the equivalent circuit of Figure 5.22. Thus we have<br />
K=*K (5-67)<br />
and<br />
hfoSfi (5.68)<br />
We do not intend to make much use of the complete A-parameter circuit in the design or analysis.<br />
However, data sheets sometimes contain information about the ^-parameters. We have included<br />
this discussion primarily so that you will be familiar with thes> parameters when you encounter<br />
them in the literature or on data sheets.<br />
5.12 The Hybrid-* Model<br />
A small-signal equivalent circuit for the BJT known as the hybrid-Tt is shown in Figure 5.30. This<br />
model is motivated by the internal physics of the device. It includes charge storage effects and is<br />
useful over a wide range of frequencies. The resistance r h called die base-spreading resistance,<br />
accounts for the ohmic resistance of the base region. Typically, it is small compared to r x , ranging<br />
from 10 to 100 Q for small-signal devices. Its vale is nearly independent of the operating point.<br />
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Analog Electronics /BJT Circuits<br />
The resistance r K represents the dynamic resistance of the base-emitter junction as seen from the<br />
"internal" base terminal. It is the same as the r K shown in Figure 5.22 and its value is given by<br />
Equation (5.33). The resistance r M accounts for the effects of base-width modulation on the input<br />
characteristic. In other words, r M represents feedback from the collector to the base. In this sense,<br />
it plays virtually the same role that b„ plays in the /^-parameter equivalent circuit The following<br />
approximate formula relates these parameters:<br />
Ke=—— = — ( 5 - 69 )<br />
The value of r M is very large - several megaohms is typical. For simplicity, we often replace it by<br />
an open circuit At high frequencies, this is justified even further because r M is shunted by the<br />
much lower impedance of Cf,.<br />
Figure 5.30 Hybrid-7i equivalent circuit<br />
OE<br />
The resistance r, accounts approximately for the upward slope of the output characteristics of die<br />
transistor. Thus it plays approximately the same role as h m of the ^parameter equivalent circuit.<br />
We can write<br />
r 0 =T- (5.70)<br />
"oe<br />
Sometimes, to simplify analysis, we replace r a by an open circuit<br />
The capacitance C M is the depletion capacitance of the base-collector junction. Its value depends<br />
on the dc base-collector voltage V^ and the device type. Values are often given on data sheets as<br />
Cobo or C Vt . For example, the data sheet for the 2N2222A device lists Cbo value of 8 pF for V^<br />
= -10V.<br />
Sometimes the time constant of the RC circuit between the collector and base terminals is given<br />
on the data sheet For example, the data sheet for the 2N2222A gives the value labeled as r b C f<br />
This time constant is approximately equal to r/7^. Assuming that C M is known, we can use the<br />
value given for the time constant to find r k .<br />
The capacitance C„ accounts for the diffusion base capacitance and junction capacitance of the<br />
base-emitter junction. The value of C K depends on the jg-point and the transistor type. Values<br />
typically range from 10 to 1000 pF for small-signal devices.<br />
Usually, data sheets do:not give values for C K directly. However, the transition frequency^ is<br />
often given. The transition frequency is related to hybrid-7t parameters by the approximate<br />
formula<br />
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Analog Electronics/BJT Circuits<br />
The controlled source gj> x shown in Figure 5.30 accounts for the amplification properties of the<br />
transistor. Using Equation (5.36) we can compute £, from knowledge of the j2-point (and<br />
temperature). It is easy to demonstrate diat for low frequencies and r k = 0, r M = oo and r 0 =
Analog Electronics /BJT Circuits<br />
due to the difference inj2-points. Therefore, we use^ = 300 MHz in computing a value for C^.<br />
Solving Equation (5.71) for C K and substituting values we find that<br />
P 200<br />
C * ~ 2»Sr/r -C„=-<br />
%pF = \96pF<br />
2^x520x300x10'<br />
Finally, the data sheet gives a maximum value for the collector-base time constant of 150 pF.<br />
Thus we have<br />
/fcCy = 150xlO" 12<br />
Solving for r b and substituting the value found for C M , we have<br />
/i=190<br />
Thus we have used the value published in the data sheet to find values for the parameters of the<br />
hybrid-7t equivalent circuit The circuit and values are shown in Figure 5.31.<br />
As you can see, determination of parameter values for a BJT model from the data sheet is not an<br />
exact science. Many parameter, such as E5, show large unit-to-unit variation. Since we must design<br />
circuits that work with all the devices of a given type, an exact model for a particular unit is not<br />
important. Often, we use the worst-case device specification in finding a device model. If our<br />
circuit design meets its goals with a range of device model parameters, including the worst case,<br />
we can be reasonably sure that it can be mass-produced with an acceptable rejection rate.<br />
The hybrid-7i model is useful for die analysis of single- and multistage amplifiers in a wide<br />
frequency range. Slighdy modified, it is incorporated into the PSpice program to represent the<br />
BJT properties for ac analysis.<br />
5.13 Bipolar Transistor Behavior at High Frequencies<br />
The hybrid-7l model can be used to determine the transistor behavior at high frequencies. To<br />
derive the current gain p as a function of complex frequency s, a current source I h (s) is connected<br />
between the base and emitter, and a short circuit is placed between the collector and emitter<br />
terminals, as shown in Figure 5.32. To simplify the analysis, the resistances r u and r, have been<br />
replaced by open circuits.<br />
B<br />
r b B' „ c u C<br />
Figure 5 32 7 quivalent circuit used to derive die short-circuit current gain of die bipolar transistor as a<br />
function of frequency<br />
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Analog Electronics /BJT Circuits<br />
From the K.CL applied to the collector node, we have<br />
lc(s) = gmVA')-sC M V„{s)<br />
i \ (5.74)<br />
For sufficiently low frequencies (still being in the high frequency range) the following inequality<br />
can be fulfilled: &n»sC u , and accordingly Equation (5.74) can be simplified as follows<br />
I c (s) = g m V x (s) (5.75)<br />
On die other hand, from the KVL applied to the input loop one can obtain the relationship<br />
between the base voltage and base current<br />
V x (s) = *„ „ s (5.76)<br />
where &t=1/r& Substituting Equation (5.76) into (5.75) we obtain<br />
i c (s)=— gm !i {s) „ x ( 5 - 77 )<br />
which allows us to derive expression for die short-circuit current gain<br />
Multiplying numerator and denominator of Equation (5.78) by r K and making use of Equation<br />
(5.73) we have<br />
"W-1WC.+C,) «"*><br />
where symbol /, is used to denote low-frequency value of p. Putting s = j
Analog Electronics /BJT Circuits<br />
It follows from Equation (5.82) that the magnitude of the short-circuit common-emitter current<br />
gain P decreases with frequency. This is illustrated by Figure 5.33. At f—fp the gain magnitude is<br />
lower by v 2 (or 3 dB) compared to its low-frequency value p o . This gives an interpretation to<br />
the beta cutoff frequency defined by Equation (5.80).<br />
The parameter^ as described by Equation (5.71) is the common-emitter transition frequency<br />
or unity-gain crossover frequency. In other words, f T is the frequency at which the magnitude<br />
of P is equal to unity. Putting<br />
|A/TO| =<br />
we obtain<br />
A<br />
1+<br />
v 2<br />
\fpj<br />
# = i+ V2 V 2<br />
fp) \fp \jpj<br />
= 1 (5.83)<br />
where the value oifi was assume much bigger than^g. Finally, we have<br />
(5.84)<br />
(5.85)<br />
The value oif T can be found in transistor data sheets. For example, minimum value oif T for the<br />
2N2222A transistor is specified as being equal to 300 MHz. One has to remember that in fact for<br />
a real transistor | P(/^) | is usually larger than unity, due to the current flowing from the base to<br />
collector terminals through capacitance C M , that was neglected under the assumption g m »sC fl .<br />
The parameter^- is thus used to describe the P frequency dependence for frequencies lower than<br />
f T , say foif
Analog Electronics /BJT Circuits<br />
It is easy to find in Fig. 5.23 that the dc base voltage is approximately equal to 1.8 V. Assuming<br />
I/ B£ =0.7 V, we calculate the dc emitter voltage V E - 1 V and the emitter current I E £ 1mA. For a<br />
typical, which is reasonably high, current gain f3 0 we may write<br />
and<br />
V CE =V CC -R C I C -R E I E =5AV<br />
From the transistor data book one can find at I c = 1 mA and V^ = 5 V:<br />
f T = 130 MHz, p 0 = b (e = 600, r Q = 1/A* = 25 kQ. Similarly,<br />
v C B=Vcc-Rck-Vcc-^nr= 4 - 6W -<br />
A] +K2<br />
For this value of V^ one can find from the transistor data book:<br />
C M =C C = 2.6 pF.<br />
The transconductance can be calculated from Equation (5.36) to obtain gn = 38.5 mS. This can<br />
be substituted to Equation (5.85) that can be solved for C„:<br />
Q = 8m •C M s44.5pF.<br />
2nfT<br />
Also from Equation (533) we have r„ S 15.6 kQ. The parameter r h is estimated from the<br />
collector-base time constant as r b = 25 £2.<br />
To simplify the analysis, it is reasonable to apply the Miller theorem to the circuit of Fig. 5.34.<br />
For this purpose we note that A - Vol V„ S -#nR' L - From Equation (5.87), R' L = 4.6 kfi, then A<br />
s -177. Consequendy, C m \ = 2.6x(l+177) s 462.8 pF and Cm2 = 2.6x178/177 = 2.6 pF. Now we<br />
can draw the simplified equivalent circuit for the common-emitter amplifier, where<br />
Ci = C^ + C m] = 507.3 pF, C 2 = C m2 = 2.6 pF. This circuit is shown in Fig. 5.35.<br />
Figure 5.35 Simplified equivalent circuit of the common-emitter amplifier<br />
The schematic diagram of Fig. 5.35 can be further simplified by using Thevenin's theorem to<br />
modify the input circuit, where<br />
r„ + R s +r b<br />
and is equal to 124 Q in the present example, and<br />
v' s =v r n<br />
s<br />
Rs+rb+r*<br />
The resulting final equivalent circuit is shown in Fig. 5.36.<br />
(5.88)<br />
(5.89)<br />
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Analog Electronics /BJT Circuits<br />
For the circuit of Fig. 5.36 we have<br />
Vs<br />
1<br />
V -<br />
1 + JaX'sCi (590)<br />
-y<br />
r n *<br />
**j+'&+'* 1 + 7'®/®!<br />
where ©j = l/(^Cj) s 15.9 Mrd/s, and<br />
y o =-gmV^L7-^~r- (5.91)<br />
where fi>2 = 1/(^1^2) = 83.6 Mrd/s. Combining Equations (5.90) and (5.91) we may write<br />
down the effective voltage gain of the common-emitter amplifier as:<br />
A =YjL = -Po*l> 1 !__ (5.92)<br />
^s<br />
V s R s +1% + r x 1 + joaltox l + ja)/a>2<br />
This is a transfer function of the type discussed in Section 2.6. Using Equation (2.60) and (2.61)<br />
we have<br />
2.12 MHz ,« Q)^ one can write an approximate expression<br />
/ // =® 1 /(2^) = 1/(^C 1 ) (5.94)<br />
Since the gain A in the Miller equations is proportional to the load resistance, the capacitance C,<br />
< •<br />
increases with R^ . Then the upper cut-off frequencyincreases with the Ri decrease. The largest<br />
(<br />
bandwidth is for Ri tending to zero:<br />
On the other hand, it follows from Equation (5.88) that resistance R s depends on the input<br />
signal source resistance. It decreases with R, -• 0. Finally we note that the resistance r K = I c /gn is<br />
t<br />
typically much larger than the base resistance r ¥ We conclude that in the limit of Ri -» 0 and<br />
Rs -> 0, the upper 3-dB frequency of the common-emitter amplifier is equal to the so-called<br />
transverse cutoff frequency<br />
f b = (5.96)<br />
Jb<br />
2nr b (C„+C M )<br />
This frequency determines the largest bandwiddi of a common-emitter amplifier without<br />
feedback. In the present example,_/J =135 MHz.<br />
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Analog Electronics /BJT Circuits<br />
Figure 5.37 Amplitude characteristics of the common-emitter amplifier for different load resistances<br />
With the load resistance decreasing, as the bandwidth increases, the midband gain decreases. This<br />
follows from Equation (5.92) and is illustrated by Fig. 5.37, which is a result of PSpice simulation<br />
performed for the circuit of Fig. 5.35. A summary of PSpice results is presented in Table 5.1.<br />
TABLE 5.1 MIDBAND GAIN AND UPPER 3-DB FREQUENCY<br />
OF THE COMMON-EMITTER AMPLIFIER<br />
Re kQ 5.6 1 0.1<br />
Avso v/v 175 36.7 3.8<br />
fH MHz 2.16 8.14 22.4<br />
teak -. i.e» . i«» iee» ' " v -jJ*f<br />
o ttCttVlCg*)! » wtZZJ/MHiZ) a M«2VMBS3}<br />
.:* frequency<br />
i«o> -<br />
iee»i<br />
Figure 5.38 Magnitude of common-emitter amplifier input impedance as a function of frequency<br />
To find the input impedance dependence on frequency one can use the equivalent circuit in<br />
Fig. 5.35, namely<br />
Zie=r b +:<br />
'x (5.97)<br />
\ + j6)/a)j<br />
where 0)j =\/(r 7r C\).<br />
amplifier is equal to (r^ +r n )<br />
For low frequencies, the input impedance of the common-emitter<br />
that is 15.7 kQ in our example. Zi e decreases with frequency, and<br />
-169
Analog Electronics /BJT Circuits<br />
since the break frequency depends on the Miller capacitance C u it depends also on amplifier load<br />
resistance. For high frequencies, the input impedance goes to r b . This property is sometimes used<br />
to measure the base resistance of bipolar transistors. The PSpice-simulated dependence of the<br />
magnitude of input impedance on frequency, for different load resistances is shown in Fig. 5.38.<br />
Example 5.6 The common-base amplifier of Fig. 5.26 employs a BC548C bipolar transistor. Use<br />
PSpice to compute the effective voltage gain of the amplifier at high frequencies. Assume R, =<br />
100 Q, R, = 68 kQ, R 2 = 12 kQ, RE = 1.1 kQ, Re = 5.6 kQ, R L = oo, Vcc = 12 V.<br />
Solution. Since the^-point of the transistor is the same as calculated in Example 5.5, we can use<br />
the above-obtained values of equivalent circuit elements: r n = 15.6 kQ, ^ = 38.5 mS, C K — 44.5<br />
pF, C M - 2.6 pF, r Q = 25 kQ, r h = 25 Q. The equivalent circuit of this amplifier is shown in Fig.<br />
5.39.<br />
Figure 5.39 Small-signal equivalent circuit of the common-base amplifier<br />
at medium and high frequencies<br />
A PSpice simulation was performed for the circuit of Fig. 5.39. A summary of the simulation<br />
results is presented in Table 5.2.<br />
TABLE 5.2 MIDBAND GAIN AND UPPER 3-DB FREQUENCY<br />
OF THE COMMON-BASE<br />
AMPLIFIER<br />
Re kQ 5.6 1 0.1<br />
41.5 7.7 0.78<br />
fH MHz 9.13 42.4 113.4<br />
Avso v/v<br />
Comparing the contents of Table 5.1 and 5.2, one can notice that the midband gain of the<br />
common-base amplifier is (for the same load resistance) lower than the gain of the commonemitter<br />
circuit. This is due to the fact that we compare the values of the effective voltage gain<br />
A vs =V 0 IV S that takes into account the input signal attenuation in the circuit made of R s and R,,<br />
The input resistance R, for the common-base circuit is much smaller than that of the commonemitter<br />
circuit. Indeed, in the discussed example R, = 31 Q and thus only V* of the signal<br />
amplitude excites the amplifier. On the other hand, the gain A v = V 0 I V i is the same for both<br />
amplifiers. For R^ = 5.6 kQ it is equal to 176 in Examples 5.5 and 5.6. Notice that the commonbase<br />
is a noninverting amplifier, unlike the common-emitter circuit.<br />
The bandwidth of the common-base amplifier is much larger than the bandwidth of the<br />
common-emitter amplifier. This is also seen in' Tables 5.1 and 5.2. The properties of the<br />
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Analog Electronics /BJT Circuits<br />
common-emitter and common-base circuit resemble those of the common-source and commongate<br />
amplifiers, respectively, discussed in Chapter 4. Main differences between them come from<br />
the generally lower transconductance in FETs.<br />
Example 5.7 The common-collector amplifier of Fig. 5.24 employs a BC548C bipolar transistor.<br />
Use PSpice to compute the effective voltage gain and input impedance of the amplifier at high<br />
frequencies. Assume R, = 100 Q, R, = 68 kO, R 2 = 12 kQ, R E = 1.1 kfi, R L = oo, Vcc = 12 V.<br />
Solution. The base-collector voltage V BC is larger in magnitude in this example as compared to<br />
Examples 5.5 and 5.6. To account for this difference, we have C M = 2.1 pF. The other elements<br />
take the previously determined values: r„ = 15.6 kQ, ^ = 38.5 mS, C n — 44.5 pF, r 0 = 25 kQ, r b =<br />
25 Q. The equivalent circuit of this amplifier is shown in Fig. 5.40, where it was assumed that<br />
Rs
Analog Electronics /BJT Circuits<br />
Figure 5.41 Magnitude of the input impedance of the common-collector amplifier<br />
as a function of frequency<br />
One can demonstrate by using analytical derivations applied to the circuit of Fig. 5.40 that its<br />
output impedance is inductive. Then, being very small at low frequencies, it increases in<br />
magnitude with the frequency increases. This behavior is illustrated by Fig. 5.41. Th output<br />
impedance has a small value of about 26 Q at low frequencies; however, its magnitude doubles at<br />
about 50 MHz.<br />
Exercise 5.27. Consider the amplifier shown in Figure 5.43. Both transistors are of the same,<br />
2N2222A, type. Assume Rs = 1 k«, J^ = 1.2 kQ, Re = 1.2 kQ, ^ = 10 kQ. Find device Q-<br />
points and transconductance. Draw the small-signal equivalent circuit valid for medium and high<br />
frequencies. Derive formula for the midband effective gain of this amplifier. Run .ac PSpice<br />
analysis to find the amplitude characteristic of the amplifier using the device model from<br />
EVAL.LIB library. Determine me effective gain and bandwidth of the whole cascode as well as<br />
gain and bandwidth of its Individual stages.<br />
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Analog Electronics/BJT Circuits<br />
5.14 Large-Signal Dynamic Model for the Bipolar Transistor<br />
In Section 5.4 we presented simple large-signal dc models for the BJT in the various operating<br />
regions. These models are shown in Figure 5.14 and are appropriate for analysis of dc circuits. A<br />
nonlinear large-signal model for the BJT, known as the Ebera-Moll model is shown in Figure<br />
5.44. This model is suitable for computer simulation of the transistor static behavior in all the<br />
regions of operation. The diodes D E and D c model the base-emitter and base-collector junction,<br />
respectively. In parallel with each diode is a current-controlled current source, and the controlling<br />
current is the current in the other diode. This model is valid for low-frequency signals in all four<br />
operating regions.<br />
BO<br />
apiDE<br />
ORiDC<br />
Figure 5.44 Ebers-Moll static model<br />
We have used subscripts to distinguish a F and a R . Previously, we have been concerned mainly<br />
with the forward active region, and we used the symbol a instead of a P In equation form<br />
c<br />
forward active region<br />
In a similar fashion, we have<br />
l E<br />
'C<br />
reverse active region<br />
(5.98)<br />
(5.99)<br />
-173-
Analog Electronics /BJT Circuits<br />
We have used the = sign in Equations (5.98) and (5.99) because these expressions neglect the<br />
reverse leakage currents of D B and D 0<br />
Equation (5.9) gives (3 in terms of a. We can write similar equations for fipin terms of a F and for<br />
/ R in terms of a R . Thus we have<br />
P F =-^— (5.100)<br />
\-a F<br />
and<br />
A-r£" ( 5101 )<br />
\-a R<br />
Typical values for this parameters are a = a F = 0.99, 0 = fip - 100, a R = 0.5, fi R = 1. Let us<br />
consider die physical basis for dieses parameter values, assuming an npn device. Transistors are<br />
usually designed to be operated in die forward active region. Thus the doping of die emitter is<br />
much heavier dian that of die base. Furthermore, the collector junction has a relatively large area<br />
to collect the minority carriers (electrons) diffusing dirough die base. Moreover, due to<br />
nonuniform base doping^ there is an electric field "built-in" in die base which accelerates<br />
electrons toward die collector, reduces their transit time dirough me base and dius decreases die<br />
electron loss due recombination. These features ensure that almost all of the carriers crossing die<br />
emitter-base junction are swept into the collector. Thus in the forward active region, i c = i E , and<br />
a F is close to unity.<br />
In die reverse active region, die base-collector junction is forward biased and die base-emitter<br />
junction is reverse-biased. The collector is not as heavily doped as die emitter is. Thus a<br />
significant fraction of the current crossing die collector-base junction is due to holes crossing<br />
from me base into die collector. Furthermore, the electrons mat are injected into die base region<br />
take longer to diffuse to die emitter junction. The emitter junction is smaller and it takes longer<br />
for die electrons to "find" the junction and be swept into the emitter. Consequently, more of die<br />
electrons recombine in die base. This is why i E is typically only half of i c in die reverse active<br />
region.<br />
The currents in diodes D c and D E of die Ebers-Moll model are given by the Schockley equation.<br />
Thus we have<br />
4tY<br />
»D£=/£Sexp|^-)-l (5.102)<br />
and<br />
'DC = /csexp^^|-l (5.103)<br />
The collector current and emitter current are given by<br />
i c = a F i DE -ipc (5.104)<br />
and<br />
'£ = -
Analog Electronics/BJT Circuits<br />
where 7, is known as the device scale current, firstintroduced in Equation (5.5). Since a F = 1, we can<br />
write<br />
I s = IES ( 5 - 108 )<br />
Therefore, these symbols are sometimes used interchangeably.<br />
Figure 5.45 Dynamic BJT model<br />
Base and Collector Resistance. All components in an integrated circuit are fabricated on a<br />
single piece of semiconductor material called the substrate. A consequence is that external<br />
connections to the base, emitter and collector are located at the top of the IC as shown in Fig.<br />
5.1a. The transistor in this figureis a vertical transistor because current flows vertically through the<br />
active region beneath the emitter material. Three parasitic resistances are thus important in the<br />
planar bipolar transistor. The first,the base spreading resistance r h is the ohmic resistance of the base<br />
current path from the junction to the base contact at the surface. This parameter has been<br />
accounted for in the hybrid-n model of the transistor. It is important in high-current transistors<br />
and significantly influences amplifier frequency response. Next in importance is the ohmic<br />
resistance of the collector, r c . Because N D in the collector is relatively low to reduce base width<br />
modulation, the collector region has rather high resistivity. The result is a collector resistance of<br />
the order 10 - 100 Q that may cause internal transistor saturation due to the i c r c voltage drop on<br />
it A special highly conduction buried layer helps reduce r c . Of lesser importance than the other<br />
two is r e , the ohmic resistance in the highly doped emitter material. A typical value is 1 CI. Figure<br />
5.45 shows a large-signal transistor model, which comprises the Ebers-Moll model with parasitic<br />
resistances added.<br />
Parasitic Capacitances. We know that diodes possess parasitic internal capacitances, nonlinear<br />
Q versus V relationships that are transparent to slow signals but important when rapid changes in<br />
voltage or current are imposed upon the device. Since the BJT contains two pn junctions, we<br />
expect it to have similar dynamic limitations. Associated with each junction are depletion and<br />
diffusion capacitances, which limit high frequency performance. In forward active region,<br />
depletion capacitance is dominant at the reverse-bias collector-base junction. At the forwardbiased<br />
base-emitter junction, diffusion capacitance and depletion capacitances are both<br />
important<br />
-175-
Analog Electronics /BJT Circuits<br />
The transistor depletion capacitances are exactly those we described in diode theory. Thus the<br />
parameter values in Equation (3.40) and the capacitance characteristic within the transistor<br />
depend upon the individual junction grading and geometry.<br />
The diffusion capacitance for a transistor differs slightly from that of an isolated diode because of<br />
the narrow base. For the forward active transistor, the minority charge concentration profile in<br />
the base is triangular as in Figure 5.46. This is because base width W is much smaller than the<br />
electron diffusion length, and because the electric field at the collector junction sweeps away<br />
electrons as fast as they arrive, pinning down the concentration at the collector end of the base to<br />
zero.<br />
Emitter 0 Base W Collector<br />
Figure 5.46 Excess minority charge stored in the base of a forward active npn transistor<br />
For a base-emitter junction of cross-sectional area A, we use Figure 5.46 to calculate that the<br />
quantity of minority charge stored in the base is<br />
Q FA =qA~n[Q)W (5.109)<br />
Diode theory tells us that the electron concentration at the emitter end of the base is controlled<br />
by the base-emitter junction voltage v BE<br />
where N cb is the concentrations of acceptor ions in the base material. Substituting Equation<br />
(5.110) into (5.109) gives the charge-voltage relationship that characterizes the diffusion<br />
capacitance of the forward-active transistor<br />
QFA =<br />
qAW nf<br />
-fe)<br />
(5.111)<br />
2 N ab yr T<br />
This particular collection of stored charge represents electrons in transit from emitter to<br />
collector. On the average, these injected electrons take T F seconds to traverse the base, where T F<br />
is called the forward transit time. For integrated npn transistors, the transit time is of the order<br />
of 1 ns, for integrated/>»p transistors T F = 30 ns. It can be shown that the forward transit time is<br />
related to the transition-frequency by<br />
*'-W T (5 - 1,2 ><br />
Similarly to the forward transit time, r R is the average time that a minority carrier spends in the<br />
base region for operation in the reverse active region. It can be shown that<br />
P F r F =P R r R (5.113)<br />
Figure 5.45 introduces a dynamic BJT model. We recognize it as the Ebers-Moll model of Fig. 5.44<br />
augmented by nonlinear diffusion (subscript d) and depletion (subscript J) capacitances. Each<br />
diffusion capacitance is a nonlinear Q versus V relation, which for the base-emitter diffusion<br />
capacitance takes the form of Equation (5.111). In amplifiers, these internal capacitances reduce<br />
-176-
Analog Electronics /BJT Circuits<br />
the high-frequency gain. In digital circuits, the capacitances introduce switching delays that will<br />
be considered in the following section.<br />
SPICE Parameters for the BJT. Table 5.3 lists basic parameters required to model the static<br />
and dynamic behavior of the transistor using PSpice. It includes second-order effects, such as the<br />
Early effect and ohmic resistances. As shown in the table, the parameters fall into three groups.<br />
First are the parameters that model the static characteristics of the device (IS, BF, BR, RB, RC,<br />
RE, VAF). The second group of parameters models the depletion capacitances of the two<br />
junctions (CJC, MJC, VJC, CJE, MJE, VJE). These parameters are similar to those discussed in<br />
Section 3 for/w-junction diodes. The third group of parameters (TF, TR) models charge storage<br />
in the base region.<br />
Text<br />
notation<br />
Tal Die 5.3 SPICE Model Parameters for the BJT*)<br />
SPICE Parameter name Typical<br />
notation<br />
value<br />
Default<br />
value<br />
I, IS Scale current 1E-14A 1.0E-16A<br />
A<br />
BF Forward beta 100 100<br />
A<br />
BR Reverse beta 1 1<br />
h RB Ohmic base resistance 10 Q 0<br />
r c RC Ohmic collector resistance \Cl 0<br />
r, RE Ohmic emitter resistance 0.1 Q. 0<br />
v A<br />
VAF Forward Early voltage 100 V QO<br />
CJC B-C depletion capacitance 10 pF 0<br />
TF Forward transit time 500 ps _ 0<br />
„. \- ,._<br />
TR Reverse transit time 50 ns J 0<br />
*Typical values of the parameters are shown for a discrete general-purpose device<br />
5.15 Switching Behavior of the Bipolar Junction Transistor<br />
Many transistor applications such as digital logic gates, interfacing circuits, power supplies and<br />
communication circuits use the BJT as a switch operated by a control signal. In such applications<br />
the transistor operates as a two-state device, with saturation corresponding to a closed switch.<br />
In this section we discuss briefly the switching behavior of the BJT. The primary objective of this<br />
section is to relate switching behavior to the internal device physics. Consider the simple RTL<br />
inverter shown in Figure 5.47. We use the PSpice code as listed in the Figure to analyze the<br />
circuit and generate the waveforms shown in Figure 5.48.<br />
-177-
Analog Electronics /BJT<br />
Circuits<br />
^cc= + 3V<br />
BJT switching bahaviour<br />
Vin 1 0 PWL(0 0 O.lu O O.llu 3 0.3u 3 0.31u O)<br />
KB 1 2 5K<br />
Ql 3 2 0 Q2N2222A<br />
.LIB EVAL.LIB<br />
RC 4 3 2k<br />
Vec 4 03V<br />
.TBAN lOOn lu 0 In<br />
.and<br />
Figure 5.47 RTL inverter<br />
The input voltage v iH is the 3-V pulse shown in Figure 5.48a. Initially, the input voltage is zero,<br />
and the transistor is in thecutoff region. Therefore, the base current is 2ero, the collector current<br />
is zero and the output voltage v t is 3 V.<br />
During the time interval from / = 0.10 )j.s to / = 0.11 |4.s, v- m rises rapidly to 3 V. The immediate<br />
effect is to cause i B to increase rapidly. This is shown in Figure 5.48b. The current that flows into<br />
-178-
Analog Electronics /BIT Circuits<br />
the base charges die B-E junction depletion capacitance and dius raises the base-to-emitter<br />
voltage.<br />
Part of the base current flows through the collector junction capadtance and out die collector<br />
lead (opposite to the usual current direction for an npn transistor in die active region, see Figure<br />
5.38b). This current causes die output voltage to increase. Notice diat die output voltage actually<br />
goes slighdy higher dian die supply voltage (which is 3 V).<br />
Shortly after the beginning of die input pulse, tine base voltage rises high enough to forward bias<br />
die emitter junction. Then electrons cross from the emitter into the base. These electrons diffuse<br />
into me collector junction. Thus conventional current begins to flow into the collector, and die<br />
collector voltage v, starts to drop. At about / = 0.19 ps, die transistor enters the saturation region<br />
(P's > 'o c f- Figure 5.48b). Then die collector voltage becomes approximately constant at a few<br />
tendi of a volt.<br />
The input switches back to zero during the time interval from / = 0.30 u.s to / = 0.31 us.<br />
However, die output voltage remains low until approximately / = 0.52 u.s. The reason for diat is<br />
die excess minority carriers (electrons) stored in die base region. When the transistor is driven<br />
into saturation, bodi junctions are forward biased. Thus a large concentration of electrons builds<br />
up in die base. Until diese electrons have been removed from the base, forward, current<br />
continues to flow across die junctions. Notice that the base current actually reverses directions at<br />
die end of die input pulse. This is due to stored charge flowing out of the base terminal.<br />
At about / = 0.52 p.s, most of die excess charge in the base has been removed and die collector<br />
current begins to fall as shown in Figure 5.48b, causing die output voltage to rise (Figure 5.48a).<br />
However, die output voltage rises gradually because of die junction capacitances. The transistor<br />
returns to die cutoff state at / > lu.s.<br />
The circuit of Figure 5.47 acts as a logic inverter. When die input is low, die output eventually<br />
becomes high. Similarly, when the input is high, the output eventually becomes low. Because of<br />
the charge storage effects, changes in the output do not occur immediately when die input<br />
changes. Of course, in most applications it is desirable for the switching delays to be as short as<br />
possible Several aspects of die device construction influence the switching speed. For example,<br />
reducing junction areas can reduce die device capadtances. Doping levels and junction grading<br />
also affect junction capadtances. A tiunner base region leads to quicker diffusion of minority<br />
charge carriers out of die base region. Selected impurities can be used to reduce die minority<br />
carrier lifetime.<br />
Often, BJT data sheets give specifications for switching time intervals for test circuits similar to<br />
die RTL inverter. We define die start of a logic transition as die point at which 10% of die<br />
voltage change has occurred. For example, the start of die leading edge of the 3-V input pulse is<br />
die point at which die input pulse reaches 0.3 V. Similady, die start of the leading edge of die<br />
output pulse is die point at which % has fallen to 2.7 V. These start points are labeled in Fig. 5.49.<br />
Similady, we define die end of a logic transition as die point for which 90% of the voltage<br />
(current) change has occurred.<br />
-179-
Analog Electronics /BJT Circuits<br />
4.6U-T ,<br />
2.8U.<br />
Start of leading edge of Vo<br />
•ts-<br />
•»-N<br />
if<br />
A<br />
2.7V<br />
/ End of<br />
/ trailing<br />
/ edge of Vo<br />
End of<br />
leading edge of Vo /<br />
z=*<br />
0.3V<br />
[Start of leading edge of Vin<br />
— i — - -<br />
h<br />
200ns<br />
400ns<br />
au(l) ou(3)<br />
Tine<br />
r -1 " "I<br />
660ns<br />
Figure~5.49 Waveforms illustrating turn-on and turn-off rimes<br />
Data sheets for BJTs intended for switching applications often specify the following switching<br />
intervals:<br />
• t d is the delay time measured from start of the input leading edge to the start of the output<br />
leading edge.<br />
• t r is the rise time, measured from the start point to the end point of the leading edge of the<br />
output pulse. Notice that the rise time is defined for the leading edge of the output pulse even<br />
though this is the negative-going edge.<br />
• /, is the storage time, measured from the start point on the trailing edge of the input pulse to<br />
the start point on the trailing edge of the output pulse.<br />
• ^is the fall time measured between the start and end points of the trailing edge of the output<br />
pulse.<br />
Turn-on and turn-off times, respectively t on =t d +t r and t 0 ff = f, +/y, are given on transistors<br />
data sheets. Typically, the switching times are much longer for power transistors than for smallsignal<br />
devices. This is due to larger junction capacitances and charge stored in a larger volume of<br />
the base region.<br />
C s =20pF<br />
Vaf*W<br />
Schottky-claapad RTL invartar<br />
Vin 1 0 FML(0 0 O.lu 0 O.llu 3 0.3u 3 0.31u 0)<br />
RB 1 2 5K<br />
Ca 1 2 20pF<br />
Ql 3 2 0 Q2N2222A<br />
Dl 2 3 DSH<br />
.MODIL DSH D(I«-l«-8 CJO-2pF VJ-0.6 M-0.5<br />
.LIB EVAL.LIB<br />
A (v 2N2222A RC 4 3 2k<br />
^ L Vcc 4 03V<br />
.TRAM O.lu lu 0 In<br />
. «nd<br />
Figure 5.50 RTL inverter with speed-up capacitor and Schottky clamp diode<br />
TT-0)<br />
-180-
Analog Electronics / BIT Circuits<br />
Techniques for speeding-up the transitions of the RTL inverter are of much interest in many<br />
applications. Two such techniques are illustrated in Figure 5.50. First, a speed-up capacitor has<br />
been added in parallel with die base resistor Rj. Second, a Schottky clamp diode has been<br />
added between the base and the collector terminal. Figure 5.51 shows waveforms generated by<br />
the PSpice program shown in Figure 5.50.<br />
*.4n<br />
fine<br />
«.tes<br />
Figure 5.51 Voltage waveforms for the Schottky-clamped RTL inverter<br />
Notice that die switching times for diis circuit are much smaller than for the simple RTL inverter<br />
of Figure 5.37. The speed-up capacitor couples the leading edge of the input pulse to the base.<br />
The voltage across the capacitor cannot change instantaneously. Thus the rapid increase in the<br />
input pulse causes a rapid increase in v BE . Thus the transistor is forced to turn on very quickly.<br />
Moreover, without the speed-up capacitor, the junction capacitances must be charged through<br />
Rg, and v BE rises more gradually.<br />
The Schottky diode prevents the transistor from entering the saturation region. When the<br />
collector voltage reaches approximately 0.4 V, the diode conducts and reduces the portion of the<br />
base current available to the transistor. Thus the output voltage is not allowed to fall below 0.4V<br />
and the transistor remains in the active region. This greatly reduces the concentration of electrons<br />
in the base region.<br />
The important point for the circuit designer is that if fast switching is important, the circuit should be<br />
designed so that the transistors do not enter saturation.<br />
5.16 Summary<br />
The bipolar junction transistor is a solid-state device consisting of two pn junctions fabricated in<br />
close proximity on single-crystal semiconductor. A large-signal, static, nonlinear Ebers-Moll<br />
model, embodied in an equivalent circuit and a pair of corresponding simultaneous equations,<br />
help us understand the transistor in terms of the theory of pn junctions. For small-signal linear<br />
applications, we use external dc sources to bias the transistor in its forward active state. For this<br />
state, the Ebers-Moll predicts the characteristic curves and linear equations of a currentcontrolled<br />
current source. This leads to a simple linear equivalent circuit that we use to predict<br />
how die transistor interacts with other circuit elements. To do the ac circuit analysis we replace<br />
me transistor with its equivalent circuit. Parameters of this circuit depend on the device jg-point<br />
that results from the particular bias. The BJT has two other states of major importance:<br />
saturation, in which the transistor resembles a closed switch, and cut-off, where the transistor<br />
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Analog Electronics / BJT Circuits<br />
represents an open switch. The third state, inverse active, is of little practical importance. Each of<br />
die four states corresponds to operation in a particular region of the transistor output<br />
characteristics, and each has a circuit model, related in an obvious way to the characteristic<br />
curves. For amplifier applications the BJT is operated in the active state. Switching applications<br />
make use of the cut-off and saturation states. A BJT operating in the active state provides a<br />
collector current ic = isexp(J v BE \ /F T ). The base current is i B = ; c /p, and the emitter current i E =<br />
i c + i B . Also, i c = ai E and thus P=a/(l-a) and 50 V. For i E = 0, the breakdown voltage is less than<br />
BVCM- In the common-emitter configuration the breakdown voltage specified is BV^g, which is<br />
about half BV CBO . The emitter-base junction breaks down at the reverse bias of 6-8 V. There are<br />
also dynamic transistor limitations embodied in the depletion and diffusion capacitances of the<br />
junctions and between the collector and the substrate. Except for minor differences they are the<br />
same nonlinear capacitances we encounter in diodes. SPICE transistor models enable us to<br />
simulate both static and dynamic behavior of transistors, including all of the major nonlinearities.<br />
We generally use our simplified and more intuitive transistor concept to design, and then follow<br />
up with accurate computer simulations that include the second-order effects we consciously<br />
ignored to make our initial design work tractable. We examine and evaluate the simulation results<br />
in terms of our simple conceptual ideas and then redesign, if necessary. The dc analysis of<br />
transistor amplifiers is gready simplified by assuming diat | V BE \ = 0.7 V. To operate as a linear<br />
amplifier, the BJT is biased in the active region and the signal v h is kept small (v k « K T ). Bias<br />
design seeks to establish a dc collector current that is as independent of the value of p as<br />
possible. For small signals, the BJT functions as a linear voltage-controlled current source with a<br />
transconductance &n - IJ Vv Th e inp ut resistance between base and emitter, looking into the<br />
base is r„ = P/#n. For a common-emitter configuration, a high voltage gain and reasonable input<br />
impedance are obtained, but the high-frequency response is limited. Including an unbypassed<br />
resistance in the emitter lead can increase the input resistance of a common-emitter amplifier. In<br />
the common-base configuration, a high voltage gain (from emitter to collector) and an excellent<br />
high-frequency response can be obtained, but the input resistance is low. The CB amplifier is<br />
useful as a current buffer. In the emitter follower (common-collector amplifier) the voltage gain<br />
is less than unity, the input resistance is very high, and the output resistance is very low. The<br />
circuit is useful as a voltage buffer.<br />
-182-
Analog Electronics / Feedback Circuits<br />
6 Feedback Circuits<br />
Feedback consists of returning part of the output of a circuit or system to its input In an<br />
amplifier with negative feedback, a portion of the output signal is returned in opposition to the<br />
original input signal. In positive feedback, the feedback signal aids the original input Usually, in<br />
amplifiers, negative feedback is more useful than the positive feedback. However, the positive<br />
feedback is useful in the design of oscillators, which are considered later. The advantages of<br />
adding a negative feedback to an amplifier are<br />
• reduced sensitivity to parameter variations<br />
• increased bandwidth<br />
• reduced nonlinear distortion<br />
• improved input and output resistances<br />
One disadvantage is the reduction of gain; however, gain is easy to obtain with modern circuits,<br />
so this is a small price to pay. The other disadvantage, a possibility of unwanted oscillations or<br />
instability, is more serious, for oscillations make the circuit worthless as an amplifier.<br />
Fig. 6.1 shows the general structure of & feedback amplifier. A nonfeedback amplifier with gain A<br />
(the A circuit) delivers an output signal x, = Ax, to an external load. Instead of using signal x, as<br />
the amplifier input, a feedback circuit (p circuit) produces a feedback signal x f = fix, to form the<br />
actual input x> The feedback factor, P, used extensively in this chapter is unrelated to the bipolar transistor beta.<br />
Figure 6.1 Feedback amplifier structure<br />
Feedback theory applies to all four amplifier types named in Chapter 2.1,-but each type implies a<br />
different interpretation of Fig. 6.1. For a voltage amplifier, A denotes voltage gain and x e and x,<br />
are voltages. The external source must be a voltage source x s (ideally having zero internal<br />
resistance) and there is a voltage subtraction at the input. The feedback factor P = x/x. is a<br />
voltage gain (or attenuation) in this case.<br />
For a current amplifier, A denotes current gain. The input comes from a source of current x s<br />
(ideally having infinite internal resistance) and the current subtraction is required at the input.<br />
The p denotes the current gain of the feedback circuits.<br />
In a transconductance amplifier, A is transconductance gain with dimensions of amperes/volt.<br />
Thus output x, is a current and the source x t is the voltage source; the subtraction at the input is<br />
the voltage subtraction. For this case, P has a dimension of volts/ampere, or transresistance.<br />
Finally, the transresistance amplifier has transresistance gain with dimensions of volts/ampere.<br />
Thus output x c is a voltage and the external input source is the current source. The subtraction is<br />
a current subtraction. For this case, p has a dimension of transconductance.<br />
From Fig. 6.1 one can write<br />
-183-
Analog Electronics / Feedback Circuits<br />
x 0 = Axi = A(x s -x/) = A(x s - p* 0 )<br />
Solving for the gain of the feedback amplifier, Aj- = x 0 I x s , gives<br />
which applies to all four amplifier classes.<br />
Reduction of Gain. For midrange frequencies, both A and p are real quantities having the same<br />
algebraic sign. Equation (6.1) shows one of the prices we pay for negative feedback, a gain<br />
reduction. For example, suppose A~\W and the fraction of x, that is fed back to the input is<br />
P=0.01. Then the resulting feedback amplifier has gain of only<br />
10000 nn<br />
Usually, as in this illustration, ^4P»1, and (6.1) gives an important approximation<br />
A f =- (6-2)<br />
P<br />
For a voltage amplifier, common practice is to obtain P from a resistor network of lowtemperature<br />
coefficient, such as from a voltage divider, giving<br />
_ 1 R x +R 2 . %<br />
In an IC realization, such a P is easily controlled to within 1% or so by masking tolerances, and<br />
the temperature variations cancel over a wide temperature range. Thus Afis quite constant, even<br />
though A might vary greatly with temperature or other factors.<br />
Improvement Factor. The denominator of (6.1), 1+^P, is of considerable importance in<br />
feedback theory. This factor by which the gain is reduced also turns out to be the degree of<br />
improvement effected by introducing feedback. Ideally, parameter sensitivity, distortion,<br />
bandwidth, input resistance and output resistance all improve by \+A$ when one adds feedback.<br />
Thus the quantity is referred to as the improvement factor.<br />
6.1 Effects on Sensitivity, Bandwidth and Distortion<br />
We will first develop an intuitive notion of how the feedback works. Suppose in Fig. 6.1, while<br />
the input x t is held constant, output x, decreases in amplitude for any reason. Being proportional<br />
to *•„ feedback signal xyalso decreases, thereby increasing x ; to compensate, at least partially, for<br />
the original change. A complementary scenario opposes increases in x,. Thus negative feedback<br />
opposes any change in x, caused by an event unrelated to x> If the cause is variation in an<br />
internal parameter/), we say that feedback has reduced the sensitivity. If it is loss of gain at either<br />
low or high frequencies because of amplifier capacitances, we say feedback has improved the<br />
frequency response. If x, changes in a manner not proportional to x s because of nonlinearities<br />
within the amplifier, we say feedback has reduced distortion. We now examine the details to<br />
obtain a more quantitative understanding to use in analysis and design.<br />
6.1.1 Effect of Feedback on Sensitivity<br />
If the sensitivity of gain A to parameter/) is Sff, adding negative feedback results in an amplifier<br />
of gain Aj with lower sensitivity; specifically,<br />
-184-
Analog Electronics /Feedback Circuits<br />
To prove this, we need only use the definition<br />
s*f _ P M f _ P d[AI{\ + AP)}<br />
p<br />
Af dp Af dp<br />
Since the circuits we design employ feedback p that is independent of p, the derivative gives<br />
A f<br />
(1 + AP){dA I dp) - AfiidA I dp)<br />
(1 + A0) 2 P<br />
A f<br />
A/3 dA<br />
(1 + AP) (i + AJJ) 2 J dp<br />
Substituting for A, from (6.1) gives an equation that is equivalent to (6.3).<br />
Exercise 6.1 A nonfeedback amplifier with A = 347 contains a critical resistor R. By laboratory<br />
measurements we determine that SR =1.12. After adding negative feedback to reduce the<br />
sensitivity, we find the amplifier gain is 24. Find the gain sensitivity of the feedback amplifier to<br />
changes in K Ans. 0.077.<br />
Example 6.1 We have an amplifier with a gain of 800. Sensitivity of gain to temperature change<br />
is 0.1; however, our specification requires temperature sensitivity to be no more than 0.001.<br />
Investigate the possibility of using negative feedback to bring the temperature sensitivity within<br />
specification.<br />
Solution. From (6.3), we need an improvement factor of<br />
Since A = 800, P must satisfy<br />
1 + 800^=100<br />
or P = 0.124. The resulting feedback amplifier meets the temperature-sensitivity specification;<br />
however, its gain is only 800/100 = 8. +<br />
Sensitivity of Cascaded Feedback Amplifiers. Example 6.1 shows that we can improve<br />
sensitivity by sacrificing gain. Because specifications often involve both gain and sensitivity, it is<br />
interestirg to see if we can come out ahead by using a cascade'of low-gain, low-sensitivity<br />
feedback amplifiers.<br />
Consider a cascade of n feedback amplifiers, each of gain Af. We denote the overall gain by G =<br />
(A)", and now need to find the sensitivity of G to parameter/). By definition,<br />
SG EdG p ,dAf_<br />
p<br />
G dp G v J' dp<br />
Substituting G = (A)* gives<br />
cG P „,, sn-ldA* m P dA f<br />
Sp^niA/) -d7 =n^Hp-<br />
We conclude that<br />
Sf=nSp<br />
which shows that sensitivity increases only in proportion to n as we cascade stages, whereas G<br />
varies as die »-th power of gain. This suggests that we should be able to be better off using<br />
feedback. Table 6.1 illustrates the point using numbers from Example 6.1. Cascading feedback<br />
amplifiers is obviously an effective strategy.<br />
-185-
Analog Electronics / Feedback Circuits<br />
TABLE 6.1 GAIN AND SENSITIVITY OF CASCADED FEEDBACK AMPLIFIERS<br />
6.1.2 Effect of Feedback on Bandwidth<br />
n G<br />
^P<br />
1 ' 8 0.001<br />
2 64 0.002<br />
3 512 0.003<br />
4 4096 0.004<br />
Upper Half-Power Frequency. Consider using feedback to increase the bandwidth of an<br />
amplifier described by<br />
A = A(co) = A 0 , *" (6.4)<br />
where A e is the midband gain. Substituting this expression into (6.1) gives<br />
a> H /(ja) + a> H )<br />
Af<br />
or<br />
— A t<br />
f °l + A 0 [a> H /(j6> + o> H )y3<br />
= 4<br />
A f = A of<br />
where<br />
° ja> + H p<br />
+ a, H (\ + A o P)\ + A o 0<br />
a>Hf<br />
(6.5)<br />
J6) + a> Hf<br />
A n t =<br />
of = l + A B<br />
and<br />
a W = aH ® + A °®'<br />
Comparing (6.5) and (6.4) one can see that the feedback amplifier's gain function has the same<br />
general form as the original; however, its upper half-power frequency is higher by (l+A$) and its<br />
midrange gain is lower by the same factor. Figure 6.2a compares the two frequency response<br />
curves. Notice the original and final gain-bandwidth products, Afi) H and A^Q) H j. We see that the<br />
gain-bandwidth product is preserved when one adds feedback. We conclude that for a one-pole<br />
amplifier described by (6.4), negative feedback facilitates a direct trade-off of gain for bandwidth<br />
as in Fig. 6.2a. Amplifiers with more complex gain functions do not give an exact trade-off;<br />
however one can expect a dominant high-frequency pole to approximate such a trade-off.<br />
Gain (dB)<br />
Gain (dB)<br />
Analog Electronics / Feedback Circuits<br />
Lower Half-Power Frequency. Consider a nonfeedback amplifier described by<br />
id)<br />
A = A(a>) = A 0 / (6.6)<br />
Substituting into (6.1) gives<br />
A =A ja>l(J(Q + a>L)<br />
f °\ + A o [ja>/U L )]fi<br />
Algebraic manipulations similar to those for the high frequency case lead to<br />
id)<br />
A f = A of -H (6.7)<br />
J<br />
° J ja) + 80, f L < 50 Hz,<br />
f H > 15 kHz, and sensitivity to power supply changes < 0.2. We have an amplifier with gain =<br />
1000,^ = 400 Hz,f H — 9 kHz and its sensitivity to changes in supply voltage is 1.5. Determine<br />
whether we can meet the specifications by adding feedback to the existing amplifier. If so, find an<br />
acceptal e value of P and give final specifications for the feedback amplifier.<br />
Solution. Assume that a pair of dominant poles characterizes the frequency response.<br />
Considering each specification individually gives the following requirements:<br />
1000<br />
gain: -—,^,,^80<br />
6<br />
1 +1000^<br />
400<br />
lower -3 dB frequency:<br />
M }<br />
-—, nnn •- < 50/fe<br />
1 + 1000/<br />
upper -3 dB frequency: 9000(1 + 1000/ff) £ 15000/fe<br />
sensitivity: -—.„„„„ ^ 0.2<br />
y<br />
1 + 1000^<br />
These lead, respectively, to the requirements l+10 3 p < 12.5, 1+HPP > 8, l+10 3 p > 1.67, and<br />
1+10 3 P > 7.5. Sorting out these inequalities shows that any P that satisfies 8 < 1+10^ < 12.5 is<br />
acceptable. To leave room for error, choose 1+10 3 P = 10, which requires P = 0.009. Then the<br />
final amplifier will have gain = 100,^ = 40 Hz,^ = 90 kHz and supply sensitivity of 0.15, all<br />
within specifications.<br />
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Analog Electronics / Feedback Circuits<br />
6.1.3 Effect of Feedback on Nonlinear Distortion<br />
Nonlinear distortion is normally not a problem in the small-signal amplifiers. However, in power<br />
amplifiers, output signal must be large enough to develop a specified amount of power in the<br />
load. This often requires signal swings large enough to traverse a significant portion of the<br />
amplifier's nonlinear transfer characteristic. When this occurs, the output signal is the amplified<br />
input signal, plus additive harmonic distortion components that arise within the amplifier itself.<br />
Amazingly, negative feedback can be used to feed these distortion components back into the<br />
input in such a way that they subtract from themselves. The feedback also causes some signal to<br />
subtract from itself; however, this is the gain reduction we expect with negative feedback, and we<br />
can compensate for it by adding a preamplifier. The bottom line is that negative feedback reduces<br />
internally generated distortions by (\+A$). The following quasi-numerical development shows<br />
how it works.<br />
XJ(0=0.001COS(
Analog Electronics / Feedback Circuits<br />
x o (t) = d(t) + A[x s (t)-0 Xo (t)]<br />
or<br />
d(t)<br />
\ + A0 \ + A0 MO sy<br />
Using P = 0.01, as an example, gives<br />
x 0 (0 = 0.0099 COS(GJT) + 99x s (r) (6.8)<br />
showing that distortion is reduced to 1 % of its former value. Notice, however, that the new<br />
input xj(t} is multiplied by only 99 in (6.8) instead of the original 10 4 . Because specifications<br />
require 10cos(©i) at the output, from Eq. (6.8) the input to the feedback amplifier must satisfy<br />
99x s (0 = 10cos(fi#)<br />
or x,= 0.101cos(©/), showing that the feedback amplifier requires a larger input voltage that the<br />
nonfeedback amplifier for the same output (The corresponding transfer characteristic of the<br />
feedback amplifier, x, versus x„ is much more linear than the original curve, but has lower slope.)<br />
Since only 0.001cos(©/) is available for us for our io^ut signal, we must add a preamplifier of gain<br />
Ap at the input that satisfies<br />
0.001^=0.101<br />
or<br />
4, = 101.<br />
Figure 6.3c summarizes the design, both in general notation and in the numerical values used as<br />
examples. For this strategy to succeed, we must construct a preamplifier that does not produce<br />
distortion. The key observation is that the signal amplitude required at the preamplifier output is<br />
much smaller than the specified amplifier output voltage. That is, it is much easier to produce a<br />
distortion-free output voltage of 0.101 V than 10 V.<br />
Vcc = +15V<br />
V<br />
K £ £ = -15V<br />
Figure 6.4 Nonlinear class-B power amplifier<br />
Example 6.3: Crossover distortion. Distortion is mainly a problem in power amplifiers. A<br />
simplified example of an audio-amplifier output stage is shown in Fig. 6.4. Notice that if v s = 0,<br />
both transistors are in cutoff since there is no forward bias of the base-emitter junctions. In fact,<br />
neither transistor conducts until v, swings outside the range from -0.6 V to 0.6 V (for typical<br />
silicon power transistors). With both transistors cut off, the output voltage is zero. As v, swings<br />
higher than 0.6 V, the npn transistor J2, turns on and supplies current to the load. In this case the<br />
output voltage is given by, approximately,<br />
v 0 = v 5 - 0.6 for v s > 0.6<br />
If v s is less than -0.6 V, the npn is off and the pnp transistor Q^ is in the active region. Then we<br />
have<br />
v 0 =v s + 0.6 for v,
Analog Electronics / Feedback Circuits<br />
The transfer characteristic for the amplifier is shown in Fig. 6.5. Notice the nonlinearity in the<br />
region around v t = 0. This nonlinearity causes ctossover distortion when conduction is changing<br />
from one transistor to the other. Also, notice that the voltage gain, which is the slope of the<br />
transfer characteristic, is approximately unity (except in the region around zero input).<br />
5.W<br />
-S.W +<br />
-6.W<br />
-4.MI<br />
Figure 6.5 Transfer characteristic for the amplifier of Fig. 6.4<br />
This circuit is an example of a class B amplifier, in which each device conducts for<br />
approximately half of the signal cycle. Figure 6.6 shows the class B output stage driven by a<br />
differential amplifier that has a differential gain of 1000. The feedback network consisting of R,<br />
and R 2 returns part of the output voltage to the inverting input of the differential amplifier.<br />
Normally the switch would be in position JB, so the output voltage across the load is fed back.<br />
However, we will also analyze the circuit with the switch in position A to illustrate the crossover<br />
distortion of the output stage.<br />
The feedback ratio P is given by<br />
V *2<br />
P =<br />
Ri +R-, = 0.1<br />
"o -4 ••• A 2<br />
Since the gain of the differential amplifier is 1000 and the gain of the class B stage is<br />
approximately unity, the overall open-loop gain isA= 1000. Thus we have A$ = 100, which is<br />
much larger than unity. Consequendy, we expect to 6ndA/= 1/P = 10.<br />
RL=&n<br />
00<br />
F££=-15V<br />
-190-
Analog Electronics /Feedback Circuits<br />
Figure 6.6 Class B power amplifier with feedback:<br />
(a) circuit diagram, (b) model for die differential amplifier<br />
The differential amplifier provides the means for subtracting the feedback signal v } from the<br />
source voltage. We use the circuit model for the differential amplifier shown in Fig. 6.6b. The<br />
SPICE program to analyze the circuit is listed below.<br />
Class B Feedback Example<br />
Vs 1 0 sin(0 0.2 1000)<br />
82 4 0 Ik<br />
Rl 2 4 9k; change first node to 3 for switch at B<br />
EA 2 0 1 4 1000; voltage-controlled voltage source<br />
Rin 1 4 1MEG<br />
Ql 5 2 3 npnpower<br />
Q2 6 2 3 pnppower<br />
RL 3 0 8.0<br />
Vcc 5 0 15V<br />
Vee 6 0 -15V<br />
.model npnpower npn(bf=150 Is=le-12)<br />
.model pnppower pnp(bf=150 Is=le-12)<br />
.tran lOOus 2ms 0 5us<br />
.end<br />
After executing this program, we request plots of the drive voltage V(2) at the bases of J2, and Q 2<br />
as well as the output voltage v t — V(3). The result is shown in Fig. 6.7a. In this case, the switch is<br />
in position A, so the nonlinearity of the output stage is not included in the feedback loop. The<br />
output signal waveform thus deviates from an ideal, distortion-free shape and, consequendy, a<br />
significant distortion signal d(t) is a part of the output, as is also shown in Fig. 6.7a. The base<br />
drive is sinusoidal, but the output demonstrates considerable crossover distortion.<br />
-191-
Analog Electronics / Feedback Circuits<br />
Tlaa<br />
(b) Waveforms for the switch in position B<br />
Figure 6.7 Waveforms for the circuit of Fig. 6.6<br />
Then we change the program to place the switch in position B, obtaining the results shown in<br />
Fig. 6.7b. In this case the output voltage is almost free of distortion, d{t) = 0. Notice that the base<br />
drive voltage V(2) has been predistorted to compensate for the nonlinearity of the output stage.<br />
Also notice that, as expected, the output voltage is Aj = 10 times larger that the source voltage<br />
signal.<br />
Exercise 6.3 Suppose that we need to change the amplifier of Fig. 6.6, so that the gain Aj is<br />
approximately 20. What changes do you suggest Include component values.<br />
Exercise 6.4 Change the resistor values in Fig. 6.6 to R 2 = lOfi and R, = 9990Q. What is the<br />
approximate value of A$ Use a Spice program to find the output waveform for the switch in<br />
position B and v s — 0.004sin(2000rc/). Is the feedback effective in reducing distortion in this case<br />
Explain.<br />
6.1.4 Effect of Feedback on Noise<br />
An undesirable aspect of amplifiers is that they add unwanted noise to the desired signal. Sources<br />
of this noise include power-supply hum, coupling of signals from other circuits, and thermally<br />
generated noise in resistors. Another noise is shot noise caused because current flow is not<br />
continuous; instead, charge is carried in discrete quantities by individual electrons. Still another<br />
source is microphone noise, which is an electrical signal arising from vibration of circuit<br />
mechanical components.<br />
Some source of noise can, in principle, be eliminated. For example, power-supply hum can be<br />
reduced by additional filter circuitry in the power supply. However, some of the noise sources,<br />
such as thermal and shot noise, stem from the basic natural processes and cannot be totally<br />
eliminated. Thus all amplifiers add noise, but some amplifiers are much worse than others are. In<br />
this section we wish to show that feedback can, under certain circumstances, reduce noise.<br />
If d(t) introduced in Section 6.2.3 represents noise arising within the nonfeedback amplifier,<br />
negative feedback reduces output noise just as it reduces distortion; however, it can be shown<br />
that adding negative feedback results in no improvement in the input signal-to-noise-ratio of an<br />
amplifier. Since this ratio is usually the critical factor, adding negative feedback is not a generally<br />
effective noise reduction strategy.<br />
-192-
Analog Electronics / Feedback Circuits<br />
Figure 6.8 Model that accounts for the addition of noise in amplifiers<br />
The additive noise can be modeled as shown in Fig. 6.8. The amplifier gain is denoted as A,. To<br />
quantify noise performance, engineers use the signal-to-noise tatio, which is the desired signal<br />
power delivered to the load divided by the noise power. We denote the rms values of the signal<br />
and noise by X, and X,. The rms signal delivered to the load in Fig. 6.8 is A,X S and the rms noise<br />
is A,X M . If the signals are voltages, the powers delivered to the load are<br />
Ps =<br />
and<br />
(<br />
Ps = (Ax ny<br />
^ (6.9)<br />
R,<br />
The signal-to-noise ratio is given by<br />
(6.10)<br />
Equation (6.11) also applies if X s and X, are currents.]<br />
(6.11)<br />
Figure 6.8 Model that accounts for the addition of noise-in amplifiers<br />
Now consider the feedback amplifier shown in Figure 6.9. X, is the rms noise of amplifier A,.<br />
Amplifier A 2 has been added to increase the open-loop gain of the amplifier. Amplifier A 2 is<br />
assumed to be noise-free. This is a reasonable assumption if we have a situation in which<br />
amplifier A, is very noisy and amplifier A 2 is well designed, so its noise is very small. For<br />
example, A, can be a very high power amplifier with a great deal of power-supply hum, but A 2 is<br />
supplied with a well-filtered power. (Perhaps the designer is trying to be economical by using less<br />
filtering for the power to amplifier^!,.)<br />
We analyze the system shown in Figure 6.9 to find an expression for the signal-to-noise ratio. We<br />
can write<br />
x 2 {t) = x s {t)-px 0 {t) (6.12)<br />
x l (t) = A 2 x 2 (t) + x n (t) (6.13)<br />
x 0 (t) = A lXl (t) (6.14)<br />
Substitution of Equation (6.12) into (6.13) and the result into (6.14) results in<br />
x 0 {t) = A x {A 2 [x s (t) - Px 0 {t)\ + x n {t)} (6.15)<br />
Solving for x,[t), we find that<br />
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Analog Electronics / Feedback Circuits<br />
*»
Analog Electronics /Feedback Circuits<br />
The units of p are the inverse of the units of the gain for each type of feedback. Refer to Figure<br />
6.9b, as an example. Notice that the units of the transconductance gain G m are Siemens. Also, we<br />
see that Vf=$i c . Therefore, p is a transresistance parameter with units of ohms.<br />
Similarly, for parallel voltage feedback, the gain parameter is a transresistance, and the feedback<br />
ratio p is a transconductance. For series voltage feedback A = A r which is unidess, and P is also<br />
unidess. Finally, for parallel current feedback, A = A t and P are both unitless.<br />
The effect of each type of feedback on input and output impedance of an amplifier is different.<br />
In design, we select the type of feedback in accordance with the design objectives.<br />
(b) Series current feedback<br />
(c) Parallel voltage feedback<br />
(d) Parallel current feedback<br />
Figure 6.9 Types of feedback<br />
-195-
Analog Electronics / Feedback Circuits<br />
6.3 Effect of Feedback Types on Input and Output Impedance<br />
Now we examine the effect of series feedback on input impedance. The model for our discussion<br />
is shown in Figure 6.10. The output signal x, is sampled by the feedback network, which<br />
produces a feedback voltage signal v f = fix, connected in series with the source and the input<br />
terminals of the amplifier. The original (before the feedback is added) input impedance of the<br />
amplifier is R,. The input impedance of the amplifier with feedback is<br />
%=7" (6-18)<br />
Writing a voltage equation around the loop in Figure 6.10, we obtain<br />
v, = *,-/, + v f (6.19)<br />
But «y=P^ so we have<br />
v s = R,i s +0K o (6.20)<br />
Also, the input voltage is given by<br />
Vi = Rii s (6.21)<br />
and the output is given by<br />
x 0 = Av t (6.22)<br />
where A=A r is a voltage gain if x,=v„ or A—G m is a transconductance gain if die output is a<br />
current x=i,. Substituting Equation (6.21) into (6.22) and the result into (6.20), we obtain<br />
v^Riis + A/SR^ (6.23)<br />
which can be solved for the input impedance with feedback<br />
R if =f = R i (l + Afi) (6.24)<br />
Recall that for negative feedback the factor (\+A$)<br />
feedback increases input impedance.<br />
is larger than unity. Thus negative series<br />
Load<br />
Figure 6.10 Model for analysis of the effect of series feedback on input impedance<br />
Load<br />
Figure 6.11 Model for analysis of the effect of parallel feedback on input impedance<br />
Next, we consider the effect of parallel feedback on the input impedance. The model is shown in<br />
Figure 6.11. It can be shown that the input impedance in this case is<br />
-O-<br />
-196-
Analog Electronics / Feedback Circuits<br />
Ri<br />
Thus negative parallel feedback reduces input impedance.<br />
Exercise 6.5 Derive Equation (6.25).<br />
To find the output impedance of an amplifier, we turn off die input source, remove the load, and<br />
look back into the output terminals. A model for the voltage feedback amplifier with these<br />
changes is shown in Figure 6.12. A test voltage source v M has replaced the load at the output<br />
terminals of the feedback amplifier. The output impedance with feedback is<br />
v<br />
R test<br />
of =<br />
(6.26)<br />
hest<br />
To simplify our analysis, we assume that the input impedance of the feedback network is infinite.<br />
Thus the feedback network does not load the amplifier output.<br />
Xs=0 +<br />
'Jest<br />
v test<br />
Figure 6.12 Model for the analysis of output impedance widi voltage feedback<br />
The output circuit of the amplifier is modeled by a controlled voltage source with gain parameter<br />
A^ The subscripts of the gain parameter indicate that it is the open-circuit amplifier gain. If x,=f,<br />
we have series voltage feedback and A K = A.,^. On the other hand, if x~ij, we have parallel<br />
voltage feedback and A K = R^ In any case, the resistance R, shown in Figure 6.12 is the output<br />
resistance of the amplifier before feedback.<br />
For die output loop of Figure 6.12 we can write<br />
v test ~ ^ohest + ^oc x i (6.27)<br />
However, we have<br />
*/ = -Potest (6-28)<br />
Substituting Equation (6.28) into (6.27) and solving for the output resistance with feedback, we<br />
have<br />
v<br />
R test<br />
R„<br />
of =<br />
(6.29)<br />
hest<br />
1 + fiA,<br />
oc<br />
Thus negative voltage feedback reduces the output impedance of an amplifier.<br />
Next, we consider the effect of current feedback on output resistance. The model for this analysis<br />
is shown in Figure 6.13. As before, the source signal x/is set to 2ero, the load is removed, and a<br />
test source is connected to the output terminals. The feedback network is assumed to have zero<br />
input impedance, so it produces no loading effects at the amplifier output.<br />
197
Analog Electronics / Feedback Circuits<br />
x=0 +<br />
^-40-^<br />
&==&, a ^"Irjf<br />
Figure 6.13 Model for the analysis of output impedance with current feedback<br />
The output of the amplifier is modeled by a controlled current source in parallel with the output<br />
resistance. The gain parameter A x has subscripts indicating that it is the gain of the amplifier with<br />
a short-circuited load. For parallel current feedback, the gain is the short-circuit current gain A x<br />
= A isf For series current feedback, the gain is the short-circuit transconductance gain A x = G au ,<br />
For the system of Figure 6.13 we can show that<br />
R of = v test = R 0 (1 + J3A SC ) (6.30)<br />
hest<br />
Thus negative current feedback increases the output impedance of an amplifier.<br />
Exercise 6.6 Derive Equation (6.30).<br />
6.4 Summary of the Effects of Various Feedback Types<br />
We have seen that four types of feedback are possible. One effect of feedback is to stabilize and<br />
linearize gain. (i.e. Aj tends to be independent of A). However, the particular type of gain<br />
stabilized depends on the type of feedback. Table 6.1 shows the type of gain stabilized and<br />
linearized for each type of feedback.<br />
We have seen that (negative) series feedback increases input impedance, whereas parallel<br />
feedback reduces input impedance. If yip is very large, the input impedance tends toward either<br />
an open circuit or a short circuit. The formulas for input impedance are shown in Table 6.1.<br />
TABLE 6.1 EFFECTS OF FEEDBACK<br />
FEEDBACK<br />
TYPE x t x f<br />
'<br />
GAIN<br />
STABILIZED<br />
INPUT<br />
IMPEDANCE<br />
Series voltage t>, *>. A V-\ + A v 0 RiQ + A v /><br />
Series current », i.<br />
A<br />
OUTPUT<br />
IMPEDANCE<br />
Ro<br />
1 + AvocP<br />
G m<br />
mf ~\ + G m p Ri(l + G m )T> R 0 Q + G msc P)<br />
IDEAL<br />
AMPLIFIER<br />
Voltage<br />
Transconductance<br />
Parallel<br />
Ri Ro Transresistance<br />
Rm<br />
j<br />
voltage ', ».<br />
i + R m P 1 + RmocP<br />
Parallel<br />
Ai<br />
A<br />
Ri<br />
current *, '. »-l + A iP 1 + 4/ R o (\ + A isc 0) Current<br />
-198-
Analog Electronics /Feedback Circuits<br />
To reduce output impedance we could employ voltage feedback. On the other hand, to increase<br />
output impedance, we could choose current feedback. Of course, in making these statements, we<br />
assume negative feedback - the effect of positive feedback is the opposite. Table 6.1 also<br />
contains formulas for the output impedance for each of the four feedback types.<br />
We can summarize the effect of each type of feedback by stating that it tends to produce an ideal<br />
amplifier of a certain type. For example, series voltage feedback increases input impedance,<br />
reduces output impedance and stabilizes voltage gain. Thus series voltage feedback tends to<br />
produce an ideal voltage amplifier. As summarized in Table 6.1, similar statements can be made<br />
for the other feedback types.<br />
6.5 Practical Feedback Networks<br />
So far, we have modeled feedback networks as controlled sources. This approach simplified the<br />
analysis and allowed us to focus on the main effects of the various types of feedback. However,<br />
in practice we use simple networks of resistors (or in some cases resistors and capacitors). This<br />
components are available with precise and stable values (over time and with temperature<br />
changes) compared to the parameter values of active components (transistors). We employ<br />
negative feedback, so the amplifier characteristics depend mainly on the feedback network,<br />
thereby achieving amplifiers having precision and stability. Figure 6.14 shows examples of<br />
feedback amplifiers using practical resistive feedback networks.<br />
V f<br />
n<br />
(a) Series voltage, p = = — — (assuming U £ 0)<br />
v 0 R\ + R 2<br />
R 2<br />
f<br />
(b) Series voltage, / = -;— = Rf (assuming U = 0)<br />
-199-
Analog Electronics / Feedback Circuits<br />
l f<br />
n<br />
(c) Parallel voltage, p = — = — —— (assuming v,- 2 0)<br />
v o<br />
>L _<br />
l<br />
R f<br />
n if R\<br />
(d) Parallel current, p = T~ = ~ T 7T (assuming p,- = 0)<br />
l 0 R\ + K 2<br />
Figure 6.14 Examples of resistive feedback networks<br />
Notice that we have modeled the source as a voltage source for series feedback and as a current<br />
source for parallel feedback. This is consistent with Figure 6.9. The Thevenin model for the<br />
source is more natural for series feedback because the feedback voltage j^is subtracted from the<br />
source voltage v, in a series connection. The Norton model is more natural for parallel feedback<br />
because the feedback current ij\& subtracted from the source current i s in a parallel connection.<br />
Each of the feedback amplifiers shown in Figure 6.14 has negative feedback. For example, in the<br />
series voltage case shown in part (a) of the Figure, suppose that v s has a positive value. This<br />
results in a positive voltage at the noninverting input. The amplifier, in turn, produces a positive<br />
output voltage. The feedback network, composed of R, and R*, returns a fraction of the output<br />
voltage to the inverting input. This reduces the input voltage v f Thus the feedback signal acts in<br />
opposition to the original source signal, and we have negative feedback. If the inverting and<br />
noninverting input terminals were interchanged, positive feedback would result. A similar<br />
discussion applies to the remaining feedback amplifiers shown in Figure 6.14 b, c, and d.<br />
We can identify series feedback and parallel feedback by examination of the circuit configuration<br />
at the amplifier input. Study Figure 6.14a and b to verify that the signal source, the amplifierinput<br />
terminals and the output of the feedback network are in series. Also, verify the parallel<br />
connection for Figure 6.14c and d.<br />
To test for cutrent feedback, open-circuit the load so that the output current becomes zero. If<br />
the signal returned to the amplifier input by the feedback network becomes zero, the amplifier<br />
has current feedback.<br />
-200-
Analog Electronics / Feedback Circuits<br />
To test for voltage feedback, short-circuit the load so that the output voltage becomes zero. If<br />
the signal returned to the amplifier input by the feedback network becomes zero, the amplifier<br />
has voltage feedback. Verify that the types of feedback are correcdy labeled in Figure 6.14 by use<br />
of these tests.<br />
Exercise 6.7 For each of the circuits shown in Figure 6.15, identify the type of feedback present<br />
(negative-positive, series-parallel, and voltage-current). Determine the value of the feedback<br />
ratio, assuming zero input current and zero input voltage of the non-feedback amplifier, where<br />
appropriate. What type of ideal amplifier results if A$ is very large What is the gain of this ideal<br />
amplifier What value (0 or oo) do the input and output resistances approach Ans. (a) Negative<br />
series voltage, 3 = 1, ideal voltage amplifier, A 4 =l,K,-=°o,R, = 0<br />
(b) negative parallel current, P = 1, ideal current amplifier, A^= 1, R, = 0, R, = oo,<br />
(c) negative parallel voltage, P=-1/(3R), ideal transresistance amplifier, R^=-3R, R,=0, R„=0,<br />
(d) negative series current, P=R/2, ideal transconductance amplifier, G^ = 2/R, R,= oo, R = oo,<br />
(e) negative series voltage, p=l/12, ideal voltage amplifier, >4^= 12, R, = oo, R, - 0.<br />
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Analog Electronics / Feedback Circuits<br />
6.6 Stability of Feedback Amplifiers<br />
In the above discussion, the nonfeedback amplifier (A circuit) was considered memoryless, for<br />
simplicity. Therefore, a zero phase shift between its output and input was assumed. Because of<br />
nonzero phase shift within any real amplifier, it is possible that a component of the feedback<br />
signal at some particular frequency/ is actually added rather than subtracted from die signal<br />
source. If this component is sufficiently large, the result is sustained oscillation at frequency/ -<br />
the circuit has become an oscillator or signal generator instead of an amplifier, and we say the<br />
circuit is unstable.<br />
AiS)<br />
Figure 6.16 Loop gain in a feedback amplifier<br />
For concrete illustration of how oscillations can occur, consider a series voltage circuit of Figure<br />
6.16, where sinusoidal voltages are indicated as phasors. With the switch in position 1, we have<br />
the feedback amplifier; position 2 gives the nonfeedback amplifier. Usually, P is a constant and<br />
does not contribute to the phase shift At midband frequencies, A((0) is real. Therefore, with die<br />
switch in position 1, the feedback phasor, Vf=\SA(
Analog Electronics / Feedback Circuits<br />
When this occurs, we say we have positive feedback at frequency/. It is possible for feedback<br />
to be negative for midrange components and positive for frequencies outside the -3dB passband<br />
of A(f) where additional phase shift occurs.<br />
With the switch in position 2 and sinusoidal excitation at frequency/, suppose in Equation (6.36)<br />
that in addition to ^(/ 0 ) = 180°, we also have<br />
Mfoi * i ( 6 - 38 ><br />
This amplitude condition leads to two interesting possibilities. Equality in Equation (6.38)<br />
implies<br />
v f (/) = V sm{l7rf 0 t +180°) = -V sm{2nf 0 t +180°) (6.39)<br />
When this condition is satisfied, we can use Vj to replace V f That is, once the circuit is running,<br />
we can flip the switch to position 1, turn off the external signal and use V { as the input signal.<br />
Thereafter, there would be a sustained sinusoidal output at frequency/. Circuits that operate like<br />
this are called non-self-starting oscillators.<br />
When the inequality occurs in Equation (6.38), V f is identical in frequency and phase to V s but<br />
greater in amplitude. In this case, the sinusoid of frequency/ increases in strength until circuit<br />
nonlinearities limit its amplitude. The result is a sustained oscillation with a periodic output<br />
waveform of fundamental frequency/. A circuit deliberately designed to operate in this way is<br />
called a self-starting oscillator. If such oscillations occur in an amplifier, we say the amplifier is<br />
unstable.<br />
Taking into account the complex-valued gain of the nonfeedback amplifier, the closed-loop gain<br />
of a feedback amplifier, as given by Equation (6.1), can be described by<br />
A{f)<br />
Af(f) = —^±L-!— (6.40)<br />
f U J<br />
K }<br />
l + Mf) QA(f)<br />
For a given frequency/, if pVl(/5 = -1> the closed-loop gain becomes infinite. This means that<br />
even a very small input signal may cause an infinite amplifier response. Such an amplifier is<br />
unstable and may produce oscillations with no input signal. The amplitude and phase conditions<br />
associated with oscillations both are related to the complex product<br />
L(f)=6A(f) (6.41)<br />
called the loop gain. The loop gain L0 is the total gain of the feedback loop from the amplifier<br />
input back to the point of signal subtraction, including all loading effects at input and output.<br />
Figure 6.16 shows that JL0 is the gain VJ V s when the switch is in position 2, that is with the<br />
feedback loop open.<br />
We now state the Nyquist stability criterion, a necessary and sufficient condition for feedback<br />
amplifiers to be unstable. If there exists any frequency/ such that the loop gain<br />
L(f 0 ) = jfl4(/ 0 ) = MZl80°, and M > 1 (6.42)<br />
then the amplifier is unstable, and there will be oscillations at/. Otherwise, the amplifier is stable.<br />
The justification for such a simple stability criterion is that random noise is present in every<br />
circuit with its power distributed over all frequencies - an infinity of tiny signal sources. For this<br />
reason, if there is any frequency whatsoever at which Equation (6.42) is satisfied, oscillations are<br />
inevitable even with no external signal applied to the circuit With an external signal applied, the<br />
oscillations simply superimpose upon it<br />
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Analog Electronics / Feedback Circuits<br />
Gain Margin and Phase Margin. In design of feedback amplifiers, it is often helpful to<br />
consider Bode plots of me magnitude and phase of the loop gain $A(fi. For real and positive (3,<br />
its effect on the magnitude plot is simply to shift it vertically by 201og(P) and there is no effect on<br />
the phase plot. Thus the Bode plots of the loop gain $A(fi are the same as the Bode plots of the<br />
amplifier open-loop gain A(J) except for the vertical shift in the magnitude plot<br />
An example of the Bode plots for a BJT amplifier is shown in Figure 6.17. In considering the<br />
stability of an amplifier, we examine the Bode plot for the loop gain $A(fi to find the frequency<br />
f GM fot which the phase shift is 180°. If the magnitude of the loop gain is less than unity at this<br />
frequency, die amplifier is stable. On die other hand, if the loop gain magnitude is greater than<br />
unity, the amplifier is unstable.<br />
For a stable amplifier, the gain at/^ is less than unity in magnitude (it is negative when expressed<br />
in decibels). The amount mat the gain magnitude is below 0 dB is called die gain margin. The<br />
gain margin is illustrated in Figure 6.17. It can be shown that a gain margin of zero implies a pole<br />
lies on they'll) axis on the .r-plane. As gain margin becomes larger, the pole moves back into die<br />
left half of the .r-plane. In general, larger gain margin results in less ringing and faster decay of the<br />
transient response.<br />
Another measure of stability that can be obtained from the Bode plots is the phase margin.<br />
Phase margin is determined at the frequency f m for which the loop gain $A(f PA j) is unity in<br />
magnitude (i.e., 201og | fyAffpy) \ — 0 dB). The phase margin is the difference between me actual<br />
phase and 180°. This is also illustrated in Figure 6.17.<br />
As we noted earlier, we usually want to design feedback amplifiers to avoid ringing transient<br />
response and gain peaks in the frequency response. A. generally accepted rule of thumb is to design for a<br />
minimum gain margin qflOdB and a minimum phase margin of 45 °<br />
For the amplifier illustrated by Figure 6.17, the frequency f GM is approximately equal to 30.1<br />
MHz, and the gain margin equals to 21.7 dB. The phase margin can be determined at frequency<br />
f PM £ 3.1 MHz as being equal to 79°. Thus the example amplifier is stable and shows reasonable<br />
gain and phase margins.<br />
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Analog Electronics / Feedback Circuits<br />
Often an amplifier is unstable for a given gain l/p\ which is especially true for multistage<br />
nonfeedback amplifiers that have complicated frequency response. We can make such amplifier<br />
stable by altering its open-loop gain curve A(J). Deliberately changing the frequency response of<br />
the nonfeedback amplifier to make a feedback amplifier stable is called frequency<br />
compensation. Some techniques have been developed for frequency compensation, such as pole<br />
addition used for operational amplifier design. However, the topic of frequency compensation is<br />
outside the scope of this textbook. The modern operational amplifiers, which are most often<br />
used as nonfeedback amplifiers, are internally compensated by adding an on-chip capacitor to<br />
introduce the dominant pole for compensation.<br />
Exercise 6.8 Use PSpice to find gain margin and phase margin for the uA741 operational<br />
amplifier. Hint Run the .ac analysis and use evailib library.<br />
6.7 Sinusoidal Oscillators<br />
Oscillators are intentionally unstable circuits that serve as sources of electrical waveforms. There<br />
are two broad classes of oscillators: sinusoidal oscillators, which produce sinusoidal waveforms,<br />
and relaxation oscillators, which produce triangular, or rectangular, waveforms. Both classes of<br />
oscillators are widely used for time bases in test and measurement equipment, and for signal<br />
processing in analogue and digital communication systems. Here we concentrate on sinusoidal<br />
oscillators.<br />
6.7.1 General Theory of Sinusoidal Oscillators<br />
A sinusoidal oscillator has three functional parts, a phase shifter to establish the frequency of<br />
oscillation, a gain circuit to compensate for energy losses in the phase shifter, and a limiter to<br />
control the amplitude of the oscillations. The gain circuit might be an operational amplifier or a<br />
transistor amplifier. The phase shifter is typically an RC or JJC circuit. The limiter might be a<br />
diode, a thermistor, or a variable-gain amplifier. In some oscillators the basic functions are<br />
combined rather than relegated to individual subcircuits. For example, the internal capacitances<br />
of the transistor that provides gain might contribute to the phase shifter, and inherent transistor<br />
nonlinearities often provide the limiting. Common to all oscillator circuits is instability, which is<br />
best understood in terms of positive feedback theory.<br />
Figure 6.18 General structure of a sinusoidal oscillator<br />
The voltage-shunt feedback structure of Fig. 6.18 describes many sinusoidal oscillators. A<br />
voltage amplifier with gain A((o) = VJV-, provides the gain, and a feedback network described<br />
by P(co) = VjfV, is the phase shifter. An oscillator representation, such as Fig. 6.18, differs in<br />
several ways from a feedback amplifier diagram: (3 ((D) is defined without the notion of an input<br />
subtraction; the feedback network includes reactive elements to provide the phase shift required<br />
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Analog Electronics / Feedback Circuits<br />
for positive feedback; and, of course, there is no external signal source. Nonlinearities that limit<br />
the signal amplitude invariably arise but do not appear in this linear model. The switch helps us<br />
examine the loop gain of the circuit.<br />
Barkhausen Criterion. Assume that A((&) and (3(co) are defined in such a way that no loading<br />
occurs when the switch is closed. The Barkhausen criterion states that there will be sinusoidal<br />
oscillations at frequency C0 o when the switch is closed, provided that with the switch open, the<br />
loop gain is<br />
V f I V t = A{o) 0 )P{co 0 ) = M{co 0 )Z{co 0 ) = 1 (6.43)<br />
When this condition is satisfied, a hypothetical sinusoidal signal generator V; attached to the<br />
input can be removed when the switch is closed, because the amplitude and phase of the signal<br />
fed back to the input are exactly those needed to replace this source. Since the Barkhausen<br />
criterion involves a complex-valued function, it implies two conditions for oscillations, a<br />
magnitude condition and a phase condition. We use the magnitude condition. M(C0 o ) — 1, as a<br />
test to determine whether oscillations can exist in a given circuit. This condition arises from the<br />
physical requirement that the amplifier provide sufficient gain to make up exacdy for energy<br />
losses in the circuit. If Af(C0 o ) exceeds one, the oscillator is self-starting, with the oscillation arising<br />
spontaneously and increasing in amplitude until nonlinearities cause a reduction in M((0 0 )- Some<br />
oscillator circuits require- a signal generator for start-up; however, self-starting circuits are die<br />
norm. Provided that oscillations can occur, the phase condition
Analog Electronics / Feedback Circuits<br />
1/coC<br />
co„+Aco<br />
(c)<br />
Figure 6.19 Wien bridge oscillator: (a) schematic; (b) redrawn to sliow the bridge;<br />
(c) illustration of frequency stability.<br />
To find design equations for this or any oscillator, we apply the Barkhausen criterion. From Fig.<br />
6.19a, P(ffl) is the transfer function<br />
where Z, and Z 2 are the impedances of the parallel RC and series RC circuits, respectively. Since<br />
A(a>) is the gain of the noninverting amplifier, Eq. (6.43) requires<br />
A{G> 0 )P{a> 0 ) =<br />
1 + *2<br />
R \J 1 + j
Analog Electronics / Feedback Circuits<br />
not particularly low values. To give an intuitive idea of what is involved, Fig. 6.19c shows Eq.<br />
(6.46) as the graphical solution of the equation 1/toC = R. The dashed lines show how C0 o<br />
changes with variations in C. (Like the sensitivity expression, this diagram assumes that the<br />
resistor and capacitor pairs in die P circuit are matched.)<br />
The next example demonstrates another useful way to investigate frequency stability of an<br />
oscillator - using SPICE to plot the phase of A(a>)p((o).<br />
Example 6.4 Plot the phase shift of the loop gain for a Wien bridge oscillator with R = 1591.5<br />
Q and C = 1000 pF. Find the change in frequency if the value of the shunt capacitor increases by<br />
10%.<br />
Solution. Figure 6.20a shows the phase-shifting network - Fig. 6.20b the SPICE code. An<br />
asterisk marks the statement that describes C 2 for the second run. Since Eq. (6.46) indicates an<br />
oscillation frequency of 100 kHz, the phase of P(
Analog Electronics / Feedback Circuits<br />
Phase-Shift Oscillator. Figure 6.21a shows the phase-shift oscillator, The phase shifter consists<br />
of three RC sections, The gain element is represented as an ideal inverting amplifier with voltage<br />
gain -K.<br />
To find amplitude and phase conditions from the Barkhausen criterion, we analyze the phaseshifting<br />
circuit of Fig. 6.21b. The transfer characteristic' of such a ladder circuit is most easily<br />
found by systematic analysis from output to input as suggested by the following equations.<br />
' - * •<br />
2<br />
R<br />
l<br />
V: +<br />
1<br />
= 1+ ,VjcoRC)<br />
'<br />
K jaRC) R R<br />
Continuing in this fashion finally gives<br />
2 + jcoRC) R<br />
v i 1<br />
5 1<br />
1 + jcoRC o 2 R 2 C 2+J co 3 R 3 C 3<br />
Thus our design must satisfy<br />
-K<br />
A{O) 0 ){3{CD 0 ) = ^- =<br />
= 1<br />
6 5 1<br />
1 +<br />
jco 0 RC~ CO 2 OR 2 C 2+J o) 3 0R 3 C 3<br />
To find the phase condition, we set the imaginary part of the denominator to zero. This gives an<br />
oscillation frequency of<br />
(6 ' 47)<br />
^-7SE<br />
It is easy to show that the sensitivity to changes in R and C is the same as for the Wien bridge<br />
circuit. Substituting co 0 from Eq. (9,39) into the preceding equation gives the gain condition<br />
-K<br />
TTir 1<br />
Thus the circuit oscillates for any K > 29.<br />
A(
Analog Electronics / Feedback Circuits<br />
Ans. Vj =<br />
jaRC (wRC) 2 V t<br />
Amplitude Limitets. To make an oscillator self-starting and to allow for uncertainties in<br />
parameter values, we usually design the circuit so that the gain condition is exceeded. The<br />
amplitude of the oscillation then increases until some nonlinearity reduces the effective loop gain.<br />
If the signal amplitude becomes too large, the signal traverses a large segment of the nonlinear<br />
transfer characteristic of the active device causing the sinusoidal output waveform to be highly<br />
distorted. There are three basic approaches to controlling the signal amplitude while keeping the<br />
waveform reasonably sinusoidal.<br />
When the gain condition is not gready exceeded, a design can rely on inherent transistor<br />
nonlinearities to limit the signal amplitude to a value corresponding to a reasonably undistorted<br />
sine wave. This does not produce very robust designs, however, because component values are<br />
rather critically related to waveform purity.<br />
The second approach is to insert a special nonlinear component into the loop so that loop gain<br />
begins to diminish with signal amplitude while signal amplitude is still small. A thermistor with<br />
resistance that decreases- by self-heating, or a strategically placed diode are examples of<br />
components used for this purpose. An example is Fig. 6.22a, which shows the phase-shift<br />
oscillator of Fig. 6.21a with two diodes added for limiting. As long as the voltage across resistor<br />
Rj has peak amplitude less than 0.5 V the circuit is approximately the same as Fig. 6.22a;<br />
however, when output amplitude exceeds the forward-biased diode voltage, the diodes introduce<br />
a low resistance in parallel with ly This nonlinear resistance decreases with increasing amplitude,<br />
lowering the gain of the inverting amplifier and thereby limiting the oscillation amplitude. The<br />
following example investigates this limiter in some detail.<br />
Example 6.5 Use PSpice to examine the output waveform of the phase-shift oscillator of Fig.<br />
6.22a without and with the diode limiter. Values are R = 10 kQ, K = 50, and C = 3000 pF. Use a<br />
dependent source with gain 10 5 and input impedance of 1 MQ for the op amp.<br />
Solution. Figure 6.22b is the PSpice code with diodes omitted. The initial condition statement,<br />
".IC V(3) = 0.1," changes the initial voltage at node 3 to a nonequilibrium value to help start<br />
oscillations. Figure 6.22c shows the output without the diode statements. Since the linear circuit<br />
model has no limiting whatsoever, the oscillation amplitude quickly increases to tens of volts in<br />
the simulation. The output of a real opamp would be driven to its saturation limits, giving a<br />
highly distorted output voltage, a statement readily verified using the more realistic operational<br />
amplifier model, e.g. from the EVAL.LIB library.<br />
Figure 6.22d shows the output with the diode statements present in the input code. The<br />
waveform quickly converges to a sinusoidal waveshape, with amplitude limited by the diodes and<br />
virtual ground to the ±0.5 V range.<br />
+<br />
Exercise 6.10 Calculate the expected oscillation frequency in Example 6.5.<br />
Ans. About 1.7kHz with limiting diodes omitted; 2.17 kHz with limiting diodes present.<br />
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Analog Electronics /Feedback Circuits<br />
(c)<br />
(d)<br />
Figure 6.22 Phase-shift oscillator with diode limiter (a) schematicj-(b) PSpice code;<br />
(c) output with limiting diodes omitted; (d) output with limiting diodes included.<br />
For sinusoids of very high quality, a „linear amplifier" can provide limiting with gain that<br />
decreases as amplitude increases. In Fig. 6.23, the voltage-controlled amplifier is the gain element<br />
in a Wien bridge oscillator. A half-wave rectifier with a capacitive load (envelope detector)<br />
produces a dc control signal, V c , proportional to signal amplitude. The follower isolates the<br />
control circuit from the RC bridge so amplitude and phase conditions are unchanged. As<br />
oscillation amplitude increases, V c becomes more negative, and gain automatically decreases. The<br />
detector time constant R D C D should be several periods of the oscillator waveform.<br />
Because it involves nonlinear operation, limiting always introduces "impurity" into the oscillator<br />
output waveform, causing the output to differ from the desired single-frequency sinusoid. One<br />
can describe any periodic waveform as a Fourier series<br />
00<br />
v(0= T,A„cos(na) 0 t+ „)<br />
n=0<br />
For an oscillator, the ideal output is the n = 1 term alone; terms for which n>2 are undesired<br />
impurity terms introduced by the limiter. The smaller these harmonic terms, the greater the<br />
-211-
Analog Electronics / Feedback Circuits<br />
waveform purity. A useful measure of waveform impurity is the percent total harmonic distortion,<br />
THD, where<br />
rms value of harmonic components<br />
THD =<br />
xl00%<br />
rms value of fundamental frequency terms<br />
If we know the fundamental frequency^. = C0 o /27t of the oscillator output, we can use PSpice to<br />
compute THD by adding a SPICE statement ".FOUR". This asks SPICE to compute amplitudes<br />
of the first nine Fourier series components and to use them to estimate THD. Adding the<br />
statement<br />
.FOUR2.0E3V(1)<br />
reveals that the output voltage waveform contains 6.22% distortion (look into the PSpice output<br />
file). The advantage of more sophisticated limiters like Fig. 6.23 is improved waveform purity.<br />
The oscillator designer is often required to meet a THD specification along with specifications of<br />
frequency and amplitude.<br />
Figure 6.23 A limiter that uses sip~-' amplitude to control loop gain<br />
6.7.3 LC Oscillators<br />
Two important oscillators use the thtee-element n structure of Fig. 6.24a for the phase shifter. In<br />
Fig. 6.24b, a transistor biased for small-signal active operation provides the gain. From Fig. 6.24b,<br />
00 (b)<br />
Figure 6.24 Oscillator configuration with three-element ladder phase shifter:<br />
(a) general structure; (b) oscillator with transistor active element<br />
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Analog Electronics / Feedback Circuits<br />
A(a>) = V f = -g m [R 0 \\Z l \\{Z 2 + Z 3 )]<br />
and<br />
z 3<br />
This gives the loop gain<br />
i4(«)fl») =<br />
Z + Zi<br />
~ l s ^<br />
ZJ + Z<br />
„<br />
J + *<br />
A +1<br />
*o Zl<br />
The Barkhausen criterion requires<br />
r<br />
Z 1 Z 2 +Z 1 Z 3 +i 0 (Z3+Z2+Z 1 )<br />
v<br />
'<br />
If each impedance is an LC element, then Z,- = jXj, where X, = fflJL,-for an inductor and X s<br />
//(oC for a capacitor. Then<br />
MZd> = SmKZfo = lzoo M (649)<br />
K<br />
^ -(X l X 2 +X l X 3 ) + jR 0 (X l+ X 2 + X 3 )<br />
><br />
Because die numerator is real, the phase condition is satisfied only if<br />
X x + X 2 + X 3 = 0 (6.50)<br />
When Eq. (6.50) is satisfied, the gain condition in Eq. (6.49) reduces to<br />
-gmV^^ (651)<br />
X 2 +X 3<br />
We next use these conditions to study two specific oscillators.<br />
Colpitts Oscillator. In the Colpitts oscillator, Z 2 is an inductor and Z, and Z, axe capacitors as in<br />
Fig. 6.25. Substituting Z 2 -faL.^ Z, = 1/foC t and Z } = 1//oC } into Eq. (6.50) gives<br />
1 , 1 n<br />
Solving forOf) gives the phase condition<br />
2<br />
C l +C 3<br />
ffl »=^A<br />
(6 - 52)<br />
which establishes the frequency of osculation. A second design condition comes from Eq. (6.51),<br />
If!^=_s^al (6 . 53)<br />
0> o L 3<br />
Substituting C0 o from Eq. (6.52) leads to the second design equation<br />
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Analog Electronics / Feedback Circuits<br />
g m Ro> (6.54)<br />
which specifies the gain required for sustained oscillations.<br />
Exercise 6.11 Compute the sensitivity of the resonant frequency of a Colpitts oscillator to L<br />
Use your answer to estimate the actual resonant frequency of an oscillator designed to operate at<br />
1 MHz if L 2 is 12% high. Ans. -0.5, 940 kHz.<br />
+12V +12V<br />
+12V +12V<br />
Figure 6.26 Colpitts oscillator realizations: (a) circuit diagram for a BJT oscillator;<br />
(b) small-signal equivalent for BJT circuit; (c) MOSFET oscillator<br />
Example 6.6 The Colpitts oscillator of Fig. 6.26a has a transistor biased at 0.5 mA; pV = 120; C c<br />
is a large coupling capacitor. Find values for L^ C, and C, so the circuit oscillates atf, = 1 MHz.<br />
Ignore transistor capacitances.<br />
Solution. Figure 6.26b shows the high-frequency equivalent circuit. At 0.5 mA,&, = 0.02 S and r n<br />
- 6 kQ. The small-signal equivalent circuit is Fig. 6.26b, where<br />
5.5*0 = ^ ||159*Q||112Afi<br />
From Eq. (6.54),<br />
(0.02)(6xl0 3 ) = 120>§-<br />
c l<br />
(6.55)<br />
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Analog Electronics /Feedback Circuits<br />
and from Eq. (6.52),<br />
LoCea = 7TT = 25.3 x 10" 15 (6.56)<br />
1<br />
** (2/rl0 6 ) 2<br />
where C tq = C,C 3 /(C t + Q.<br />
We now have two equations involving C h C s and L. 2 . In a FET design we would make an<br />
arbitrary choice of one component value; however, in a BJT design we must minimize the effect<br />
of r„, since our theory does not include a resistor in this location. Therefore, we select C3 such<br />
that its reactance is much smaller than r x = 5.5 kQ. This gives the third design equation. Using<br />
two orders of magnitude to assure r n has negligible effect gives<br />
1 1<br />
2*10 6 C 3 " 100<br />
orCjS2894pF.<br />
5.5 xlO 3<br />
Since our design depends upon approximation, and since actual component values may not have<br />
exacdy the values we expect, we satisfy Eq. (6.55) by using C,/C f = 75 instead of the limiting<br />
value of 120 to ensure self-starting oscillations. With C } previously selected, this gives<br />
2894<br />
Q= — = 38.6pF<br />
and C, q = 38.1 pF. From Eq. (6.56)<br />
25.3 xlO -15 n, tre TT<br />
L) = 7T = 0.65 5mH<br />
38.6 x 10" 12<br />
The coupling capacitor C c must have reactance oL 2 at 1 MHz. Since the latter is 4.11 kfi, C c<br />
- 10 nF will do.<br />
In Colpitts oscillators, an inductor called an RF choke usually replaces the collector or drain<br />
resistor. The choke coil is a short circuit for biasing purposes but presents an open circuit at RF<br />
(radio frequency) oscillator frequencies. When a choke is used, R, in Fig. 6.25 becomes the<br />
output resistance r„ of the transistor. The RF choke reduces power dissipation of the circuit and<br />
improves the purity of the output waveform.<br />
Exercise 6.12 Figure 6.26c shows a MOSFET oscillator with drain biased at 1 mA through an<br />
RF choke. If transistor parameters are K = 4 mA/V 2 , V, = 1.2 V, and V A = 70 V, find the<br />
condition for oscillation. Ans. 197 > C 3 /C t .<br />
We have seen that SPICE simulations are useful in verifying oscillator designs, examining<br />
distortion, and exploring sensitivity limitations. There are some practical simulation difficulties<br />
when large bypass and coupling capacitors are included in simulations along with components<br />
having short time constants. Sometimes there are convergence problems in the numerical<br />
algoriuims. Sometimes a very large number of oscillator cycles are required before the circuit<br />
settles into steady-state operation. The following example shows a way to avoid time constant<br />
problems in oscillator simulations. An initial dc analysis determines the voltages across the large<br />
capacitors, which we then replace by dc voltage sources of appropriate polarity.<br />
-215-
Analog Electronics / Feedback Circuits<br />
Example 6.7 Use PSpice to show how the oscillations arise in die circuit designed in Example<br />
6.6.<br />
Solution. The SPICE code of Fig. 6.27a uses values determined in die design of Fig. 6.26a.<br />
Following initial dc analysis, capacitors C E and C c were replaced, respectively, by sources VEE<br />
and VCC. Because the oscillation period is expected to be approximately 1 Lis, the initial .TRAN<br />
statement runs the simulation for 30 periods to show die build-up of oscillations.<br />
Figure 6.27b shows that die oscillation is superimposed upon a 9.2 V dc collector voltage. By<br />
measuring die average period of the last nine cycles from the output data, we find that^ = 0.9414<br />
MHz. The oscillations reach steady-state conditions after about 15 Lis; however, longer times<br />
should be expected if die capacitors C E and C c are not replaced by voltage sources.<br />
This simulation demonstrates limiting performed by inherent transistor nonlinearities rather man<br />
by a special limiter circuit Because we used C 3 /C, = 75 in our design, the loop gain is rather high<br />
and die resulting oscillation has peak amplitude of about 3.5 V. Harmonic distortion is about<br />
13%.<br />
Hartley Oscillator. The Hartley oscillator, Fig. 6.28, is Fig. 6.24b with inductors for Z, and Z,<br />
and a capacitor for Z For diis circuit, Eq. (6.50) gives<br />
(0 0 L\~—— + G) o L 3 =0<br />
tf>o c 2<br />
which establishes the oscillator frequency<br />
1<br />
Analog Electronics / Feedback Circuits<br />
-ZmKOok Zm R o C 2<br />
>1<br />
1<br />
1<br />
Substituting Eq. (6.57) into this expression and simplifying gives the gain condition<br />
(6.58)<br />
Figure 6.28 Hartley oscillator small-signal circuit<br />
6.7.4 Quartz Crystal Oscillators<br />
Frequency Stability. We know that frequency stability is an important consideration in an<br />
oscillator. The Colpitts and Hartley design equations show that in these circuits the frequency<br />
depends entirely upon the reactive components in the resonators. We are therefore concerned<br />
with variations in these components due to aging, temperature, and tolerances, especially since<br />
transistor capacitances are sometimes part of the phase shifter.<br />
Reactance<br />
1/(0 C.<br />
Figure 6.29 Frequency stability of Colpitts oscillator<br />
By defining C tq = C,C } /(C, + C,) for the Colpitts oscillator, we can view
Analog Electronics / Feedback Circuits<br />
example, consider a bar of quartz firmly held at the left-hand end but free to flex up and down at<br />
the right-hand end as illustrated in Fig. 6.30. Conducting, e.g. silver, electrodes are plated to the<br />
upper and lower faces of the bar. Under suitable conditions, voltage applied to the electrodes<br />
forces the right-hand end of the bar to move upward. On the other hand, voltage of the opposite<br />
polarity flexes the bar downward. The piezoelectric effect is reciprocal. In other words, if the<br />
terminals are open circuited and a force is applied to flex the bar, a voltage appears across the<br />
electrodes.<br />
\<br />
Figure 6.30 Simplified physical structure of piezoelectric crystal<br />
In quartz crystals, slight; reversible, physical deformations result in an electrical voltage, and,<br />
conversely, applied voltage produces physical deformations. The crystal is thus an<br />
electromechanical device in which electrical excitation and mechanical deformation are tightly<br />
coupled, a feature that makes the crystal highly useful as a transducer. Another unusual property<br />
of a quartz crystal is that, once set in motion, its energy losses per cycle are very slight. Its<br />
electrical equivalent circuit is an LC resonant circuit like Fig. 6.31a, in which the energy losses of<br />
the crystal are embodied in the crystal parameter r, and C is associated with the external holder<br />
that makes electrical contacts to the quartz. Representative component values for a 90 kHz<br />
crystal are L = 137 H, C = 0.0235 pF, r- 15 kQ and C - 3.5 pF.<br />
When used as a frequency-determining element, the crystal is mounted so that it can vibrate<br />
freely at die desired frequency. The mechanical vibrations result in an ac current in the external<br />
circuit. In an oscillator circuit, an amplifier maintains the vibrations. Because quartz is an<br />
extremely stable material, frequency variations due to changes in power-supply voltage or<br />
temperature are very small compared to those of UZ or RC oscillators.<br />
4<br />
C<br />
(a)<br />
(b)<br />
Figure 6.31 Crystal resonator: (a) schematic symbol and electrical equivalent circuit;<br />
(b) approximate reactance curve<br />
We now derive an expression for the reactance of the quartz crystal that allows us to compare the<br />
crystal resonator characteristics with the JJC reactance curves of Fig 6.29. Near resonance where<br />
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Analog Electronics / Feedback Circuits<br />
me crystal is used, r « ©L. With resistance omitted to simplify die development, the impedance<br />
of the crystal in Fig. 6.31a is<br />
jd)L + 1 1<br />
j 5 LCC+ja>(C + C)<br />
jooC jaC<br />
where the second expression follows from multiplying numerator and denominator by<br />
{/
Analog Electronics /Feedback Circuits<br />
The graphical construction of Fig. 6.32b shows why the oscillation frequency of the Pierce<br />
oscillator is virtually independent of variations in resonator capacitance. Another popular crystal<br />
oscillator circuit is obtained by replacing one of the inductors in a Hartley oscillator with a crystal.<br />
Usually, a quartz crystal can vibrate in many different ways called modes. For example, returning<br />
to die bar of quartz fixed at one end, the bar could flex up and down. On the other hand, it could<br />
flex sideways. If the widdi and height of the bar are different, the frequency for the sideways<br />
motion is different from that of vertical flexure. Another possibility is for the bar to twist around<br />
its axis.<br />
End<br />
stationary<br />
A<br />
Stationary<br />
point<br />
(c) Third overtone<br />
Figure 6.33 Overtone vibrations<br />
Commonly, there are overtone vibrations for each mode. For example, several overtone<br />
vibrations are shown for vertical flexure of a bar in Fig. 6.33. The lowest frequency is called<br />
fundamental. The «th overtone frequency is nearly — but not exactly — n times the frequency of<br />
the fundamental vibration. {The amplitudes of vibrations in Fig. 6.33 are exaggerated for clarity.<br />
Actual amplitudes of vibration in quartz crystal are much smaller.)<br />
The flexure modes that are illustrated in Fig. 6.33 are not often used for crystals. (An exception is<br />
32,768-Hz crystal used in electronic watches.) We have discussed this mode mainly because it is<br />
easy to illustrate. Typical high-frequency crystals use shear modes. Crystals are practical as<br />
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Analog Electronics / Feedback Circuits<br />
frequency determining elements for frequencies in die approximate range from 10 kHz to 200<br />
MHz. Below about 30 MHz, the fundamental mode is used. At higher frequencies, overtones are<br />
used.<br />
6.8 Summary<br />
Adding negative feedback to an amplifier reduces sensitivity to parameter variations, increases<br />
bandwidth, and reduces nonlinear distortion. We can also use feedback to increase or decrease<br />
midrange input resistance and (independendy) increase or decrease output resistance. All<br />
improvements involve multiplication or division by the improvement factor 1 +Ap. The closedloop<br />
gain is simultaneously reduced by diis factor; however, diis counts as an improvement once<br />
we realize that die new, lower, gain usually approximates 1/p. By using resistor ratios for P we<br />
can control this closed-loop gain to ±1%.<br />
With four classes of feedback, we can make our nonfeedback amplifier more closely resemble an<br />
ideal voltage, current, transresistance, or transconductance amplifier at midrange frequencies. For<br />
each class of feedback, the definition of gain, A, corresponds to that of the ideal amplifier. The<br />
origin of the feedback signal defines the output circuit of the feedback amplifier-voltage (current)<br />
feedback lowers (raises) output resistance, making the original amplifier more closely resemble a<br />
dependent voltage (current) source. The way the feedback signal subtracts from die input signal<br />
determines die nature of die input circuit. Series (shunt) feedback involves a voltage (current)<br />
subtraction that increases (decreases) input resistance. This makes die amplifier better represent a<br />
voltage- (current-) controlled dependent source.<br />
The resistive P circuits we use in practical feedback amplifiers introduce loading at input and<br />
output. To apply ideal feedback equations to this case, we represent die p circuit by a two-port<br />
equivalent - the one that corresponds to the particular kind of feedback we employ.<br />
To successfully implement feedback or evaluate die designs of others, we must be able to<br />
recognize some standard practical feedback topologies. The difference amplifier structure is a<br />
voltage-series feedback arrangement that bases the input subtraction on an amplifier's differential<br />
input. In classical voltage-feedback circuits, as in the difference amplifier topology, the output<br />
node of die nonfeedback amplifier connects direcdy to the P circuit. Current feedback features<br />
indirect sensing of output current using an unbypassed emitter or source resistor. Classical series<br />
feedback involves a connection from die P circuit to an unbypassed emitter or source resistor in<br />
the input circuit of the nonfeedback amplifier; shunt feedback uses a direct connection from die<br />
P circuit to an input node of the nonfeedback amplifier. The A circuit must provide a 180° phase<br />
shift to facilitate the current subtraction needed for shunt feedback; zero phase shift is required<br />
for series feedback.<br />
To ensure that our feedback amplifier does not oscillate, we examine die magnitude and phase of<br />
its loop-gain function, the product of the A circuit and P circuit gains. If diere exists no<br />
frequency where the loop gain is negative and also greater than one in magnitude, the feedback<br />
amplifier will be stable. Gain and phase margins are two measures of the degree of stability that<br />
might be included in design specifications. If die feedback amplifier is destined to be unstable, we<br />
must compensate it by modifying die open-loop gain curve to produce appropriate gain and<br />
phase margins. This process, called frequency compensation, usually involves adding capacitance<br />
to reduce die bandwiddi of die A circuit.<br />
-221 -
Analog Electronics / Feedback Circuits<br />
Oscillators are circuits intentionally made unstable by positive feedback. Common to all<br />
oscillators are phase shifters, which determine the frequency of oscillation, gain circuits to make<br />
up for energy losses in the phase shifters, and limiters to control oscillation amplitude. The<br />
Barkhausen stability criterion, based upon conditions for positive feedback, gives a complex<br />
valued equation for any oscillator. The Barkhausen conditions give an equation for the frequency<br />
of oscillation and an amplitude condition that must be satisfied for oscillations to occur. In this<br />
chapter only oscillators with sinusoidal output waveforms were considered. Phase-shift and Wien<br />
bridge oscillators use RC circuits for phase shifters; Colpitis and Hartley oscillators employ tuned<br />
circuits.<br />
Important considerations in sinusoidal oscillator design are the harmonic purity of the waveform<br />
and frequency stability, the relative insensitivity of the oscillation frequency to variations in circuit<br />
parameters, and environmental factors. Total harmonic distortion measures the impurity of the<br />
output waveform in terms of the amplitudes of undesired harmonics present. The sensitivity<br />
definitions are useful aids in oscillator analysis and design. SPICE simulations help us address<br />
both distortion and sensitivity issues in a practical fashion. Quartz crystals introduced into<br />
oscillator phase shifters result in great improvements in frequency stability.<br />
Notes<br />
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Analog Electronics / Feedback Circuits<br />
References<br />
1. D. Christiansen (Ed.), Electronics Engineers'Handbook, McGraw-Hill, 1996.<br />
2. A. R. Hambley, Electronics, Macmillan, 1994.<br />
3. J. Keown, PSpice and Circuit Analysis, Maxwell Macmillan, 1991.<br />
4. N. R. Malik, Electronic Circuits, Prentice Hall, 1995.<br />
5. R Mauro, Engineering Electronics, Prentice Hall, 1989.<br />
6. J. Millman and A. Grabel, Microelectronics, 2 nd edition, McGraw-Hill, 1987.<br />
7. J. F. Morris, Introduction to PSpice, Houghton Mifflin, 1991.<br />
8. C. J. Savant, M. £J. Roden and G. L. Carpenter, Electronic Design, The Benjamin/Cummings,<br />
1991.<br />
9. J. Scott, Analog Electronic Design, Prentice Hall, 1991.<br />
10. A. S. Sedra and K. C. Smith, Microelectronic Circuits, Saunders College, 1992.<br />
11. W.J. Tompkins (Ed), Biomedical Digital Signal Processing, Prentice-Hall, 1993.<br />
12. P. W. Tuinenga, SPICE: A Guide to Circuit Simulation and Analysis Using PSpice, Prentice Hall,<br />
1992.<br />
-223-
Analog Electronics /Review Questions<br />
Review Questions<br />
Chapter 1: introduction<br />
1.1 List five examples of electronic systems. Try to think of new examples that have not been<br />
mentioned in this chapter.<br />
1.2 Discuss briefly what the spectrum of a signal is and why it is important.<br />
1.3 Give five examples of useful signals and their spectra.<br />
1.4 List five types of functional blocks found in electronic systems.<br />
1.5 Discuss how analog signals can be converted to digital form.<br />
1.6 List the relative advantages of digital systems compared to analog systems and vice versa.<br />
1.7 Explain why at certain frequencies a physical resistor can be perceived as a capacitor or<br />
inductor.<br />
Chapter 2: Amplifiers<br />
2.1 How does an inverting amplifier differ from a noninverting one<br />
2.2 Draw the voltage amplifier model. Is the gain parameter measured under open-circuit or<br />
short-circuit conditions Repeat for current, transconductance and transresistance models.<br />
2.3 What are "loading effects" in an amplifier circuit<br />
2.4 Draw the cascade connection of two amplifiers. What is the voltage gain of the cascade<br />
connection in terms of the voltage gains of the individual stages<br />
2.5 Define the efficiency of a power amplifier. What form does the dissipated power take<br />
2.6 How is power gain converted to decibels Voltage gain<br />
2.7 Give the input and output resistances of an ideal voltage amplifier. Repeat for other ideal<br />
amplifier types.<br />
2.8 Sketch the gain magnitude of a typical dc-coupled amplifier versus frequency. Repeat for an<br />
ac-coupled amplifier.<br />
2.9 How is a narrowband amplifier different from a wideband one<br />
2.10 Discuss the Miller theorem. Explain its significance to circuit analysis.<br />
2.11 What are the requirements for the gain magnitude and phase of an amplifier so that linear<br />
distortion does not occur<br />
2.12 Sketch the pulse response of an amplifier, showing the rise time, overshoot, ringing and tilt.<br />
Give an approximate relationship between rise time and the upper half-power frequency of a<br />
broadband amplifier. Give an approximate relationship between percentage tilt and the lower<br />
half-power frequency.<br />
2.13 What is the compensated oscilloscope probe What for is it used in electronics<br />
2.14 What is harmonic distortion What causes it Is it a problem for narrowband amplifiers<br />
Explain.<br />
2.15 Discuss briefly intermodulation and crossmodulation.<br />
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Analog Electronics /Review Questions<br />
Chapter 3: Diode Circuits<br />
3.1 Draw the circuit symbol for a diode. Label the anode and the cathode. Make a reference to<br />
die p-type and »-type regions of a corresponding/^ junction.<br />
3.2 Draw the volt-ampere characteristic of a typical diode and label the various regions of<br />
operation.<br />
3.3 What is a Zener diode For what is it typically used What are two other names for it<br />
3.4 Draw a circuit diagram of a simple voltage regulator.<br />
3.5 Draw the volt-ampere characteristic of an ideal 5.8-V Zener diode.<br />
3.6 Write the Schockley equation and define all the terms.<br />
3.7 How does the forward voltage of a silicon diode change with temperature for a fixed value of<br />
current Explain.<br />
3.8 What is an ideal diode Draw its characteristic.<br />
3.9 After solving a circuit with ideal diodes, what check is necessary for diodes initially assumed<br />
to be on Off<br />
3.10 If a nonlinear two-terminal device is modeled by die piecewise-linear approach, what is die<br />
equivalent circuit of die device for each linear segment<br />
3.11 A resistor R a is in series with a voltage source V a . Draw the circuit. Label die voltage across<br />
die combination as v and the current as /. Draw and label the volt-ampere characteristic (I<br />
versus v).<br />
3.12 Draw the circuit diagram of a half-wave rectifier for producing a nearly steady dc voltage<br />
from an ac source. Include a transformer to adjust the voltage level. Draw two different fullwave<br />
circuits.<br />
3.13 What is a clipper circuit Draw an example circuit diagram including component values, an<br />
input waveform, and the corresponding output waveform.<br />
3.14 Repeat Question 3.13 for a clamp circuit.<br />
3.15 Draw die circuit diagram of a two-input diode OR gate. Repeat for an AND gate.<br />
3.16 Logic 1 voltages for a digital system are defined as being larger than 3V. Consider a number<br />
k of two-input OR gates employing silicon diodes. Connect one input of each gate to the<br />
ground (logic 0). Cascade the gates such diat the output of a gate is connected to the<br />
remaining input of another gate that follows in the cascade. Apply the 5-V voltage to die input<br />
and measure die output of the cascade. At what value of k die output voltage can not be<br />
recopiized as logic 1<br />
3.17 Try to construct a logic inverter using diodes. Can you succeed Based on results you<br />
obtained answering Questions 3.16 and 3.17, describe two serious drawbacks of diode logic<br />
circuits.<br />
3.18 Of what does die small-signal equivalent circuit of a diode consist<br />
3.19 How is the dynamic resistance of a nonlinear circuit element determined at a given<br />
operating point<br />
3.20 Sketch die voltage and current waveforms corresponding to large-signal diode switching.<br />
Define and explain the delay times in die diode response.<br />
3.21 What is die Schottky diode What are its properties and applications<br />
3.22 Explain die difference between the photodiode and solar cell.<br />
3.23 What is die construction of an optical isolator List applications of diis device diat are<br />
known to you.<br />
Chapter 4: FET Circuits<br />
4.1 Sketch the simplified physical structure of an »-channel JFET. Label the terminals and die<br />
channel region. Draw the corresponding circuit symbol.<br />
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Analog Electronics /Review Questions<br />
4.2 In normal operation, what bias condition exists between gate and channel of JFET<br />
4.3 Define the pinch-off voltage and I DSS of a JFET.<br />
4.4 Write an equation for the drain current of a JFET in the saturation (pinch-off) in terms of<br />
device voltages.<br />
4.5 Sketch the characteristics of an «-channel JFET. Label the saturation, linear and cutoff<br />
regions. Repeat for the/>-channel device.<br />
4.6 Give the ranges of v GS and v GD in terms of the pinch-off voltage V p for each region (cutoff,<br />
saturation and linear) of an »-channel JFET and depletion MOSFET.<br />
4.7 Sketch the physical structure of an ^-channel depletion MOSFET. Label the terminals and<br />
the channel region. Draw the corresponding circuit symbol. Repeat for a ^-channel<br />
enhancement MOSFET.<br />
4.8 Explain the physical origin of the variations in FET parameters with temperature.<br />
4.9 What is "gate protection" for a MOSFET Why is it necessary<br />
4.10 Draw the load line for a simple FET amplifier.<br />
4.11 Why does nonlinear distortion occur in FET amplifiers<br />
4.12 Draw the diagram of the fixed-bias circuit, the self-bias circuit and the fixed- plus self-bias<br />
circuit for a FET. In general, which circuit maintains the most constant drain current from<br />
device to device Which shows the greatest variation Which is used for enhancement<br />
devices Why<br />
4.13 Draw the small-signal equivalent circuit for the FET including r^<br />
4.14 Give definitions of^n and r rf as partial derivatives.<br />
4.15 Draw the circuit diagram of a resistance-capacitance coupled common-source amplifier.<br />
Repeat for the source follower. Which amplifier would be used if a voltage gain magnitude<br />
larger than unity is needed Which would be used to obtain low output resistance<br />
4.16 Draw the circuit diagram of the FET amplifier most useful if extremely high input resistance<br />
is required.<br />
4.17 What is the function of coupling capacitors With what are they replaced in a midband<br />
small-signal equivalent circuit In general, what effect do the coupling capacitors have on the<br />
gain of the amplifier as a function of frequency<br />
4.18 Compare gain, bandwidth, input and output impedance values of basic FET amplifier<br />
configurations.<br />
4.19 What is the value of ^n for V DS =0 Draw the small-signal equivalent circuit at this bias<br />
point. For what applications is the FET used at this bias point<br />
4.20 Draw the circuit diagram of a CMOS inverter. Repeat for a two-input NOR gate.<br />
4.21 Of what does the input impedance of a CMOS inverter consist<br />
4.22 What is the static power consumption of CMOS gates<br />
4.23 Draw the circuit diagram of the CMOS transmission gate.<br />
4.24 Draw the dynamic circuit model of the »-channel JFET. Repeat for/(-channel device and all<br />
kinds of MOSFET transistors.<br />
4.25 Explain how the channel-length modulation effect is incorporated into the SPICE model of<br />
the FET.<br />
Chapter 5: BJT Circuits<br />
5.1 Draw the circuit symbol for an npn BJT. Label the terminals and the currents. Choose<br />
reference directions that agree with the true current direction for operation in the active<br />
region.<br />
5.2 Repeat Question 5.1 for zpnp transistor.<br />
5.3 In normal operation, which type of bias (forward or reverse) is applied to the emitter-base<br />
junction The collector-base junction<br />
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Analog Electronics /Review Questions<br />
5.4 To forward-bias apn junction, which side of the junction should be connected to the positive<br />
voltage<br />
5.5 Write the Shockley equation for the emitter current of an npn transistor.<br />
5.6 Give the definition of a and p for a BJT. What bias conditions for each junction are assumed<br />
in diese definitions<br />
5.7 Sketch the input characteristic curve for a typical small-signal silicon npn BJT at room<br />
temperature. Sketch the output characteristic curves if P = 100. Isabel the cutoff, active and<br />
saturation regions.<br />
5.8 Draw the load lines on the input and output characteristic planes of the npn BJTfor a simple<br />
amplifier. Repeat for thepnp device.<br />
5.9 Why does distortion occur in BJT amplifiers<br />
5.10 Sketch the output characteristics of a BJT, illustrating the Early voltage and collector<br />
breakdown.<br />
5.11 Explain the base-width modulation effect.<br />
5.12 Discuss the BJT parameter variation with temperature.<br />
5.13 What is the typical extreme variation of P from unit to unit for a given type of BJT<br />
5.14 How does v Bh vary with temperature for a fixed emitter current Assume a small-signal<br />
silicon transistor.<br />
5.15 Draw the large-signal dc circuit model for a silicon npn transistor in the active region at<br />
room temperature. Include the constraints of currents and/or voltages that guarantee<br />
operation in the active region. Repeat for the saturation region. Repeat for the cutoff region.<br />
5.16 Repeat Question 5.12 for &pnp transistor.<br />
5.17 In the active region, how is the base-collector junction biased (forward or reverse) How is<br />
the base-emitter junction biased<br />
5.18 Repeat Question 5.14 for the saturation region.<br />
5.19 Repeat Question 5.14 for the cutoff region.<br />
5.20 Briefly discuss the procedure for dc analysis of a BJT circuit using the large-signal circuit<br />
models.<br />
5.21 Draw the fixed base bias circuit. What is the principal reason that this circuit is unsuitable<br />
for mass production of amplifier circuit<br />
5.22 Draw the four-resistor bias circuit for the BJT. Give the rule-of-thumb design guidelines for<br />
this circuit.<br />
5.23 Whv are coupling capacitors often used to connect the signal source and the load to<br />
amplifier circuits Should coupling capacitors be used if it is necessary to amplify dc signals<br />
Explain.<br />
5.24 Draw the small-signal equivalent circuit for the BJT.<br />
5.25 Give the formula for determination of r x , assuming that P and the Q-point are known.<br />
5.26 Draw the circuit diagram of a common-emitter amplifier circuit that uses the four-resistor<br />
biasing network. Include a signal source and a load resistance.<br />
5.27 Repeat Question 5.23 for an emitter follower. What resistance did you omit from the bias<br />
Why<br />
5.28 For a small-signal midband analysis of an amplifier, with what do we replace the coupling<br />
capacitors Dc voltage sources Dc current sources Very large inductors<br />
5.29 Outline the small-signal analysis procedure to find the output resistance of an amplifier.<br />
5.30 What are three important features in the structure of a BJT for high P (i.e., for the base<br />
current to be small compared to the collector current in the active region of operation) ,<br />
5.31 Sketch the common-emittet input characteristics of an npn transistor. Indicate the effect of<br />
base width modulation.<br />
5.32 Prepare a table showing the bias conditions (forward or reverse) for the collector junction in<br />
each of the four regions of operation of a BJT.<br />
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Analog Electronics /Review Questions<br />
5.33 Draw the common-emitter h-parameter equivalent circuit for the BJT, labeling each<br />
parameter.<br />
5.34 Draw the hybrid-7l model for the BJT. Characterize each element of the circuit.<br />
5.35 Discuss the P dependence of frequency.<br />
4.26 Compare gain, bandwidth, input and output impedance values of basic BJT amplifier<br />
configurations.<br />
5.36 What is the cascode amplifier What are its properties<br />
5.37 Draw the Ebers Moll dynamic model for the BJT. Characterize each element of the model.<br />
5.38 Draw the circuit diagram of an RTL inverter. Sketch a positive input pulse and the<br />
corresponding output voltage. Label the delay time, the rise time, the storage time, and the fall<br />
time.<br />
5.39 For fast switching, do we want a BJT with a thin base region or a thick base region<br />
Explain.<br />
5.40 Draw the circuit diagram of an RTL inverter including a speed up capacitor and a Schottky<br />
clamp diode. Discuss how the Schottky clamp diode improves switching time.<br />
5.41 What is the function of the rt buried layer under the collector region of an npn BJT on an<br />
IC<br />
Chapter 6: Feedback Circuits<br />
6.1 List four benefits that potentially result from the use of negative feedback.<br />
6.2 What problems are associated with positive feedback in amplifiers<br />
6.3 Under what condition is feedback able to reduce nonlinear distortion Draw the feedback<br />
amplifier circuit and derive appropriate expression.<br />
6.4 Define signal-to-noise ratio. Under what condition is feedback able to improve signal-tonoise<br />
ratio Draw the feedback amplifier circuit and derive appropriate expression.<br />
6.5 Define the following terms: voltage feedback, current feedback, series feedback and parallel<br />
feedback.<br />
6.6 Describe a way to test a circuit for the presence of voltage feedback. Draw a schematic<br />
diagram of such a feedback circuit. Repeat for current feedback.<br />
6.7 In a series feedback, we usually consider the input signal to be a voltage. Explain why. In a<br />
parallel feedback we usually consider the input signal to be a current. Explain why.<br />
6.8 Sketch the circuit diagram of the simple class B amplifier that was discussed in this chapter.<br />
What causes crossover distortion in this circuit<br />
6.9 List four types of feedback and give the appropriate amplifier gain parameter for each type.<br />
Also give the units of P for each type.<br />
6.10 What type of negative feedback should be employed to increase input impedance To<br />
reduce input impedance<br />
6.11 What type of negative feedback should be employed to make the amplifier output behave<br />
as a nearly ideal voltage source As a nearly ideal current source<br />
6.12 What type of (negative) feedback should be used to obtain a nearly ideal current amplifier<br />
Transconductance amplifier Voltage amplifier Transresistance amplifier<br />
6.13 Draw the circuit diagram of a negative feedback amplifier, including a resistive feedback<br />
network for series current feedback; for parallel current feedback; for series voltage feedback;<br />
for parallel voltage feedback. In each case give the value of the feedback ratio in terms of the<br />
resistor values. Assume an amplifier having a differential input.<br />
6.14 In series feedback we usually try to select small values for the resistors in the feedback<br />
network. Explain why.<br />
6.15 In parallel feedback we usually try to select large values for the resistors in the feedback<br />
network. Explain why.<br />
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Analog Electronics /Review Questions<br />
6.16 In voltage feedback we usually try to select large values for the feedback resistors. Explain<br />
why.<br />
6.17 In current feedback we usually try to select small values for the feedback resistors. Explain<br />
why.<br />
6.18 Define gain margin and phase margin for a feedback amplifier.<br />
6.19 What are the rule-of-thumb minimum values of gain margin and phase margin used in<br />
design of feedback amplifiers<br />
6.20 Can a single-pole amplifier become unstable if negative feedback having constant feedback<br />
ratio P is employed<br />
6.21 Explain the Barkhausen criterion of oscillations in a feedback circuit.<br />
6.22 Draw the circuit diagram of a Wien-bridge oscillator. Explain its operation.<br />
6.23 Draw the circuit diagram of a Wien-bridge oscillator. Explain its operation.<br />
6.24 Explain the role of amplitude limiters in oscillator circuits. Draw schematic diagrams of<br />
diode and FET limiters circuits used to stabilize the output waveform generated by a Wienbridge<br />
oscillator.<br />
6.25 Draw a block diagram of LC oscillators. Modify it to obtain (a) Collpits, and (b) Hartley<br />
oscillator.<br />
6.26 Briefly describe the piezoelectric effect.<br />
6.27 What is a crystal as the term used in relation to oscillator circuits<br />
6.28 Draw the equivalent circuit of a crystal and sketch its reactance versus frequency. Label the<br />
series resonant frequency and the parallel resonant frequency.<br />
6.29 A crystal has a fundamental mode at 10 MHz. What is the approximate frequency of the<br />
second overtone Third overtone<br />
6.30 Briefly discuss the way to use quartz crystal to stabilize the frequency of a conventional LC<br />
oscillator.<br />
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Analog Electronics /Problems<br />
Problems<br />
Chapter 1: Introduction<br />
1.1 A sinusoidal signal source has an open-circuit voltage of 10 mV and a short-circuit current of<br />
10 u A. What is the source resistance<br />
1.2 Give expressions for the sine-wave voltage signals having:<br />
(a) 10-V peak amplitude and 10-kHz frequency,<br />
(b) 120-V rms and 60-Hz frequency,<br />
(c) 0.2-V peak-to-peak and 1000-rd/s frequency,<br />
(d) 100-mV peak and 1-ms period.<br />
1.3 Illustrate the composition of a square-wave signal by sketching the first four terms of its<br />
Fourier series and then by performing graphical summations.<br />
1.4 For a square-wave audio signal, what fraction of the available signal energy is perceived by an<br />
average adult listener of age 40 whose hearing extends only to 16 kHz<br />
1.5 What fraction of the energy contained in a square wave of frequency / and peak-to-peak<br />
amplitude U is contained in the harmonic at frequency 9ft<br />
Chapter 2: Amplifiers<br />
2.1 A signal source with an open-circuit voltage of V s = 2mV rms and an internal resistance of<br />
50kA is connected to the input terminals of an amplifier having an open-circuit voltage gain of<br />
100, an input resistance of lOOkQ and an output resistance of 4Q. A 4-fi load is connected to the<br />
output terminals. Find the voltage gains A„ = vjv t and A r - vjv t Also find the current gain and<br />
the power gain.<br />
2.2. A certain amplifier has an open-circuit voltage gain of unity, an input resistance of 1MQ, and<br />
an output resistance of 100Q. The signal source has an internal voltage of 5mV rms and an<br />
internal resistance of lOOkfl. The load resistance is 50£X If the signal source is connected to the<br />
amplifier-input terminals and the load is connected to the output terminals, find the voltage<br />
across the load and the power delivered to the load. Next consider connecting the load direcdy<br />
across the signal source without the amplifier and again find the voltage and power. Compare the<br />
results. What do you conclude about the usefulness of a unity-gain amplifier in delivering power<br />
to the load<br />
2.3. An amplifier has an open-circuit voltage gain of 100. With a 10-kQ load connected, die<br />
voltage gain is found to be only 90. Find the output resistance of the amplifier.<br />
2.4. The output voltage v, of the circuit of Fig. P2.4 is lOOmV with the switch closed. With the<br />
switch open, the output voltage is 50mV. Find the input resistance of the amplifier.<br />
4-r"T-4-(><br />
v,(0<br />
—c<br />
Figure P2.4<br />
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Analog Electronics /Problems<br />
2.5. Two amplifiers have the characteristics shown in Table P2.5. If the amplifiers are cascaded in<br />
order A-B, find the input impedance, output impedance and an open-circuit voltage gain of the<br />
cascade. Repeat if die order is B-A.<br />
2.6 A certain amplifier has an input voltage of lOOmV rms, an input resistance of lOOkfl, and<br />
produces an output of lOVrms across an 8-Q resistance. The power supply has a voltage of 15V<br />
and delivers an average current of 2A. Find the power dissipated in die amplifier and the<br />
efficiency of the amplifier.<br />
2.7. An amplifier has an input voltage of lOmV rms and an output voltage of 5V rms across a 10-<br />
Q load. The input current is l^iA rms. Find the input resistance. Find the voltage gain, current<br />
gain and power gain as ratios and in decibels.<br />
2.8. An amplifier has a voltage gain of 30dB and a current gain of 70dB. What is the power gain<br />
in decibels If the input resistance is 100k£2, what is the load resistance<br />
2.9. Find the voltage across a 50-fi resistance corresponding to (a) lOdBV, (b) -30dBV, (c) 10<br />
dBmV, (d) 20dBW.<br />
2.10. Find the power levels in watts corresponding to (a) 20dBm, (b) -60dBW, and (c) lOdBW.<br />
2.11. An amplifier has an input resistance of lOOCt, an output resistance of 10Q, and a shortcircuit<br />
current gain of 500. Draw the current and voltage amplifier models for the amplifier,<br />
including numerical values of all parameters. Repeat for transconductance and transtesistance<br />
models.<br />
2.12. Amplifier A has an input resistance of 1MQ, an output resistance of 200Q and an opencircuit<br />
transresistance gain of 100MQ. Amplifier B has an input resistance of 50fi, an output<br />
resistance of 500k£2 and a short-circuit current gain of 100. Find the voltage amplifier model for<br />
the cascade of A followed by B. Find the corresponding transconductance amplifier model.<br />
2.13 Repeat Problem 2.12 if the order of the cascade is changed to B-A.<br />
2.14. An ideal transconductance amplifier having a short-circuit transconductance gain of 0.1 S is<br />
connected as shown in Fig. P2.14. Find the resistance JR,,= vji x seen at the input terminals.<br />
Figure P2.14<br />
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Analog Electronics /Problems<br />
2.15. Repeat Problem 2.14 if the amplifier has an input resistance of lkft, an output resistance of<br />
20Q and an open-circuit transresistance gain of 1 Okfi.<br />
2.16. An amplifier has an input resistance of 1Q, an output resistance of 1Q, and an open-circuit<br />
voltage gain of 10. Classify this amplifier as an approximate ideal type and find the corresponding<br />
gain parameter. In deciding of an amplifier classification, assume that the source and load<br />
resistances are on the order of lkQ.<br />
2.17. Repeat Problem 2.16 if the input resistance is 1MQ, the output resistance is lMft, and the<br />
open-circuit voltage gain is 100.<br />
2.18. In a certain application, an amplifier is needed to sense an open-circuit voltage of a source<br />
and force current to flow through a load. The source and load resistances are variable. The<br />
current delivered to the load is to be nearly independent of both the source resistance and load<br />
resistance. What type of amplifier is needed If the source resistance varies from 1 to 2kQ and<br />
this causes a 1-% decrease in load current, what is the value of the input resistance If the load<br />
resistance varies from 100 to 300Q and this causes a 1-% decrease in load current, what is the<br />
value of the output resistance<br />
2.19. The input signal to an amplifier is v,(t) = 0.01COS(2000TI/) + 0.02cos(40007t/). The gain of the<br />
amplifier as a function of frequency is given by<br />
100<br />
A ~ \ + j(f/1000)<br />
Find an expression for the output signal of the amplifier as a function of time.<br />
2.20. The input signal to an amplifier is the same as in Problem 2.19. The complex gain of the<br />
amplifier at lOOOHz is 100Z-45 0 . What complex value must the gain have at 2000Hz for<br />
distortionless amplification<br />
2.21. Consider the simple low-pass filter shown in Fig. P.21.<br />
(a) Find the complex gain A = V2I Fir as a function of frequency. What are the magnitudes of A<br />
at dc and at very high frequencies Find the half-power bandwidth B of the circuit in terms of R<br />
and C.<br />
(b) Consider the case for which the capacitor is initially uncharged and v,{l) is a unit step function.<br />
Find v 2 (t) and an expression for its rise time t r in terms of R and C.<br />
(c) Combine the results found in parts (a) and (b) to obtain a relationship between bandwidth and<br />
rise time for the circuit. Compare the results to Equation (2.22).<br />
R<br />
—O<br />
Figure P.21 Low-pass filter<br />
2.22. Consider the simple high-pass filter shown in Fig. P.22a.<br />
(a) Find the complex gain A = V2I Vt as a function of frequency.<br />
(b) What is the magnitude of the gain at dc At very high frequencies Find the half-power<br />
frequency in terms of R and C.<br />
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Analog Electronics /Problems<br />
(c) Consider the input signal shown in Fig. P.22b. Assuming that the capacitor is initially<br />
uncharged, find an expression for the output voltage v^t) for / between 0 and T. Assuming diat<br />
RC is much greater than T, find an approximate expression for percentage tilt<br />
(d) Combine the results of parts (b) and (c) to find relationship between percentage tilt and halfpower<br />
frequency.<br />
v;(0<br />
0 T t<br />
(a)<br />
(b)<br />
Figure P22 High-pass filter (a), its input signal (b)<br />
2.23. An audio amplifier is specified to have half-power frequencies of 15Hz and 15kHz. The<br />
amplifier is to be used to amplify the pulse shown in Fig. P.22b. Estimate the rise time and<br />
percentage tilt of the amplifier output The pulse width T is 2ms.<br />
2.24. The gain magnitudes of several amplifiers are shown versus frequency in Fig. P.24. If the<br />
input to the amplifiers is the pulse shown in the figure, sketch the output of each amplifier versus<br />
time. Give quantitative estimates of as many features of each waveform as you can.<br />
A(/)<br />
(a)<br />
100kHz<br />
Figure P24<br />
2.25. The input signal and the corresponding output are shown for several amplifiers in Fig. P.25.<br />
Sketch the gain magnitude of each amplifier versus frequency. Give quantitative estimates of as<br />
many features on die gain sketches as you can.<br />
2.26. (a) A 1-kHz sinusoid is applied to the input of a nonlinear amplifier. list the frequencies of<br />
at least six frequency components that might be present at the amplifier output.<br />
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Analog Electronics /Problems<br />
(b) Repeat if the input is the sum of a 1-kHz sinusoid and a 1.1-kHz sinusoid.<br />