UM10211 - Standard ICs

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NXP Semiconductors UM10211 LPC2364/66/68/78 User manual Revision history Rev Date Description 01 20070327 Changes made to the 20061013 edition: • V DD(1V8) pins are left unconnected • Deep power-down mode removed 01 20061013 Changes made to 20061006 edition: • Flash memory programming firmware chapter updated 20061006 Changes made to 20061002 edition: • Pad structure details added in Table 8–79 “LPC2364/66/68 pin description” and Table 8–80 “LPC2378 pin description” • order of the “On-Chip RAM“ elements adjusted in Table 2–3 “LPC2300 memory usage” 20061002 Preliminary LPC234/6/8/78 User manual Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com UM10211_1 © NXP B.V. 2007. All rights reserved. User manual Rev. 01 — 27 March 2007 2 of 613
UM10211 Chapter 1: Introductory information Rev. 01 — 27 March 2007 User manual 1. Introduction 2. Features LPC2364/6/8/78 is an ARM-based microcontroller for applications requiring serial communications for a variety of purposes. These microcontrollers incorporate a 10/100 Ethernet MAC, USB 2.0 Full Speed interface, four UARTs, two CAN channels, an SPI interface, two Synchronous Serial Ports (SSP), three I 2 C interfaces, an I2S interface, and a MiniBus (LPC2378 only: 8-bit data/16-bit address parallel bus). Important: Term “LPC2300“ in the following text will be used as a generic name for all four parts covered with this user manual: LPC2364, LPC2366, LPC2368, and LPC2378. Only when needed, a specific device name will be used to single out one of them. • ARM7TDMI-S processor, running at up to 72 MHz. • Up to 512 kB on-chip Flash Program Memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. Single Flash sector or full chip erase in 400 ms and 256 bytes programming in 1 ms. Flash program memory is on the ARM local bus for high performance CPU access. • Up to 32 kB of SRAM on the ARM local bus for high performance CPU access. • 16 kB Static RAM for Ethernet interface. Can also be used as general purpose SRAM. • 8 kB Static RAM for USB interface. Can also be used as general purpose SRAM. • Dual AHB system that provides for simultaneous Ethernet DMA, USB DMA, and program execution from on-chip Flash with no contention between those functions. A bus bridge allows the Ethernet DMA to access the other AHB subsystem. • External memory controller that supports static devices such as Flash and SRAM. An 8-bit data/16-bit address parallel bus is available in LPC2378 only. • Advanced Vectored Interrupt Controller, supporting up to 32 vectored interrupts. • General Purpose AHB DMA controller (GPDMA) that can be used with the SSP serial interfaces, the I2S port, and the SD/MMC card port, as well as for memory-to-memory transfers. • Serial Interfaces: – Ethernet MAC with associated DMA controller. These functions reside on an independent AHB bus. – USB 2.0 Device with on-chip PHY and associated DMA controller. – Four UARTs with fractional baud rate generation, one with modem control I/O, one with IrDA support, all with FIFO. These reside on the APB bus. – Two CAN channels with Acceptance Filter/FullCAN mode reside on the APB bus. – SPI controller, residing on the APB bus. – Two SSP controllers with FIFO and multi-protocol capabilities. One is an alternate for the SPI port, sharing its interrupt and pins. The SSP controllers can be used with the GPDMA controller and reside on the APB bus. UM10211_1 © NXP B.V. 2007. All rights reserved. User manual Rev. 01 — 27 March 2007 3 of 613
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UM10211 - Standard ICs

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