Visual System Simulator™

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Visual System Simulator (additional positioning line AXIEM here ???) White Paper of input data. When sampled appropriately, this leads to a nearly unmanageable number of spectral frequencies that must be solved for simultaneously using HB techniques. In addition, when designers need to simulate memory effects using HB simulation techniques, the aperiodicity must first be reformulated as a predictable signal. This can result in correlation effects (that are not part of the actual physical phenomena) that can then cause inaccuracies. Additionally, today’s designs need to include feedback that allows the circuit simulation to be controlled by the system simulation using previous circuit-simulation time samples. Unfortunately, this type of cosimulation cannot be performed with a steady-state HB circuit simulator, but it can be achieved by using time-domain techniques. TIME DOMAIN TECHNIQUES Time domain simulation enables designers to capture dynamic operating phenomena such as memory effects, and it is traditionally done using a transient, SPICE-type solver, which unlike HB, requires the entire waveform to be sampled. So, for example, a 5 MHz modulated signal on a 2 GHz carrier would need an integer multiple (N) of 2 GHz as a sampling frequency. If the simulated signal frame is 10 ms long, then the simulation engine must simulate N*2 GHz*10ms or N*2e7 samples to achieve results. Certainly, this technique will produce a solution, but since it requires a large number of time steps, designers can expect the simulation to run for a long time. ENTER CIRCUIT ENVELOPE Unlike HB, time-domain techniques can capture the non-periodic dynamic operating-point information that is required for simulating memory effects. Specifically, circuit envelope simulation presumes that the input waveform has somewhat different characteristics and it samples only the modulation envelope (instead of the RF carrier). So, in the previous example, this translates into N*5 MHz*10ms or N*5e4 samples, which is a 400x reduction in the number of time steps. In a circuit envelope simulation, as implemented within AWR 2011, each time sample must solve the harmonic balance equations at the modulation carrier and related harmonic frequencies. So, while a single time sample in envelope takes more time than a single SPICE transient time point (typically 10- 100x slower), the 400x reduction in time samples results in a 4-40x improvement for circuit envelope simulation time when compared to that of SPICE. Nonetheless, as the modulation bandwidth increases, the benefits of circuit envelope simulation do decrease. So, for very wideband modulation, a SPICE-type simulation approach can be faster. Given that AWR’s Visual System Simulator (VSS) samples the modulation envelope while creating, demodulating, and analyzing modulated waveforms such as LTE and 802.11ac it makes for a great co-simulation toolset for circuit envelope simulation. With AWR’s circuit envelope simulation feature and VSS, designers can place N-port Microwave Office circuit schematics directly into VSS system diagrams, simulate, and analyze how it behaves in the presence of modulated waveforms. A designer can also consider dynamic voltages and currents, which will enable the simulation of power-added efficiency (PAE). Within the AWR design environment, it is also possible to quickly switch between simulation and analysis techniques, enabling linear, HB, transient, and circuit envelope simulation to coexist – all within the same schematic. Circuit envelope simulation is effectively a time-domain technique, so it is necessary to specify voltage and current probe points on the schematic. The example shown in Figure 1 is of Infineon Technologies’ ELMO models for LD9-based smart discrete devices. In this design, traditional input/ output ports for the design are handled by PORT elements, but additional probes can be placed at the drain and in the Figure 1: Circuit level hierarchical schematic of Infineon power amplifier with RF and DC ports for circuit envelope simulation.
Visual System Simulator (additional positioning line AXIEM here ???) White Paper DC bias path to monitor RF and DC voltage and current. Designers can also incorporate other time-domain criteria such as dynamic bias amplifiers, bias turn-down, or active equalization into the simulation. 4G PA DESIGN EXAMPLE Before including the PA in a circuit envelope test bench in VSS software, the designer needs a Microwave Office design/project. The subcircuit element representing the PA design (Figure 2) has a typical PORT input driven by a source and a corresponding PORT output.The element is also augmented by additional pins defined by the named connectors. Using the envelope schematic, designers can construct a complete PA from its constituent parts. Then, using Visual System Simulator software, the designer can combine the simulated device with other functions, such as digital pre-distortion, filtering, and antenna and channel models. The software allows port definitions to be added to the element that describe port functionality relative to the circuit simulation. This allows the input port(s), output ports, and DC or bias input lines to be controlled and monitored. Total DC power dissipation can be monitored as a separate port, calculated within the Microwave Office simulation and sent to VSS for analyses of power-added efficiency and other DC-related parameters. Specifically, the FCOUTSPEC parameter specifies which harmonic envelope is to be simulated. To complete the design, RF source and signal blocks combined with a vector signal analyzer (VSA) block can be used to determine simulation criteria. A more complex design might include dynamic biasing, active time-domain circuitry, MAC or PHY layer control, or even feedback. These options are simply not possible with linear or HB analyses alone. In Figure 3, a digital pre-distortion circuit precedes the Microwave Office PA in the signal path to create a more efficient, highly-linear design. Even this simulation would not be possible using only a time-domain or HB simulator. Figure 2: Circuit envelope nonlinear simulation-based instance of Infineon power amplifier. Figure 3: Complete VSS diagram with circuit envelope co-simulation and predistortion. The analysis results provide all of the information for system and circuit co-design without constraints on the simulation techniques used (Figure 4). With this approach, designers can perform time-domain circuit envelope and steady-state frequency domain analyses, analyzing harmonic content, spectral masks, ACPR, EVM, Pin-versus-Pout curves, and gain in a single environment. As a next step, designers
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