P89V51RB2/RC2/RD2 8-bit 80C51 5 V low power 16/32 ... - NetMedia

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NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core Table 33. WDTC - Watchdog control register (address COH) bit allocation Bit addressable; Reset value: 00H Bit 7 6 5 4 3 2 1 0 Symbol - - - WDOUT WDRE WDTS WDT SWDT Table 34. WDTC - Watchdog control register (address COH) bit description Bit Symbol Description 7 to 5 - Reserved for future use. Should be set to ‘0’ by user programs. 4 WDOUT Watchdog output enable. When this bit and WDRE are both set, a Watchdog reset will drive the reset pin active for 32 clocks. 3 WDRE Watchdog timer reset enable. When set enables a watchdog timer reset. 2 WDTS Watchdog timer reset flag, when set indicates that a WDT reset occurred. Reset in software. 1 WDT Watchdog timer refresh. Set by software to force a WDT reset. 0 SWDT Start watchdog timer, when set starts the WDT. When cleared, stops the WDT. 6.9 PCA The PCA includes a special 16-bit Timer that has five 16-bit capture/compare modules associated with it. Each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or PWM. Each module has a pin associated with it in port 1. Module 0 is connected to P1.3 (CEX0), module 1 to P1.4 (CEX1), etc. Registers CH and CL contain current value of the free running up counting 16-bit PCA timer. The PCA timer is a common time base for all five modules and can be programmed to run at: 1 ⁄ 6 the oscillator frequency, 1 ⁄ 2 the oscillator frequency, the Timer 0 overflow, or the input on the ECI pin (P1.2). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (see Table 35 and Table 36). 16 bits MODULE0 P1.3/CEX0 16 bits MODULE1 P1.4/CEX1 PCA TIMER/COUNTER MODULE2 P1.5/CEX2 time base for PCA modules Module functions: - 16-bit capture - 16-bit timer - 16-bit high speed output - 8-bit PWM - watchdog timer (module 4 only) MODULE3 MODULE4 P1.6/CEX3 P1.7/CEX4 002aaa532 Fig 21. PCA P89V51RB2_RC2_RD2_4 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 04 — 1 May 2007 46 of 80
NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core In the CMOD SFR there are three additional bits associated with the PCA. They are CIDL which allows the PCA to stop during Idle mode, WDTE which enables or disables the Watchdog function on module 4, and ECF which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows. The watchdog timer function is implemented in module 4 of PCA. The CCON SFR contains the run control bit for the PCA (CR) and the flags for the PCA timer (CF) and each module (CCF4:0). To run the PCA the CR bit (CCON.6) must be set by software. The PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software. Bits 0 through 4 of the CCON register are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags can only be cleared by software. All the modules share one interrupt vector. The PCA interrupt system is shown in Figure 22. Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. The registers contain the bits that control the mode that each module will operate in. The ECCF bit (from CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on the module) enables the CCFn flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module (see Figure 22). PWM (CCAPMn.1) enables the pulse width modulation mode. The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module’s capture/compare register. The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module’s capture/compare register. The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output. P89V51RB2_RC2_RD2_4 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 04 — 1 May 2007 47 of 80
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