PCM - und Test - Daten von ASIC

PCM - und Test - Daten von ASIC 

Autor : Peter Annaheim CSEE SA 

TLD2000 MSR 27. Sep. 2000 20:10 

Wenn alles so funktioniert wie geplant, benötigt man nicht viele Daten. Sobald 

aber schlechte Ausbeuten bei der Herstellung von ASIC auftreten oder 

Ausfälle im Feld auftreten, möchte man gerne weitere Daten zur Analyse 

beiziehen. Meist sind solche vorhanden, aber es ist nicht bekannt, dass diese 

verlangt werden könnten. 

Während der Herstellung beim Foundry müssen bereits die Prozessparameter 

überwacht werden. Am Ende der Herstellung wird überprüft, ob die Wafer zu 

gebrauchen sind oder nicht. Dazu sind auf jedem Wafer Process Control 

Monitors (PCM) aufgebracht. Früher meist als Chip, heute bedingt durch die 

Belichtungsmethode mit Stepper, am Rand von Chips. 

Auf dem PCM befinden sich Referenztransistoren, Widerstände und 

Kapazitäten die ausgemessen und protokolliert werden. Im Folgenden finden 

Sie ein Beispiel der Firma Zetex von Bipolar Arrays. (Im Internet unter 

www.700series.com zu finden). 

In dem darauf folgenden Test der Kundenspezifischen Schaltung (ASIC) 

können, nach Absprache mit dem Kunden, Messdaten erfasst und protokolliert 

werden, so dass im Bedarfsfall Daten zur Analyse vorhanden sind. 

Ungenügend wäre es, lediglich eine Aussage über die Ausbeute (go-nogo) zu 

erfassen. 

CSEE SA CH 2000 Neuchâtel ) 032 / 729 11 30 3 032 / 729 11 39 info@csee.ch

Production Flow 

E:\CSEE\DOK\SEMINARE\PRODUCTION FLOW.VSD PETER ANNAHEIM 25.9.00 

Manufacturer Acceptance Parameter 

E:\CSEE\DOK\SEMINARE\MAP.VSD PETERANNAHEIM 21.09.00 

Manufacturing Acceptance Parameters (MAP) 

Grow silicon cristal 

Slice crystal into wafers 

Polish and inspect wafers 

Ion implant or diffuse and 

apply conducting layers 

Etch wafer to remove 

photoresist 

Develop, rinse and bake wafer 

Repeat steps 12 - 15 for successive masking layers 

Oxidize wafers 

Apply photoresist to 

wafers and bake 

Align working mask with wafer 

and expose 

Process Control Monitors 

(PCM) 

Scribe Line Monitors 

(SLM) 

CSEE SA CH 2000 Neuchâtel info@csee.ch 

CSEE SA CH 2000 Neuchâtel info@csee.ch

Wafer with PCM 

E:\CSEE\DOK\SEMINARE\WAFERWITHPCM.VSD PETERANNAHEIM 22.09.00 

Testpattern 700 Series 

E:\CSEE\DOK\SEMINARE\TESTPATTERN700SERIES.VSD PETERANNAHEIM 23.09.00 

Process Control Monitor 

PCM 



Wafer with Scribe Line Monitors 

E:\CSEE\DOK\SEMINARE\WAFERWITHSLM.VSD PETERANNAHEIM 22.09.00 

Zetex Test Pattern (PCM) Evaluation 

700 Series Linear Bipolar Arrays 

Limits File: Extract CA700 SERIES Limits v1.4 21/3/97 

Wafer Identification Number : 

Lot Number : 

Parent Device : 

Device : 

Date : 

2747C7 

F9733C4B 

CA734A 

PROTO 

14/OCT/97 

Flat 

SLM 

at min max 

1 NPN BVCEO 10 uA 20 33.1 32.7 33.5 32.3 32.9 Volts 

2 hFE Ib=1uA, VCE=5V 100 350 133 135 146 183 161 

3 VBE 10 uA 0.700 0.6465 0.6474 0.6447 0.6368 0.6420 Volts 

4 ICEO 20 V 10 0 0 0 0 0 nA 

5 BVEBO 10 uA 5.6 6.1 5. 92 5.91 5.92 5. 94 5.92 Volts 

6 RC 200 85 80 93 91 88 Ohm 

7 PNP BVCEO 10 uA 20 31.7 30.0 29.9 30.4 30.4 Volts 

8 hFE Ib=1uA, VCE=5V 40 120 74 74 81 76 76 

9 ICEO 20 V 10 0 0 0 0 0 nA 

10 LNPN BVCEO 10 uA 20 33.9 33.5 34.2 32. 9 33.5 Volts 

11 hFE Ib=2uA, VCE=5V 40 150 74 75 75 79 77 

12 ICEO 20 V 50 0 0 0 0 0 nA 

13 LPNP BVCEO 10 uA 20 34.7 34.2 33.4 34.9 35.3 Volts 

14 hFE Ib=100uA, VCE=5V 5 22 22 23 22 22 

15 ICEO 20 V 20 0 0 0 0 0 nA 

16 RB R 600 900 660.7 654.5 670.4 661.5 662. 6 Ohm 

17 Delta 5 -0.4 -1.5 -2.3 -2.6 -4.2 % 

Edges from stepper 

Inkpoints indicate bad chips 

18 SD VF 10 uA 300 400 0.374 0.383 0. 382 0.376 0.371 Volts 

19 IR 20 V 50 0 0 0 0 0 nA 

20 RBP Current 5 V 10 150 85 85 71 47 60 uA 

21 REP Current 20 V 1 8 3.8 3.3 4.8 4.4 4.6 uA 

22 METAL R 500 squares 40 19 20 18 18 20 Ohm 

23 JCAP BV 10 uA 9 12.3 10.4 13.1 13.0 12.8 Volts 

24 IR 20 V 50 0 0 0 0 0 nA 

Design Manual Zetex 700 Series Linear Bipolar Semicustom Arrays (V2.0 Dec 96) Chapter 10 E:\CSEE\DOK\Seminare\PCM example.doc 23.Nov.97 16:41 

CSEE SA Ruelle Vaucher 22 CH 2000 Neuchâtel ) 032 / 729 11 30 3 032 / 729 11 39 info@csee.ch 


Binning : Fail-Summary Sentry 

Binning : Fail-Summary Sentry 

E:\CSEE\DOK\SEMINARE\BINNING FAIL-SUMMARY SENTRY.VSD PETER ANNAHEIM 23.09.00 

E:\CSEE\DOK\SEMINARE\BINNING FAIL-SUMMARY SENTRY.VSD PETER ANNAHEIM 23.09.00 

STAT4 14.02.99 15:46 

TEST PROGRAM D251 S/N 14484 

OM1056-3D 95547 WAFER NO 9 

FAIL SUMMARY 

TOTALS: 

TOTAL PASSED 96 30 % 

TOTAL FAILED 222 70 % 

TOTAL TESTED 318 100 % 

STAT4 14.02.99 15:46 

TEST PROGRAM D251 S/N 14484 

OM1056-3D 95547 WAFER NO 9 

FAIL SUMMARY 

TT = 1 4 FAILS 2 % 

TT = 2 110 FAILS 50 % 

TT = 3 5 FAILS 2 % 

TT = 17 43 FAILS 19 % 

TT = 18 18 FAILS 8 % 

TT = 20 26 FAILS 12 % 

TT = 22 11 FAILS 5 % 

TT = 23 5 FAILS 2 % 

PIN = 1 4 FAILS 2 % 




PIN = 11 1 FAILS 0 % 

PIN = 16 6 FAILS 3 % 

PIN = 17 1 FAILS 0 % 

PIN = 59 110 FAILS 50 % 

FCT 90 FAILS 41 % 

IDD standby 

IDD operate 

V doubler 

Continuity 

Shorts 

FCT VDDnom 

FCT VDDmin 

FCT VDDmax 

DCT 

FCT 

96 

222 

318 

TOTALS: 

TOTAL PASSED 96 30 % 

TOTAL FAILED 222 70 % 

TOTAL TESTED 318 100 % 



Binning with measures 

E:\CSEE\DOK\SEMINARE\BINNINGWITHMEASURES.VSD PETERANNAHEIM 23.09.00 

Example of Datalog 

STAT4 08:45 27.OCT99 

TEST PROGRAM YOUR_ASIC S/N 7 

E:\CSEE\DOK\Diag\Datalog short.doc 1. Aug. 2000 15:03 

circuit: XXXX11 SUMMARY: CSEE 04-13-1999 05:40:47 

-------- 

fail_bin: 

fail_cont: 

CONTINUITY : 52 6.3 

SYSTEM : 25 3.0 

PREAMP : 19 2.3 

FILTER.LBP : 10 1.2 

AMP A1 : 3 0.4 

AMP A2 : 27 3.3 

MPO : 0 0.0 

AMP D : 24 2.9 

SQUELCH : 0 0.0 

IN/OUT : 10 1.2 

Circuits tested: 825 

Good devices : 655 79.4 % 

Bad devices : 170 20.6 % 

IDENT:TG9259/02 CSEE 129 

TEST NAME@MIN limit@MAX limit@MEAN@SIGMA@MIN mes@MAX mes 

=========@=========@=========@====@=====@=======@======= 

1.1.1 IP0 @ 8.00E-07@ 1.30E-06@ 1.00E-06@ 2.76E-08@ 9.41E-07@ 1.06E-06 

1.1.3 IVHH @ 2.00E-06@ 5.00E-06@ 3.60E-06@ 3.29E-08@ 3.52E-06@ 3.65E-06 

1.1.4 IVP @ 0.00E+00@ 1.00E-05@ 4.49E-06@ 1.62E-07@ 3.82E-06@ 4.63E-06 

1.1.2 IVSS @-1.50E-07@-2.10E-07@ 3.96E-04@ 8.98E-06@ 3.73E-04@ 4.14E-04 

1.1.5 VAGND @-1.35E+00@-1.25E+00@-1.29E+00@ 3.76E-03@-1.30E+00@-1.28E+00 

1.1.6 MICVCC @-2.50E-01@-1.50E-01@-2.18E-01@ 2.10E-03@-2.23E-01@-2.14E-01 

1.2.1 OUTA0/MIC @ 1.55E+01@ 1.75E+01@ 1.68E+01@ 6.64E-02@ 1.66E+01@ 1.69E+01 

1.2.2 OUTA12/OUTA0 @-1.50E+00@ 5.00E-01@-3.60E-01@ 1.31E-02@-3.95E-01@-3.37E-01 

1.2.3 INA2/OUTA0 @-1.50E+00@ 5.00E-01@-7.08E-01@ 6.36E-02@-8.54E-01@-6.12E-01 

1.2.4 OUTA2/INA2 @-1.50E+00@ 5.00E-01@-6.44E-01@ 6.36E-02@-8.06E-01@-5.27E-01 

1.2.5 OUTMPO @ 5.00E-02@ 7.94E-02@ 6.48E-02@ 1.14E-03@ 6.28E-02@ 6.74E-02 

1.2.7 U(INV)ref @ 1.00E+00@ 1.15E+00@ 1.08E+00@ 6.79E-04@ 1.08E+00@ 1.08E+00 

1.2.8 OUT.NF/OUT.MP@-1.00E+00@ 1.00E+00@ 2.41E-01@ 1.12E-01@ 3.52E-02@ 5.10E-01 

1.2.8.a OUT.NF dist@-3.00E+00@ 3.00E+00@ 8.86E-01@ 1.34E-01@ 7.02E-01@ 1.22E+00 

1.2.9 BUFF/OUTA2 @-5.00E-01@ 1.50E+00@ 6.25E-01@ 4.07E-02@ 5.28E-01@ 7.17E-01 

1.2.10 IVP @ 8.00E-04@ 1.20E-03@ 9.75E-04@ 1.10E-06@ 9.73E-04@ 9.78E-04 

2.1 A0.MICref @ 5.50E+00@ 8.00E+00@ 7.13E+00@ 4.42E-02@ 7.04E+00@ 7.20E+00 

2.2 @ 1.00E+00@ 3.00E+00@ 1.90E+00@ 1.23E-02@ 1.88E+00@ 1.93E+00 

2.3 @ 3.00E+00@ 5.00E+00@ 3.85E+00@ 1.68E-02@ 3.82E+00@ 3.90E+00 

. 

. 

. 

=====> CONTINUITY I= -100.0E-06 

TT= 1 MOD= 0 

INST # PIN MEASURED LT GT 

587 1 -670.0MV -0.200 V -2 V 

593 2 -680.0MV -0.200 V -2 V 

599 3 -680.0MV -0.200 V -2 V 

=====> ISS STAND-BY VSS=-1.800 

TT= 2 MOD= 1 


1406 -8.500E-06 -9.600E-06 

=====> FUNCTION TEST (MIN. SUPPLY) VSS=-1.120 

TT= 7 MOD= 2 

INST= 1602 

LOCAL MEMORY 

LOC COUNT 1 11 21 31 41 

indicate functional errors 

51 

3395 0000000000 0000000000 1100001010 1010000000 0100000000 00./1.0/00 

=====> INPUT LEACKAGE CURRENT VSS=-1.800 

TT= 15 MOD= 1 


2243 2 -99.00NA -70.00NA F 70.00NA **** 

2247 3 -9.000NA -70.00NA 70.00NA 

2251 4 -7.000NA -70.00NA 70.00NA 

=====> OUTPUT LEACKAGE CURRENT VSS=-1.800 

TT= 25 MOD= 1 


2299 28 0 A -200.0UA 200.0UA 

2301 28 -10.00UA -200.0UA 200.0UA 

2305 30 0 A -200.0UA 200.0UA 

2307 30 -10.00UA -200.0UA 200.0UA 

=====> INPUT CURRENT (PULL-DOWN RESISTORS) VSS=-1.550 

TT= 16 MOD= 1 


2478 26 12.30UA 2.000UA 80.00UA 

2481 27 11.50UA 2.000UA 80.00UA 

=====> OUTPUT CURRENT VSS=-1.550 

TT= 26 MOD= 1 


2541 28 1.540MA 1.000MA 2.000MA 

2549 30 1.320MA 1.000MA 2.000MA 

2557 32 1.430MA 1.000MA 2.000MA 

indicate parametric error 


2594 28 -1.320MA -2.000MA -1.000MA 

2602 30 -1.540MA -2.000MA -1.000MA 

2610 32 -1.450MA -2.000MA -1.000MA 


EIR 1........10 FCT DCT 

0000000000 FAIL FAIL EOT 

CSEE SA Ruelle Vaucher 22 CH 2000 Neuchâtel 

) 032 / 729 11 30 2 032 / 729 11 39 info@csee.ch

Shmoo Plot 

tpd = f(VDD) 

E:\CSEE\DOK\SEMINARE\SPLOT TPD.VSD PETER ANNAHEIM 22.09.00 

STAT4 17.12.94 18:54 

TEST PROGRAM L5AD843 S/N 372 

EDGE SHMOO PLOT AT STATEMENT NUMBER 0611 SPLOT RELEASE 16.8 

DPS1 YSTART= 6 V YSTOP= 4 V YDELT= 100.0MV WAS AT= 5 V 

EA1 YSTART= 6 V YSTOP= 4 V YDELT= 100.0MV WAS AT= 5 V 

PD 7 XSTART= 0US XSTOP= 1US XDELT= 20.00NS WAS AT= 700.0NS 

TEST TYPE: 

NORMAL 

DPS1 

LML 

6 V 687 . XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX. . 844 

6.900 V 687 . XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX. . 844 

6.800 V 687 . XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX. . 844 

6.700 V 687 . XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX. . 844 



6.400 V 654 . .XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX. . 643 

6.300 V 532 . .XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX. . 643 

6.200 V 532 . . XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX. . 643 

6.100 V 532 . . XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX. . 544 

5 V 532 > . . XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX. . 544 

5.900 V 489 . . XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX. . 432 

5.800 V 489 . . XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX. . 401 

5.700 V 489 . . XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX. . 380 

5.600 V 456 . . .XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX. . 380 

5.500 V 456 . . . XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX. . 365 

5.400 V 456 . . . XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX. . 345 

5.300 V 456 . . . XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX. . 333 

5.200 V 211 . . . . XXXXXXXXXXXXXXXXXXXXXXXXXXXX. . 265 

5.100 V 211 . . . . XXXXXXXXXXXXXXXXXXXXXXXXXX. . 234 

4 V 211 . . . . . XXXXXXXXXXXXXXXXXXXXXXX. . 103 

0*********1*********2*********3****^****4*********5 

200.0NS 400.0NS 600.0NS 800.0NS 1US 

PD 7 


CentreSuissed'Essais des Composants Electroniques 

CMOS/BiCMOS /Bipolar 

LowPower 

Low/HighVoltage 

ProductionTesting 

IncomingInspection 

Wafer and PackagedIC's 

Analog/Digital 

Cell-/Transistor -Array 

Evaluation /Verification 

Reliability Testing 

Prototyping 

Std/Special Package 

e.g.Optical Package 

HighTemperatureStorage 

Thermal cycling 

Burn-In 

etc. 

Boards /Systems 

based onMIL HDBK217 

SoftwareMILLIandRelCalc 

Upscreening 

Qualification 

basedon ESA /SCC 

CSEESA CH2000Neuchâtel ) 032/7291130 3 032/729 1139 info@csee.ch

Se 

ics 

Se 

ics 

ar ou n d 

th 

e M 

ar ou n d 

th 

e M 

ic e s 

rv 

ic ro e le ct 

r on 

ic e s 

rv 

ic ro e le ct 

r on 

CSEE SA is your partner able to support you from the 

design through to the procurement of the tested and 

packaged circuit. In the field of analog / digital ASIC’s, 

we have several experienced partners and foundries. 

As a main contractor for the supply of customerspecific 

ASIC’s, we can offer a wide range of 

technologies, such as CMOS, Bipolar, High / Low 

Voltage, Arrays, Cell arrays, Fullcustom. 

Thanks to our close and well-established relationship 

with several partners having a large know-how, we can 

take in charge the design and development of your 

specific analog and digital ASIC. 

• Small series (1’000 pieces) up to large volumes 

• Foundries : 

■ Austria Mikro Systeme International AG 

■ Silicium Microelectronic Integration GmbH 

■ ZETEX plc. 

• Technologies : 

■ CMOS 

■ BiCMOS 

■ Bipolar. 

• Our design-partners in Switzerland : 

■ SUTER IC-DESIGN, Waldenburg 

■ MICROSWISS Centers : 

Rapperswil, Yverdon-les-Bains, Oensingen 

• Cell-Arrays or Full-Custom Design 

• Design based on the arrays : 

■ MD 100 : CMOS 1.5 to 5 volts 

■ HV 500 CMOS 3 to 25 volts 

■ 700 Series Bipolar 3 to 25 volts 

CSEE SA still offers this service and provides state-ofthe-art 

testing capability for standard components, as 

well as for customer specific IC’s. Our specialized staff 

is at your disposal to develop the test program based 

on your specifications and requirements. 

When choosing a component, the most critical point is 

the manufacturer. In fact, he defines and organizes the 

production and quality insurance himself. During the 

evaluation and qualification, the performances (limits 

of operation and tolerances) of the component will 

appear. 

The screening is necessary when a higher reliability is 

required. We are prepared to perform different 

environmental tests, such as Burn - In, Thermal 

cycling, Acceleration, etc. 

• Development of test programs 

• Electrical test from - 55 to + 150°C 

• Wafer test 

• Package test 

• Failure Analysis 

• Choice of the manufacturer 

• Estimation of the technologies 

• Design verification 

• Characterization of the ASIC 

• Specification for the quality supervision 

• Examples : 

■ High temperature storage 125 ° C 

■ Thermal cycling -40 °C / +125 °C 

■ Burn-In 125 °C / stat. / dyn. 

■ Acceleration 

In-house : 

We are proud to be the only company in Switzerland 

who provides an in-house capability for the assembly 

in special plastic packages. 

By our subcontractor : 

Do you need larger quantities of standard packages, 

from 1’000 pieces onward ? We can also offer you this 

service for most used packages at very competitive 

prices. 

• Prototypes of standard packages 

• Production of small std packages at short notice 

• Special packages, for example optical applic. 

• Packages for sensors 

• DIL - SO - PQFP - PLCC - etc. 

Electronic components are not always available in the 

required quality for space application. By upscreening 

industrial parts you can reach the requested quality. 

• Upscreening according to the standards 

ESA / SCC 

• R, L, C, discreet and integrated semiconductors 

• Upscreening of electromechanical components 

• Ageing of laserdiodes 

ACTIV_E.DOC 000927 

The person in charge of the development of a system 

should be able to estimate the reliability of his 

equipment in order to obtain optimal results. With 

MILLI you get a tool easy to use and which brings you 

quick results. 

With the Reliability Prediction Software RelCalc for 

Windows you can calculate the exact value of 

reliability according to MIL HDBK 217 standard. 

• MILLI : 

■ for the development 

■ easy and fast calculation 

■ integrated database approaching MIL HDBK 217 

• RelCalc : 

■ For the quality insurance 

■ Calculation according to MIL HDBK 217 

■ Integrated and external database 

Sales and general technical questions : Peter Annaheim 

Software MILLI and RelCalc (technology) : Jean-Pierre Frauche 

Operational Service : Jean-Luc Décrevel 

CSEE SA CH 2000 Neuchâtel ) 032 / 729 11 30 2 032 / 729 11 39 info@csee.ch 

CSEE SA CH 2000 Neuchâtel ) 032 / 729 11 30 2 032 / 729 11 39 info@csee.ch

PCM - und Test - Daten von ASIC

Create successful ePaper yourself

Delete template?

Save as template ?